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crypto: caam - fix aead sglen for case 'dst != src'
[linux-2.6-block.git] / drivers / crypto / talitos.c
CommitLineData
9c4a7965
KP		 1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
5228f0f7 4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
9c4a7965
KP		 5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/crypto.h>
34#include <linux/hw_random.h>
5af50730
RH		 35#include <linux/of_address.h>
36#include <linux/of_irq.h>
9c4a7965
KP		 37#include <linux/of_platform.h>
38#include <linux/dma-mapping.h>
39#include <linux/io.h>
40#include <linux/spinlock.h>
41#include <linux/rtnetlink.h>
5a0e3ad6 42#include <linux/slab.h>
9c4a7965
KP		 43
44#include <crypto/algapi.h>
45#include <crypto/aes.h>
3952f17e 46#include <crypto/des.h>
9c4a7965 47#include <crypto/sha.h>
497f2e6b 48#include <crypto/md5.h>
9c4a7965
KP		 49#include <crypto/aead.h>
50#include <crypto/authenc.h>
4de9d0b5 51#include <crypto/skcipher.h>
acbf7c62
LN		 52#include <crypto/hash.h>
53#include <crypto/internal/hash.h>
4de9d0b5 54#include <crypto/scatterwalk.h>
9c4a7965
KP		 55
56#include "talitos.h"
57
81eb024c
KP		 58static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
59{
60 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
a752447a 61 talitos_ptr->eptr = upper_32_bits(dma_addr);
81eb024c
KP		 62}
63
9c4a7965
KP		 64/*
65 * map virtual single (contiguous) pointer to h/w descriptor pointer
66 */
67static void map_single_talitos_ptr(struct device *dev,
68 struct talitos_ptr *talitos_ptr,
69 unsigned short len, void *data,
70 unsigned char extent,
71 enum dma_data_direction dir)
72{
81eb024c
KP		 73 dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
74
9c4a7965 75 talitos_ptr->len = cpu_to_be16(len);
81eb024c 76 to_talitos_ptr(talitos_ptr, dma_addr);
9c4a7965
KP		 77 talitos_ptr->j_extent = extent;
78}
79
80/*
81 * unmap bus single (contiguous) h/w descriptor pointer
82 */
83static void unmap_single_talitos_ptr(struct device *dev,
84 struct talitos_ptr *talitos_ptr,
85 enum dma_data_direction dir)
86{
87 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
88 be16_to_cpu(talitos_ptr->len), dir);
89}
90
91static int reset_channel(struct device *dev, int ch)
92{
93 struct talitos_private *priv = dev_get_drvdata(dev);
94 unsigned int timeout = TALITOS_TIMEOUT;
95
ad42d5fc 96 setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
9c4a7965 97
ad42d5fc 98 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
9c4a7965
KP		 99 && --timeout)
100 cpu_relax();
101
102 if (timeout == 0) {
103 dev_err(dev, "failed to reset channel %d\n", ch);
104 return -EIO;
105 }
106
81eb024c 107 /* set 36-bit addressing, done writeback enable and done IRQ enable */
ad42d5fc 108 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
81eb024c 109 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
9c4a7965 110
fe5720e2
KP		 111 /* and ICCR writeback, if available */
112 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
ad42d5fc 113 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
fe5720e2
KP		 114 TALITOS_CCCR_LO_IWSE);
115
9c4a7965
KP		 116 return 0;
117}
118
119static int reset_device(struct device *dev)
120{
121 struct talitos_private *priv = dev_get_drvdata(dev);
122 unsigned int timeout = TALITOS_TIMEOUT;
c3e337f8 123 u32 mcr = TALITOS_MCR_SWR;
9c4a7965 124
c3e337f8 125 setbits32(priv->reg + TALITOS_MCR, mcr);
9c4a7965
KP		 126
127 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
128 && --timeout)
129 cpu_relax();
130
2cdba3cf 131 if (priv->irq[1]) {
c3e337f8
KP		 132 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
133 setbits32(priv->reg + TALITOS_MCR, mcr);
134 }
135
9c4a7965
KP		 136 if (timeout == 0) {
137 dev_err(dev, "failed to reset device\n");
138 return -EIO;
139 }
140
141 return 0;
142}
143
144/*
145 * Reset and initialize the device
146 */
147static int init_device(struct device *dev)
148{
149 struct talitos_private *priv = dev_get_drvdata(dev);
150 int ch, err;
151
152 /*
153 * Master reset
154 * errata documentation: warning: certain SEC interrupts
155 * are not fully cleared by writing the MCR:SWR bit,
156 * set bit twice to completely reset
157 */
158 err = reset_device(dev);
159 if (err)
160 return err;
161
162 err = reset_device(dev);
163 if (err)
164 return err;
165
166 /* reset channels */
167 for (ch = 0; ch < priv->num_channels; ch++) {
168 err = reset_channel(dev, ch);
169 if (err)
170 return err;
171 }
172
173 /* enable channel done and error interrupts */
174 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
175 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
176
fe5720e2
KP		 177 /* disable integrity check error interrupts (use writeback instead) */
178 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
179 setbits32(priv->reg + TALITOS_MDEUICR_LO,
180 TALITOS_MDEUICR_LO_ICE);
181
9c4a7965
KP		 182 return 0;
183}
184
185/**
186 * talitos_submit - submits a descriptor to the device for processing
187 * @dev: the SEC device to be used
5228f0f7 188 * @ch: the SEC device channel to be used
9c4a7965
KP		 189 * @desc: the descriptor to be processed by the device
190 * @callback: whom to call when processing is complete
191 * @context: a handle for use by caller (optional)
192 *
193 * desc must contain valid dma-mapped (bus physical) address pointers.
194 * callback must check err and feedback in descriptor header
195 * for device processing status.
196 */
865d5061
HG		 197int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
198 void (*callback)(struct device *dev,
199 struct talitos_desc *desc,
200 void *context, int error),
201 void *context)
9c4a7965
KP		 202{
203 struct talitos_private *priv = dev_get_drvdata(dev);
204 struct talitos_request *request;
5228f0f7 205 unsigned long flags;
9c4a7965
KP		 206 int head;
207
4b992628 208 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
9c4a7965 209
4b992628 210 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
ec6644d6 211 /* h/w fifo is full */
4b992628 212 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 213 return -EAGAIN;
214 }
215
4b992628
KP		 216 head = priv->chan[ch].head;
217 request = &priv->chan[ch].fifo[head];
ec6644d6 218
9c4a7965
KP		 219 /* map descriptor and save caller data */
220 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
221 DMA_BIDIRECTIONAL);
222 request->callback = callback;
223 request->context = context;
224
225 /* increment fifo head */
4b992628 226 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
9c4a7965
KP		 227
228 smp_wmb();
229 request->desc = desc;
230
231 /* GO! */
232 wmb();
ad42d5fc
KP		 233 out_be32(priv->chan[ch].reg + TALITOS_FF,
234 upper_32_bits(request->dma_desc));
235 out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
a752447a 236 lower_32_bits(request->dma_desc));
9c4a7965 237
4b992628 238 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 239
240 return -EINPROGRESS;
241}
865d5061 242EXPORT_SYMBOL(talitos_submit);
9c4a7965
KP		 243
244/*
245 * process what was done, notify callback of error if not
246 */
247static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
248{
249 struct talitos_private *priv = dev_get_drvdata(dev);
250 struct talitos_request *request, saved_req;
251 unsigned long flags;
252 int tail, status;
253
4b992628 254 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
9c4a7965 255
4b992628
KP		 256 tail = priv->chan[ch].tail;
257 while (priv->chan[ch].fifo[tail].desc) {
258 request = &priv->chan[ch].fifo[tail];
9c4a7965
KP		 259
260 /* descriptors with their done bits set don't get the error */
261 rmb();
ca38a814 262 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
9c4a7965 263 status = 0;
ca38a814 264 else
9c4a7965
KP		 265 if (!error)
266 break;
267 else
268 status = error;
269
270 dma_unmap_single(dev, request->dma_desc,
e938e465
KP		 271 sizeof(struct talitos_desc),
272 DMA_BIDIRECTIONAL);
9c4a7965
KP		 273
274 /* copy entries so we can call callback outside lock */
275 saved_req.desc = request->desc;
276 saved_req.callback = request->callback;
277 saved_req.context = request->context;
278
279 /* release request entry in fifo */
280 smp_wmb();
281 request->desc = NULL;
282
283 /* increment fifo tail */
4b992628 284 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
9c4a7965 285
4b992628 286 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
ec6644d6 287
4b992628 288 atomic_dec(&priv->chan[ch].submit_count);
ec6644d6 289
9c4a7965
KP		 290 saved_req.callback(dev, saved_req.desc, saved_req.context,
291 status);
292 /* channel may resume processing in single desc error case */
293 if (error && !reset_ch && status == error)
294 return;
4b992628
KP		 295 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
296 tail = priv->chan[ch].tail;
9c4a7965
KP		 297 }
298
4b992628 299 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
9c4a7965
KP		 300}
301
302/*
303 * process completed requests for channels that have done status
304 */
c3e337f8
KP		 305#define DEF_TALITOS_DONE(name, ch_done_mask) \
306static void talitos_done_##name(unsigned long data) \
307{ \
308 struct device *dev = (struct device *)data; \
309 struct talitos_private *priv = dev_get_drvdata(dev); \
511d63cb 310 unsigned long flags; \
c3e337f8
KP		 311 \
312 if (ch_done_mask & 1) \
313 flush_channel(dev, 0, 0, 0); \
314 if (priv->num_channels == 1) \
315 goto out; \
316 if (ch_done_mask & (1 << 2)) \
317 flush_channel(dev, 1, 0, 0); \
318 if (ch_done_mask & (1 << 4)) \
319 flush_channel(dev, 2, 0, 0); \
320 if (ch_done_mask & (1 << 6)) \
321 flush_channel(dev, 3, 0, 0); \
322 \
323out: \
324 /* At this point, all completed channels have been processed */ \
325 /* Unmask done interrupts for channels completed later on. */ \
511d63cb 326 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 327 setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
328 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); \
511d63cb 329 spin_unlock_irqrestore(&priv->reg_lock, flags); \
9c4a7965 330}
c3e337f8
KP		 331DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
332DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
333DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
9c4a7965
KP		 334
335/*
336 * locate current (offending) descriptor
337 */
3e721aeb 338static u32 current_desc_hdr(struct device *dev, int ch)
9c4a7965
KP		 339{
340 struct talitos_private *priv = dev_get_drvdata(dev);
4b992628 341 int tail = priv->chan[ch].tail;
9c4a7965
KP		 342 dma_addr_t cur_desc;
343
ad42d5fc 344 cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
9c4a7965 345
4b992628 346 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
9c4a7965 347 tail = (tail + 1) & (priv->fifo_len - 1);
4b992628 348 if (tail == priv->chan[ch].tail) {
9c4a7965 349 dev_err(dev, "couldn't locate current descriptor\n");
3e721aeb 350 return 0;
9c4a7965
KP		 351 }
352 }
353
3e721aeb 354 return priv->chan[ch].fifo[tail].desc->hdr;
9c4a7965
KP		 355}
356
357/*
358 * user diagnostics; report root cause of error based on execution unit status
359 */
3e721aeb 360static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
9c4a7965
KP		 361{
362 struct talitos_private *priv = dev_get_drvdata(dev);
363 int i;
364
3e721aeb 365 if (!desc_hdr)
ad42d5fc 366 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
3e721aeb
KP		 367
368 switch (desc_hdr & DESC_HDR_SEL0_MASK) {
9c4a7965
KP		 369 case DESC_HDR_SEL0_AFEU:
370 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
371 in_be32(priv->reg + TALITOS_AFEUISR),
372 in_be32(priv->reg + TALITOS_AFEUISR_LO));
373 break;
374 case DESC_HDR_SEL0_DEU:
375 dev_err(dev, "DEUISR 0x%08x_%08x\n",
376 in_be32(priv->reg + TALITOS_DEUISR),
377 in_be32(priv->reg + TALITOS_DEUISR_LO));
378 break;
379 case DESC_HDR_SEL0_MDEUA:
380 case DESC_HDR_SEL0_MDEUB:
381 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
382 in_be32(priv->reg + TALITOS_MDEUISR),
383 in_be32(priv->reg + TALITOS_MDEUISR_LO));
384 break;
385 case DESC_HDR_SEL0_RNG:
386 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
387 in_be32(priv->reg + TALITOS_RNGUISR),
388 in_be32(priv->reg + TALITOS_RNGUISR_LO));
389 break;
390 case DESC_HDR_SEL0_PKEU:
391 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
392 in_be32(priv->reg + TALITOS_PKEUISR),
393 in_be32(priv->reg + TALITOS_PKEUISR_LO));
394 break;
395 case DESC_HDR_SEL0_AESU:
396 dev_err(dev, "AESUISR 0x%08x_%08x\n",
397 in_be32(priv->reg + TALITOS_AESUISR),
398 in_be32(priv->reg + TALITOS_AESUISR_LO));
399 break;
400 case DESC_HDR_SEL0_CRCU:
401 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
402 in_be32(priv->reg + TALITOS_CRCUISR),
403 in_be32(priv->reg + TALITOS_CRCUISR_LO));
404 break;
405 case DESC_HDR_SEL0_KEU:
406 dev_err(dev, "KEUISR 0x%08x_%08x\n",
407 in_be32(priv->reg + TALITOS_KEUISR),
408 in_be32(priv->reg + TALITOS_KEUISR_LO));
409 break;
410 }
411
3e721aeb 412 switch (desc_hdr & DESC_HDR_SEL1_MASK) {
9c4a7965
KP		 413 case DESC_HDR_SEL1_MDEUA:
414 case DESC_HDR_SEL1_MDEUB:
415 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
416 in_be32(priv->reg + TALITOS_MDEUISR),
417 in_be32(priv->reg + TALITOS_MDEUISR_LO));
418 break;
419 case DESC_HDR_SEL1_CRCU:
420 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
421 in_be32(priv->reg + TALITOS_CRCUISR),
422 in_be32(priv->reg + TALITOS_CRCUISR_LO));
423 break;
424 }
425
426 for (i = 0; i < 8; i++)
427 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
ad42d5fc
KP		 428 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
429 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
9c4a7965
KP		 430}
431
432/*
433 * recover from error interrupts
434 */
5e718a09 435static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
9c4a7965 436{
9c4a7965
KP		 437 struct talitos_private *priv = dev_get_drvdata(dev);
438 unsigned int timeout = TALITOS_TIMEOUT;
439 int ch, error, reset_dev = 0, reset_ch = 0;
40405f10 440 u32 v, v_lo;
9c4a7965
KP		 441
442 for (ch = 0; ch < priv->num_channels; ch++) {
443 /* skip channels without errors */
444 if (!(isr & (1 << (ch * 2 + 1))))
445 continue;
446
447 error = -EINVAL;
448
ad42d5fc
KP		 449 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
450 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
9c4a7965
KP		 451
452 if (v_lo & TALITOS_CCPSR_LO_DOF) {
453 dev_err(dev, "double fetch fifo overflow error\n");
454 error = -EAGAIN;
455 reset_ch = 1;
456 }
457 if (v_lo & TALITOS_CCPSR_LO_SOF) {
458 /* h/w dropped descriptor */
459 dev_err(dev, "single fetch fifo overflow error\n");
460 error = -EAGAIN;
461 }
462 if (v_lo & TALITOS_CCPSR_LO_MDTE)
463 dev_err(dev, "master data transfer error\n");
464 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
465 dev_err(dev, "s/g data length zero error\n");
466 if (v_lo & TALITOS_CCPSR_LO_FPZ)
467 dev_err(dev, "fetch pointer zero error\n");
468 if (v_lo & TALITOS_CCPSR_LO_IDH)
469 dev_err(dev, "illegal descriptor header error\n");
470 if (v_lo & TALITOS_CCPSR_LO_IEU)
471 dev_err(dev, "invalid execution unit error\n");
472 if (v_lo & TALITOS_CCPSR_LO_EU)
3e721aeb 473 report_eu_error(dev, ch, current_desc_hdr(dev, ch));
9c4a7965
KP		 474 if (v_lo & TALITOS_CCPSR_LO_GB)
475 dev_err(dev, "gather boundary error\n");
476 if (v_lo & TALITOS_CCPSR_LO_GRL)
477 dev_err(dev, "gather return/length error\n");
478 if (v_lo & TALITOS_CCPSR_LO_SB)
479 dev_err(dev, "scatter boundary error\n");
480 if (v_lo & TALITOS_CCPSR_LO_SRL)
481 dev_err(dev, "scatter return/length error\n");
482
483 flush_channel(dev, ch, error, reset_ch);
484
485 if (reset_ch) {
486 reset_channel(dev, ch);
487 } else {
ad42d5fc 488 setbits32(priv->chan[ch].reg + TALITOS_CCCR,
9c4a7965 489 TALITOS_CCCR_CONT);
ad42d5fc
KP		 490 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
491 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
9c4a7965
KP		 492 TALITOS_CCCR_CONT) && --timeout)
493 cpu_relax();
494 if (timeout == 0) {
495 dev_err(dev, "failed to restart channel %d\n",
496 ch);
497 reset_dev = 1;
498 }
499 }
500 }
c3e337f8 501 if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
9c4a7965
KP		 502 dev_err(dev, "done overflow, internal time out, or rngu error: "
503 "ISR 0x%08x_%08x\n", isr, isr_lo);
504
505 /* purge request queues */
506 for (ch = 0; ch < priv->num_channels; ch++)
507 flush_channel(dev, ch, -EIO, 1);
508
509 /* reset and reinitialize the device */
510 init_device(dev);
511 }
512}
513
c3e337f8
KP		 514#define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
515static irqreturn_t talitos_interrupt_##name(int irq, void *data) \
516{ \
517 struct device *dev = data; \
518 struct talitos_private *priv = dev_get_drvdata(dev); \
519 u32 isr, isr_lo; \
511d63cb 520 unsigned long flags; \
c3e337f8 521 \
511d63cb 522 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 523 isr = in_be32(priv->reg + TALITOS_ISR); \
524 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
525 /* Acknowledge interrupt */ \
526 out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
527 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
528 \
511d63cb
HG		 529 if (unlikely(isr & ch_err_mask || isr_lo)) { \
530 spin_unlock_irqrestore(&priv->reg_lock, flags); \
531 talitos_error(dev, isr & ch_err_mask, isr_lo); \
532 } \
533 else { \
c3e337f8
KP		 534 if (likely(isr & ch_done_mask)) { \
535 /* mask further done interrupts. */ \
536 clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
537 /* done_task will unmask done interrupts at exit */ \
538 tasklet_schedule(&priv->done_task[tlet]); \
539 } \
511d63cb
HG		 540 spin_unlock_irqrestore(&priv->reg_lock, flags); \
541 } \
c3e337f8
KP		 542 \
543 return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
544 IRQ_NONE; \
9c4a7965 545}
c3e337f8
KP		 546DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
547DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
548DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
9c4a7965
KP		 549
550/*
551 * hwrng
552 */
553static int talitos_rng_data_present(struct hwrng *rng, int wait)
554{
555 struct device *dev = (struct device *)rng->priv;
556 struct talitos_private *priv = dev_get_drvdata(dev);
557 u32 ofl;
558 int i;
559
560 for (i = 0; i < 20; i++) {
561 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
562 TALITOS_RNGUSR_LO_OFL;
563 if (ofl || !wait)
564 break;
565 udelay(10);
566 }
567
568 return !!ofl;
569}
570
571static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
572{
573 struct device *dev = (struct device *)rng->priv;
574 struct talitos_private *priv = dev_get_drvdata(dev);
575
576 /* rng fifo requires 64-bit accesses */
577 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
578 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
579
580 return sizeof(u32);
581}
582
583static int talitos_rng_init(struct hwrng *rng)
584{
585 struct device *dev = (struct device *)rng->priv;
586 struct talitos_private *priv = dev_get_drvdata(dev);
587 unsigned int timeout = TALITOS_TIMEOUT;
588
589 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
590 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
591 && --timeout)
592 cpu_relax();
593 if (timeout == 0) {
594 dev_err(dev, "failed to reset rng hw\n");
595 return -ENODEV;
596 }
597
598 /* start generating */
599 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
600
601 return 0;
602}
603
604static int talitos_register_rng(struct device *dev)
605{
606 struct talitos_private *priv = dev_get_drvdata(dev);
607
608 priv->rng.name = dev_driver_string(dev),
609 priv->rng.init = talitos_rng_init,
610 priv->rng.data_present = talitos_rng_data_present,
611 priv->rng.data_read = talitos_rng_data_read,
612 priv->rng.priv = (unsigned long)dev;
613
614 return hwrng_register(&priv->rng);
615}
616
617static void talitos_unregister_rng(struct device *dev)
618{
619 struct talitos_private *priv = dev_get_drvdata(dev);
620
621 hwrng_unregister(&priv->rng);
622}
623
624/*
625 * crypto alg
626 */
627#define TALITOS_CRA_PRIORITY 3000
357fb605 628#define TALITOS_MAX_KEY_SIZE 96
3952f17e 629#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
70bcaca7 630
497f2e6b 631#define MD5_BLOCK_SIZE 64
9c4a7965
KP		 632
633struct talitos_ctx {
634 struct device *dev;
5228f0f7 635 int ch;
9c4a7965
KP		 636 __be32 desc_hdr_template;
637 u8 key[TALITOS_MAX_KEY_SIZE];
70bcaca7 638 u8 iv[TALITOS_MAX_IV_LENGTH];
9c4a7965
KP		 639 unsigned int keylen;
640 unsigned int enckeylen;
641 unsigned int authkeylen;
642 unsigned int authsize;
643};
644
497f2e6b
LN		 645#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
646#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
647
648struct talitos_ahash_req_ctx {
60f208d7 649 u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
497f2e6b
LN		 650 unsigned int hw_context_size;
651 u8 buf[HASH_MAX_BLOCK_SIZE];
652 u8 bufnext[HASH_MAX_BLOCK_SIZE];
60f208d7 653 unsigned int swinit;
497f2e6b
LN		 654 unsigned int first;
655 unsigned int last;
656 unsigned int to_hash_later;
5e833bc4 657 u64 nbuf;
497f2e6b
LN		 658 struct scatterlist bufsl[2];
659 struct scatterlist *psrc;
660};
661
56af8cd4
LN		 662static int aead_setauthsize(struct crypto_aead *authenc,
663 unsigned int authsize)
9c4a7965
KP		 664{
665 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
666
667 ctx->authsize = authsize;
668
669 return 0;
670}
671
56af8cd4
LN		 672static int aead_setkey(struct crypto_aead *authenc,
673 const u8 *key, unsigned int keylen)
9c4a7965
KP		 674{
675 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
c306a98d 676 struct crypto_authenc_keys keys;
9c4a7965 677
c306a98d 678 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
9c4a7965
KP		 679 goto badkey;
680
c306a98d 681 if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
9c4a7965
KP		 682 goto badkey;
683
c306a98d
MK		 684 memcpy(ctx->key, keys.authkey, keys.authkeylen);
685 memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
9c4a7965 686
c306a98d
MK		 687 ctx->keylen = keys.authkeylen + keys.enckeylen;
688 ctx->enckeylen = keys.enckeylen;
689 ctx->authkeylen = keys.authkeylen;
9c4a7965
KP		 690
691 return 0;
692
693badkey:
694 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
695 return -EINVAL;
696}
697
698/*
56af8cd4 699 * talitos_edesc - s/w-extended descriptor
79fd31d3 700 * @assoc_nents: number of segments in associated data scatterlist
9c4a7965
KP		 701 * @src_nents: number of segments in input scatterlist
702 * @dst_nents: number of segments in output scatterlist
79fd31d3 703 * @assoc_chained: whether assoc is chained or not
2a1cfe46
HG		 704 * @src_chained: whether src is chained or not
705 * @dst_chained: whether dst is chained or not
79fd31d3 706 * @iv_dma: dma address of iv for checking continuity and link table
9c4a7965
KP		 707 * @dma_len: length of dma mapped link_tbl space
708 * @dma_link_tbl: bus physical address of link_tbl
709 * @desc: h/w descriptor
710 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
711 *
712 * if decrypting (with authcheck), or either one of src_nents or dst_nents
713 * is greater than 1, an integrity check value is concatenated to the end
714 * of link_tbl data
715 */
56af8cd4 716struct talitos_edesc {
79fd31d3 717 int assoc_nents;
9c4a7965
KP		 718 int src_nents;
719 int dst_nents;
79fd31d3 720 bool assoc_chained;
2a1cfe46
HG		 721 bool src_chained;
722 bool dst_chained;
79fd31d3 723 dma_addr_t iv_dma;
9c4a7965
KP		 724 int dma_len;
725 dma_addr_t dma_link_tbl;
726 struct talitos_desc desc;
727 struct talitos_ptr link_tbl[0];
728};
729
4de9d0b5
LN		 730static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
731 unsigned int nents, enum dma_data_direction dir,
2a1cfe46 732 bool chained)
4de9d0b5
LN		 733{
734 if (unlikely(chained))
735 while (sg) {
736 dma_map_sg(dev, sg, 1, dir);
737 sg = scatterwalk_sg_next(sg);
738 }
739 else
740 dma_map_sg(dev, sg, nents, dir);
741 return nents;
742}
743
744static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
745 enum dma_data_direction dir)
746{
747 while (sg) {
748 dma_unmap_sg(dev, sg, 1, dir);
749 sg = scatterwalk_sg_next(sg);
750 }
751}
752
753static void talitos_sg_unmap(struct device *dev,
754 struct talitos_edesc *edesc,
755 struct scatterlist *src,
756 struct scatterlist *dst)
757{
758 unsigned int src_nents = edesc->src_nents ? : 1;
759 unsigned int dst_nents = edesc->dst_nents ? : 1;
760
761 if (src != dst) {
2a1cfe46 762 if (edesc->src_chained)
4de9d0b5
LN		 763 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
764 else
765 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
766
497f2e6b 767 if (dst) {
2a1cfe46 768 if (edesc->dst_chained)
497f2e6b
LN		 769 talitos_unmap_sg_chain(dev, dst,
770 DMA_FROM_DEVICE);
771 else
772 dma_unmap_sg(dev, dst, dst_nents,
773 DMA_FROM_DEVICE);
774 }
4de9d0b5 775 } else
2a1cfe46 776 if (edesc->src_chained)
4de9d0b5
LN		 777 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
778 else
779 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
780}
781
9c4a7965 782static void ipsec_esp_unmap(struct device *dev,
56af8cd4 783 struct talitos_edesc *edesc,
9c4a7965
KP		 784 struct aead_request *areq)
785{
786 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
787 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
788 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
789 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
790
79fd31d3
HG		 791 if (edesc->assoc_chained)
792 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
935e99a3 793 else if (areq->assoclen)
79fd31d3
HG		 794 /* assoc_nents counts also for IV in non-contiguous cases */
795 dma_unmap_sg(dev, areq->assoc,
796 edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
797 DMA_TO_DEVICE);
9c4a7965 798
4de9d0b5 799 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
9c4a7965
KP		 800
801 if (edesc->dma_len)
802 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
803 DMA_BIDIRECTIONAL);
804}
805
806/*
807 * ipsec_esp descriptor callbacks
808 */
809static void ipsec_esp_encrypt_done(struct device *dev,
810 struct talitos_desc *desc, void *context,
811 int err)
812{
813 struct aead_request *areq = context;
9c4a7965
KP		 814 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
815 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 816 struct talitos_edesc *edesc;
9c4a7965
KP		 817 struct scatterlist *sg;
818 void *icvdata;
819
19bbbc63
KP		 820 edesc = container_of(desc, struct talitos_edesc, desc);
821
9c4a7965
KP		 822 ipsec_esp_unmap(dev, edesc, areq);
823
824 /* copy the generated ICV to dst */
60542505 825 if (edesc->dst_nents) {
9c4a7965 826 icvdata = &edesc->link_tbl[edesc->src_nents +
79fd31d3
HG		 827 edesc->dst_nents + 2 +
828 edesc->assoc_nents];
9c4a7965
KP		 829 sg = sg_last(areq->dst, edesc->dst_nents);
830 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
831 icvdata, ctx->authsize);
832 }
833
834 kfree(edesc);
835
836 aead_request_complete(areq, err);
837}
838
fe5720e2 839static void ipsec_esp_decrypt_swauth_done(struct device *dev,
e938e465
KP		 840 struct talitos_desc *desc,
841 void *context, int err)
9c4a7965
KP		 842{
843 struct aead_request *req = context;
9c4a7965
KP		 844 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
845 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 846 struct talitos_edesc *edesc;
9c4a7965
KP		 847 struct scatterlist *sg;
848 void *icvdata;
849
19bbbc63
KP		 850 edesc = container_of(desc, struct talitos_edesc, desc);
851
9c4a7965
KP		 852 ipsec_esp_unmap(dev, edesc, req);
853
854 if (!err) {
855 /* auth check */
856 if (edesc->dma_len)
857 icvdata = &edesc->link_tbl[edesc->src_nents +
79fd31d3
HG		 858 edesc->dst_nents + 2 +
859 edesc->assoc_nents];
9c4a7965
KP		 860 else
861 icvdata = &edesc->link_tbl[0];
862
863 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
864 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
865 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
866 }
867
868 kfree(edesc);
869
870 aead_request_complete(req, err);
871}
872
fe5720e2 873static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
e938e465
KP		 874 struct talitos_desc *desc,
875 void *context, int err)
fe5720e2
KP		 876{
877 struct aead_request *req = context;
19bbbc63
KP		 878 struct talitos_edesc *edesc;
879
880 edesc = container_of(desc, struct talitos_edesc, desc);
fe5720e2
KP		 881
882 ipsec_esp_unmap(dev, edesc, req);
883
884 /* check ICV auth status */
e938e465
KP		 885 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
886 DESC_HDR_LO_ICCR1_PASS))
887 err = -EBADMSG;
fe5720e2
KP		 888
889 kfree(edesc);
890
891 aead_request_complete(req, err);
892}
893
9c4a7965
KP		 894/*
895 * convert scatterlist to SEC h/w link table format
896 * stop at cryptlen bytes
897 */
70bcaca7 898static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
9c4a7965
KP		 899 int cryptlen, struct talitos_ptr *link_tbl_ptr)
900{
70bcaca7
LN		 901 int n_sg = sg_count;
902
903 while (n_sg--) {
81eb024c 904 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
9c4a7965
KP		 905 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
906 link_tbl_ptr->j_extent = 0;
907 link_tbl_ptr++;
908 cryptlen -= sg_dma_len(sg);
4de9d0b5 909 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 910 }
911
70bcaca7 912 /* adjust (decrease) last one (or two) entry's len to cryptlen */
9c4a7965 913 link_tbl_ptr--;
c0e741d4 914 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
70bcaca7
LN		 915 /* Empty this entry, and move to previous one */
916 cryptlen += be16_to_cpu(link_tbl_ptr->len);
917 link_tbl_ptr->len = 0;
918 sg_count--;
919 link_tbl_ptr--;
920 }
7291a932 921 be16_add_cpu(&link_tbl_ptr->len, cryptlen);
9c4a7965
KP		 922
923 /* tag end of link table */
924 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
70bcaca7
LN		 925
926 return sg_count;
9c4a7965
KP		 927}
928
929/*
930 * fill in and submit ipsec_esp descriptor
931 */
56af8cd4 932static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
79fd31d3
HG		 933 u64 seq, void (*callback) (struct device *dev,
934 struct talitos_desc *desc,
935 void *context, int error))
9c4a7965
KP		 936{
937 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
938 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
939 struct device *dev = ctx->dev;
940 struct talitos_desc *desc = &edesc->desc;
941 unsigned int cryptlen = areq->cryptlen;
942 unsigned int authsize = ctx->authsize;
e41256f1 943 unsigned int ivsize = crypto_aead_ivsize(aead);
fa86a267 944 int sg_count, ret;
fe5720e2 945 int sg_link_tbl_len;
9c4a7965
KP		 946
947 /* hmac key */
948 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
949 0, DMA_TO_DEVICE);
79fd31d3 950
9c4a7965 951 /* hmac data */
79fd31d3
HG		 952 desc->ptr[1].len = cpu_to_be16(areq->assoclen + ivsize);
953 if (edesc->assoc_nents) {
954 int tbl_off = edesc->src_nents + edesc->dst_nents + 2;
955 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
956
957 to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
958 sizeof(struct talitos_ptr));
959 desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
960
961 /* assoc_nents - 1 entries for assoc, 1 for IV */
962 sg_count = sg_to_link_tbl(areq->assoc, edesc->assoc_nents - 1,
963 areq->assoclen, tbl_ptr);
964
965 /* add IV to link table */
966 tbl_ptr += sg_count - 1;
967 tbl_ptr->j_extent = 0;
968 tbl_ptr++;
969 to_talitos_ptr(tbl_ptr, edesc->iv_dma);
970 tbl_ptr->len = cpu_to_be16(ivsize);
971 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
972
973 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
974 edesc->dma_len, DMA_BIDIRECTIONAL);
975 } else {
935e99a3
HG		 976 if (areq->assoclen)
977 to_talitos_ptr(&desc->ptr[1],
978 sg_dma_address(areq->assoc));
979 else
980 to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
79fd31d3
HG		 981 desc->ptr[1].j_extent = 0;
982 }
983
9c4a7965 984 /* cipher iv */
79fd31d3
HG		 985 to_talitos_ptr(&desc->ptr[2], edesc->iv_dma);
986 desc->ptr[2].len = cpu_to_be16(ivsize);
987 desc->ptr[2].j_extent = 0;
988 /* Sync needed for the aead_givencrypt case */
989 dma_sync_single_for_device(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
9c4a7965
KP		 990
991 /* cipher key */
992 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
993 (char *)&ctx->key + ctx->authkeylen, 0,
994 DMA_TO_DEVICE);
995
996 /*
997 * cipher in
998 * map and adjust cipher len to aead request cryptlen.
999 * extent is bytes of HMAC postpended to ciphertext,
1000 * typically 12 for ipsec
1001 */
1002 desc->ptr[4].len = cpu_to_be16(cryptlen);
1003 desc->ptr[4].j_extent = authsize;
1004
e938e465
KP		 1005 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1006 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1007 : DMA_TO_DEVICE,
2a1cfe46 1008 edesc->src_chained);
9c4a7965
KP		 1009
1010 if (sg_count == 1) {
81eb024c 1011 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
9c4a7965 1012 } else {
fe5720e2
KP		 1013 sg_link_tbl_len = cryptlen;
1014
962a9c99 1015 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
fe5720e2 1016 sg_link_tbl_len = cryptlen + authsize;
e938e465 1017
fe5720e2 1018 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
70bcaca7
LN		 1019 &edesc->link_tbl[0]);
1020 if (sg_count > 1) {
1021 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
81eb024c 1022 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
e938e465
KP		 1023 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1024 edesc->dma_len,
1025 DMA_BIDIRECTIONAL);
70bcaca7
LN		 1026 } else {
1027 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1028 to_talitos_ptr(&desc->ptr[4],
1029 sg_dma_address(areq->src));
70bcaca7 1030 }
9c4a7965
KP		 1031 }
1032
1033 /* cipher out */
1034 desc->ptr[5].len = cpu_to_be16(cryptlen);
1035 desc->ptr[5].j_extent = authsize;
1036
e938e465 1037 if (areq->src != areq->dst)
4de9d0b5
LN		 1038 sg_count = talitos_map_sg(dev, areq->dst,
1039 edesc->dst_nents ? : 1,
2a1cfe46 1040 DMA_FROM_DEVICE, edesc->dst_chained);
9c4a7965
KP		 1041
1042 if (sg_count == 1) {
81eb024c 1043 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
9c4a7965 1044 } else {
79fd31d3
HG		 1045 int tbl_off = edesc->src_nents + 1;
1046 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
9c4a7965 1047
81eb024c 1048 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
79fd31d3 1049 tbl_off * sizeof(struct talitos_ptr));
fe5720e2 1050 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
79fd31d3 1051 tbl_ptr);
fe5720e2 1052
f3c85bc1 1053 /* Add an entry to the link table for ICV data */
79fd31d3
HG		 1054 tbl_ptr += sg_count - 1;
1055 tbl_ptr->j_extent = 0;
1056 tbl_ptr++;
1057 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1058 tbl_ptr->len = cpu_to_be16(authsize);
9c4a7965
KP		 1059
1060 /* icv data follows link tables */
79fd31d3
HG		 1061 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1062 (tbl_off + edesc->dst_nents + 1 +
1063 edesc->assoc_nents) *
81eb024c 1064 sizeof(struct talitos_ptr));
9c4a7965
KP		 1065 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1066 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1067 edesc->dma_len, DMA_BIDIRECTIONAL);
1068 }
1069
1070 /* iv out */
1071 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1072 DMA_FROM_DEVICE);
1073
5228f0f7 1074 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
fa86a267
KP		 1075 if (ret != -EINPROGRESS) {
1076 ipsec_esp_unmap(dev, edesc, areq);
1077 kfree(edesc);
1078 }
1079 return ret;
9c4a7965
KP		 1080}
1081
9c4a7965
KP		 1082/*
1083 * derive number of elements in scatterlist
1084 */
2a1cfe46 1085static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
9c4a7965
KP		 1086{
1087 struct scatterlist *sg = sg_list;
1088 int sg_nents = 0;
1089
2a1cfe46 1090 *chained = false;
4de9d0b5 1091 while (nbytes > 0) {
9c4a7965
KP		 1092 sg_nents++;
1093 nbytes -= sg->length;
4de9d0b5 1094 if (!sg_is_last(sg) && (sg + 1)->length == 0)
2a1cfe46 1095 *chained = true;
4de9d0b5 1096 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 1097 }
1098
1099 return sg_nents;
1100}
1101
1102/*
56af8cd4 1103 * allocate and map the extended descriptor
9c4a7965 1104 */
4de9d0b5 1105static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
79fd31d3 1106 struct scatterlist *assoc,
4de9d0b5
LN		 1107 struct scatterlist *src,
1108 struct scatterlist *dst,
79fd31d3
HG		 1109 u8 *iv,
1110 unsigned int assoclen,
4de9d0b5
LN		 1111 unsigned int cryptlen,
1112 unsigned int authsize,
79fd31d3 1113 unsigned int ivsize,
4de9d0b5
LN		 1114 int icv_stashing,
1115 u32 cryptoflags)
9c4a7965 1116{
56af8cd4 1117 struct talitos_edesc *edesc;
79fd31d3
HG		 1118 int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
1119 bool assoc_chained = false, src_chained = false, dst_chained = false;
1120 dma_addr_t iv_dma = 0;
4de9d0b5 1121 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
586725f8 1122 GFP_ATOMIC;
9c4a7965 1123
4de9d0b5
LN		 1124 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1125 dev_err(dev, "length exceeds h/w max limit\n");
9c4a7965
KP		 1126 return ERR_PTR(-EINVAL);
1127 }
1128
935e99a3 1129 if (ivsize)
79fd31d3
HG		 1130 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1131
935e99a3 1132 if (assoclen) {
79fd31d3
HG		 1133 /*
1134 * Currently it is assumed that iv is provided whenever assoc
1135 * is.
1136 */
1137 BUG_ON(!iv);
1138
1139 assoc_nents = sg_count(assoc, assoclen, &assoc_chained);
1140 talitos_map_sg(dev, assoc, assoc_nents, DMA_TO_DEVICE,
1141 assoc_chained);
1142 assoc_nents = (assoc_nents == 1) ? 0 : assoc_nents;
1143
1144 if (assoc_nents || sg_dma_address(assoc) + assoclen != iv_dma)
1145 assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1146 }
1147
4de9d0b5 1148 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
9c4a7965
KP		 1149 src_nents = (src_nents == 1) ? 0 : src_nents;
1150
602499a3 1151 if (!dst) {
497f2e6b 1152 dst_nents = 0;
9c4a7965 1153 } else {
497f2e6b
LN		 1154 if (dst == src) {
1155 dst_nents = src_nents;
1156 } else {
1157 dst_nents = sg_count(dst, cryptlen + authsize,
1158 &dst_chained);
1159 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1160 }
9c4a7965
KP		 1161 }
1162
1163 /*
1164 * allocate space for base edesc plus the link tables,
f3c85bc1 1165 * allowing for two separate entries for ICV and generated ICV (+ 2),
9c4a7965
KP		 1166 * and the ICV data itself
1167 */
56af8cd4 1168 alloc_len = sizeof(struct talitos_edesc);
79fd31d3
HG		 1169 if (assoc_nents || src_nents || dst_nents) {
1170 dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
1171 sizeof(struct talitos_ptr) + authsize;
9c4a7965
KP		 1172 alloc_len += dma_len;
1173 } else {
1174 dma_len = 0;
4de9d0b5 1175 alloc_len += icv_stashing ? authsize : 0;
9c4a7965
KP		 1176 }
1177
586725f8 1178 edesc = kmalloc(alloc_len, GFP_DMA | flags);
9c4a7965 1179 if (!edesc) {
935e99a3
HG		 1180 if (assoc_chained)
1181 talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1182 else if (assoclen)
1183 dma_unmap_sg(dev, assoc,
1184 assoc_nents ? assoc_nents - 1 : 1,
1185 DMA_TO_DEVICE);
1186
79fd31d3
HG		 1187 if (iv_dma)
1188 dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
935e99a3 1189
4de9d0b5 1190 dev_err(dev, "could not allocate edescriptor\n");
9c4a7965
KP		 1191 return ERR_PTR(-ENOMEM);
1192 }
1193
79fd31d3 1194 edesc->assoc_nents = assoc_nents;
9c4a7965
KP		 1195 edesc->src_nents = src_nents;
1196 edesc->dst_nents = dst_nents;
79fd31d3 1197 edesc->assoc_chained = assoc_chained;
2a1cfe46
HG		 1198 edesc->src_chained = src_chained;
1199 edesc->dst_chained = dst_chained;
79fd31d3 1200 edesc->iv_dma = iv_dma;
9c4a7965 1201 edesc->dma_len = dma_len;
497f2e6b
LN		 1202 if (dma_len)
1203 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1204 edesc->dma_len,
1205 DMA_BIDIRECTIONAL);
9c4a7965
KP		 1206
1207 return edesc;
1208}
1209
79fd31d3 1210static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
4de9d0b5
LN		 1211 int icv_stashing)
1212{
1213 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1214 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
79fd31d3 1215 unsigned int ivsize = crypto_aead_ivsize(authenc);
4de9d0b5 1216
79fd31d3
HG		 1217 return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1218 iv, areq->assoclen, areq->cryptlen,
1219 ctx->authsize, ivsize, icv_stashing,
4de9d0b5
LN		 1220 areq->base.flags);
1221}
1222
56af8cd4 1223static int aead_encrypt(struct aead_request *req)
9c4a7965
KP		 1224{
1225 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1226 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1227 struct talitos_edesc *edesc;
9c4a7965
KP		 1228
1229 /* allocate extended descriptor */
79fd31d3 1230 edesc = aead_edesc_alloc(req, req->iv, 0);
9c4a7965
KP		 1231 if (IS_ERR(edesc))
1232 return PTR_ERR(edesc);
1233
1234 /* set encrypt */
70bcaca7 1235 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965 1236
79fd31d3 1237 return ipsec_esp(edesc, req, 0, ipsec_esp_encrypt_done);
9c4a7965
KP		 1238}
1239
56af8cd4 1240static int aead_decrypt(struct aead_request *req)
9c4a7965
KP		 1241{
1242 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1243 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1244 unsigned int authsize = ctx->authsize;
fe5720e2 1245 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
56af8cd4 1246 struct talitos_edesc *edesc;
9c4a7965
KP		 1247 struct scatterlist *sg;
1248 void *icvdata;
1249
1250 req->cryptlen -= authsize;
1251
1252 /* allocate extended descriptor */
79fd31d3 1253 edesc = aead_edesc_alloc(req, req->iv, 1);
9c4a7965
KP		 1254 if (IS_ERR(edesc))
1255 return PTR_ERR(edesc);
1256
fe5720e2 1257 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
e938e465
KP		 1258 ((!edesc->src_nents && !edesc->dst_nents) ||
1259 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
9c4a7965 1260
fe5720e2 1261 /* decrypt and check the ICV */
e938e465
KP		 1262 edesc->desc.hdr = ctx->desc_hdr_template |
1263 DESC_HDR_DIR_INBOUND |
fe5720e2 1264 DESC_HDR_MODE1_MDEU_CICV;
9c4a7965 1265
fe5720e2
KP		 1266 /* reset integrity check result bits */
1267 edesc->desc.hdr_lo = 0;
9c4a7965 1268
79fd31d3 1269 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_hwauth_done);
e938e465 1270 }
fe5720e2 1271
e938e465
KP		 1272 /* Have to check the ICV with software */
1273 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
fe5720e2 1274
e938e465
KP		 1275 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1276 if (edesc->dma_len)
1277 icvdata = &edesc->link_tbl[edesc->src_nents +
79fd31d3
HG		 1278 edesc->dst_nents + 2 +
1279 edesc->assoc_nents];
e938e465
KP		 1280 else
1281 icvdata = &edesc->link_tbl[0];
fe5720e2 1282
e938e465 1283 sg = sg_last(req->src, edesc->src_nents ? : 1);
fe5720e2 1284
e938e465
KP		 1285 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1286 ctx->authsize);
fe5720e2 1287
79fd31d3 1288 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_swauth_done);
9c4a7965
KP		 1289}
1290
56af8cd4 1291static int aead_givencrypt(struct aead_givcrypt_request *req)
9c4a7965
KP		 1292{
1293 struct aead_request *areq = &req->areq;
1294 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1295 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1296 struct talitos_edesc *edesc;
9c4a7965
KP		 1297
1298 /* allocate extended descriptor */
79fd31d3 1299 edesc = aead_edesc_alloc(areq, req->giv, 0);
9c4a7965
KP		 1300 if (IS_ERR(edesc))
1301 return PTR_ERR(edesc);
1302
1303 /* set encrypt */
70bcaca7 1304 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1305
1306 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
ba95487d
KP		 1307 /* avoid consecutive packets going out with same IV */
1308 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
9c4a7965 1309
79fd31d3 1310 return ipsec_esp(edesc, areq, req->seq, ipsec_esp_encrypt_done);
9c4a7965
KP		 1311}
1312
4de9d0b5
LN		 1313static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1314 const u8 *key, unsigned int keylen)
1315{
1316 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
4de9d0b5
LN		 1317
1318 memcpy(&ctx->key, key, keylen);
1319 ctx->keylen = keylen;
1320
1321 return 0;
4de9d0b5
LN		 1322}
1323
1324static void common_nonsnoop_unmap(struct device *dev,
1325 struct talitos_edesc *edesc,
1326 struct ablkcipher_request *areq)
1327{
1328 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1329 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1330 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1331
1332 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1333
1334 if (edesc->dma_len)
1335 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1336 DMA_BIDIRECTIONAL);
1337}
1338
1339static void ablkcipher_done(struct device *dev,
1340 struct talitos_desc *desc, void *context,
1341 int err)
1342{
1343 struct ablkcipher_request *areq = context;
19bbbc63
KP		 1344 struct talitos_edesc *edesc;
1345
1346 edesc = container_of(desc, struct talitos_edesc, desc);
4de9d0b5
LN		 1347
1348 common_nonsnoop_unmap(dev, edesc, areq);
1349
1350 kfree(edesc);
1351
1352 areq->base.complete(&areq->base, err);
1353}
1354
1355static int common_nonsnoop(struct talitos_edesc *edesc,
1356 struct ablkcipher_request *areq,
4de9d0b5
LN		 1357 void (*callback) (struct device *dev,
1358 struct talitos_desc *desc,
1359 void *context, int error))
1360{
1361 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1362 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1363 struct device *dev = ctx->dev;
1364 struct talitos_desc *desc = &edesc->desc;
1365 unsigned int cryptlen = areq->nbytes;
79fd31d3 1366 unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
4de9d0b5
LN		 1367 int sg_count, ret;
1368
1369 /* first DWORD empty */
1370 desc->ptr[0].len = 0;
81eb024c 1371 to_talitos_ptr(&desc->ptr[0], 0);
4de9d0b5
LN		 1372 desc->ptr[0].j_extent = 0;
1373
1374 /* cipher iv */
79fd31d3
HG		 1375 to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
1376 desc->ptr[1].len = cpu_to_be16(ivsize);
1377 desc->ptr[1].j_extent = 0;
4de9d0b5
LN		 1378
1379 /* cipher key */
1380 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1381 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1382
1383 /*
1384 * cipher in
1385 */
1386 desc->ptr[3].len = cpu_to_be16(cryptlen);
1387 desc->ptr[3].j_extent = 0;
1388
1389 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1390 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1391 : DMA_TO_DEVICE,
2a1cfe46 1392 edesc->src_chained);
4de9d0b5
LN		 1393
1394 if (sg_count == 1) {
81eb024c 1395 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
4de9d0b5
LN		 1396 } else {
1397 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1398 &edesc->link_tbl[0]);
1399 if (sg_count > 1) {
81eb024c 1400 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
4de9d0b5 1401 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
e938e465
KP		 1402 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1403 edesc->dma_len,
1404 DMA_BIDIRECTIONAL);
4de9d0b5
LN		 1405 } else {
1406 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1407 to_talitos_ptr(&desc->ptr[3],
1408 sg_dma_address(areq->src));
4de9d0b5
LN		 1409 }
1410 }
1411
1412 /* cipher out */
1413 desc->ptr[4].len = cpu_to_be16(cryptlen);
1414 desc->ptr[4].j_extent = 0;
1415
1416 if (areq->src != areq->dst)
1417 sg_count = talitos_map_sg(dev, areq->dst,
1418 edesc->dst_nents ? : 1,
2a1cfe46 1419 DMA_FROM_DEVICE, edesc->dst_chained);
4de9d0b5
LN		 1420
1421 if (sg_count == 1) {
81eb024c 1422 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
4de9d0b5
LN		 1423 } else {
1424 struct talitos_ptr *link_tbl_ptr =
1425 &edesc->link_tbl[edesc->src_nents + 1];
1426
81eb024c
KP		 1427 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1428 (edesc->src_nents + 1) *
1429 sizeof(struct talitos_ptr));
4de9d0b5 1430 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
4de9d0b5
LN		 1431 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1432 link_tbl_ptr);
1433 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1434 edesc->dma_len, DMA_BIDIRECTIONAL);
1435 }
1436
1437 /* iv out */
1438 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1439 DMA_FROM_DEVICE);
1440
1441 /* last DWORD empty */
1442 desc->ptr[6].len = 0;
81eb024c 1443 to_talitos_ptr(&desc->ptr[6], 0);
4de9d0b5
LN		 1444 desc->ptr[6].j_extent = 0;
1445
5228f0f7 1446 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
4de9d0b5
LN		 1447 if (ret != -EINPROGRESS) {
1448 common_nonsnoop_unmap(dev, edesc, areq);
1449 kfree(edesc);
1450 }
1451 return ret;
1452}
1453
e938e465
KP		 1454static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1455 areq)
4de9d0b5
LN		 1456{
1457 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1458 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
79fd31d3 1459 unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
4de9d0b5 1460
79fd31d3
HG		 1461 return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1462 areq->info, 0, areq->nbytes, 0, ivsize, 0,
1463 areq->base.flags);
4de9d0b5
LN		 1464}
1465
1466static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1467{
1468 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1469 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1470 struct talitos_edesc *edesc;
1471
1472 /* allocate extended descriptor */
1473 edesc = ablkcipher_edesc_alloc(areq);
1474 if (IS_ERR(edesc))
1475 return PTR_ERR(edesc);
1476
1477 /* set encrypt */
1478 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1479
febec542 1480 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1481}
1482
1483static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1484{
1485 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1486 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1487 struct talitos_edesc *edesc;
1488
1489 /* allocate extended descriptor */
1490 edesc = ablkcipher_edesc_alloc(areq);
1491 if (IS_ERR(edesc))
1492 return PTR_ERR(edesc);
1493
1494 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1495
febec542 1496 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1497}
1498
497f2e6b
LN		 1499static void common_nonsnoop_hash_unmap(struct device *dev,
1500 struct talitos_edesc *edesc,
1501 struct ahash_request *areq)
1502{
1503 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1504
1505 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1506
1507 /* When using hashctx-in, must unmap it. */
1508 if (edesc->desc.ptr[1].len)
1509 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1510 DMA_TO_DEVICE);
1511
1512 if (edesc->desc.ptr[2].len)
1513 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1514 DMA_TO_DEVICE);
1515
1516 talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1517
1518 if (edesc->dma_len)
1519 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1520 DMA_BIDIRECTIONAL);
1521
1522}
1523
1524static void ahash_done(struct device *dev,
1525 struct talitos_desc *desc, void *context,
1526 int err)
1527{
1528 struct ahash_request *areq = context;
1529 struct talitos_edesc *edesc =
1530 container_of(desc, struct talitos_edesc, desc);
1531 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1532
1533 if (!req_ctx->last && req_ctx->to_hash_later) {
1534 /* Position any partial block for next update/final/finup */
1535 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
5e833bc4 1536 req_ctx->nbuf = req_ctx->to_hash_later;
497f2e6b
LN		 1537 }
1538 common_nonsnoop_hash_unmap(dev, edesc, areq);
1539
1540 kfree(edesc);
1541
1542 areq->base.complete(&areq->base, err);
1543}
1544
1545static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1546 struct ahash_request *areq, unsigned int length,
1547 void (*callback) (struct device *dev,
1548 struct talitos_desc *desc,
1549 void *context, int error))
1550{
1551 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1552 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1553 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1554 struct device *dev = ctx->dev;
1555 struct talitos_desc *desc = &edesc->desc;
1556 int sg_count, ret;
1557
1558 /* first DWORD empty */
1559 desc->ptr[0] = zero_entry;
1560
60f208d7
KP		 1561 /* hash context in */
1562 if (!req_ctx->first || req_ctx->swinit) {
497f2e6b
LN		 1563 map_single_talitos_ptr(dev, &desc->ptr[1],
1564 req_ctx->hw_context_size,
1565 (char *)req_ctx->hw_context, 0,
1566 DMA_TO_DEVICE);
60f208d7 1567 req_ctx->swinit = 0;
497f2e6b
LN		 1568 } else {
1569 desc->ptr[1] = zero_entry;
1570 /* Indicate next op is not the first. */
1571 req_ctx->first = 0;
1572 }
1573
1574 /* HMAC key */
1575 if (ctx->keylen)
1576 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1577 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1578 else
1579 desc->ptr[2] = zero_entry;
1580
1581 /*
1582 * data in
1583 */
1584 desc->ptr[3].len = cpu_to_be16(length);
1585 desc->ptr[3].j_extent = 0;
1586
1587 sg_count = talitos_map_sg(dev, req_ctx->psrc,
1588 edesc->src_nents ? : 1,
2a1cfe46 1589 DMA_TO_DEVICE, edesc->src_chained);
497f2e6b
LN		 1590
1591 if (sg_count == 1) {
1592 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1593 } else {
1594 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1595 &edesc->link_tbl[0]);
1596 if (sg_count > 1) {
1597 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1598 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1599 dma_sync_single_for_device(ctx->dev,
1600 edesc->dma_link_tbl,
1601 edesc->dma_len,
1602 DMA_BIDIRECTIONAL);
1603 } else {
1604 /* Only one segment now, so no link tbl needed */
1605 to_talitos_ptr(&desc->ptr[3],
1606 sg_dma_address(req_ctx->psrc));
1607 }
1608 }
1609
1610 /* fifth DWORD empty */
1611 desc->ptr[4] = zero_entry;
1612
1613 /* hash/HMAC out -or- hash context out */
1614 if (req_ctx->last)
1615 map_single_talitos_ptr(dev, &desc->ptr[5],
1616 crypto_ahash_digestsize(tfm),
1617 areq->result, 0, DMA_FROM_DEVICE);
1618 else
1619 map_single_talitos_ptr(dev, &desc->ptr[5],
1620 req_ctx->hw_context_size,
1621 req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1622
1623 /* last DWORD empty */
1624 desc->ptr[6] = zero_entry;
1625
5228f0f7 1626 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
497f2e6b
LN		 1627 if (ret != -EINPROGRESS) {
1628 common_nonsnoop_hash_unmap(dev, edesc, areq);
1629 kfree(edesc);
1630 }
1631 return ret;
1632}
1633
1634static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1635 unsigned int nbytes)
1636{
1637 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1638 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1639 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1640
79fd31d3
HG		 1641 return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1642 nbytes, 0, 0, 0, areq->base.flags);
497f2e6b
LN		 1643}
1644
1645static int ahash_init(struct ahash_request *areq)
1646{
1647 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1648 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1649
1650 /* Initialize the context */
5e833bc4 1651 req_ctx->nbuf = 0;
60f208d7
KP		 1652 req_ctx->first = 1; /* first indicates h/w must init its context */
1653 req_ctx->swinit = 0; /* assume h/w init of context */
497f2e6b
LN		 1654 req_ctx->hw_context_size =
1655 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1656 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1657 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1658
1659 return 0;
1660}
1661
60f208d7
KP		 1662/*
1663 * on h/w without explicit sha224 support, we initialize h/w context
1664 * manually with sha224 constants, and tell it to run sha256.
1665 */
1666static int ahash_init_sha224_swinit(struct ahash_request *areq)
1667{
1668 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1669
1670 ahash_init(areq);
1671 req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1672
a752447a
KP		 1673 req_ctx->hw_context[0] = SHA224_H0;
1674 req_ctx->hw_context[1] = SHA224_H1;
1675 req_ctx->hw_context[2] = SHA224_H2;
1676 req_ctx->hw_context[3] = SHA224_H3;
1677 req_ctx->hw_context[4] = SHA224_H4;
1678 req_ctx->hw_context[5] = SHA224_H5;
1679 req_ctx->hw_context[6] = SHA224_H6;
1680 req_ctx->hw_context[7] = SHA224_H7;
60f208d7
KP		 1681
1682 /* init 64-bit count */
1683 req_ctx->hw_context[8] = 0;
1684 req_ctx->hw_context[9] = 0;
1685
1686 return 0;
1687}
1688
497f2e6b
LN		 1689static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1690{
1691 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1692 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1693 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1694 struct talitos_edesc *edesc;
1695 unsigned int blocksize =
1696 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1697 unsigned int nbytes_to_hash;
1698 unsigned int to_hash_later;
5e833bc4 1699 unsigned int nsg;
2a1cfe46 1700 bool chained;
497f2e6b 1701
5e833bc4
LN		 1702 if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1703 /* Buffer up to one whole block */
497f2e6b
LN		 1704 sg_copy_to_buffer(areq->src,
1705 sg_count(areq->src, nbytes, &chained),
5e833bc4
LN		 1706 req_ctx->buf + req_ctx->nbuf, nbytes);
1707 req_ctx->nbuf += nbytes;
497f2e6b
LN		 1708 return 0;
1709 }
1710
5e833bc4
LN		 1711 /* At least (blocksize + 1) bytes are available to hash */
1712 nbytes_to_hash = nbytes + req_ctx->nbuf;
1713 to_hash_later = nbytes_to_hash & (blocksize - 1);
1714
1715 if (req_ctx->last)
1716 to_hash_later = 0;
1717 else if (to_hash_later)
1718 /* There is a partial block. Hash the full block(s) now */
1719 nbytes_to_hash -= to_hash_later;
1720 else {
1721 /* Keep one block buffered */
1722 nbytes_to_hash -= blocksize;
1723 to_hash_later = blocksize;
1724 }
1725
1726 /* Chain in any previously buffered data */
1727 if (req_ctx->nbuf) {
1728 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1729 sg_init_table(req_ctx->bufsl, nsg);
1730 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1731 if (nsg > 1)
1732 scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
497f2e6b 1733 req_ctx->psrc = req_ctx->bufsl;
5e833bc4 1734 } else
497f2e6b 1735 req_ctx->psrc = areq->src;
5e833bc4
LN		 1736
1737 if (to_hash_later) {
1738 int nents = sg_count(areq->src, nbytes, &chained);
d0525723 1739 sg_pcopy_to_buffer(areq->src, nents,
5e833bc4
LN		 1740 req_ctx->bufnext,
1741 to_hash_later,
1742 nbytes - to_hash_later);
497f2e6b 1743 }
5e833bc4 1744 req_ctx->to_hash_later = to_hash_later;
497f2e6b 1745
5e833bc4 1746 /* Allocate extended descriptor */
497f2e6b
LN		 1747 edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1748 if (IS_ERR(edesc))
1749 return PTR_ERR(edesc);
1750
1751 edesc->desc.hdr = ctx->desc_hdr_template;
1752
1753 /* On last one, request SEC to pad; otherwise continue */
1754 if (req_ctx->last)
1755 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1756 else
1757 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1758
60f208d7
KP		 1759 /* request SEC to INIT hash. */
1760 if (req_ctx->first && !req_ctx->swinit)
497f2e6b
LN		 1761 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1762
1763 /* When the tfm context has a keylen, it's an HMAC.
1764 * A first or last (ie. not middle) descriptor must request HMAC.
1765 */
1766 if (ctx->keylen && (req_ctx->first || req_ctx->last))
1767 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1768
1769 return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1770 ahash_done);
1771}
1772
1773static int ahash_update(struct ahash_request *areq)
1774{
1775 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1776
1777 req_ctx->last = 0;
1778
1779 return ahash_process_req(areq, areq->nbytes);
1780}
1781
1782static int ahash_final(struct ahash_request *areq)
1783{
1784 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1785
1786 req_ctx->last = 1;
1787
1788 return ahash_process_req(areq, 0);
1789}
1790
1791static int ahash_finup(struct ahash_request *areq)
1792{
1793 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1794
1795 req_ctx->last = 1;
1796
1797 return ahash_process_req(areq, areq->nbytes);
1798}
1799
1800static int ahash_digest(struct ahash_request *areq)
1801{
1802 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
60f208d7 1803 struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
497f2e6b 1804
60f208d7 1805 ahash->init(areq);
497f2e6b
LN		 1806 req_ctx->last = 1;
1807
1808 return ahash_process_req(areq, areq->nbytes);
1809}
1810
79b3a418
LN		 1811struct keyhash_result {
1812 struct completion completion;
1813 int err;
1814};
1815
1816static void keyhash_complete(struct crypto_async_request *req, int err)
1817{
1818 struct keyhash_result *res = req->data;
1819
1820 if (err == -EINPROGRESS)
1821 return;
1822
1823 res->err = err;
1824 complete(&res->completion);
1825}
1826
1827static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1828 u8 *hash)
1829{
1830 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1831
1832 struct scatterlist sg[1];
1833 struct ahash_request *req;
1834 struct keyhash_result hresult;
1835 int ret;
1836
1837 init_completion(&hresult.completion);
1838
1839 req = ahash_request_alloc(tfm, GFP_KERNEL);
1840 if (!req)
1841 return -ENOMEM;
1842
1843 /* Keep tfm keylen == 0 during hash of the long key */
1844 ctx->keylen = 0;
1845 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1846 keyhash_complete, &hresult);
1847
1848 sg_init_one(&sg[0], key, keylen);
1849
1850 ahash_request_set_crypt(req, sg, hash, keylen);
1851 ret = crypto_ahash_digest(req);
1852 switch (ret) {
1853 case 0:
1854 break;
1855 case -EINPROGRESS:
1856 case -EBUSY:
1857 ret = wait_for_completion_interruptible(
1858 &hresult.completion);
1859 if (!ret)
1860 ret = hresult.err;
1861 break;
1862 default:
1863 break;
1864 }
1865 ahash_request_free(req);
1866
1867 return ret;
1868}
1869
1870static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1871 unsigned int keylen)
1872{
1873 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1874 unsigned int blocksize =
1875 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1876 unsigned int digestsize = crypto_ahash_digestsize(tfm);
1877 unsigned int keysize = keylen;
1878 u8 hash[SHA512_DIGEST_SIZE];
1879 int ret;
1880
1881 if (keylen <= blocksize)
1882 memcpy(ctx->key, key, keysize);
1883 else {
1884 /* Must get the hash of the long key */
1885 ret = keyhash(tfm, key, keylen, hash);
1886
1887 if (ret) {
1888 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1889 return -EINVAL;
1890 }
1891
1892 keysize = digestsize;
1893 memcpy(ctx->key, hash, digestsize);
1894 }
1895
1896 ctx->keylen = keysize;
1897
1898 return 0;
1899}
1900
1901
9c4a7965 1902struct talitos_alg_template {
d5e4aaef
LN		 1903 u32 type;
1904 union {
1905 struct crypto_alg crypto;
acbf7c62 1906 struct ahash_alg hash;
d5e4aaef 1907 } alg;
9c4a7965
KP		 1908 __be32 desc_hdr_template;
1909};
1910
1911static struct talitos_alg_template driver_algs[] = {
991155ba 1912 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
d5e4aaef
LN		 1913 { .type = CRYPTO_ALG_TYPE_AEAD,
1914 .alg.crypto = {
56af8cd4
LN		 1915 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1916 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1917 .cra_blocksize = AES_BLOCK_SIZE,
1918 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 1919 .cra_aead = {
56af8cd4
LN		 1920 .ivsize = AES_BLOCK_SIZE,
1921 .maxauthsize = SHA1_DIGEST_SIZE,
1922 }
1923 },
9c4a7965
KP		 1924 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1925 DESC_HDR_SEL0_AESU |
1926 DESC_HDR_MODE0_AESU_CBC |
1927 DESC_HDR_SEL1_MDEUA |
1928 DESC_HDR_MODE1_MDEU_INIT |
1929 DESC_HDR_MODE1_MDEU_PAD |
1930 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
70bcaca7 1931 },
d5e4aaef
LN		 1932 { .type = CRYPTO_ALG_TYPE_AEAD,
1933 .alg.crypto = {
56af8cd4
LN		 1934 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1935 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1936 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1937 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 1938 .cra_aead = {
56af8cd4
LN		 1939 .ivsize = DES3_EDE_BLOCK_SIZE,
1940 .maxauthsize = SHA1_DIGEST_SIZE,
1941 }
1942 },
70bcaca7
LN		 1943 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1944 DESC_HDR_SEL0_DEU |
1945 DESC_HDR_MODE0_DEU_CBC |
1946 DESC_HDR_MODE0_DEU_3DES |
1947 DESC_HDR_SEL1_MDEUA |
1948 DESC_HDR_MODE1_MDEU_INIT |
1949 DESC_HDR_MODE1_MDEU_PAD |
1950 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
3952f17e 1951 },
357fb605
HG		 1952 { .type = CRYPTO_ALG_TYPE_AEAD,
1953 .alg.crypto = {
1954 .cra_name = "authenc(hmac(sha224),cbc(aes))",
1955 .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
1956 .cra_blocksize = AES_BLOCK_SIZE,
1957 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 1958 .cra_aead = {
357fb605
HG		 1959 .ivsize = AES_BLOCK_SIZE,
1960 .maxauthsize = SHA224_DIGEST_SIZE,
1961 }
1962 },
1963 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1964 DESC_HDR_SEL0_AESU |
1965 DESC_HDR_MODE0_AESU_CBC |
1966 DESC_HDR_SEL1_MDEUA |
1967 DESC_HDR_MODE1_MDEU_INIT |
1968 DESC_HDR_MODE1_MDEU_PAD |
1969 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1970 },
1971 { .type = CRYPTO_ALG_TYPE_AEAD,
1972 .alg.crypto = {
1973 .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
1974 .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
1975 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1976 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 1977 .cra_aead = {
357fb605
HG		 1978 .ivsize = DES3_EDE_BLOCK_SIZE,
1979 .maxauthsize = SHA224_DIGEST_SIZE,
1980 }
1981 },
1982 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1983 DESC_HDR_SEL0_DEU |
1984 DESC_HDR_MODE0_DEU_CBC |
1985 DESC_HDR_MODE0_DEU_3DES |
1986 DESC_HDR_SEL1_MDEUA |
1987 DESC_HDR_MODE1_MDEU_INIT |
1988 DESC_HDR_MODE1_MDEU_PAD |
1989 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1990 },
d5e4aaef
LN		 1991 { .type = CRYPTO_ALG_TYPE_AEAD,
1992 .alg.crypto = {
56af8cd4
LN		 1993 .cra_name = "authenc(hmac(sha256),cbc(aes))",
1994 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1995 .cra_blocksize = AES_BLOCK_SIZE,
1996 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 1997 .cra_aead = {
56af8cd4
LN		 1998 .ivsize = AES_BLOCK_SIZE,
1999 .maxauthsize = SHA256_DIGEST_SIZE,
2000 }
2001 },
3952f17e
LN		 2002 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2003 DESC_HDR_SEL0_AESU |
2004 DESC_HDR_MODE0_AESU_CBC |
2005 DESC_HDR_SEL1_MDEUA |
2006 DESC_HDR_MODE1_MDEU_INIT |
2007 DESC_HDR_MODE1_MDEU_PAD |
2008 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2009 },
d5e4aaef
LN		 2010 { .type = CRYPTO_ALG_TYPE_AEAD,
2011 .alg.crypto = {
56af8cd4
LN		 2012 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2013 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2014 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2015 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2016 .cra_aead = {
56af8cd4
LN		 2017 .ivsize = DES3_EDE_BLOCK_SIZE,
2018 .maxauthsize = SHA256_DIGEST_SIZE,
2019 }
2020 },
3952f17e
LN		 2021 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2022 DESC_HDR_SEL0_DEU |
2023 DESC_HDR_MODE0_DEU_CBC |
2024 DESC_HDR_MODE0_DEU_3DES |
2025 DESC_HDR_SEL1_MDEUA |
2026 DESC_HDR_MODE1_MDEU_INIT |
2027 DESC_HDR_MODE1_MDEU_PAD |
2028 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2029 },
d5e4aaef 2030 { .type = CRYPTO_ALG_TYPE_AEAD,
357fb605
HG		 2031 .alg.crypto = {
2032 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2033 .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2034 .cra_blocksize = AES_BLOCK_SIZE,
2035 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2036 .cra_aead = {
357fb605
HG		 2037 .ivsize = AES_BLOCK_SIZE,
2038 .maxauthsize = SHA384_DIGEST_SIZE,
2039 }
2040 },
2041 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2042 DESC_HDR_SEL0_AESU |
2043 DESC_HDR_MODE0_AESU_CBC |
2044 DESC_HDR_SEL1_MDEUB |
2045 DESC_HDR_MODE1_MDEU_INIT |
2046 DESC_HDR_MODE1_MDEU_PAD |
2047 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2048 },
2049 { .type = CRYPTO_ALG_TYPE_AEAD,
2050 .alg.crypto = {
2051 .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2052 .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2053 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2054 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2055 .cra_aead = {
357fb605
HG		 2056 .ivsize = DES3_EDE_BLOCK_SIZE,
2057 .maxauthsize = SHA384_DIGEST_SIZE,
2058 }
2059 },
2060 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2061 DESC_HDR_SEL0_DEU |
2062 DESC_HDR_MODE0_DEU_CBC |
2063 DESC_HDR_MODE0_DEU_3DES |
2064 DESC_HDR_SEL1_MDEUB |
2065 DESC_HDR_MODE1_MDEU_INIT |
2066 DESC_HDR_MODE1_MDEU_PAD |
2067 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2068 },
2069 { .type = CRYPTO_ALG_TYPE_AEAD,
2070 .alg.crypto = {
2071 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2072 .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2073 .cra_blocksize = AES_BLOCK_SIZE,
2074 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2075 .cra_aead = {
357fb605
HG		 2076 .ivsize = AES_BLOCK_SIZE,
2077 .maxauthsize = SHA512_DIGEST_SIZE,
2078 }
2079 },
2080 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2081 DESC_HDR_SEL0_AESU |
2082 DESC_HDR_MODE0_AESU_CBC |
2083 DESC_HDR_SEL1_MDEUB |
2084 DESC_HDR_MODE1_MDEU_INIT |
2085 DESC_HDR_MODE1_MDEU_PAD |
2086 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2087 },
2088 { .type = CRYPTO_ALG_TYPE_AEAD,
2089 .alg.crypto = {
2090 .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2091 .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2092 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2093 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2094 .cra_aead = {
357fb605
HG		 2095 .ivsize = DES3_EDE_BLOCK_SIZE,
2096 .maxauthsize = SHA512_DIGEST_SIZE,
2097 }
2098 },
2099 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2100 DESC_HDR_SEL0_DEU |
2101 DESC_HDR_MODE0_DEU_CBC |
2102 DESC_HDR_MODE0_DEU_3DES |
2103 DESC_HDR_SEL1_MDEUB |
2104 DESC_HDR_MODE1_MDEU_INIT |
2105 DESC_HDR_MODE1_MDEU_PAD |
2106 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2107 },
2108 { .type = CRYPTO_ALG_TYPE_AEAD,
d5e4aaef 2109 .alg.crypto = {
56af8cd4
LN		 2110 .cra_name = "authenc(hmac(md5),cbc(aes))",
2111 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2112 .cra_blocksize = AES_BLOCK_SIZE,
2113 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2114 .cra_aead = {
56af8cd4
LN		 2115 .ivsize = AES_BLOCK_SIZE,
2116 .maxauthsize = MD5_DIGEST_SIZE,
2117 }
2118 },
3952f17e
LN		 2119 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2120 DESC_HDR_SEL0_AESU |
2121 DESC_HDR_MODE0_AESU_CBC |
2122 DESC_HDR_SEL1_MDEUA |
2123 DESC_HDR_MODE1_MDEU_INIT |
2124 DESC_HDR_MODE1_MDEU_PAD |
2125 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2126 },
d5e4aaef
LN		 2127 { .type = CRYPTO_ALG_TYPE_AEAD,
2128 .alg.crypto = {
56af8cd4
LN		 2129 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2130 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2131 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2132 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2133 .cra_aead = {
56af8cd4
LN		 2134 .ivsize = DES3_EDE_BLOCK_SIZE,
2135 .maxauthsize = MD5_DIGEST_SIZE,
2136 }
2137 },
3952f17e
LN		 2138 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2139 DESC_HDR_SEL0_DEU |
2140 DESC_HDR_MODE0_DEU_CBC |
2141 DESC_HDR_MODE0_DEU_3DES |
2142 DESC_HDR_SEL1_MDEUA |
2143 DESC_HDR_MODE1_MDEU_INIT |
2144 DESC_HDR_MODE1_MDEU_PAD |
2145 DESC_HDR_MODE1_MDEU_MD5_HMAC,
4de9d0b5
LN		 2146 },
2147 /* ABLKCIPHER algorithms. */
d5e4aaef
LN		 2148 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2149 .alg.crypto = {
4de9d0b5
LN		 2150 .cra_name = "cbc(aes)",
2151 .cra_driver_name = "cbc-aes-talitos",
2152 .cra_blocksize = AES_BLOCK_SIZE,
2153 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2154 CRYPTO_ALG_ASYNC,
4de9d0b5 2155 .cra_ablkcipher = {
4de9d0b5
LN		 2156 .min_keysize = AES_MIN_KEY_SIZE,
2157 .max_keysize = AES_MAX_KEY_SIZE,
2158 .ivsize = AES_BLOCK_SIZE,
2159 }
2160 },
2161 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2162 DESC_HDR_SEL0_AESU |
2163 DESC_HDR_MODE0_AESU_CBC,
2164 },
d5e4aaef
LN		 2165 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2166 .alg.crypto = {
4de9d0b5
LN		 2167 .cra_name = "cbc(des3_ede)",
2168 .cra_driver_name = "cbc-3des-talitos",
2169 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2170 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2171 CRYPTO_ALG_ASYNC,
4de9d0b5 2172 .cra_ablkcipher = {
4de9d0b5
LN		 2173 .min_keysize = DES3_EDE_KEY_SIZE,
2174 .max_keysize = DES3_EDE_KEY_SIZE,
2175 .ivsize = DES3_EDE_BLOCK_SIZE,
2176 }
2177 },
2178 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2179 DESC_HDR_SEL0_DEU |
2180 DESC_HDR_MODE0_DEU_CBC |
2181 DESC_HDR_MODE0_DEU_3DES,
497f2e6b
LN		 2182 },
2183 /* AHASH algorithms. */
2184 { .type = CRYPTO_ALG_TYPE_AHASH,
2185 .alg.hash = {
497f2e6b
LN		 2186 .halg.digestsize = MD5_DIGEST_SIZE,
2187 .halg.base = {
2188 .cra_name = "md5",
2189 .cra_driver_name = "md5-talitos",
2190 .cra_blocksize = MD5_BLOCK_SIZE,
2191 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2192 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2193 }
2194 },
2195 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2196 DESC_HDR_SEL0_MDEUA |
2197 DESC_HDR_MODE0_MDEU_MD5,
2198 },
2199 { .type = CRYPTO_ALG_TYPE_AHASH,
2200 .alg.hash = {
497f2e6b
LN		 2201 .halg.digestsize = SHA1_DIGEST_SIZE,
2202 .halg.base = {
2203 .cra_name = "sha1",
2204 .cra_driver_name = "sha1-talitos",
2205 .cra_blocksize = SHA1_BLOCK_SIZE,
2206 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2207 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2208 }
2209 },
2210 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2211 DESC_HDR_SEL0_MDEUA |
2212 DESC_HDR_MODE0_MDEU_SHA1,
2213 },
60f208d7
KP		 2214 { .type = CRYPTO_ALG_TYPE_AHASH,
2215 .alg.hash = {
60f208d7
KP		 2216 .halg.digestsize = SHA224_DIGEST_SIZE,
2217 .halg.base = {
2218 .cra_name = "sha224",
2219 .cra_driver_name = "sha224-talitos",
2220 .cra_blocksize = SHA224_BLOCK_SIZE,
2221 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2222 CRYPTO_ALG_ASYNC,
60f208d7
KP		 2223 }
2224 },
2225 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2226 DESC_HDR_SEL0_MDEUA |
2227 DESC_HDR_MODE0_MDEU_SHA224,
2228 },
497f2e6b
LN		 2229 { .type = CRYPTO_ALG_TYPE_AHASH,
2230 .alg.hash = {
497f2e6b
LN		 2231 .halg.digestsize = SHA256_DIGEST_SIZE,
2232 .halg.base = {
2233 .cra_name = "sha256",
2234 .cra_driver_name = "sha256-talitos",
2235 .cra_blocksize = SHA256_BLOCK_SIZE,
2236 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2237 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2238 }
2239 },
2240 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2241 DESC_HDR_SEL0_MDEUA |
2242 DESC_HDR_MODE0_MDEU_SHA256,
2243 },
2244 { .type = CRYPTO_ALG_TYPE_AHASH,
2245 .alg.hash = {
497f2e6b
LN		 2246 .halg.digestsize = SHA384_DIGEST_SIZE,
2247 .halg.base = {
2248 .cra_name = "sha384",
2249 .cra_driver_name = "sha384-talitos",
2250 .cra_blocksize = SHA384_BLOCK_SIZE,
2251 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2252 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2253 }
2254 },
2255 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2256 DESC_HDR_SEL0_MDEUB |
2257 DESC_HDR_MODE0_MDEUB_SHA384,
2258 },
2259 { .type = CRYPTO_ALG_TYPE_AHASH,
2260 .alg.hash = {
497f2e6b
LN		 2261 .halg.digestsize = SHA512_DIGEST_SIZE,
2262 .halg.base = {
2263 .cra_name = "sha512",
2264 .cra_driver_name = "sha512-talitos",
2265 .cra_blocksize = SHA512_BLOCK_SIZE,
2266 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2267 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2268 }
2269 },
2270 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2271 DESC_HDR_SEL0_MDEUB |
2272 DESC_HDR_MODE0_MDEUB_SHA512,
2273 },
79b3a418
LN		 2274 { .type = CRYPTO_ALG_TYPE_AHASH,
2275 .alg.hash = {
79b3a418
LN		 2276 .halg.digestsize = MD5_DIGEST_SIZE,
2277 .halg.base = {
2278 .cra_name = "hmac(md5)",
2279 .cra_driver_name = "hmac-md5-talitos",
2280 .cra_blocksize = MD5_BLOCK_SIZE,
2281 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2282 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2283 }
2284 },
2285 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2286 DESC_HDR_SEL0_MDEUA |
2287 DESC_HDR_MODE0_MDEU_MD5,
2288 },
2289 { .type = CRYPTO_ALG_TYPE_AHASH,
2290 .alg.hash = {
79b3a418
LN		 2291 .halg.digestsize = SHA1_DIGEST_SIZE,
2292 .halg.base = {
2293 .cra_name = "hmac(sha1)",
2294 .cra_driver_name = "hmac-sha1-talitos",
2295 .cra_blocksize = SHA1_BLOCK_SIZE,
2296 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2297 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2298 }
2299 },
2300 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2301 DESC_HDR_SEL0_MDEUA |
2302 DESC_HDR_MODE0_MDEU_SHA1,
2303 },
2304 { .type = CRYPTO_ALG_TYPE_AHASH,
2305 .alg.hash = {
79b3a418
LN		 2306 .halg.digestsize = SHA224_DIGEST_SIZE,
2307 .halg.base = {
2308 .cra_name = "hmac(sha224)",
2309 .cra_driver_name = "hmac-sha224-talitos",
2310 .cra_blocksize = SHA224_BLOCK_SIZE,
2311 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2312 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2313 }
2314 },
2315 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2316 DESC_HDR_SEL0_MDEUA |
2317 DESC_HDR_MODE0_MDEU_SHA224,
2318 },
2319 { .type = CRYPTO_ALG_TYPE_AHASH,
2320 .alg.hash = {
79b3a418
LN		 2321 .halg.digestsize = SHA256_DIGEST_SIZE,
2322 .halg.base = {
2323 .cra_name = "hmac(sha256)",
2324 .cra_driver_name = "hmac-sha256-talitos",
2325 .cra_blocksize = SHA256_BLOCK_SIZE,
2326 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2327 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2328 }
2329 },
2330 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2331 DESC_HDR_SEL0_MDEUA |
2332 DESC_HDR_MODE0_MDEU_SHA256,
2333 },
2334 { .type = CRYPTO_ALG_TYPE_AHASH,
2335 .alg.hash = {
79b3a418
LN		 2336 .halg.digestsize = SHA384_DIGEST_SIZE,
2337 .halg.base = {
2338 .cra_name = "hmac(sha384)",
2339 .cra_driver_name = "hmac-sha384-talitos",
2340 .cra_blocksize = SHA384_BLOCK_SIZE,
2341 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2342 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2343 }
2344 },
2345 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2346 DESC_HDR_SEL0_MDEUB |
2347 DESC_HDR_MODE0_MDEUB_SHA384,
2348 },
2349 { .type = CRYPTO_ALG_TYPE_AHASH,
2350 .alg.hash = {
79b3a418
LN		 2351 .halg.digestsize = SHA512_DIGEST_SIZE,
2352 .halg.base = {
2353 .cra_name = "hmac(sha512)",
2354 .cra_driver_name = "hmac-sha512-talitos",
2355 .cra_blocksize = SHA512_BLOCK_SIZE,
2356 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2357 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2358 }
2359 },
2360 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2361 DESC_HDR_SEL0_MDEUB |
2362 DESC_HDR_MODE0_MDEUB_SHA512,
2363 }
9c4a7965
KP		 2364};
2365
2366struct talitos_crypto_alg {
2367 struct list_head entry;
2368 struct device *dev;
acbf7c62 2369 struct talitos_alg_template algt;
9c4a7965
KP		 2370};
2371
2372static int talitos_cra_init(struct crypto_tfm *tfm)
2373{
2374 struct crypto_alg *alg = tfm->__crt_alg;
19bbbc63 2375 struct talitos_crypto_alg *talitos_alg;
9c4a7965 2376 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
5228f0f7 2377 struct talitos_private *priv;
9c4a7965 2378
497f2e6b
LN		 2379 if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2380 talitos_alg = container_of(__crypto_ahash_alg(alg),
2381 struct talitos_crypto_alg,
2382 algt.alg.hash);
2383 else
2384 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2385 algt.alg.crypto);
19bbbc63 2386
9c4a7965
KP		 2387 /* update context with ptr to dev */
2388 ctx->dev = talitos_alg->dev;
19bbbc63 2389
5228f0f7
KP		 2390 /* assign SEC channel to tfm in round-robin fashion */
2391 priv = dev_get_drvdata(ctx->dev);
2392 ctx->ch = atomic_inc_return(&priv->last_chan) &
2393 (priv->num_channels - 1);
2394
9c4a7965 2395 /* copy descriptor header template value */
acbf7c62 2396 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
9c4a7965 2397
602dba5a
KP		 2398 /* select done notification */
2399 ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2400
497f2e6b
LN		 2401 return 0;
2402}
2403
2404static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2405{
2406 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2407
2408 talitos_cra_init(tfm);
9c4a7965
KP		 2409
2410 /* random first IV */
70bcaca7 2411 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
9c4a7965
KP		 2412
2413 return 0;
2414}
2415
497f2e6b
LN		 2416static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2417{
2418 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2419
2420 talitos_cra_init(tfm);
2421
2422 ctx->keylen = 0;
2423 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2424 sizeof(struct talitos_ahash_req_ctx));
2425
2426 return 0;
2427}
2428
9c4a7965
KP		 2429/*
2430 * given the alg's descriptor header template, determine whether descriptor
2431 * type and primary/secondary execution units required match the hw
2432 * capabilities description provided in the device tree node.
2433 */
2434static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2435{
2436 struct talitos_private *priv = dev_get_drvdata(dev);
2437 int ret;
2438
2439 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2440 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2441
2442 if (SECONDARY_EU(desc_hdr_template))
2443 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2444 & priv->exec_units);
2445
2446 return ret;
2447}
2448
2dc11581 2449static int talitos_remove(struct platform_device *ofdev)
9c4a7965
KP		 2450{
2451 struct device *dev = &ofdev->dev;
2452 struct talitos_private *priv = dev_get_drvdata(dev);
2453 struct talitos_crypto_alg *t_alg, *n;
2454 int i;
2455
2456 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
acbf7c62
LN		 2457 switch (t_alg->algt.type) {
2458 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2459 case CRYPTO_ALG_TYPE_AEAD:
2460 crypto_unregister_alg(&t_alg->algt.alg.crypto);
2461 break;
2462 case CRYPTO_ALG_TYPE_AHASH:
2463 crypto_unregister_ahash(&t_alg->algt.alg.hash);
2464 break;
2465 }
9c4a7965
KP		 2466 list_del(&t_alg->entry);
2467 kfree(t_alg);
2468 }
2469
2470 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2471 talitos_unregister_rng(dev);
2472
4b992628 2473 for (i = 0; i < priv->num_channels; i++)
0b798247 2474 kfree(priv->chan[i].fifo);
9c4a7965 2475
4b992628 2476 kfree(priv->chan);
9c4a7965 2477
c3e337f8 2478 for (i = 0; i < 2; i++)
2cdba3cf 2479 if (priv->irq[i]) {
c3e337f8
KP		 2480 free_irq(priv->irq[i], dev);
2481 irq_dispose_mapping(priv->irq[i]);
2482 }
9c4a7965 2483
c3e337f8 2484 tasklet_kill(&priv->done_task[0]);
2cdba3cf 2485 if (priv->irq[1])
c3e337f8 2486 tasklet_kill(&priv->done_task[1]);
9c4a7965
KP		 2487
2488 iounmap(priv->reg);
2489
2490 dev_set_drvdata(dev, NULL);
2491
2492 kfree(priv);
2493
2494 return 0;
2495}
2496
2497static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2498 struct talitos_alg_template
2499 *template)
2500{
60f208d7 2501 struct talitos_private *priv = dev_get_drvdata(dev);
9c4a7965
KP		 2502 struct talitos_crypto_alg *t_alg;
2503 struct crypto_alg *alg;
2504
2505 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2506 if (!t_alg)
2507 return ERR_PTR(-ENOMEM);
2508
acbf7c62
LN		 2509 t_alg->algt = *template;
2510
2511 switch (t_alg->algt.type) {
2512 case CRYPTO_ALG_TYPE_ABLKCIPHER:
497f2e6b
LN		 2513 alg = &t_alg->algt.alg.crypto;
2514 alg->cra_init = talitos_cra_init;
d4cd3283 2515 alg->cra_type = &crypto_ablkcipher_type;
b286e003
KP		 2516 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2517 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2518 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2519 alg->cra_ablkcipher.geniv = "eseqiv";
497f2e6b 2520 break;
acbf7c62
LN		 2521 case CRYPTO_ALG_TYPE_AEAD:
2522 alg = &t_alg->algt.alg.crypto;
497f2e6b 2523 alg->cra_init = talitos_cra_init_aead;
d4cd3283 2524 alg->cra_type = &crypto_aead_type;
b286e003
KP		 2525 alg->cra_aead.setkey = aead_setkey;
2526 alg->cra_aead.setauthsize = aead_setauthsize;
2527 alg->cra_aead.encrypt = aead_encrypt;
2528 alg->cra_aead.decrypt = aead_decrypt;
2529 alg->cra_aead.givencrypt = aead_givencrypt;
2530 alg->cra_aead.geniv = "<built-in>";
acbf7c62
LN		 2531 break;
2532 case CRYPTO_ALG_TYPE_AHASH:
2533 alg = &t_alg->algt.alg.hash.halg.base;
497f2e6b 2534 alg->cra_init = talitos_cra_init_ahash;
d4cd3283 2535 alg->cra_type = &crypto_ahash_type;
b286e003
KP		 2536 t_alg->algt.alg.hash.init = ahash_init;
2537 t_alg->algt.alg.hash.update = ahash_update;
2538 t_alg->algt.alg.hash.final = ahash_final;
2539 t_alg->algt.alg.hash.finup = ahash_finup;
2540 t_alg->algt.alg.hash.digest = ahash_digest;
2541 t_alg->algt.alg.hash.setkey = ahash_setkey;
2542
79b3a418 2543 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
0b2730d8
KP		 2544 !strncmp(alg->cra_name, "hmac", 4)) {
2545 kfree(t_alg);
79b3a418 2546 return ERR_PTR(-ENOTSUPP);
0b2730d8 2547 }
60f208d7 2548 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
79b3a418
LN		 2549 (!strcmp(alg->cra_name, "sha224") ||
2550 !strcmp(alg->cra_name, "hmac(sha224)"))) {
60f208d7
KP		 2551 t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2552 t_alg->algt.desc_hdr_template =
2553 DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2554 DESC_HDR_SEL0_MDEUA |
2555 DESC_HDR_MODE0_MDEU_SHA256;
2556 }
497f2e6b 2557 break;
1d11911a
KP		 2558 default:
2559 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2560 return ERR_PTR(-EINVAL);
acbf7c62 2561 }
9c4a7965 2562
9c4a7965 2563 alg->cra_module = THIS_MODULE;
9c4a7965 2564 alg->cra_priority = TALITOS_CRA_PRIORITY;
9c4a7965 2565 alg->cra_alignmask = 0;
9c4a7965 2566 alg->cra_ctxsize = sizeof(struct talitos_ctx);
d912bb76 2567 alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
9c4a7965 2568
9c4a7965
KP		 2569 t_alg->dev = dev;
2570
2571 return t_alg;
2572}
2573
c3e337f8
KP		 2574static int talitos_probe_irq(struct platform_device *ofdev)
2575{
2576 struct device *dev = &ofdev->dev;
2577 struct device_node *np = ofdev->dev.of_node;
2578 struct talitos_private *priv = dev_get_drvdata(dev);
2579 int err;
2580
2581 priv->irq[0] = irq_of_parse_and_map(np, 0);
2cdba3cf 2582 if (!priv->irq[0]) {
c3e337f8
KP		 2583 dev_err(dev, "failed to map irq\n");
2584 return -EINVAL;
2585 }
2586
2587 priv->irq[1] = irq_of_parse_and_map(np, 1);
2588
2589 /* get the primary irq line */
2cdba3cf 2590 if (!priv->irq[1]) {
c3e337f8
KP		 2591 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2592 dev_driver_string(dev), dev);
2593 goto primary_out;
2594 }
2595
2596 err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2597 dev_driver_string(dev), dev);
2598 if (err)
2599 goto primary_out;
2600
2601 /* get the secondary irq line */
2602 err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2603 dev_driver_string(dev), dev);
2604 if (err) {
2605 dev_err(dev, "failed to request secondary irq\n");
2606 irq_dispose_mapping(priv->irq[1]);
2cdba3cf 2607 priv->irq[1] = 0;
c3e337f8
KP		 2608 }
2609
2610 return err;
2611
2612primary_out:
2613 if (err) {
2614 dev_err(dev, "failed to request primary irq\n");
2615 irq_dispose_mapping(priv->irq[0]);
2cdba3cf 2616 priv->irq[0] = 0;
c3e337f8
KP		 2617 }
2618
2619 return err;
2620}
2621
1c48a5c9 2622static int talitos_probe(struct platform_device *ofdev)
9c4a7965
KP		 2623{
2624 struct device *dev = &ofdev->dev;
61c7a080 2625 struct device_node *np = ofdev->dev.of_node;
9c4a7965
KP		 2626 struct talitos_private *priv;
2627 const unsigned int *prop;
2628 int i, err;
2629
2630 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2631 if (!priv)
2632 return -ENOMEM;
2633
2634 dev_set_drvdata(dev, priv);
2635
2636 priv->ofdev = ofdev;
2637
511d63cb
HG		 2638 spin_lock_init(&priv->reg_lock);
2639
c3e337f8
KP		 2640 err = talitos_probe_irq(ofdev);
2641 if (err)
9c4a7965 2642 goto err_out;
9c4a7965 2643
2cdba3cf 2644 if (!priv->irq[1]) {
c3e337f8
KP		 2645 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2646 (unsigned long)dev);
2647 } else {
2648 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2649 (unsigned long)dev);
2650 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2651 (unsigned long)dev);
9c4a7965
KP		 2652 }
2653
c3e337f8
KP		 2654 INIT_LIST_HEAD(&priv->alg_list);
2655
9c4a7965
KP		 2656 priv->reg = of_iomap(np, 0);
2657 if (!priv->reg) {
2658 dev_err(dev, "failed to of_iomap\n");
2659 err = -ENOMEM;
2660 goto err_out;
2661 }
2662
2663 /* get SEC version capabilities from device tree */
2664 prop = of_get_property(np, "fsl,num-channels", NULL);
2665 if (prop)
2666 priv->num_channels = *prop;
2667
2668 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2669 if (prop)
2670 priv->chfifo_len = *prop;
2671
2672 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2673 if (prop)
2674 priv->exec_units = *prop;
2675
2676 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2677 if (prop)
2678 priv->desc_types = *prop;
2679
2680 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2681 !priv->exec_units || !priv->desc_types) {
2682 dev_err(dev, "invalid property data in device tree node\n");
2683 err = -EINVAL;
2684 goto err_out;
2685 }
2686
f3c85bc1
LN		 2687 if (of_device_is_compatible(np, "fsl,sec3.0"))
2688 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2689
fe5720e2 2690 if (of_device_is_compatible(np, "fsl,sec2.1"))
60f208d7 2691 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
79b3a418
LN		 2692 TALITOS_FTR_SHA224_HWINIT |
2693 TALITOS_FTR_HMAC_OK;
fe5720e2 2694
4b992628
KP		 2695 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2696 priv->num_channels, GFP_KERNEL);
2697 if (!priv->chan) {
2698 dev_err(dev, "failed to allocate channel management space\n");
9c4a7965
KP		 2699 err = -ENOMEM;
2700 goto err_out;
2701 }
2702
c3e337f8
KP		 2703 for (i = 0; i < priv->num_channels; i++) {
2704 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2cdba3cf 2705 if (!priv->irq[1] || !(i & 1))
c3e337f8
KP		 2706 priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2707 }
ad42d5fc 2708
9c4a7965 2709 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2710 spin_lock_init(&priv->chan[i].head_lock);
2711 spin_lock_init(&priv->chan[i].tail_lock);
9c4a7965
KP		 2712 }
2713
2714 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2715
2716 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2717 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2718 priv->fifo_len, GFP_KERNEL);
2719 if (!priv->chan[i].fifo) {
9c4a7965
KP		 2720 dev_err(dev, "failed to allocate request fifo %d\n", i);
2721 err = -ENOMEM;
2722 goto err_out;
2723 }
2724 }
2725
ec6644d6 2726 for (i = 0; i < priv->num_channels; i++)
4b992628
KP		 2727 atomic_set(&priv->chan[i].submit_count,
2728 -(priv->chfifo_len - 1));
9c4a7965 2729
81eb024c
KP		 2730 dma_set_mask(dev, DMA_BIT_MASK(36));
2731
9c4a7965
KP		 2732 /* reset and initialize the h/w */
2733 err = init_device(dev);
2734 if (err) {
2735 dev_err(dev, "failed to initialize device\n");
2736 goto err_out;
2737 }
2738
2739 /* register the RNG, if available */
2740 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2741 err = talitos_register_rng(dev);
2742 if (err) {
2743 dev_err(dev, "failed to register hwrng: %d\n", err);
2744 goto err_out;
2745 } else
2746 dev_info(dev, "hwrng\n");
2747 }
2748
2749 /* register crypto algorithms the device supports */
9c4a7965
KP		 2750 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2751 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2752 struct talitos_crypto_alg *t_alg;
acbf7c62 2753 char *name = NULL;
9c4a7965
KP		 2754
2755 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2756 if (IS_ERR(t_alg)) {
2757 err = PTR_ERR(t_alg);
0b2730d8 2758 if (err == -ENOTSUPP)
79b3a418 2759 continue;
9c4a7965
KP		 2760 goto err_out;
2761 }
2762
acbf7c62
LN		 2763 switch (t_alg->algt.type) {
2764 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2765 case CRYPTO_ALG_TYPE_AEAD:
2766 err = crypto_register_alg(
2767 &t_alg->algt.alg.crypto);
2768 name = t_alg->algt.alg.crypto.cra_driver_name;
2769 break;
2770 case CRYPTO_ALG_TYPE_AHASH:
2771 err = crypto_register_ahash(
2772 &t_alg->algt.alg.hash);
2773 name =
2774 t_alg->algt.alg.hash.halg.base.cra_driver_name;
2775 break;
2776 }
9c4a7965
KP		 2777 if (err) {
2778 dev_err(dev, "%s alg registration failed\n",
acbf7c62 2779 name);
9c4a7965 2780 kfree(t_alg);
991155ba 2781 } else
9c4a7965 2782 list_add_tail(&t_alg->entry, &priv->alg_list);
9c4a7965
KP		 2783 }
2784 }
5b859b6e
KP		 2785 if (!list_empty(&priv->alg_list))
2786 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2787 (char *)of_get_property(np, "compatible", NULL));
9c4a7965
KP		 2788
2789 return 0;
2790
2791err_out:
2792 talitos_remove(ofdev);
9c4a7965
KP		 2793
2794 return err;
2795}
2796
6c3f975a 2797static const struct of_device_id talitos_match[] = {
9c4a7965
KP		 2798 {
2799 .compatible = "fsl,sec2.0",
2800 },
2801 {},
2802};
2803MODULE_DEVICE_TABLE(of, talitos_match);
2804
1c48a5c9 2805static struct platform_driver talitos_driver = {
4018294b
GL		 2806 .driver = {
2807 .name = "talitos",
2808 .owner = THIS_MODULE,
2809 .of_match_table = talitos_match,
2810 },
9c4a7965 2811 .probe = talitos_probe,
596f1034 2812 .remove = talitos_remove,
9c4a7965
KP		 2813};
2814
741e8c2d 2815module_platform_driver(talitos_driver);
9c4a7965
KP		 2816
2817MODULE_LICENSE("GPL");
2818MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2819MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
Linux 6.x block layer and io_uring tree(s)