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crypto: talitos - ensure request ordering within a single tfm
[linux-2.6-block.git] / drivers / crypto / talitos.c
CommitLineData
9c4a7965
KP		 1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
5228f0f7 4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
9c4a7965
KP		 5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/crypto.h>
34#include <linux/hw_random.h>
35#include <linux/of_platform.h>
36#include <linux/dma-mapping.h>
37#include <linux/io.h>
38#include <linux/spinlock.h>
39#include <linux/rtnetlink.h>
5a0e3ad6 40#include <linux/slab.h>
9c4a7965
KP		 41
42#include <crypto/algapi.h>
43#include <crypto/aes.h>
3952f17e 44#include <crypto/des.h>
9c4a7965 45#include <crypto/sha.h>
497f2e6b 46#include <crypto/md5.h>
9c4a7965
KP		 47#include <crypto/aead.h>
48#include <crypto/authenc.h>
4de9d0b5 49#include <crypto/skcipher.h>
acbf7c62
LN		 50#include <crypto/hash.h>
51#include <crypto/internal/hash.h>
4de9d0b5 52#include <crypto/scatterwalk.h>
9c4a7965
KP		 53
54#include "talitos.h"
55
56#define TALITOS_TIMEOUT 100000
57#define TALITOS_MAX_DATA_LEN 65535
58
59#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
60#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
61#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
62
63/* descriptor pointer entry */
64struct talitos_ptr {
65 __be16 len; /* length */
66 u8 j_extent; /* jump to sg link table and/or extent */
67 u8 eptr; /* extended address */
68 __be32 ptr; /* address */
69};
70
497f2e6b
LN		 71static const struct talitos_ptr zero_entry = {
72 .len = 0,
73 .j_extent = 0,
74 .eptr = 0,
75 .ptr = 0
76};
77
9c4a7965
KP		 78/* descriptor */
79struct talitos_desc {
80 __be32 hdr; /* header high bits */
81 __be32 hdr_lo; /* header low bits */
82 struct talitos_ptr ptr[7]; /* ptr/len pair array */
83};
84
85/**
86 * talitos_request - descriptor submission request
87 * @desc: descriptor pointer (kernel virtual)
88 * @dma_desc: descriptor's physical bus address
89 * @callback: whom to call when descriptor processing is done
90 * @context: caller context (optional)
91 */
92struct talitos_request {
93 struct talitos_desc *desc;
94 dma_addr_t dma_desc;
95 void (*callback) (struct device *dev, struct talitos_desc *desc,
96 void *context, int error);
97 void *context;
98};
99
4b992628
KP		 100/* per-channel fifo management */
101struct talitos_channel {
102 /* request fifo */
103 struct talitos_request *fifo;
104
105 /* number of requests pending in channel h/w fifo */
106 atomic_t submit_count ____cacheline_aligned;
107
108 /* request submission (head) lock */
109 spinlock_t head_lock ____cacheline_aligned;
110 /* index to next free descriptor request */
111 int head;
112
113 /* request release (tail) lock */
114 spinlock_t tail_lock ____cacheline_aligned;
115 /* index to next in-progress/done descriptor request */
116 int tail;
117};
118
9c4a7965
KP		 119struct talitos_private {
120 struct device *dev;
2dc11581 121 struct platform_device *ofdev;
9c4a7965
KP		 122 void __iomem *reg;
123 int irq;
124
125 /* SEC version geometry (from device tree node) */
126 unsigned int num_channels;
127 unsigned int chfifo_len;
128 unsigned int exec_units;
129 unsigned int desc_types;
130
f3c85bc1
LN		 131 /* SEC Compatibility info */
132 unsigned long features;
133
9c4a7965
KP		 134 /*
135 * length of the request fifo
136 * fifo_len is chfifo_len rounded up to next power of 2
137 * so we can use bitwise ops to wrap
138 */
139 unsigned int fifo_len;
140
4b992628 141 struct talitos_channel *chan;
9c4a7965 142
4b992628
KP		 143 /* next channel to be assigned next incoming descriptor */
144 atomic_t last_chan ____cacheline_aligned;
9c4a7965
KP		 145
146 /* request callback tasklet */
147 struct tasklet_struct done_task;
9c4a7965
KP		 148
149 /* list of registered algorithms */
150 struct list_head alg_list;
151
152 /* hwrng device */
153 struct hwrng rng;
154};
155
f3c85bc1
LN		 156/* .features flag */
157#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
fe5720e2 158#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
60f208d7 159#define TALITOS_FTR_SHA224_HWINIT 0x00000004
f3c85bc1 160
81eb024c
KP		 161static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
162{
163 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
a752447a 164 talitos_ptr->eptr = upper_32_bits(dma_addr);
81eb024c
KP		 165}
166
9c4a7965
KP		 167/*
168 * map virtual single (contiguous) pointer to h/w descriptor pointer
169 */
170static void map_single_talitos_ptr(struct device *dev,
171 struct talitos_ptr *talitos_ptr,
172 unsigned short len, void *data,
173 unsigned char extent,
174 enum dma_data_direction dir)
175{
81eb024c
KP		 176 dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
177
9c4a7965 178 talitos_ptr->len = cpu_to_be16(len);
81eb024c 179 to_talitos_ptr(talitos_ptr, dma_addr);
9c4a7965
KP		 180 talitos_ptr->j_extent = extent;
181}
182
183/*
184 * unmap bus single (contiguous) h/w descriptor pointer
185 */
186static void unmap_single_talitos_ptr(struct device *dev,
187 struct talitos_ptr *talitos_ptr,
188 enum dma_data_direction dir)
189{
190 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
191 be16_to_cpu(talitos_ptr->len), dir);
192}
193
194static int reset_channel(struct device *dev, int ch)
195{
196 struct talitos_private *priv = dev_get_drvdata(dev);
197 unsigned int timeout = TALITOS_TIMEOUT;
198
199 setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
200
201 while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
202 && --timeout)
203 cpu_relax();
204
205 if (timeout == 0) {
206 dev_err(dev, "failed to reset channel %d\n", ch);
207 return -EIO;
208 }
209
81eb024c
KP		 210 /* set 36-bit addressing, done writeback enable and done IRQ enable */
211 setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |
212 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
9c4a7965 213
fe5720e2
KP		 214 /* and ICCR writeback, if available */
215 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
216 setbits32(priv->reg + TALITOS_CCCR_LO(ch),
217 TALITOS_CCCR_LO_IWSE);
218
9c4a7965
KP		 219 return 0;
220}
221
222static int reset_device(struct device *dev)
223{
224 struct talitos_private *priv = dev_get_drvdata(dev);
225 unsigned int timeout = TALITOS_TIMEOUT;
226
227 setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
228
229 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
230 && --timeout)
231 cpu_relax();
232
233 if (timeout == 0) {
234 dev_err(dev, "failed to reset device\n");
235 return -EIO;
236 }
237
238 return 0;
239}
240
241/*
242 * Reset and initialize the device
243 */
244static int init_device(struct device *dev)
245{
246 struct talitos_private *priv = dev_get_drvdata(dev);
247 int ch, err;
248
249 /*
250 * Master reset
251 * errata documentation: warning: certain SEC interrupts
252 * are not fully cleared by writing the MCR:SWR bit,
253 * set bit twice to completely reset
254 */
255 err = reset_device(dev);
256 if (err)
257 return err;
258
259 err = reset_device(dev);
260 if (err)
261 return err;
262
263 /* reset channels */
264 for (ch = 0; ch < priv->num_channels; ch++) {
265 err = reset_channel(dev, ch);
266 if (err)
267 return err;
268 }
269
270 /* enable channel done and error interrupts */
271 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
272 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
273
fe5720e2
KP		 274 /* disable integrity check error interrupts (use writeback instead) */
275 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
276 setbits32(priv->reg + TALITOS_MDEUICR_LO,
277 TALITOS_MDEUICR_LO_ICE);
278
9c4a7965
KP		 279 return 0;
280}
281
282/**
283 * talitos_submit - submits a descriptor to the device for processing
284 * @dev: the SEC device to be used
5228f0f7 285 * @ch: the SEC device channel to be used
9c4a7965
KP		 286 * @desc: the descriptor to be processed by the device
287 * @callback: whom to call when processing is complete
288 * @context: a handle for use by caller (optional)
289 *
290 * desc must contain valid dma-mapped (bus physical) address pointers.
291 * callback must check err and feedback in descriptor header
292 * for device processing status.
293 */
5228f0f7 294static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
9c4a7965
KP		 295 void (*callback)(struct device *dev,
296 struct talitos_desc *desc,
297 void *context, int error),
298 void *context)
299{
300 struct talitos_private *priv = dev_get_drvdata(dev);
301 struct talitos_request *request;
5228f0f7 302 unsigned long flags;
9c4a7965
KP		 303 int head;
304
305 /* select done notification */
306 desc->hdr |= DESC_HDR_DONE_NOTIFY;
307
4b992628 308 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
9c4a7965 309
4b992628 310 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
ec6644d6 311 /* h/w fifo is full */
4b992628 312 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 313 return -EAGAIN;
314 }
315
4b992628
KP		 316 head = priv->chan[ch].head;
317 request = &priv->chan[ch].fifo[head];
ec6644d6 318
9c4a7965
KP		 319 /* map descriptor and save caller data */
320 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
321 DMA_BIDIRECTIONAL);
322 request->callback = callback;
323 request->context = context;
324
325 /* increment fifo head */
4b992628 326 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
9c4a7965
KP		 327
328 smp_wmb();
329 request->desc = desc;
330
331 /* GO! */
332 wmb();
a752447a 333 out_be32(priv->reg + TALITOS_FF(ch), upper_32_bits(request->dma_desc));
81eb024c 334 out_be32(priv->reg + TALITOS_FF_LO(ch),
a752447a 335 lower_32_bits(request->dma_desc));
9c4a7965 336
4b992628 337 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 338
339 return -EINPROGRESS;
340}
341
342/*
343 * process what was done, notify callback of error if not
344 */
345static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
346{
347 struct talitos_private *priv = dev_get_drvdata(dev);
348 struct talitos_request *request, saved_req;
349 unsigned long flags;
350 int tail, status;
351
4b992628 352 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
9c4a7965 353
4b992628
KP		 354 tail = priv->chan[ch].tail;
355 while (priv->chan[ch].fifo[tail].desc) {
356 request = &priv->chan[ch].fifo[tail];
9c4a7965
KP		 357
358 /* descriptors with their done bits set don't get the error */
359 rmb();
ca38a814 360 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
9c4a7965 361 status = 0;
ca38a814 362 else
9c4a7965
KP		 363 if (!error)
364 break;
365 else
366 status = error;
367
368 dma_unmap_single(dev, request->dma_desc,
e938e465
KP		 369 sizeof(struct talitos_desc),
370 DMA_BIDIRECTIONAL);
9c4a7965
KP		 371
372 /* copy entries so we can call callback outside lock */
373 saved_req.desc = request->desc;
374 saved_req.callback = request->callback;
375 saved_req.context = request->context;
376
377 /* release request entry in fifo */
378 smp_wmb();
379 request->desc = NULL;
380
381 /* increment fifo tail */
4b992628 382 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
9c4a7965 383
4b992628 384 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
ec6644d6 385
4b992628 386 atomic_dec(&priv->chan[ch].submit_count);
ec6644d6 387
9c4a7965
KP		 388 saved_req.callback(dev, saved_req.desc, saved_req.context,
389 status);
390 /* channel may resume processing in single desc error case */
391 if (error && !reset_ch && status == error)
392 return;
4b992628
KP		 393 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
394 tail = priv->chan[ch].tail;
9c4a7965
KP		 395 }
396
4b992628 397 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
9c4a7965
KP		 398}
399
400/*
401 * process completed requests for channels that have done status
402 */
403static void talitos_done(unsigned long data)
404{
405 struct device *dev = (struct device *)data;
406 struct talitos_private *priv = dev_get_drvdata(dev);
407 int ch;
408
409 for (ch = 0; ch < priv->num_channels; ch++)
410 flush_channel(dev, ch, 0, 0);
1c2e8811
LN		 411
412 /* At this point, all completed channels have been processed.
413 * Unmask done interrupts for channels completed later on.
414 */
fe5720e2
KP		 415 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
416 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
9c4a7965
KP		 417}
418
419/*
420 * locate current (offending) descriptor
421 */
422static struct talitos_desc *current_desc(struct device *dev, int ch)
423{
424 struct talitos_private *priv = dev_get_drvdata(dev);
4b992628 425 int tail = priv->chan[ch].tail;
9c4a7965
KP		 426 dma_addr_t cur_desc;
427
428 cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
429
4b992628 430 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
9c4a7965 431 tail = (tail + 1) & (priv->fifo_len - 1);
4b992628 432 if (tail == priv->chan[ch].tail) {
9c4a7965
KP		 433 dev_err(dev, "couldn't locate current descriptor\n");
434 return NULL;
435 }
436 }
437
4b992628 438 return priv->chan[ch].fifo[tail].desc;
9c4a7965
KP		 439}
440
441/*
442 * user diagnostics; report root cause of error based on execution unit status
443 */
e938e465
KP		 444static void report_eu_error(struct device *dev, int ch,
445 struct talitos_desc *desc)
9c4a7965
KP		 446{
447 struct talitos_private *priv = dev_get_drvdata(dev);
448 int i;
449
450 switch (desc->hdr & DESC_HDR_SEL0_MASK) {
451 case DESC_HDR_SEL0_AFEU:
452 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
453 in_be32(priv->reg + TALITOS_AFEUISR),
454 in_be32(priv->reg + TALITOS_AFEUISR_LO));
455 break;
456 case DESC_HDR_SEL0_DEU:
457 dev_err(dev, "DEUISR 0x%08x_%08x\n",
458 in_be32(priv->reg + TALITOS_DEUISR),
459 in_be32(priv->reg + TALITOS_DEUISR_LO));
460 break;
461 case DESC_HDR_SEL0_MDEUA:
462 case DESC_HDR_SEL0_MDEUB:
463 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
464 in_be32(priv->reg + TALITOS_MDEUISR),
465 in_be32(priv->reg + TALITOS_MDEUISR_LO));
466 break;
467 case DESC_HDR_SEL0_RNG:
468 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
469 in_be32(priv->reg + TALITOS_RNGUISR),
470 in_be32(priv->reg + TALITOS_RNGUISR_LO));
471 break;
472 case DESC_HDR_SEL0_PKEU:
473 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
474 in_be32(priv->reg + TALITOS_PKEUISR),
475 in_be32(priv->reg + TALITOS_PKEUISR_LO));
476 break;
477 case DESC_HDR_SEL0_AESU:
478 dev_err(dev, "AESUISR 0x%08x_%08x\n",
479 in_be32(priv->reg + TALITOS_AESUISR),
480 in_be32(priv->reg + TALITOS_AESUISR_LO));
481 break;
482 case DESC_HDR_SEL0_CRCU:
483 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
484 in_be32(priv->reg + TALITOS_CRCUISR),
485 in_be32(priv->reg + TALITOS_CRCUISR_LO));
486 break;
487 case DESC_HDR_SEL0_KEU:
488 dev_err(dev, "KEUISR 0x%08x_%08x\n",
489 in_be32(priv->reg + TALITOS_KEUISR),
490 in_be32(priv->reg + TALITOS_KEUISR_LO));
491 break;
492 }
493
494 switch (desc->hdr & DESC_HDR_SEL1_MASK) {
495 case DESC_HDR_SEL1_MDEUA:
496 case DESC_HDR_SEL1_MDEUB:
497 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
498 in_be32(priv->reg + TALITOS_MDEUISR),
499 in_be32(priv->reg + TALITOS_MDEUISR_LO));
500 break;
501 case DESC_HDR_SEL1_CRCU:
502 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
503 in_be32(priv->reg + TALITOS_CRCUISR),
504 in_be32(priv->reg + TALITOS_CRCUISR_LO));
505 break;
506 }
507
508 for (i = 0; i < 8; i++)
509 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
510 in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
511 in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
512}
513
514/*
515 * recover from error interrupts
516 */
40405f10 517static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
9c4a7965
KP		 518{
519 struct device *dev = (struct device *)data;
520 struct talitos_private *priv = dev_get_drvdata(dev);
521 unsigned int timeout = TALITOS_TIMEOUT;
522 int ch, error, reset_dev = 0, reset_ch = 0;
40405f10 523 u32 v, v_lo;
9c4a7965
KP		 524
525 for (ch = 0; ch < priv->num_channels; ch++) {
526 /* skip channels without errors */
527 if (!(isr & (1 << (ch * 2 + 1))))
528 continue;
529
530 error = -EINVAL;
531
532 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
533 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
534
535 if (v_lo & TALITOS_CCPSR_LO_DOF) {
536 dev_err(dev, "double fetch fifo overflow error\n");
537 error = -EAGAIN;
538 reset_ch = 1;
539 }
540 if (v_lo & TALITOS_CCPSR_LO_SOF) {
541 /* h/w dropped descriptor */
542 dev_err(dev, "single fetch fifo overflow error\n");
543 error = -EAGAIN;
544 }
545 if (v_lo & TALITOS_CCPSR_LO_MDTE)
546 dev_err(dev, "master data transfer error\n");
547 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
548 dev_err(dev, "s/g data length zero error\n");
549 if (v_lo & TALITOS_CCPSR_LO_FPZ)
550 dev_err(dev, "fetch pointer zero error\n");
551 if (v_lo & TALITOS_CCPSR_LO_IDH)
552 dev_err(dev, "illegal descriptor header error\n");
553 if (v_lo & TALITOS_CCPSR_LO_IEU)
554 dev_err(dev, "invalid execution unit error\n");
555 if (v_lo & TALITOS_CCPSR_LO_EU)
556 report_eu_error(dev, ch, current_desc(dev, ch));
557 if (v_lo & TALITOS_CCPSR_LO_GB)
558 dev_err(dev, "gather boundary error\n");
559 if (v_lo & TALITOS_CCPSR_LO_GRL)
560 dev_err(dev, "gather return/length error\n");
561 if (v_lo & TALITOS_CCPSR_LO_SB)
562 dev_err(dev, "scatter boundary error\n");
563 if (v_lo & TALITOS_CCPSR_LO_SRL)
564 dev_err(dev, "scatter return/length error\n");
565
566 flush_channel(dev, ch, error, reset_ch);
567
568 if (reset_ch) {
569 reset_channel(dev, ch);
570 } else {
571 setbits32(priv->reg + TALITOS_CCCR(ch),
572 TALITOS_CCCR_CONT);
573 setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
574 while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
575 TALITOS_CCCR_CONT) && --timeout)
576 cpu_relax();
577 if (timeout == 0) {
578 dev_err(dev, "failed to restart channel %d\n",
579 ch);
580 reset_dev = 1;
581 }
582 }
583 }
584 if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
585 dev_err(dev, "done overflow, internal time out, or rngu error: "
586 "ISR 0x%08x_%08x\n", isr, isr_lo);
587
588 /* purge request queues */
589 for (ch = 0; ch < priv->num_channels; ch++)
590 flush_channel(dev, ch, -EIO, 1);
591
592 /* reset and reinitialize the device */
593 init_device(dev);
594 }
595}
596
597static irqreturn_t talitos_interrupt(int irq, void *data)
598{
599 struct device *dev = data;
600 struct talitos_private *priv = dev_get_drvdata(dev);
601 u32 isr, isr_lo;
602
603 isr = in_be32(priv->reg + TALITOS_ISR);
604 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
ca38a814
LN		 605 /* Acknowledge interrupt */
606 out_be32(priv->reg + TALITOS_ICR, isr);
607 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
9c4a7965 608
ca38a814 609 if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
40405f10 610 talitos_error((unsigned long)data, isr, isr_lo);
ca38a814 611 else
1c2e8811
LN		 612 if (likely(isr & TALITOS_ISR_CHDONE)) {
613 /* mask further done interrupts. */
614 clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
615 /* done_task will unmask done interrupts at exit */
9c4a7965 616 tasklet_schedule(&priv->done_task);
1c2e8811 617 }
9c4a7965
KP		 618
619 return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
620}
621
622/*
623 * hwrng
624 */
625static int talitos_rng_data_present(struct hwrng *rng, int wait)
626{
627 struct device *dev = (struct device *)rng->priv;
628 struct talitos_private *priv = dev_get_drvdata(dev);
629 u32 ofl;
630 int i;
631
632 for (i = 0; i < 20; i++) {
633 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
634 TALITOS_RNGUSR_LO_OFL;
635 if (ofl || !wait)
636 break;
637 udelay(10);
638 }
639
640 return !!ofl;
641}
642
643static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
644{
645 struct device *dev = (struct device *)rng->priv;
646 struct talitos_private *priv = dev_get_drvdata(dev);
647
648 /* rng fifo requires 64-bit accesses */
649 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
650 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
651
652 return sizeof(u32);
653}
654
655static int talitos_rng_init(struct hwrng *rng)
656{
657 struct device *dev = (struct device *)rng->priv;
658 struct talitos_private *priv = dev_get_drvdata(dev);
659 unsigned int timeout = TALITOS_TIMEOUT;
660
661 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
662 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
663 && --timeout)
664 cpu_relax();
665 if (timeout == 0) {
666 dev_err(dev, "failed to reset rng hw\n");
667 return -ENODEV;
668 }
669
670 /* start generating */
671 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
672
673 return 0;
674}
675
676static int talitos_register_rng(struct device *dev)
677{
678 struct talitos_private *priv = dev_get_drvdata(dev);
679
680 priv->rng.name = dev_driver_string(dev),
681 priv->rng.init = talitos_rng_init,
682 priv->rng.data_present = talitos_rng_data_present,
683 priv->rng.data_read = talitos_rng_data_read,
684 priv->rng.priv = (unsigned long)dev;
685
686 return hwrng_register(&priv->rng);
687}
688
689static void talitos_unregister_rng(struct device *dev)
690{
691 struct talitos_private *priv = dev_get_drvdata(dev);
692
693 hwrng_unregister(&priv->rng);
694}
695
696/*
697 * crypto alg
698 */
699#define TALITOS_CRA_PRIORITY 3000
700#define TALITOS_MAX_KEY_SIZE 64
3952f17e 701#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
70bcaca7 702
497f2e6b 703#define MD5_BLOCK_SIZE 64
9c4a7965
KP		 704
705struct talitos_ctx {
706 struct device *dev;
5228f0f7 707 int ch;
9c4a7965
KP		 708 __be32 desc_hdr_template;
709 u8 key[TALITOS_MAX_KEY_SIZE];
70bcaca7 710 u8 iv[TALITOS_MAX_IV_LENGTH];
9c4a7965
KP		 711 unsigned int keylen;
712 unsigned int enckeylen;
713 unsigned int authkeylen;
714 unsigned int authsize;
715};
716
497f2e6b
LN		 717#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
718#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
719
720struct talitos_ahash_req_ctx {
60f208d7 721 u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
497f2e6b
LN		 722 unsigned int hw_context_size;
723 u8 buf[HASH_MAX_BLOCK_SIZE];
724 u8 bufnext[HASH_MAX_BLOCK_SIZE];
60f208d7 725 unsigned int swinit;
497f2e6b
LN		 726 unsigned int first;
727 unsigned int last;
728 unsigned int to_hash_later;
5e833bc4 729 u64 nbuf;
497f2e6b
LN		 730 struct scatterlist bufsl[2];
731 struct scatterlist *psrc;
732};
733
56af8cd4
LN		 734static int aead_setauthsize(struct crypto_aead *authenc,
735 unsigned int authsize)
9c4a7965
KP		 736{
737 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
738
739 ctx->authsize = authsize;
740
741 return 0;
742}
743
56af8cd4
LN		 744static int aead_setkey(struct crypto_aead *authenc,
745 const u8 *key, unsigned int keylen)
9c4a7965
KP		 746{
747 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
748 struct rtattr *rta = (void *)key;
749 struct crypto_authenc_key_param *param;
750 unsigned int authkeylen;
751 unsigned int enckeylen;
752
753 if (!RTA_OK(rta, keylen))
754 goto badkey;
755
756 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
757 goto badkey;
758
759 if (RTA_PAYLOAD(rta) < sizeof(*param))
760 goto badkey;
761
762 param = RTA_DATA(rta);
763 enckeylen = be32_to_cpu(param->enckeylen);
764
765 key += RTA_ALIGN(rta->rta_len);
766 keylen -= RTA_ALIGN(rta->rta_len);
767
768 if (keylen < enckeylen)
769 goto badkey;
770
771 authkeylen = keylen - enckeylen;
772
773 if (keylen > TALITOS_MAX_KEY_SIZE)
774 goto badkey;
775
776 memcpy(&ctx->key, key, keylen);
777
778 ctx->keylen = keylen;
779 ctx->enckeylen = enckeylen;
780 ctx->authkeylen = authkeylen;
781
782 return 0;
783
784badkey:
785 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
786 return -EINVAL;
787}
788
789/*
56af8cd4 790 * talitos_edesc - s/w-extended descriptor
9c4a7965
KP		 791 * @src_nents: number of segments in input scatterlist
792 * @dst_nents: number of segments in output scatterlist
793 * @dma_len: length of dma mapped link_tbl space
794 * @dma_link_tbl: bus physical address of link_tbl
795 * @desc: h/w descriptor
796 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
797 *
798 * if decrypting (with authcheck), or either one of src_nents or dst_nents
799 * is greater than 1, an integrity check value is concatenated to the end
800 * of link_tbl data
801 */
56af8cd4 802struct talitos_edesc {
9c4a7965
KP		 803 int src_nents;
804 int dst_nents;
4de9d0b5
LN		 805 int src_is_chained;
806 int dst_is_chained;
9c4a7965
KP		 807 int dma_len;
808 dma_addr_t dma_link_tbl;
809 struct talitos_desc desc;
810 struct talitos_ptr link_tbl[0];
811};
812
4de9d0b5
LN		 813static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
814 unsigned int nents, enum dma_data_direction dir,
815 int chained)
816{
817 if (unlikely(chained))
818 while (sg) {
819 dma_map_sg(dev, sg, 1, dir);
820 sg = scatterwalk_sg_next(sg);
821 }
822 else
823 dma_map_sg(dev, sg, nents, dir);
824 return nents;
825}
826
827static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
828 enum dma_data_direction dir)
829{
830 while (sg) {
831 dma_unmap_sg(dev, sg, 1, dir);
832 sg = scatterwalk_sg_next(sg);
833 }
834}
835
836static void talitos_sg_unmap(struct device *dev,
837 struct talitos_edesc *edesc,
838 struct scatterlist *src,
839 struct scatterlist *dst)
840{
841 unsigned int src_nents = edesc->src_nents ? : 1;
842 unsigned int dst_nents = edesc->dst_nents ? : 1;
843
844 if (src != dst) {
845 if (edesc->src_is_chained)
846 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
847 else
848 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
849
497f2e6b
LN		 850 if (dst) {
851 if (edesc->dst_is_chained)
852 talitos_unmap_sg_chain(dev, dst,
853 DMA_FROM_DEVICE);
854 else
855 dma_unmap_sg(dev, dst, dst_nents,
856 DMA_FROM_DEVICE);
857 }
4de9d0b5
LN		 858 } else
859 if (edesc->src_is_chained)
860 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
861 else
862 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
863}
864
9c4a7965 865static void ipsec_esp_unmap(struct device *dev,
56af8cd4 866 struct talitos_edesc *edesc,
9c4a7965
KP		 867 struct aead_request *areq)
868{
869 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
870 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
871 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
872 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
873
874 dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
875
4de9d0b5 876 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
9c4a7965
KP		 877
878 if (edesc->dma_len)
879 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
880 DMA_BIDIRECTIONAL);
881}
882
883/*
884 * ipsec_esp descriptor callbacks
885 */
886static void ipsec_esp_encrypt_done(struct device *dev,
887 struct talitos_desc *desc, void *context,
888 int err)
889{
890 struct aead_request *areq = context;
9c4a7965
KP		 891 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
892 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 893 struct talitos_edesc *edesc;
9c4a7965
KP		 894 struct scatterlist *sg;
895 void *icvdata;
896
19bbbc63
KP		 897 edesc = container_of(desc, struct talitos_edesc, desc);
898
9c4a7965
KP		 899 ipsec_esp_unmap(dev, edesc, areq);
900
901 /* copy the generated ICV to dst */
902 if (edesc->dma_len) {
903 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 904 edesc->dst_nents + 2];
9c4a7965
KP		 905 sg = sg_last(areq->dst, edesc->dst_nents);
906 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
907 icvdata, ctx->authsize);
908 }
909
910 kfree(edesc);
911
912 aead_request_complete(areq, err);
913}
914
fe5720e2 915static void ipsec_esp_decrypt_swauth_done(struct device *dev,
e938e465
KP		 916 struct talitos_desc *desc,
917 void *context, int err)
9c4a7965
KP		 918{
919 struct aead_request *req = context;
9c4a7965
KP		 920 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
921 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 922 struct talitos_edesc *edesc;
9c4a7965
KP		 923 struct scatterlist *sg;
924 void *icvdata;
925
19bbbc63
KP		 926 edesc = container_of(desc, struct talitos_edesc, desc);
927
9c4a7965
KP		 928 ipsec_esp_unmap(dev, edesc, req);
929
930 if (!err) {
931 /* auth check */
932 if (edesc->dma_len)
933 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 934 edesc->dst_nents + 2];
9c4a7965
KP		 935 else
936 icvdata = &edesc->link_tbl[0];
937
938 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
939 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
940 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
941 }
942
943 kfree(edesc);
944
945 aead_request_complete(req, err);
946}
947
fe5720e2 948static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
e938e465
KP		 949 struct talitos_desc *desc,
950 void *context, int err)
fe5720e2
KP		 951{
952 struct aead_request *req = context;
19bbbc63
KP		 953 struct talitos_edesc *edesc;
954
955 edesc = container_of(desc, struct talitos_edesc, desc);
fe5720e2
KP		 956
957 ipsec_esp_unmap(dev, edesc, req);
958
959 /* check ICV auth status */
e938e465
KP		 960 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
961 DESC_HDR_LO_ICCR1_PASS))
962 err = -EBADMSG;
fe5720e2
KP		 963
964 kfree(edesc);
965
966 aead_request_complete(req, err);
967}
968
9c4a7965
KP		 969/*
970 * convert scatterlist to SEC h/w link table format
971 * stop at cryptlen bytes
972 */
70bcaca7 973static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
9c4a7965
KP		 974 int cryptlen, struct talitos_ptr *link_tbl_ptr)
975{
70bcaca7
LN		 976 int n_sg = sg_count;
977
978 while (n_sg--) {
81eb024c 979 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
9c4a7965
KP		 980 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
981 link_tbl_ptr->j_extent = 0;
982 link_tbl_ptr++;
983 cryptlen -= sg_dma_len(sg);
4de9d0b5 984 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 985 }
986
70bcaca7 987 /* adjust (decrease) last one (or two) entry's len to cryptlen */
9c4a7965 988 link_tbl_ptr--;
c0e741d4 989 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
70bcaca7
LN		 990 /* Empty this entry, and move to previous one */
991 cryptlen += be16_to_cpu(link_tbl_ptr->len);
992 link_tbl_ptr->len = 0;
993 sg_count--;
994 link_tbl_ptr--;
995 }
9c4a7965
KP		 996 link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
997 + cryptlen);
998
999 /* tag end of link table */
1000 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
70bcaca7
LN		 1001
1002 return sg_count;
9c4a7965
KP		 1003}
1004
1005/*
1006 * fill in and submit ipsec_esp descriptor
1007 */
56af8cd4 1008static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
9c4a7965
KP		 1009 u8 *giv, u64 seq,
1010 void (*callback) (struct device *dev,
1011 struct talitos_desc *desc,
1012 void *context, int error))
1013{
1014 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
1015 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
1016 struct device *dev = ctx->dev;
1017 struct talitos_desc *desc = &edesc->desc;
1018 unsigned int cryptlen = areq->cryptlen;
1019 unsigned int authsize = ctx->authsize;
e41256f1 1020 unsigned int ivsize = crypto_aead_ivsize(aead);
fa86a267 1021 int sg_count, ret;
fe5720e2 1022 int sg_link_tbl_len;
9c4a7965
KP		 1023
1024 /* hmac key */
1025 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
1026 0, DMA_TO_DEVICE);
1027 /* hmac data */
e41256f1
KP		 1028 map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
1029 sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
9c4a7965 1030 /* cipher iv */
9c4a7965
KP		 1031 map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
1032 DMA_TO_DEVICE);
1033
1034 /* cipher key */
1035 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1036 (char *)&ctx->key + ctx->authkeylen, 0,
1037 DMA_TO_DEVICE);
1038
1039 /*
1040 * cipher in
1041 * map and adjust cipher len to aead request cryptlen.
1042 * extent is bytes of HMAC postpended to ciphertext,
1043 * typically 12 for ipsec
1044 */
1045 desc->ptr[4].len = cpu_to_be16(cryptlen);
1046 desc->ptr[4].j_extent = authsize;
1047
e938e465
KP		 1048 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1049 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1050 : DMA_TO_DEVICE,
4de9d0b5 1051 edesc->src_is_chained);
9c4a7965
KP		 1052
1053 if (sg_count == 1) {
81eb024c 1054 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
9c4a7965 1055 } else {
fe5720e2
KP		 1056 sg_link_tbl_len = cryptlen;
1057
962a9c99 1058 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
fe5720e2 1059 sg_link_tbl_len = cryptlen + authsize;
e938e465 1060
fe5720e2 1061 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
70bcaca7
LN		 1062 &edesc->link_tbl[0]);
1063 if (sg_count > 1) {
1064 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
81eb024c 1065 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
e938e465
KP		 1066 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1067 edesc->dma_len,
1068 DMA_BIDIRECTIONAL);
70bcaca7
LN		 1069 } else {
1070 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1071 to_talitos_ptr(&desc->ptr[4],
1072 sg_dma_address(areq->src));
70bcaca7 1073 }
9c4a7965
KP		 1074 }
1075
1076 /* cipher out */
1077 desc->ptr[5].len = cpu_to_be16(cryptlen);
1078 desc->ptr[5].j_extent = authsize;
1079
e938e465 1080 if (areq->src != areq->dst)
4de9d0b5
LN		 1081 sg_count = talitos_map_sg(dev, areq->dst,
1082 edesc->dst_nents ? : 1,
1083 DMA_FROM_DEVICE,
1084 edesc->dst_is_chained);
9c4a7965
KP		 1085
1086 if (sg_count == 1) {
81eb024c 1087 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
9c4a7965
KP		 1088 } else {
1089 struct talitos_ptr *link_tbl_ptr =
f3c85bc1 1090 &edesc->link_tbl[edesc->src_nents + 1];
9c4a7965 1091
81eb024c
KP		 1092 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1093 (edesc->src_nents + 1) *
1094 sizeof(struct talitos_ptr));
fe5720e2
KP		 1095 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1096 link_tbl_ptr);
1097
f3c85bc1 1098 /* Add an entry to the link table for ICV data */
9c4a7965 1099 link_tbl_ptr += sg_count - 1;
9c4a7965 1100 link_tbl_ptr->j_extent = 0;
f3c85bc1 1101 sg_count++;
9c4a7965
KP		 1102 link_tbl_ptr++;
1103 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1104 link_tbl_ptr->len = cpu_to_be16(authsize);
1105
1106 /* icv data follows link tables */
81eb024c
KP		 1107 to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
1108 (edesc->src_nents + edesc->dst_nents + 2) *
1109 sizeof(struct talitos_ptr));
9c4a7965
KP		 1110 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1111 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1112 edesc->dma_len, DMA_BIDIRECTIONAL);
1113 }
1114
1115 /* iv out */
1116 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1117 DMA_FROM_DEVICE);
1118
5228f0f7 1119 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
fa86a267
KP		 1120 if (ret != -EINPROGRESS) {
1121 ipsec_esp_unmap(dev, edesc, areq);
1122 kfree(edesc);
1123 }
1124 return ret;
9c4a7965
KP		 1125}
1126
9c4a7965
KP		 1127/*
1128 * derive number of elements in scatterlist
1129 */
4de9d0b5 1130static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
9c4a7965
KP		 1131{
1132 struct scatterlist *sg = sg_list;
1133 int sg_nents = 0;
1134
4de9d0b5
LN		 1135 *chained = 0;
1136 while (nbytes > 0) {
9c4a7965
KP		 1137 sg_nents++;
1138 nbytes -= sg->length;
4de9d0b5
LN		 1139 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1140 *chained = 1;
1141 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 1142 }
1143
1144 return sg_nents;
1145}
1146
497f2e6b
LN		 1147/**
1148 * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1149 * @sgl: The SG list
1150 * @nents: Number of SG entries
1151 * @buf: Where to copy to
1152 * @buflen: The number of bytes to copy
1153 * @skip: The number of bytes to skip before copying.
1154 * Note: skip + buflen should equal SG total size.
1155 *
1156 * Returns the number of copied bytes.
1157 *
1158 **/
1159static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1160 void *buf, size_t buflen, unsigned int skip)
1161{
1162 unsigned int offset = 0;
1163 unsigned int boffset = 0;
1164 struct sg_mapping_iter miter;
1165 unsigned long flags;
1166 unsigned int sg_flags = SG_MITER_ATOMIC;
1167 size_t total_buffer = buflen + skip;
1168
1169 sg_flags |= SG_MITER_FROM_SG;
1170
1171 sg_miter_start(&miter, sgl, nents, sg_flags);
1172
1173 local_irq_save(flags);
1174
1175 while (sg_miter_next(&miter) && offset < total_buffer) {
1176 unsigned int len;
1177 unsigned int ignore;
1178
1179 if ((offset + miter.length) > skip) {
1180 if (offset < skip) {
1181 /* Copy part of this segment */
1182 ignore = skip - offset;
1183 len = miter.length - ignore;
7260042b
LN		 1184 if (boffset + len > buflen)
1185 len = buflen - boffset;
497f2e6b
LN		 1186 memcpy(buf + boffset, miter.addr + ignore, len);
1187 } else {
7260042b 1188 /* Copy all of this segment (up to buflen) */
497f2e6b 1189 len = miter.length;
7260042b
LN		 1190 if (boffset + len > buflen)
1191 len = buflen - boffset;
497f2e6b
LN		 1192 memcpy(buf + boffset, miter.addr, len);
1193 }
1194 boffset += len;
1195 }
1196 offset += miter.length;
1197 }
1198
1199 sg_miter_stop(&miter);
1200
1201 local_irq_restore(flags);
1202 return boffset;
1203}
1204
9c4a7965 1205/*
56af8cd4 1206 * allocate and map the extended descriptor
9c4a7965 1207 */
4de9d0b5
LN		 1208static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1209 struct scatterlist *src,
1210 struct scatterlist *dst,
497f2e6b 1211 int hash_result,
4de9d0b5
LN		 1212 unsigned int cryptlen,
1213 unsigned int authsize,
1214 int icv_stashing,
1215 u32 cryptoflags)
9c4a7965 1216{
56af8cd4 1217 struct talitos_edesc *edesc;
9c4a7965 1218 int src_nents, dst_nents, alloc_len, dma_len;
4de9d0b5
LN		 1219 int src_chained, dst_chained = 0;
1220 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
586725f8 1221 GFP_ATOMIC;
9c4a7965 1222
4de9d0b5
LN		 1223 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1224 dev_err(dev, "length exceeds h/w max limit\n");
9c4a7965
KP		 1225 return ERR_PTR(-EINVAL);
1226 }
1227
4de9d0b5 1228 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
9c4a7965
KP		 1229 src_nents = (src_nents == 1) ? 0 : src_nents;
1230
497f2e6b
LN		 1231 if (hash_result) {
1232 dst_nents = 0;
9c4a7965 1233 } else {
497f2e6b
LN		 1234 if (dst == src) {
1235 dst_nents = src_nents;
1236 } else {
1237 dst_nents = sg_count(dst, cryptlen + authsize,
1238 &dst_chained);
1239 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1240 }
9c4a7965
KP		 1241 }
1242
1243 /*
1244 * allocate space for base edesc plus the link tables,
f3c85bc1 1245 * allowing for two separate entries for ICV and generated ICV (+ 2),
9c4a7965
KP		 1246 * and the ICV data itself
1247 */
56af8cd4 1248 alloc_len = sizeof(struct talitos_edesc);
9c4a7965 1249 if (src_nents || dst_nents) {
f3c85bc1 1250 dma_len = (src_nents + dst_nents + 2) *
4de9d0b5 1251 sizeof(struct talitos_ptr) + authsize;
9c4a7965
KP		 1252 alloc_len += dma_len;
1253 } else {
1254 dma_len = 0;
4de9d0b5 1255 alloc_len += icv_stashing ? authsize : 0;
9c4a7965
KP		 1256 }
1257
586725f8 1258 edesc = kmalloc(alloc_len, GFP_DMA | flags);
9c4a7965 1259 if (!edesc) {
4de9d0b5 1260 dev_err(dev, "could not allocate edescriptor\n");
9c4a7965
KP		 1261 return ERR_PTR(-ENOMEM);
1262 }
1263
1264 edesc->src_nents = src_nents;
1265 edesc->dst_nents = dst_nents;
4de9d0b5
LN		 1266 edesc->src_is_chained = src_chained;
1267 edesc->dst_is_chained = dst_chained;
9c4a7965 1268 edesc->dma_len = dma_len;
497f2e6b
LN		 1269 if (dma_len)
1270 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1271 edesc->dma_len,
1272 DMA_BIDIRECTIONAL);
9c4a7965
KP		 1273
1274 return edesc;
1275}
1276
4de9d0b5
LN		 1277static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
1278 int icv_stashing)
1279{
1280 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1281 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1282
497f2e6b 1283 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
4de9d0b5
LN		 1284 areq->cryptlen, ctx->authsize, icv_stashing,
1285 areq->base.flags);
1286}
1287
56af8cd4 1288static int aead_encrypt(struct aead_request *req)
9c4a7965
KP		 1289{
1290 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1291 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1292 struct talitos_edesc *edesc;
9c4a7965
KP		 1293
1294 /* allocate extended descriptor */
4de9d0b5 1295 edesc = aead_edesc_alloc(req, 0);
9c4a7965
KP		 1296 if (IS_ERR(edesc))
1297 return PTR_ERR(edesc);
1298
1299 /* set encrypt */
70bcaca7 1300 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1301
1302 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1303}
1304
56af8cd4 1305static int aead_decrypt(struct aead_request *req)
9c4a7965
KP		 1306{
1307 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1308 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1309 unsigned int authsize = ctx->authsize;
fe5720e2 1310 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
56af8cd4 1311 struct talitos_edesc *edesc;
9c4a7965
KP		 1312 struct scatterlist *sg;
1313 void *icvdata;
1314
1315 req->cryptlen -= authsize;
1316
1317 /* allocate extended descriptor */
4de9d0b5 1318 edesc = aead_edesc_alloc(req, 1);
9c4a7965
KP		 1319 if (IS_ERR(edesc))
1320 return PTR_ERR(edesc);
1321
fe5720e2 1322 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
e938e465
KP		 1323 ((!edesc->src_nents && !edesc->dst_nents) ||
1324 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
9c4a7965 1325
fe5720e2 1326 /* decrypt and check the ICV */
e938e465
KP		 1327 edesc->desc.hdr = ctx->desc_hdr_template |
1328 DESC_HDR_DIR_INBOUND |
fe5720e2 1329 DESC_HDR_MODE1_MDEU_CICV;
9c4a7965 1330
fe5720e2
KP		 1331 /* reset integrity check result bits */
1332 edesc->desc.hdr_lo = 0;
9c4a7965 1333
e938e465
KP		 1334 return ipsec_esp(edesc, req, NULL, 0,
1335 ipsec_esp_decrypt_hwauth_done);
fe5720e2 1336
e938e465 1337 }
fe5720e2 1338
e938e465
KP		 1339 /* Have to check the ICV with software */
1340 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
fe5720e2 1341
e938e465
KP		 1342 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1343 if (edesc->dma_len)
1344 icvdata = &edesc->link_tbl[edesc->src_nents +
1345 edesc->dst_nents + 2];
1346 else
1347 icvdata = &edesc->link_tbl[0];
fe5720e2 1348
e938e465 1349 sg = sg_last(req->src, edesc->src_nents ? : 1);
fe5720e2 1350
e938e465
KP		 1351 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1352 ctx->authsize);
fe5720e2 1353
e938e465 1354 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
9c4a7965
KP		 1355}
1356
56af8cd4 1357static int aead_givencrypt(struct aead_givcrypt_request *req)
9c4a7965
KP		 1358{
1359 struct aead_request *areq = &req->areq;
1360 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1361 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1362 struct talitos_edesc *edesc;
9c4a7965
KP		 1363
1364 /* allocate extended descriptor */
4de9d0b5 1365 edesc = aead_edesc_alloc(areq, 0);
9c4a7965
KP		 1366 if (IS_ERR(edesc))
1367 return PTR_ERR(edesc);
1368
1369 /* set encrypt */
70bcaca7 1370 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1371
1372 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
ba95487d
KP		 1373 /* avoid consecutive packets going out with same IV */
1374 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
9c4a7965
KP		 1375
1376 return ipsec_esp(edesc, areq, req->giv, req->seq,
1377 ipsec_esp_encrypt_done);
1378}
1379
4de9d0b5
LN		 1380static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1381 const u8 *key, unsigned int keylen)
1382{
1383 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1384 struct ablkcipher_alg *alg = crypto_ablkcipher_alg(cipher);
1385
1386 if (keylen > TALITOS_MAX_KEY_SIZE)
1387 goto badkey;
1388
1389 if (keylen < alg->min_keysize || keylen > alg->max_keysize)
1390 goto badkey;
1391
1392 memcpy(&ctx->key, key, keylen);
1393 ctx->keylen = keylen;
1394
1395 return 0;
1396
1397badkey:
1398 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1399 return -EINVAL;
1400}
1401
1402static void common_nonsnoop_unmap(struct device *dev,
1403 struct talitos_edesc *edesc,
1404 struct ablkcipher_request *areq)
1405{
1406 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1407 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1408 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1409
1410 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1411
1412 if (edesc->dma_len)
1413 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1414 DMA_BIDIRECTIONAL);
1415}
1416
1417static void ablkcipher_done(struct device *dev,
1418 struct talitos_desc *desc, void *context,
1419 int err)
1420{
1421 struct ablkcipher_request *areq = context;
19bbbc63
KP		 1422 struct talitos_edesc *edesc;
1423
1424 edesc = container_of(desc, struct talitos_edesc, desc);
4de9d0b5
LN		 1425
1426 common_nonsnoop_unmap(dev, edesc, areq);
1427
1428 kfree(edesc);
1429
1430 areq->base.complete(&areq->base, err);
1431}
1432
1433static int common_nonsnoop(struct talitos_edesc *edesc,
1434 struct ablkcipher_request *areq,
1435 u8 *giv,
1436 void (*callback) (struct device *dev,
1437 struct talitos_desc *desc,
1438 void *context, int error))
1439{
1440 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1441 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1442 struct device *dev = ctx->dev;
1443 struct talitos_desc *desc = &edesc->desc;
1444 unsigned int cryptlen = areq->nbytes;
1445 unsigned int ivsize;
1446 int sg_count, ret;
1447
1448 /* first DWORD empty */
1449 desc->ptr[0].len = 0;
81eb024c 1450 to_talitos_ptr(&desc->ptr[0], 0);
4de9d0b5
LN		 1451 desc->ptr[0].j_extent = 0;
1452
1453 /* cipher iv */
1454 ivsize = crypto_ablkcipher_ivsize(cipher);
1455 map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, giv ?: areq->info, 0,
1456 DMA_TO_DEVICE);
1457
1458 /* cipher key */
1459 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1460 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1461
1462 /*
1463 * cipher in
1464 */
1465 desc->ptr[3].len = cpu_to_be16(cryptlen);
1466 desc->ptr[3].j_extent = 0;
1467
1468 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1469 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1470 : DMA_TO_DEVICE,
1471 edesc->src_is_chained);
1472
1473 if (sg_count == 1) {
81eb024c 1474 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
4de9d0b5
LN		 1475 } else {
1476 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1477 &edesc->link_tbl[0]);
1478 if (sg_count > 1) {
81eb024c 1479 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
4de9d0b5 1480 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
e938e465
KP		 1481 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1482 edesc->dma_len,
1483 DMA_BIDIRECTIONAL);
4de9d0b5
LN		 1484 } else {
1485 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1486 to_talitos_ptr(&desc->ptr[3],
1487 sg_dma_address(areq->src));
4de9d0b5
LN		 1488 }
1489 }
1490
1491 /* cipher out */
1492 desc->ptr[4].len = cpu_to_be16(cryptlen);
1493 desc->ptr[4].j_extent = 0;
1494
1495 if (areq->src != areq->dst)
1496 sg_count = talitos_map_sg(dev, areq->dst,
1497 edesc->dst_nents ? : 1,
1498 DMA_FROM_DEVICE,
1499 edesc->dst_is_chained);
1500
1501 if (sg_count == 1) {
81eb024c 1502 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
4de9d0b5
LN		 1503 } else {
1504 struct talitos_ptr *link_tbl_ptr =
1505 &edesc->link_tbl[edesc->src_nents + 1];
1506
81eb024c
KP		 1507 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1508 (edesc->src_nents + 1) *
1509 sizeof(struct talitos_ptr));
4de9d0b5 1510 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
4de9d0b5
LN		 1511 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1512 link_tbl_ptr);
1513 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1514 edesc->dma_len, DMA_BIDIRECTIONAL);
1515 }
1516
1517 /* iv out */
1518 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1519 DMA_FROM_DEVICE);
1520
1521 /* last DWORD empty */
1522 desc->ptr[6].len = 0;
81eb024c 1523 to_talitos_ptr(&desc->ptr[6], 0);
4de9d0b5
LN		 1524 desc->ptr[6].j_extent = 0;
1525
5228f0f7 1526 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
4de9d0b5
LN		 1527 if (ret != -EINPROGRESS) {
1528 common_nonsnoop_unmap(dev, edesc, areq);
1529 kfree(edesc);
1530 }
1531 return ret;
1532}
1533
e938e465
KP		 1534static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1535 areq)
4de9d0b5
LN		 1536{
1537 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1538 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1539
497f2e6b
LN		 1540 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
1541 areq->nbytes, 0, 0, areq->base.flags);
4de9d0b5
LN		 1542}
1543
1544static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1545{
1546 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1547 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1548 struct talitos_edesc *edesc;
1549
1550 /* allocate extended descriptor */
1551 edesc = ablkcipher_edesc_alloc(areq);
1552 if (IS_ERR(edesc))
1553 return PTR_ERR(edesc);
1554
1555 /* set encrypt */
1556 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1557
1558 return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1559}
1560
1561static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1562{
1563 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1564 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1565 struct talitos_edesc *edesc;
1566
1567 /* allocate extended descriptor */
1568 edesc = ablkcipher_edesc_alloc(areq);
1569 if (IS_ERR(edesc))
1570 return PTR_ERR(edesc);
1571
1572 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1573
1574 return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1575}
1576
497f2e6b
LN		 1577static void common_nonsnoop_hash_unmap(struct device *dev,
1578 struct talitos_edesc *edesc,
1579 struct ahash_request *areq)
1580{
1581 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1582
1583 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1584
1585 /* When using hashctx-in, must unmap it. */
1586 if (edesc->desc.ptr[1].len)
1587 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1588 DMA_TO_DEVICE);
1589
1590 if (edesc->desc.ptr[2].len)
1591 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1592 DMA_TO_DEVICE);
1593
1594 talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1595
1596 if (edesc->dma_len)
1597 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1598 DMA_BIDIRECTIONAL);
1599
1600}
1601
1602static void ahash_done(struct device *dev,
1603 struct talitos_desc *desc, void *context,
1604 int err)
1605{
1606 struct ahash_request *areq = context;
1607 struct talitos_edesc *edesc =
1608 container_of(desc, struct talitos_edesc, desc);
1609 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1610
1611 if (!req_ctx->last && req_ctx->to_hash_later) {
1612 /* Position any partial block for next update/final/finup */
1613 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
5e833bc4 1614 req_ctx->nbuf = req_ctx->to_hash_later;
497f2e6b
LN		 1615 }
1616 common_nonsnoop_hash_unmap(dev, edesc, areq);
1617
1618 kfree(edesc);
1619
1620 areq->base.complete(&areq->base, err);
1621}
1622
1623static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1624 struct ahash_request *areq, unsigned int length,
1625 void (*callback) (struct device *dev,
1626 struct talitos_desc *desc,
1627 void *context, int error))
1628{
1629 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1630 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1631 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1632 struct device *dev = ctx->dev;
1633 struct talitos_desc *desc = &edesc->desc;
1634 int sg_count, ret;
1635
1636 /* first DWORD empty */
1637 desc->ptr[0] = zero_entry;
1638
60f208d7
KP		 1639 /* hash context in */
1640 if (!req_ctx->first || req_ctx->swinit) {
497f2e6b
LN		 1641 map_single_talitos_ptr(dev, &desc->ptr[1],
1642 req_ctx->hw_context_size,
1643 (char *)req_ctx->hw_context, 0,
1644 DMA_TO_DEVICE);
60f208d7 1645 req_ctx->swinit = 0;
497f2e6b
LN		 1646 } else {
1647 desc->ptr[1] = zero_entry;
1648 /* Indicate next op is not the first. */
1649 req_ctx->first = 0;
1650 }
1651
1652 /* HMAC key */
1653 if (ctx->keylen)
1654 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1655 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1656 else
1657 desc->ptr[2] = zero_entry;
1658
1659 /*
1660 * data in
1661 */
1662 desc->ptr[3].len = cpu_to_be16(length);
1663 desc->ptr[3].j_extent = 0;
1664
1665 sg_count = talitos_map_sg(dev, req_ctx->psrc,
1666 edesc->src_nents ? : 1,
1667 DMA_TO_DEVICE,
1668 edesc->src_is_chained);
1669
1670 if (sg_count == 1) {
1671 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1672 } else {
1673 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1674 &edesc->link_tbl[0]);
1675 if (sg_count > 1) {
1676 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1677 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1678 dma_sync_single_for_device(ctx->dev,
1679 edesc->dma_link_tbl,
1680 edesc->dma_len,
1681 DMA_BIDIRECTIONAL);
1682 } else {
1683 /* Only one segment now, so no link tbl needed */
1684 to_talitos_ptr(&desc->ptr[3],
1685 sg_dma_address(req_ctx->psrc));
1686 }
1687 }
1688
1689 /* fifth DWORD empty */
1690 desc->ptr[4] = zero_entry;
1691
1692 /* hash/HMAC out -or- hash context out */
1693 if (req_ctx->last)
1694 map_single_talitos_ptr(dev, &desc->ptr[5],
1695 crypto_ahash_digestsize(tfm),
1696 areq->result, 0, DMA_FROM_DEVICE);
1697 else
1698 map_single_talitos_ptr(dev, &desc->ptr[5],
1699 req_ctx->hw_context_size,
1700 req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1701
1702 /* last DWORD empty */
1703 desc->ptr[6] = zero_entry;
1704
5228f0f7 1705 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
497f2e6b
LN		 1706 if (ret != -EINPROGRESS) {
1707 common_nonsnoop_hash_unmap(dev, edesc, areq);
1708 kfree(edesc);
1709 }
1710 return ret;
1711}
1712
1713static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1714 unsigned int nbytes)
1715{
1716 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1717 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1718 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1719
1720 return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, 1,
1721 nbytes, 0, 0, areq->base.flags);
1722}
1723
1724static int ahash_init(struct ahash_request *areq)
1725{
1726 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1727 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1728
1729 /* Initialize the context */
5e833bc4 1730 req_ctx->nbuf = 0;
60f208d7
KP		 1731 req_ctx->first = 1; /* first indicates h/w must init its context */
1732 req_ctx->swinit = 0; /* assume h/w init of context */
497f2e6b
LN		 1733 req_ctx->hw_context_size =
1734 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1735 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1736 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1737
1738 return 0;
1739}
1740
60f208d7
KP		 1741/*
1742 * on h/w without explicit sha224 support, we initialize h/w context
1743 * manually with sha224 constants, and tell it to run sha256.
1744 */
1745static int ahash_init_sha224_swinit(struct ahash_request *areq)
1746{
1747 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1748
1749 ahash_init(areq);
1750 req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1751
a752447a
KP		 1752 req_ctx->hw_context[0] = SHA224_H0;
1753 req_ctx->hw_context[1] = SHA224_H1;
1754 req_ctx->hw_context[2] = SHA224_H2;
1755 req_ctx->hw_context[3] = SHA224_H3;
1756 req_ctx->hw_context[4] = SHA224_H4;
1757 req_ctx->hw_context[5] = SHA224_H5;
1758 req_ctx->hw_context[6] = SHA224_H6;
1759 req_ctx->hw_context[7] = SHA224_H7;
60f208d7
KP		 1760
1761 /* init 64-bit count */
1762 req_ctx->hw_context[8] = 0;
1763 req_ctx->hw_context[9] = 0;
1764
1765 return 0;
1766}
1767
497f2e6b
LN		 1768static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1769{
1770 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1771 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1772 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1773 struct talitos_edesc *edesc;
1774 unsigned int blocksize =
1775 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1776 unsigned int nbytes_to_hash;
1777 unsigned int to_hash_later;
5e833bc4 1778 unsigned int nsg;
497f2e6b
LN		 1779 int chained;
1780
5e833bc4
LN		 1781 if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1782 /* Buffer up to one whole block */
497f2e6b
LN		 1783 sg_copy_to_buffer(areq->src,
1784 sg_count(areq->src, nbytes, &chained),
5e833bc4
LN		 1785 req_ctx->buf + req_ctx->nbuf, nbytes);
1786 req_ctx->nbuf += nbytes;
497f2e6b
LN		 1787 return 0;
1788 }
1789
5e833bc4
LN		 1790 /* At least (blocksize + 1) bytes are available to hash */
1791 nbytes_to_hash = nbytes + req_ctx->nbuf;
1792 to_hash_later = nbytes_to_hash & (blocksize - 1);
1793
1794 if (req_ctx->last)
1795 to_hash_later = 0;
1796 else if (to_hash_later)
1797 /* There is a partial block. Hash the full block(s) now */
1798 nbytes_to_hash -= to_hash_later;
1799 else {
1800 /* Keep one block buffered */
1801 nbytes_to_hash -= blocksize;
1802 to_hash_later = blocksize;
1803 }
1804
1805 /* Chain in any previously buffered data */
1806 if (req_ctx->nbuf) {
1807 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1808 sg_init_table(req_ctx->bufsl, nsg);
1809 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1810 if (nsg > 1)
1811 scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
497f2e6b 1812 req_ctx->psrc = req_ctx->bufsl;
5e833bc4 1813 } else
497f2e6b 1814 req_ctx->psrc = areq->src;
5e833bc4
LN		 1815
1816 if (to_hash_later) {
1817 int nents = sg_count(areq->src, nbytes, &chained);
1818 sg_copy_end_to_buffer(areq->src, nents,
1819 req_ctx->bufnext,
1820 to_hash_later,
1821 nbytes - to_hash_later);
497f2e6b 1822 }
5e833bc4 1823 req_ctx->to_hash_later = to_hash_later;
497f2e6b 1824
5e833bc4 1825 /* Allocate extended descriptor */
497f2e6b
LN		 1826 edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1827 if (IS_ERR(edesc))
1828 return PTR_ERR(edesc);
1829
1830 edesc->desc.hdr = ctx->desc_hdr_template;
1831
1832 /* On last one, request SEC to pad; otherwise continue */
1833 if (req_ctx->last)
1834 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1835 else
1836 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1837
60f208d7
KP		 1838 /* request SEC to INIT hash. */
1839 if (req_ctx->first && !req_ctx->swinit)
497f2e6b
LN		 1840 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1841
1842 /* When the tfm context has a keylen, it's an HMAC.
1843 * A first or last (ie. not middle) descriptor must request HMAC.
1844 */
1845 if (ctx->keylen && (req_ctx->first || req_ctx->last))
1846 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1847
1848 return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1849 ahash_done);
1850}
1851
1852static int ahash_update(struct ahash_request *areq)
1853{
1854 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1855
1856 req_ctx->last = 0;
1857
1858 return ahash_process_req(areq, areq->nbytes);
1859}
1860
1861static int ahash_final(struct ahash_request *areq)
1862{
1863 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1864
1865 req_ctx->last = 1;
1866
1867 return ahash_process_req(areq, 0);
1868}
1869
1870static int ahash_finup(struct ahash_request *areq)
1871{
1872 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1873
1874 req_ctx->last = 1;
1875
1876 return ahash_process_req(areq, areq->nbytes);
1877}
1878
1879static int ahash_digest(struct ahash_request *areq)
1880{
1881 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
60f208d7 1882 struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
497f2e6b 1883
60f208d7 1884 ahash->init(areq);
497f2e6b
LN		 1885 req_ctx->last = 1;
1886
1887 return ahash_process_req(areq, areq->nbytes);
1888}
1889
9c4a7965 1890struct talitos_alg_template {
d5e4aaef
LN		 1891 u32 type;
1892 union {
1893 struct crypto_alg crypto;
acbf7c62 1894 struct ahash_alg hash;
d5e4aaef 1895 } alg;
9c4a7965
KP		 1896 __be32 desc_hdr_template;
1897};
1898
1899static struct talitos_alg_template driver_algs[] = {
56af8cd4 1900 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
d5e4aaef
LN		 1901 { .type = CRYPTO_ALG_TYPE_AEAD,
1902 .alg.crypto = {
56af8cd4
LN		 1903 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1904 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1905 .cra_blocksize = AES_BLOCK_SIZE,
1906 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1907 .cra_type = &crypto_aead_type,
1908 .cra_aead = {
1909 .setkey = aead_setkey,
1910 .setauthsize = aead_setauthsize,
1911 .encrypt = aead_encrypt,
1912 .decrypt = aead_decrypt,
1913 .givencrypt = aead_givencrypt,
1914 .geniv = "<built-in>",
1915 .ivsize = AES_BLOCK_SIZE,
1916 .maxauthsize = SHA1_DIGEST_SIZE,
1917 }
1918 },
9c4a7965
KP		 1919 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1920 DESC_HDR_SEL0_AESU |
1921 DESC_HDR_MODE0_AESU_CBC |
1922 DESC_HDR_SEL1_MDEUA |
1923 DESC_HDR_MODE1_MDEU_INIT |
1924 DESC_HDR_MODE1_MDEU_PAD |
1925 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
70bcaca7 1926 },
d5e4aaef
LN		 1927 { .type = CRYPTO_ALG_TYPE_AEAD,
1928 .alg.crypto = {
56af8cd4
LN		 1929 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1930 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1931 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1932 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1933 .cra_type = &crypto_aead_type,
1934 .cra_aead = {
1935 .setkey = aead_setkey,
1936 .setauthsize = aead_setauthsize,
1937 .encrypt = aead_encrypt,
1938 .decrypt = aead_decrypt,
1939 .givencrypt = aead_givencrypt,
1940 .geniv = "<built-in>",
1941 .ivsize = DES3_EDE_BLOCK_SIZE,
1942 .maxauthsize = SHA1_DIGEST_SIZE,
1943 }
1944 },
70bcaca7
LN		 1945 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1946 DESC_HDR_SEL0_DEU |
1947 DESC_HDR_MODE0_DEU_CBC |
1948 DESC_HDR_MODE0_DEU_3DES |
1949 DESC_HDR_SEL1_MDEUA |
1950 DESC_HDR_MODE1_MDEU_INIT |
1951 DESC_HDR_MODE1_MDEU_PAD |
1952 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
3952f17e 1953 },
d5e4aaef
LN		 1954 { .type = CRYPTO_ALG_TYPE_AEAD,
1955 .alg.crypto = {
56af8cd4
LN		 1956 .cra_name = "authenc(hmac(sha256),cbc(aes))",
1957 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1958 .cra_blocksize = AES_BLOCK_SIZE,
1959 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1960 .cra_type = &crypto_aead_type,
1961 .cra_aead = {
1962 .setkey = aead_setkey,
1963 .setauthsize = aead_setauthsize,
1964 .encrypt = aead_encrypt,
1965 .decrypt = aead_decrypt,
1966 .givencrypt = aead_givencrypt,
1967 .geniv = "<built-in>",
1968 .ivsize = AES_BLOCK_SIZE,
1969 .maxauthsize = SHA256_DIGEST_SIZE,
1970 }
1971 },
3952f17e
LN		 1972 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1973 DESC_HDR_SEL0_AESU |
1974 DESC_HDR_MODE0_AESU_CBC |
1975 DESC_HDR_SEL1_MDEUA |
1976 DESC_HDR_MODE1_MDEU_INIT |
1977 DESC_HDR_MODE1_MDEU_PAD |
1978 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1979 },
d5e4aaef
LN		 1980 { .type = CRYPTO_ALG_TYPE_AEAD,
1981 .alg.crypto = {
56af8cd4
LN		 1982 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
1983 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1984 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1985 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1986 .cra_type = &crypto_aead_type,
1987 .cra_aead = {
1988 .setkey = aead_setkey,
1989 .setauthsize = aead_setauthsize,
1990 .encrypt = aead_encrypt,
1991 .decrypt = aead_decrypt,
1992 .givencrypt = aead_givencrypt,
1993 .geniv = "<built-in>",
1994 .ivsize = DES3_EDE_BLOCK_SIZE,
1995 .maxauthsize = SHA256_DIGEST_SIZE,
1996 }
1997 },
3952f17e
LN		 1998 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1999 DESC_HDR_SEL0_DEU |
2000 DESC_HDR_MODE0_DEU_CBC |
2001 DESC_HDR_MODE0_DEU_3DES |
2002 DESC_HDR_SEL1_MDEUA |
2003 DESC_HDR_MODE1_MDEU_INIT |
2004 DESC_HDR_MODE1_MDEU_PAD |
2005 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2006 },
d5e4aaef
LN		 2007 { .type = CRYPTO_ALG_TYPE_AEAD,
2008 .alg.crypto = {
56af8cd4
LN		 2009 .cra_name = "authenc(hmac(md5),cbc(aes))",
2010 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2011 .cra_blocksize = AES_BLOCK_SIZE,
2012 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2013 .cra_type = &crypto_aead_type,
2014 .cra_aead = {
2015 .setkey = aead_setkey,
2016 .setauthsize = aead_setauthsize,
2017 .encrypt = aead_encrypt,
2018 .decrypt = aead_decrypt,
2019 .givencrypt = aead_givencrypt,
2020 .geniv = "<built-in>",
2021 .ivsize = AES_BLOCK_SIZE,
2022 .maxauthsize = MD5_DIGEST_SIZE,
2023 }
2024 },
3952f17e
LN		 2025 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2026 DESC_HDR_SEL0_AESU |
2027 DESC_HDR_MODE0_AESU_CBC |
2028 DESC_HDR_SEL1_MDEUA |
2029 DESC_HDR_MODE1_MDEU_INIT |
2030 DESC_HDR_MODE1_MDEU_PAD |
2031 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2032 },
d5e4aaef
LN		 2033 { .type = CRYPTO_ALG_TYPE_AEAD,
2034 .alg.crypto = {
56af8cd4
LN		 2035 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2036 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2037 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2038 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2039 .cra_type = &crypto_aead_type,
2040 .cra_aead = {
2041 .setkey = aead_setkey,
2042 .setauthsize = aead_setauthsize,
2043 .encrypt = aead_encrypt,
2044 .decrypt = aead_decrypt,
2045 .givencrypt = aead_givencrypt,
2046 .geniv = "<built-in>",
2047 .ivsize = DES3_EDE_BLOCK_SIZE,
2048 .maxauthsize = MD5_DIGEST_SIZE,
2049 }
2050 },
3952f17e
LN		 2051 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2052 DESC_HDR_SEL0_DEU |
2053 DESC_HDR_MODE0_DEU_CBC |
2054 DESC_HDR_MODE0_DEU_3DES |
2055 DESC_HDR_SEL1_MDEUA |
2056 DESC_HDR_MODE1_MDEU_INIT |
2057 DESC_HDR_MODE1_MDEU_PAD |
2058 DESC_HDR_MODE1_MDEU_MD5_HMAC,
4de9d0b5
LN		 2059 },
2060 /* ABLKCIPHER algorithms. */
d5e4aaef
LN		 2061 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2062 .alg.crypto = {
4de9d0b5
LN		 2063 .cra_name = "cbc(aes)",
2064 .cra_driver_name = "cbc-aes-talitos",
2065 .cra_blocksize = AES_BLOCK_SIZE,
2066 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2067 CRYPTO_ALG_ASYNC,
2068 .cra_type = &crypto_ablkcipher_type,
2069 .cra_ablkcipher = {
2070 .setkey = ablkcipher_setkey,
2071 .encrypt = ablkcipher_encrypt,
2072 .decrypt = ablkcipher_decrypt,
2073 .geniv = "eseqiv",
2074 .min_keysize = AES_MIN_KEY_SIZE,
2075 .max_keysize = AES_MAX_KEY_SIZE,
2076 .ivsize = AES_BLOCK_SIZE,
2077 }
2078 },
2079 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2080 DESC_HDR_SEL0_AESU |
2081 DESC_HDR_MODE0_AESU_CBC,
2082 },
d5e4aaef
LN		 2083 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2084 .alg.crypto = {
4de9d0b5
LN		 2085 .cra_name = "cbc(des3_ede)",
2086 .cra_driver_name = "cbc-3des-talitos",
2087 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2088 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2089 CRYPTO_ALG_ASYNC,
2090 .cra_type = &crypto_ablkcipher_type,
2091 .cra_ablkcipher = {
2092 .setkey = ablkcipher_setkey,
2093 .encrypt = ablkcipher_encrypt,
2094 .decrypt = ablkcipher_decrypt,
2095 .geniv = "eseqiv",
2096 .min_keysize = DES3_EDE_KEY_SIZE,
2097 .max_keysize = DES3_EDE_KEY_SIZE,
2098 .ivsize = DES3_EDE_BLOCK_SIZE,
2099 }
2100 },
2101 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2102 DESC_HDR_SEL0_DEU |
2103 DESC_HDR_MODE0_DEU_CBC |
2104 DESC_HDR_MODE0_DEU_3DES,
497f2e6b
LN		 2105 },
2106 /* AHASH algorithms. */
2107 { .type = CRYPTO_ALG_TYPE_AHASH,
2108 .alg.hash = {
2109 .init = ahash_init,
2110 .update = ahash_update,
2111 .final = ahash_final,
2112 .finup = ahash_finup,
2113 .digest = ahash_digest,
2114 .halg.digestsize = MD5_DIGEST_SIZE,
2115 .halg.base = {
2116 .cra_name = "md5",
2117 .cra_driver_name = "md5-talitos",
2118 .cra_blocksize = MD5_BLOCK_SIZE,
2119 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2120 CRYPTO_ALG_ASYNC,
2121 .cra_type = &crypto_ahash_type
2122 }
2123 },
2124 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2125 DESC_HDR_SEL0_MDEUA |
2126 DESC_HDR_MODE0_MDEU_MD5,
2127 },
2128 { .type = CRYPTO_ALG_TYPE_AHASH,
2129 .alg.hash = {
2130 .init = ahash_init,
2131 .update = ahash_update,
2132 .final = ahash_final,
2133 .finup = ahash_finup,
2134 .digest = ahash_digest,
2135 .halg.digestsize = SHA1_DIGEST_SIZE,
2136 .halg.base = {
2137 .cra_name = "sha1",
2138 .cra_driver_name = "sha1-talitos",
2139 .cra_blocksize = SHA1_BLOCK_SIZE,
2140 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2141 CRYPTO_ALG_ASYNC,
2142 .cra_type = &crypto_ahash_type
2143 }
2144 },
2145 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2146 DESC_HDR_SEL0_MDEUA |
2147 DESC_HDR_MODE0_MDEU_SHA1,
2148 },
60f208d7
KP		 2149 { .type = CRYPTO_ALG_TYPE_AHASH,
2150 .alg.hash = {
2151 .init = ahash_init,
2152 .update = ahash_update,
2153 .final = ahash_final,
2154 .finup = ahash_finup,
2155 .digest = ahash_digest,
2156 .halg.digestsize = SHA224_DIGEST_SIZE,
2157 .halg.base = {
2158 .cra_name = "sha224",
2159 .cra_driver_name = "sha224-talitos",
2160 .cra_blocksize = SHA224_BLOCK_SIZE,
2161 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2162 CRYPTO_ALG_ASYNC,
2163 .cra_type = &crypto_ahash_type
2164 }
2165 },
2166 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2167 DESC_HDR_SEL0_MDEUA |
2168 DESC_HDR_MODE0_MDEU_SHA224,
2169 },
497f2e6b
LN		 2170 { .type = CRYPTO_ALG_TYPE_AHASH,
2171 .alg.hash = {
2172 .init = ahash_init,
2173 .update = ahash_update,
2174 .final = ahash_final,
2175 .finup = ahash_finup,
2176 .digest = ahash_digest,
2177 .halg.digestsize = SHA256_DIGEST_SIZE,
2178 .halg.base = {
2179 .cra_name = "sha256",
2180 .cra_driver_name = "sha256-talitos",
2181 .cra_blocksize = SHA256_BLOCK_SIZE,
2182 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2183 CRYPTO_ALG_ASYNC,
2184 .cra_type = &crypto_ahash_type
2185 }
2186 },
2187 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2188 DESC_HDR_SEL0_MDEUA |
2189 DESC_HDR_MODE0_MDEU_SHA256,
2190 },
2191 { .type = CRYPTO_ALG_TYPE_AHASH,
2192 .alg.hash = {
2193 .init = ahash_init,
2194 .update = ahash_update,
2195 .final = ahash_final,
2196 .finup = ahash_finup,
2197 .digest = ahash_digest,
2198 .halg.digestsize = SHA384_DIGEST_SIZE,
2199 .halg.base = {
2200 .cra_name = "sha384",
2201 .cra_driver_name = "sha384-talitos",
2202 .cra_blocksize = SHA384_BLOCK_SIZE,
2203 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2204 CRYPTO_ALG_ASYNC,
2205 .cra_type = &crypto_ahash_type
2206 }
2207 },
2208 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2209 DESC_HDR_SEL0_MDEUB |
2210 DESC_HDR_MODE0_MDEUB_SHA384,
2211 },
2212 { .type = CRYPTO_ALG_TYPE_AHASH,
2213 .alg.hash = {
2214 .init = ahash_init,
2215 .update = ahash_update,
2216 .final = ahash_final,
2217 .finup = ahash_finup,
2218 .digest = ahash_digest,
2219 .halg.digestsize = SHA512_DIGEST_SIZE,
2220 .halg.base = {
2221 .cra_name = "sha512",
2222 .cra_driver_name = "sha512-talitos",
2223 .cra_blocksize = SHA512_BLOCK_SIZE,
2224 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2225 CRYPTO_ALG_ASYNC,
2226 .cra_type = &crypto_ahash_type
2227 }
2228 },
2229 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2230 DESC_HDR_SEL0_MDEUB |
2231 DESC_HDR_MODE0_MDEUB_SHA512,
2232 },
9c4a7965
KP		 2233};
2234
2235struct talitos_crypto_alg {
2236 struct list_head entry;
2237 struct device *dev;
acbf7c62 2238 struct talitos_alg_template algt;
9c4a7965
KP		 2239};
2240
2241static int talitos_cra_init(struct crypto_tfm *tfm)
2242{
2243 struct crypto_alg *alg = tfm->__crt_alg;
19bbbc63 2244 struct talitos_crypto_alg *talitos_alg;
9c4a7965 2245 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
5228f0f7 2246 struct talitos_private *priv;
9c4a7965 2247
497f2e6b
LN		 2248 if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2249 talitos_alg = container_of(__crypto_ahash_alg(alg),
2250 struct talitos_crypto_alg,
2251 algt.alg.hash);
2252 else
2253 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2254 algt.alg.crypto);
19bbbc63 2255
9c4a7965
KP		 2256 /* update context with ptr to dev */
2257 ctx->dev = talitos_alg->dev;
19bbbc63 2258
5228f0f7
KP		 2259 /* assign SEC channel to tfm in round-robin fashion */
2260 priv = dev_get_drvdata(ctx->dev);
2261 ctx->ch = atomic_inc_return(&priv->last_chan) &
2262 (priv->num_channels - 1);
2263
9c4a7965 2264 /* copy descriptor header template value */
acbf7c62 2265 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
9c4a7965 2266
497f2e6b
LN		 2267 return 0;
2268}
2269
2270static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2271{
2272 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2273
2274 talitos_cra_init(tfm);
9c4a7965
KP		 2275
2276 /* random first IV */
70bcaca7 2277 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
9c4a7965
KP		 2278
2279 return 0;
2280}
2281
497f2e6b
LN		 2282static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2283{
2284 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2285
2286 talitos_cra_init(tfm);
2287
2288 ctx->keylen = 0;
2289 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2290 sizeof(struct talitos_ahash_req_ctx));
2291
2292 return 0;
2293}
2294
9c4a7965
KP		 2295/*
2296 * given the alg's descriptor header template, determine whether descriptor
2297 * type and primary/secondary execution units required match the hw
2298 * capabilities description provided in the device tree node.
2299 */
2300static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2301{
2302 struct talitos_private *priv = dev_get_drvdata(dev);
2303 int ret;
2304
2305 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2306 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2307
2308 if (SECONDARY_EU(desc_hdr_template))
2309 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2310 & priv->exec_units);
2311
2312 return ret;
2313}
2314
2dc11581 2315static int talitos_remove(struct platform_device *ofdev)
9c4a7965
KP		 2316{
2317 struct device *dev = &ofdev->dev;
2318 struct talitos_private *priv = dev_get_drvdata(dev);
2319 struct talitos_crypto_alg *t_alg, *n;
2320 int i;
2321
2322 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
acbf7c62
LN		 2323 switch (t_alg->algt.type) {
2324 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2325 case CRYPTO_ALG_TYPE_AEAD:
2326 crypto_unregister_alg(&t_alg->algt.alg.crypto);
2327 break;
2328 case CRYPTO_ALG_TYPE_AHASH:
2329 crypto_unregister_ahash(&t_alg->algt.alg.hash);
2330 break;
2331 }
9c4a7965
KP		 2332 list_del(&t_alg->entry);
2333 kfree(t_alg);
2334 }
2335
2336 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2337 talitos_unregister_rng(dev);
2338
4b992628 2339 for (i = 0; i < priv->num_channels; i++)
0b798247 2340 kfree(priv->chan[i].fifo);
9c4a7965 2341
4b992628 2342 kfree(priv->chan);
9c4a7965
KP		 2343
2344 if (priv->irq != NO_IRQ) {
2345 free_irq(priv->irq, dev);
2346 irq_dispose_mapping(priv->irq);
2347 }
2348
2349 tasklet_kill(&priv->done_task);
9c4a7965
KP		 2350
2351 iounmap(priv->reg);
2352
2353 dev_set_drvdata(dev, NULL);
2354
2355 kfree(priv);
2356
2357 return 0;
2358}
2359
2360static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2361 struct talitos_alg_template
2362 *template)
2363{
60f208d7 2364 struct talitos_private *priv = dev_get_drvdata(dev);
9c4a7965
KP		 2365 struct talitos_crypto_alg *t_alg;
2366 struct crypto_alg *alg;
2367
2368 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2369 if (!t_alg)
2370 return ERR_PTR(-ENOMEM);
2371
acbf7c62
LN		 2372 t_alg->algt = *template;
2373
2374 switch (t_alg->algt.type) {
2375 case CRYPTO_ALG_TYPE_ABLKCIPHER:
497f2e6b
LN		 2376 alg = &t_alg->algt.alg.crypto;
2377 alg->cra_init = talitos_cra_init;
2378 break;
acbf7c62
LN		 2379 case CRYPTO_ALG_TYPE_AEAD:
2380 alg = &t_alg->algt.alg.crypto;
497f2e6b 2381 alg->cra_init = talitos_cra_init_aead;
acbf7c62
LN		 2382 break;
2383 case CRYPTO_ALG_TYPE_AHASH:
2384 alg = &t_alg->algt.alg.hash.halg.base;
497f2e6b 2385 alg->cra_init = talitos_cra_init_ahash;
60f208d7
KP		 2386 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2387 !strcmp(alg->cra_name, "sha224")) {
2388 t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2389 t_alg->algt.desc_hdr_template =
2390 DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2391 DESC_HDR_SEL0_MDEUA |
2392 DESC_HDR_MODE0_MDEU_SHA256;
2393 }
497f2e6b 2394 break;
1d11911a
KP		 2395 default:
2396 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2397 return ERR_PTR(-EINVAL);
acbf7c62 2398 }
9c4a7965 2399
9c4a7965 2400 alg->cra_module = THIS_MODULE;
9c4a7965 2401 alg->cra_priority = TALITOS_CRA_PRIORITY;
9c4a7965 2402 alg->cra_alignmask = 0;
9c4a7965 2403 alg->cra_ctxsize = sizeof(struct talitos_ctx);
9c4a7965 2404
9c4a7965
KP		 2405 t_alg->dev = dev;
2406
2407 return t_alg;
2408}
2409
1c48a5c9 2410static int talitos_probe(struct platform_device *ofdev)
9c4a7965
KP		 2411{
2412 struct device *dev = &ofdev->dev;
61c7a080 2413 struct device_node *np = ofdev->dev.of_node;
9c4a7965
KP		 2414 struct talitos_private *priv;
2415 const unsigned int *prop;
2416 int i, err;
2417
2418 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2419 if (!priv)
2420 return -ENOMEM;
2421
2422 dev_set_drvdata(dev, priv);
2423
2424 priv->ofdev = ofdev;
2425
2426 tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
9c4a7965 2427
fe5720e2
KP		 2428 INIT_LIST_HEAD(&priv->alg_list);
2429
9c4a7965
KP		 2430 priv->irq = irq_of_parse_and_map(np, 0);
2431
2432 if (priv->irq == NO_IRQ) {
2433 dev_err(dev, "failed to map irq\n");
2434 err = -EINVAL;
2435 goto err_out;
2436 }
2437
2438 /* get the irq line */
2439 err = request_irq(priv->irq, talitos_interrupt, 0,
2440 dev_driver_string(dev), dev);
2441 if (err) {
2442 dev_err(dev, "failed to request irq %d\n", priv->irq);
2443 irq_dispose_mapping(priv->irq);
2444 priv->irq = NO_IRQ;
2445 goto err_out;
2446 }
2447
2448 priv->reg = of_iomap(np, 0);
2449 if (!priv->reg) {
2450 dev_err(dev, "failed to of_iomap\n");
2451 err = -ENOMEM;
2452 goto err_out;
2453 }
2454
2455 /* get SEC version capabilities from device tree */
2456 prop = of_get_property(np, "fsl,num-channels", NULL);
2457 if (prop)
2458 priv->num_channels = *prop;
2459
2460 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2461 if (prop)
2462 priv->chfifo_len = *prop;
2463
2464 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2465 if (prop)
2466 priv->exec_units = *prop;
2467
2468 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2469 if (prop)
2470 priv->desc_types = *prop;
2471
2472 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2473 !priv->exec_units || !priv->desc_types) {
2474 dev_err(dev, "invalid property data in device tree node\n");
2475 err = -EINVAL;
2476 goto err_out;
2477 }
2478
f3c85bc1
LN		 2479 if (of_device_is_compatible(np, "fsl,sec3.0"))
2480 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2481
fe5720e2 2482 if (of_device_is_compatible(np, "fsl,sec2.1"))
60f208d7
KP		 2483 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2484 TALITOS_FTR_SHA224_HWINIT;
fe5720e2 2485
4b992628
KP		 2486 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2487 priv->num_channels, GFP_KERNEL);
2488 if (!priv->chan) {
2489 dev_err(dev, "failed to allocate channel management space\n");
9c4a7965
KP		 2490 err = -ENOMEM;
2491 goto err_out;
2492 }
2493
2494 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2495 spin_lock_init(&priv->chan[i].head_lock);
2496 spin_lock_init(&priv->chan[i].tail_lock);
9c4a7965
KP		 2497 }
2498
2499 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2500
2501 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2502 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2503 priv->fifo_len, GFP_KERNEL);
2504 if (!priv->chan[i].fifo) {
9c4a7965
KP		 2505 dev_err(dev, "failed to allocate request fifo %d\n", i);
2506 err = -ENOMEM;
2507 goto err_out;
2508 }
2509 }
2510
ec6644d6 2511 for (i = 0; i < priv->num_channels; i++)
4b992628
KP		 2512 atomic_set(&priv->chan[i].submit_count,
2513 -(priv->chfifo_len - 1));
9c4a7965 2514
81eb024c
KP		 2515 dma_set_mask(dev, DMA_BIT_MASK(36));
2516
9c4a7965
KP		 2517 /* reset and initialize the h/w */
2518 err = init_device(dev);
2519 if (err) {
2520 dev_err(dev, "failed to initialize device\n");
2521 goto err_out;
2522 }
2523
2524 /* register the RNG, if available */
2525 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2526 err = talitos_register_rng(dev);
2527 if (err) {
2528 dev_err(dev, "failed to register hwrng: %d\n", err);
2529 goto err_out;
2530 } else
2531 dev_info(dev, "hwrng\n");
2532 }
2533
2534 /* register crypto algorithms the device supports */
9c4a7965
KP		 2535 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2536 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2537 struct talitos_crypto_alg *t_alg;
acbf7c62 2538 char *name = NULL;
9c4a7965
KP		 2539
2540 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2541 if (IS_ERR(t_alg)) {
2542 err = PTR_ERR(t_alg);
2543 goto err_out;
2544 }
2545
acbf7c62
LN		 2546 switch (t_alg->algt.type) {
2547 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2548 case CRYPTO_ALG_TYPE_AEAD:
2549 err = crypto_register_alg(
2550 &t_alg->algt.alg.crypto);
2551 name = t_alg->algt.alg.crypto.cra_driver_name;
2552 break;
2553 case CRYPTO_ALG_TYPE_AHASH:
2554 err = crypto_register_ahash(
2555 &t_alg->algt.alg.hash);
2556 name =
2557 t_alg->algt.alg.hash.halg.base.cra_driver_name;
2558 break;
2559 }
9c4a7965
KP		 2560 if (err) {
2561 dev_err(dev, "%s alg registration failed\n",
acbf7c62 2562 name);
9c4a7965
KP		 2563 kfree(t_alg);
2564 } else {
2565 list_add_tail(&t_alg->entry, &priv->alg_list);
acbf7c62 2566 dev_info(dev, "%s\n", name);
9c4a7965
KP		 2567 }
2568 }
2569 }
2570
2571 return 0;
2572
2573err_out:
2574 talitos_remove(ofdev);
9c4a7965
KP		 2575
2576 return err;
2577}
2578
6c3f975a 2579static const struct of_device_id talitos_match[] = {
9c4a7965
KP		 2580 {
2581 .compatible = "fsl,sec2.0",
2582 },
2583 {},
2584};
2585MODULE_DEVICE_TABLE(of, talitos_match);
2586
1c48a5c9 2587static struct platform_driver talitos_driver = {
4018294b
GL		 2588 .driver = {
2589 .name = "talitos",
2590 .owner = THIS_MODULE,
2591 .of_match_table = talitos_match,
2592 },
9c4a7965 2593 .probe = talitos_probe,
596f1034 2594 .remove = talitos_remove,
9c4a7965
KP		 2595};
2596
2597static int __init talitos_init(void)
2598{
1c48a5c9 2599 return platform_driver_register(&talitos_driver);
9c4a7965
KP		 2600}
2601module_init(talitos_init);
2602
2603static void __exit talitos_exit(void)
2604{
1c48a5c9 2605 platform_driver_unregister(&talitos_driver);
9c4a7965
KP		 2606}
2607module_exit(talitos_exit);
2608
2609MODULE_LICENSE("GPL");
2610MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2611MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
Linux 6.x block layer and io_uring tree(s)