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Change hash_64() return value to 32 bits
[linux-2.6-block.git] / drivers / crypto / omap-des.c
CommitLineData
e91aa9d5
JF		 1/*
2 * Support for OMAP DES and Triple DES HW acceleration.
3 *
4 * Copyright (c) 2013 Texas Instruments Incorporated
5 * Author: Joel Fernandes <joelf@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 *
11 */
12
13#define pr_fmt(fmt) "%s: " fmt, __func__
14
15#ifdef DEBUG
16#define prn(num) printk(#num "=%d\n", num)
17#define prx(num) printk(#num "=%x\n", num)
18#else
19#define prn(num) do { } while (0)
20#define prx(num) do { } while (0)
21#endif
22
23#include <linux/err.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/errno.h>
27#include <linux/kernel.h>
28#include <linux/platform_device.h>
29#include <linux/scatterlist.h>
30#include <linux/dma-mapping.h>
31#include <linux/dmaengine.h>
32#include <linux/omap-dma.h>
33#include <linux/pm_runtime.h>
34#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/of_address.h>
37#include <linux/io.h>
38#include <linux/crypto.h>
39#include <linux/interrupt.h>
40#include <crypto/scatterwalk.h>
41#include <crypto/des.h>
42
43#define DST_MAXBURST 2
44
45#define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
46
47#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
48
49#define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
50 ((x ^ 0x01) * 0x04))
51
52#define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
53
54#define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
55#define DES_REG_CTRL_CBC BIT(4)
56#define DES_REG_CTRL_TDES BIT(3)
57#define DES_REG_CTRL_DIRECTION BIT(2)
58#define DES_REG_CTRL_INPUT_READY BIT(1)
59#define DES_REG_CTRL_OUTPUT_READY BIT(0)
60
61#define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
62
63#define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
64
65#define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
66
67#define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
68
69#define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
70#define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
71#define DES_REG_IRQ_DATA_IN BIT(1)
72#define DES_REG_IRQ_DATA_OUT BIT(2)
73
74#define FLAGS_MODE_MASK 0x000f
75#define FLAGS_ENCRYPT BIT(0)
76#define FLAGS_CBC BIT(1)
77#define FLAGS_INIT BIT(4)
78#define FLAGS_BUSY BIT(6)
79
80struct omap_des_ctx {
81 struct omap_des_dev *dd;
82
83 int keylen;
84 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
85 unsigned long flags;
86};
87
88struct omap_des_reqctx {
89 unsigned long mode;
90};
91
92#define OMAP_DES_QUEUE_LENGTH 1
93#define OMAP_DES_CACHE_SIZE 0
94
95struct omap_des_algs_info {
96 struct crypto_alg *algs_list;
97 unsigned int size;
98 unsigned int registered;
99};
100
101struct omap_des_pdata {
102 struct omap_des_algs_info *algs_info;
103 unsigned int algs_info_size;
104
105 void (*trigger)(struct omap_des_dev *dd, int length);
106
107 u32 key_ofs;
108 u32 iv_ofs;
109 u32 ctrl_ofs;
110 u32 data_ofs;
111 u32 rev_ofs;
112 u32 mask_ofs;
113 u32 irq_enable_ofs;
114 u32 irq_status_ofs;
115
116 u32 dma_enable_in;
117 u32 dma_enable_out;
118 u32 dma_start;
119
120 u32 major_mask;
121 u32 major_shift;
122 u32 minor_mask;
123 u32 minor_shift;
124};
125
126struct omap_des_dev {
127 struct list_head list;
128 unsigned long phys_base;
129 void __iomem *io_base;
130 struct omap_des_ctx *ctx;
131 struct device *dev;
132 unsigned long flags;
133 int err;
134
135 /* spinlock used for queues */
136 spinlock_t lock;
137 struct crypto_queue queue;
138
139 struct tasklet_struct done_task;
140 struct tasklet_struct queue_task;
141
142 struct ablkcipher_request *req;
143 /*
144 * total is used by PIO mode for book keeping so introduce
145 * variable total_save as need it to calc page_order
146 */
147 size_t total;
148 size_t total_save;
149
150 struct scatterlist *in_sg;
151 struct scatterlist *out_sg;
152
153 /* Buffers for copying for unaligned cases */
154 struct scatterlist in_sgl;
155 struct scatterlist out_sgl;
156 struct scatterlist *orig_out;
157 int sgs_copied;
158
159 struct scatter_walk in_walk;
160 struct scatter_walk out_walk;
161 int dma_in;
162 struct dma_chan *dma_lch_in;
163 int dma_out;
164 struct dma_chan *dma_lch_out;
165 int in_sg_len;
166 int out_sg_len;
167 int pio_only;
168 const struct omap_des_pdata *pdata;
169};
170
171/* keep registered devices data here */
172static LIST_HEAD(dev_list);
173static DEFINE_SPINLOCK(list_lock);
174
175#ifdef DEBUG
176#define omap_des_read(dd, offset) \
177 ({ \
178 int _read_ret; \
179 _read_ret = __raw_readl(dd->io_base + offset); \
180 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
181 offset, _read_ret); \
182 _read_ret; \
183 })
184#else
185static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
186{
187 return __raw_readl(dd->io_base + offset);
188}
189#endif
190
191#ifdef DEBUG
192#define omap_des_write(dd, offset, value) \
193 do { \
194 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
195 offset, value); \
196 __raw_writel(value, dd->io_base + offset); \
197 } while (0)
198#else
199static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
200 u32 value)
201{
202 __raw_writel(value, dd->io_base + offset);
203}
204#endif
205
206static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
207 u32 value, u32 mask)
208{
209 u32 val;
210
211 val = omap_des_read(dd, offset);
212 val &= ~mask;
213 val |= value;
214 omap_des_write(dd, offset, val);
215}
216
217static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
218 u32 *value, int count)
219{
220 for (; count--; value++, offset += 4)
221 omap_des_write(dd, offset, *value);
222}
223
224static int omap_des_hw_init(struct omap_des_dev *dd)
225{
f51f593b
NM		 226 int err;
227
e91aa9d5
JF		 228 /*
229 * clocks are enabled when request starts and disabled when finished.
230 * It may be long delays between requests.
231 * Device might go to off mode to save power.
232 */
f51f593b
NM		 233 err = pm_runtime_get_sync(dd->dev);
234 if (err < 0) {
235 pm_runtime_put_noidle(dd->dev);
236 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
237 return err;
238 }
e91aa9d5
JF		 239
240 if (!(dd->flags & FLAGS_INIT)) {
241 dd->flags |= FLAGS_INIT;
242 dd->err = 0;
243 }
244
245 return 0;
246}
247
248static int omap_des_write_ctrl(struct omap_des_dev *dd)
249{
250 unsigned int key32;
251 int i, err;
252 u32 val = 0, mask = 0;
253
254 err = omap_des_hw_init(dd);
255 if (err)
256 return err;
257
258 key32 = dd->ctx->keylen / sizeof(u32);
259
260 /* it seems a key should always be set even if it has not changed */
261 for (i = 0; i < key32; i++) {
262 omap_des_write(dd, DES_REG_KEY(dd, i),
263 __le32_to_cpu(dd->ctx->key[i]));
264 }
265
266 if ((dd->flags & FLAGS_CBC) && dd->req->info)
267 omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2);
268
269 if (dd->flags & FLAGS_CBC)
270 val |= DES_REG_CTRL_CBC;
271 if (dd->flags & FLAGS_ENCRYPT)
272 val |= DES_REG_CTRL_DIRECTION;
273 if (key32 == 6)
274 val |= DES_REG_CTRL_TDES;
275
276 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
277
278 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
279
280 return 0;
281}
282
283static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
284{
285 u32 mask, val;
286
287 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
288
289 val = dd->pdata->dma_start;
290
291 if (dd->dma_lch_out != NULL)
292 val |= dd->pdata->dma_enable_out;
293 if (dd->dma_lch_in != NULL)
294 val |= dd->pdata->dma_enable_in;
295
296 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
297 dd->pdata->dma_start;
298
299 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
300}
301
302static void omap_des_dma_stop(struct omap_des_dev *dd)
303{
304 u32 mask;
305
306 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
307 dd->pdata->dma_start;
308
309 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
310}
311
312static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
313{
314 struct omap_des_dev *dd = NULL, *tmp;
315
316 spin_lock_bh(&list_lock);
317 if (!ctx->dd) {
318 list_for_each_entry(tmp, &dev_list, list) {
319 /* FIXME: take fist available des core */
320 dd = tmp;
321 break;
322 }
323 ctx->dd = dd;
324 } else {
325 /* already found before */
326 dd = ctx->dd;
327 }
328 spin_unlock_bh(&list_lock);
329
330 return dd;
331}
332
333static void omap_des_dma_out_callback(void *data)
334{
335 struct omap_des_dev *dd = data;
336
337 /* dma_lch_out - completed */
338 tasklet_schedule(&dd->done_task);
339}
340
341static int omap_des_dma_init(struct omap_des_dev *dd)
342{
343 int err = -ENOMEM;
344 dma_cap_mask_t mask;
345
346 dd->dma_lch_out = NULL;
347 dd->dma_lch_in = NULL;
348
349 dma_cap_zero(mask);
350 dma_cap_set(DMA_SLAVE, mask);
351
352 dd->dma_lch_in = dma_request_slave_channel_compat(mask,
353 omap_dma_filter_fn,
354 &dd->dma_in,
355 dd->dev, "rx");
356 if (!dd->dma_lch_in) {
357 dev_err(dd->dev, "Unable to request in DMA channel\n");
358 goto err_dma_in;
359 }
360
361 dd->dma_lch_out = dma_request_slave_channel_compat(mask,
362 omap_dma_filter_fn,
363 &dd->dma_out,
364 dd->dev, "tx");
365 if (!dd->dma_lch_out) {
366 dev_err(dd->dev, "Unable to request out DMA channel\n");
367 goto err_dma_out;
368 }
369
370 return 0;
371
372err_dma_out:
373 dma_release_channel(dd->dma_lch_in);
374err_dma_in:
375 if (err)
376 pr_err("error: %d\n", err);
377 return err;
378}
379
380static void omap_des_dma_cleanup(struct omap_des_dev *dd)
381{
382 dma_release_channel(dd->dma_lch_out);
383 dma_release_channel(dd->dma_lch_in);
384}
385
386static void sg_copy_buf(void *buf, struct scatterlist *sg,
387 unsigned int start, unsigned int nbytes, int out)
388{
389 struct scatter_walk walk;
390
391 if (!nbytes)
392 return;
393
394 scatterwalk_start(&walk, sg);
395 scatterwalk_advance(&walk, start);
396 scatterwalk_copychunks(buf, &walk, nbytes, out);
397 scatterwalk_done(&walk, out, 0);
398}
399
400static int omap_des_crypt_dma(struct crypto_tfm *tfm,
401 struct scatterlist *in_sg, struct scatterlist *out_sg,
402 int in_sg_len, int out_sg_len)
403{
404 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
405 struct omap_des_dev *dd = ctx->dd;
406 struct dma_async_tx_descriptor *tx_in, *tx_out;
407 struct dma_slave_config cfg;
408 int ret;
409
410 if (dd->pio_only) {
411 scatterwalk_start(&dd->in_walk, dd->in_sg);
412 scatterwalk_start(&dd->out_walk, dd->out_sg);
413
414 /* Enable DATAIN interrupt and let it take
415 care of the rest */
416 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
417 return 0;
418 }
419
420 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
421
422 memset(&cfg, 0, sizeof(cfg));
423
424 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
425 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
426 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
427 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
428 cfg.src_maxburst = DST_MAXBURST;
429 cfg.dst_maxburst = DST_MAXBURST;
430
431 /* IN */
432 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
433 if (ret) {
434 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
435 ret);
436 return ret;
437 }
438
439 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
440 DMA_MEM_TO_DEV,
441 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
442 if (!tx_in) {
443 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
444 return -EINVAL;
445 }
446
447 /* No callback necessary */
448 tx_in->callback_param = dd;
449
450 /* OUT */
451 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
452 if (ret) {
453 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
454 ret);
455 return ret;
456 }
457
458 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
459 DMA_DEV_TO_MEM,
460 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
461 if (!tx_out) {
462 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
463 return -EINVAL;
464 }
465
466 tx_out->callback = omap_des_dma_out_callback;
467 tx_out->callback_param = dd;
468
469 dmaengine_submit(tx_in);
470 dmaengine_submit(tx_out);
471
472 dma_async_issue_pending(dd->dma_lch_in);
473 dma_async_issue_pending(dd->dma_lch_out);
474
475 /* start DMA */
476 dd->pdata->trigger(dd, dd->total);
477
478 return 0;
479}
480
481static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
482{
483 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
484 crypto_ablkcipher_reqtfm(dd->req));
485 int err;
486
487 pr_debug("total: %d\n", dd->total);
488
489 if (!dd->pio_only) {
490 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
491 DMA_TO_DEVICE);
492 if (!err) {
493 dev_err(dd->dev, "dma_map_sg() error\n");
494 return -EINVAL;
495 }
496
497 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
498 DMA_FROM_DEVICE);
499 if (!err) {
500 dev_err(dd->dev, "dma_map_sg() error\n");
501 return -EINVAL;
502 }
503 }
504
505 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
506 dd->out_sg_len);
507 if (err && !dd->pio_only) {
508 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
509 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
510 DMA_FROM_DEVICE);
511 }
512
513 return err;
514}
515
516static void omap_des_finish_req(struct omap_des_dev *dd, int err)
517{
518 struct ablkcipher_request *req = dd->req;
519
520 pr_debug("err: %d\n", err);
521
522 pm_runtime_put(dd->dev);
523 dd->flags &= ~FLAGS_BUSY;
524
525 req->base.complete(&req->base, err);
526}
527
528static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
529{
e91aa9d5
JF		 530 pr_debug("total: %d\n", dd->total);
531
532 omap_des_dma_stop(dd);
533
534 dmaengine_terminate_all(dd->dma_lch_in);
535 dmaengine_terminate_all(dd->dma_lch_out);
536
16f080aa 537 return 0;
e91aa9d5
JF		 538}
539
26f25b26 540static int omap_des_copy_needed(struct scatterlist *sg)
e91aa9d5
JF		 541{
542 while (sg) {
543 if (!IS_ALIGNED(sg->offset, 4))
544 return -1;
545 if (!IS_ALIGNED(sg->length, DES_BLOCK_SIZE))
546 return -1;
547 sg = sg_next(sg);
548 }
549 return 0;
550}
551
26f25b26 552static int omap_des_copy_sgs(struct omap_des_dev *dd)
e91aa9d5
JF		 553{
554 void *buf_in, *buf_out;
555 int pages;
556
557 pages = dd->total >> PAGE_SHIFT;
558
559 if (dd->total & (PAGE_SIZE-1))
560 pages++;
561
562 BUG_ON(!pages);
563
564 buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
565 buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
566
567 if (!buf_in || !buf_out) {
568 pr_err("Couldn't allocated pages for unaligned cases.\n");
569 return -1;
570 }
571
572 dd->orig_out = dd->out_sg;
573
574 sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
575
576 sg_init_table(&dd->in_sgl, 1);
577 sg_set_buf(&dd->in_sgl, buf_in, dd->total);
578 dd->in_sg = &dd->in_sgl;
579
580 sg_init_table(&dd->out_sgl, 1);
581 sg_set_buf(&dd->out_sgl, buf_out, dd->total);
582 dd->out_sg = &dd->out_sgl;
583
584 return 0;
585}
586
587static int omap_des_handle_queue(struct omap_des_dev *dd,
588 struct ablkcipher_request *req)
589{
590 struct crypto_async_request *async_req, *backlog;
591 struct omap_des_ctx *ctx;
592 struct omap_des_reqctx *rctx;
593 unsigned long flags;
594 int err, ret = 0;
595
596 spin_lock_irqsave(&dd->lock, flags);
597 if (req)
598 ret = ablkcipher_enqueue_request(&dd->queue, req);
599 if (dd->flags & FLAGS_BUSY) {
600 spin_unlock_irqrestore(&dd->lock, flags);
601 return ret;
602 }
603 backlog = crypto_get_backlog(&dd->queue);
604 async_req = crypto_dequeue_request(&dd->queue);
605 if (async_req)
606 dd->flags |= FLAGS_BUSY;
607 spin_unlock_irqrestore(&dd->lock, flags);
608
609 if (!async_req)
610 return ret;
611
612 if (backlog)
613 backlog->complete(backlog, -EINPROGRESS);
614
615 req = ablkcipher_request_cast(async_req);
616
617 /* assign new request to device */
618 dd->req = req;
619 dd->total = req->nbytes;
620 dd->total_save = req->nbytes;
621 dd->in_sg = req->src;
622 dd->out_sg = req->dst;
623
624 if (omap_des_copy_needed(dd->in_sg) ||
625 omap_des_copy_needed(dd->out_sg)) {
626 if (omap_des_copy_sgs(dd))
627 pr_err("Failed to copy SGs for unaligned cases\n");
628 dd->sgs_copied = 1;
629 } else {
630 dd->sgs_copied = 0;
631 }
632
633 dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total);
634 dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total);
635 BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0);
636
637 rctx = ablkcipher_request_ctx(req);
638 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
639 rctx->mode &= FLAGS_MODE_MASK;
640 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
641
642 dd->ctx = ctx;
643 ctx->dd = dd;
644
645 err = omap_des_write_ctrl(dd);
646 if (!err)
647 err = omap_des_crypt_dma_start(dd);
648 if (err) {
649 /* des_task will not finish it, so do it here */
650 omap_des_finish_req(dd, err);
651 tasklet_schedule(&dd->queue_task);
652 }
653
654 return ret; /* return ret, which is enqueue return value */
655}
656
657static void omap_des_done_task(unsigned long data)
658{
659 struct omap_des_dev *dd = (struct omap_des_dev *)data;
660 void *buf_in, *buf_out;
661 int pages;
662
663 pr_debug("enter done_task\n");
664
665 if (!dd->pio_only) {
666 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
667 DMA_FROM_DEVICE);
668 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
669 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
670 DMA_FROM_DEVICE);
671 omap_des_crypt_dma_stop(dd);
672 }
673
674 if (dd->sgs_copied) {
675 buf_in = sg_virt(&dd->in_sgl);
676 buf_out = sg_virt(&dd->out_sgl);
677
678 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
679
680 pages = get_order(dd->total_save);
681 free_pages((unsigned long)buf_in, pages);
682 free_pages((unsigned long)buf_out, pages);
683 }
684
685 omap_des_finish_req(dd, 0);
686 omap_des_handle_queue(dd, NULL);
687
688 pr_debug("exit\n");
689}
690
691static void omap_des_queue_task(unsigned long data)
692{
693 struct omap_des_dev *dd = (struct omap_des_dev *)data;
694
695 omap_des_handle_queue(dd, NULL);
696}
697
698static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode)
699{
700 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
701 crypto_ablkcipher_reqtfm(req));
702 struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req);
703 struct omap_des_dev *dd;
704
705 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
706 !!(mode & FLAGS_ENCRYPT),
707 !!(mode & FLAGS_CBC));
708
709 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
710 pr_err("request size is not exact amount of DES blocks\n");
711 return -EINVAL;
712 }
713
714 dd = omap_des_find_dev(ctx);
715 if (!dd)
716 return -ENODEV;
717
718 rctx->mode = mode;
719
720 return omap_des_handle_queue(dd, req);
721}
722
723/* ********************** ALG API ************************************ */
724
725static int omap_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
726 unsigned int keylen)
727{
728 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(tfm);
729
730 if (keylen != DES_KEY_SIZE && keylen != (3*DES_KEY_SIZE))
731 return -EINVAL;
732
733 pr_debug("enter, keylen: %d\n", keylen);
734
735 memcpy(ctx->key, key, keylen);
736 ctx->keylen = keylen;
737
738 return 0;
739}
740
741static int omap_des_ecb_encrypt(struct ablkcipher_request *req)
742{
743 return omap_des_crypt(req, FLAGS_ENCRYPT);
744}
745
746static int omap_des_ecb_decrypt(struct ablkcipher_request *req)
747{
748 return omap_des_crypt(req, 0);
749}
750
751static int omap_des_cbc_encrypt(struct ablkcipher_request *req)
752{
753 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
754}
755
756static int omap_des_cbc_decrypt(struct ablkcipher_request *req)
757{
758 return omap_des_crypt(req, FLAGS_CBC);
759}
760
761static int omap_des_cra_init(struct crypto_tfm *tfm)
762{
763 pr_debug("enter\n");
764
765 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx);
766
767 return 0;
768}
769
770static void omap_des_cra_exit(struct crypto_tfm *tfm)
771{
772 pr_debug("enter\n");
773}
774
775/* ********************** ALGS ************************************ */
776
777static struct crypto_alg algs_ecb_cbc[] = {
778{
779 .cra_name = "ecb(des)",
780 .cra_driver_name = "ecb-des-omap",
781 .cra_priority = 100,
782 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
783 CRYPTO_ALG_KERN_DRIVER_ONLY |
784 CRYPTO_ALG_ASYNC,
785 .cra_blocksize = DES_BLOCK_SIZE,
786 .cra_ctxsize = sizeof(struct omap_des_ctx),
787 .cra_alignmask = 0,
788 .cra_type = &crypto_ablkcipher_type,
789 .cra_module = THIS_MODULE,
790 .cra_init = omap_des_cra_init,
791 .cra_exit = omap_des_cra_exit,
792 .cra_u.ablkcipher = {
793 .min_keysize = DES_KEY_SIZE,
794 .max_keysize = DES_KEY_SIZE,
795 .setkey = omap_des_setkey,
796 .encrypt = omap_des_ecb_encrypt,
797 .decrypt = omap_des_ecb_decrypt,
798 }
799},
800{
801 .cra_name = "cbc(des)",
802 .cra_driver_name = "cbc-des-omap",
803 .cra_priority = 100,
804 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
805 CRYPTO_ALG_KERN_DRIVER_ONLY |
806 CRYPTO_ALG_ASYNC,
807 .cra_blocksize = DES_BLOCK_SIZE,
808 .cra_ctxsize = sizeof(struct omap_des_ctx),
809 .cra_alignmask = 0,
810 .cra_type = &crypto_ablkcipher_type,
811 .cra_module = THIS_MODULE,
812 .cra_init = omap_des_cra_init,
813 .cra_exit = omap_des_cra_exit,
814 .cra_u.ablkcipher = {
815 .min_keysize = DES_KEY_SIZE,
816 .max_keysize = DES_KEY_SIZE,
817 .ivsize = DES_BLOCK_SIZE,
818 .setkey = omap_des_setkey,
819 .encrypt = omap_des_cbc_encrypt,
820 .decrypt = omap_des_cbc_decrypt,
821 }
822},
823{
824 .cra_name = "ecb(des3_ede)",
825 .cra_driver_name = "ecb-des3-omap",
826 .cra_priority = 100,
827 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
828 CRYPTO_ALG_KERN_DRIVER_ONLY |
829 CRYPTO_ALG_ASYNC,
830 .cra_blocksize = DES_BLOCK_SIZE,
831 .cra_ctxsize = sizeof(struct omap_des_ctx),
832 .cra_alignmask = 0,
833 .cra_type = &crypto_ablkcipher_type,
834 .cra_module = THIS_MODULE,
835 .cra_init = omap_des_cra_init,
836 .cra_exit = omap_des_cra_exit,
837 .cra_u.ablkcipher = {
838 .min_keysize = 3*DES_KEY_SIZE,
839 .max_keysize = 3*DES_KEY_SIZE,
840 .setkey = omap_des_setkey,
841 .encrypt = omap_des_ecb_encrypt,
842 .decrypt = omap_des_ecb_decrypt,
843 }
844},
845{
846 .cra_name = "cbc(des3_ede)",
847 .cra_driver_name = "cbc-des3-omap",
848 .cra_priority = 100,
849 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
850 CRYPTO_ALG_KERN_DRIVER_ONLY |
851 CRYPTO_ALG_ASYNC,
852 .cra_blocksize = DES_BLOCK_SIZE,
853 .cra_ctxsize = sizeof(struct omap_des_ctx),
854 .cra_alignmask = 0,
855 .cra_type = &crypto_ablkcipher_type,
856 .cra_module = THIS_MODULE,
857 .cra_init = omap_des_cra_init,
858 .cra_exit = omap_des_cra_exit,
859 .cra_u.ablkcipher = {
860 .min_keysize = 3*DES_KEY_SIZE,
861 .max_keysize = 3*DES_KEY_SIZE,
862 .ivsize = DES_BLOCK_SIZE,
863 .setkey = omap_des_setkey,
864 .encrypt = omap_des_cbc_encrypt,
865 .decrypt = omap_des_cbc_decrypt,
866 }
867}
868};
869
870static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
871 {
872 .algs_list = algs_ecb_cbc,
873 .size = ARRAY_SIZE(algs_ecb_cbc),
874 },
875};
876
877#ifdef CONFIG_OF
878static const struct omap_des_pdata omap_des_pdata_omap4 = {
879 .algs_info = omap_des_algs_info_ecb_cbc,
880 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
881 .trigger = omap_des_dma_trigger_omap4,
882 .key_ofs = 0x14,
883 .iv_ofs = 0x18,
884 .ctrl_ofs = 0x20,
885 .data_ofs = 0x28,
886 .rev_ofs = 0x30,
887 .mask_ofs = 0x34,
888 .irq_status_ofs = 0x3c,
889 .irq_enable_ofs = 0x40,
890 .dma_enable_in = BIT(5),
891 .dma_enable_out = BIT(6),
892 .major_mask = 0x0700,
893 .major_shift = 8,
894 .minor_mask = 0x003f,
895 .minor_shift = 0,
896};
897
898static irqreturn_t omap_des_irq(int irq, void *dev_id)
899{
900 struct omap_des_dev *dd = dev_id;
901 u32 status, i;
902 u32 *src, *dst;
903
904 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
905 if (status & DES_REG_IRQ_DATA_IN) {
906 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
907
908 BUG_ON(!dd->in_sg);
909
910 BUG_ON(_calc_walked(in) > dd->in_sg->length);
911
912 src = sg_virt(dd->in_sg) + _calc_walked(in);
913
914 for (i = 0; i < DES_BLOCK_WORDS; i++) {
915 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
916
917 scatterwalk_advance(&dd->in_walk, 4);
918 if (dd->in_sg->length == _calc_walked(in)) {
5be4d4c9 919 dd->in_sg = sg_next(dd->in_sg);
e91aa9d5
JF		 920 if (dd->in_sg) {
921 scatterwalk_start(&dd->in_walk,
922 dd->in_sg);
923 src = sg_virt(dd->in_sg) +
924 _calc_walked(in);
925 }
926 } else {
927 src++;
928 }
929 }
930
931 /* Clear IRQ status */
932 status &= ~DES_REG_IRQ_DATA_IN;
933 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
934
935 /* Enable DATA_OUT interrupt */
936 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
937
938 } else if (status & DES_REG_IRQ_DATA_OUT) {
939 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
940
941 BUG_ON(!dd->out_sg);
942
943 BUG_ON(_calc_walked(out) > dd->out_sg->length);
944
945 dst = sg_virt(dd->out_sg) + _calc_walked(out);
946
947 for (i = 0; i < DES_BLOCK_WORDS; i++) {
948 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
949 scatterwalk_advance(&dd->out_walk, 4);
950 if (dd->out_sg->length == _calc_walked(out)) {
5be4d4c9 951 dd->out_sg = sg_next(dd->out_sg);
e91aa9d5
JF		 952 if (dd->out_sg) {
953 scatterwalk_start(&dd->out_walk,
954 dd->out_sg);
955 dst = sg_virt(dd->out_sg) +
956 _calc_walked(out);
957 }
958 } else {
959 dst++;
960 }
961 }
962
42d2e780 963 BUG_ON(dd->total < DES_BLOCK_SIZE);
e91aa9d5 964
42d2e780 965 dd->total -= DES_BLOCK_SIZE;
e91aa9d5
JF		 966
967 /* Clear IRQ status */
968 status &= ~DES_REG_IRQ_DATA_OUT;
969 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
970
971 if (!dd->total)
972 /* All bytes read! */
973 tasklet_schedule(&dd->done_task);
974 else
975 /* Enable DATA_IN interrupt for next block */
976 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
977 }
978
979 return IRQ_HANDLED;
980}
981
982static const struct of_device_id omap_des_of_match[] = {
983 {
984 .compatible = "ti,omap4-des",
985 .data = &omap_des_pdata_omap4,
986 },
987 {},
988};
989MODULE_DEVICE_TABLE(of, omap_des_of_match);
990
991static int omap_des_get_of(struct omap_des_dev *dd,
992 struct platform_device *pdev)
993{
994 const struct of_device_id *match;
995
996 match = of_match_device(of_match_ptr(omap_des_of_match), &pdev->dev);
997 if (!match) {
998 dev_err(&pdev->dev, "no compatible OF match\n");
999 return -EINVAL;
1000 }
1001
1002 dd->dma_out = -1; /* Dummy value that's unused */
1003 dd->dma_in = -1; /* Dummy value that's unused */
1004 dd->pdata = match->data;
1005
1006 return 0;
1007}
1008#else
1009static int omap_des_get_of(struct omap_des_dev *dd,
1010 struct device *dev)
1011{
1012 return -EINVAL;
1013}
1014#endif
1015
1016static int omap_des_get_pdev(struct omap_des_dev *dd,
1017 struct platform_device *pdev)
1018{
1019 struct device *dev = &pdev->dev;
1020 struct resource *r;
1021 int err = 0;
1022
1023 /* Get the DMA out channel */
1024 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1025 if (!r) {
1026 dev_err(dev, "no DMA out resource info\n");
1027 err = -ENODEV;
1028 goto err;
1029 }
1030 dd->dma_out = r->start;
1031
1032 /* Get the DMA in channel */
1033 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1034 if (!r) {
1035 dev_err(dev, "no DMA in resource info\n");
1036 err = -ENODEV;
1037 goto err;
1038 }
1039 dd->dma_in = r->start;
1040
1041 /* non-DT devices get pdata from pdev */
1042 dd->pdata = pdev->dev.platform_data;
1043
1044err:
1045 return err;
1046}
1047
1048static int omap_des_probe(struct platform_device *pdev)
1049{
1050 struct device *dev = &pdev->dev;
1051 struct omap_des_dev *dd;
1052 struct crypto_alg *algp;
1053 struct resource *res;
1054 int err = -ENOMEM, i, j, irq = -1;
1055 u32 reg;
1056
1057 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
1058 if (dd == NULL) {
1059 dev_err(dev, "unable to alloc data struct.\n");
1060 goto err_data;
1061 }
1062 dd->dev = dev;
1063 platform_set_drvdata(pdev, dd);
1064
1065 spin_lock_init(&dd->lock);
1066 crypto_init_queue(&dd->queue, OMAP_DES_QUEUE_LENGTH);
1067
1068 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1069 if (!res) {
1070 dev_err(dev, "no MEM resource info\n");
1071 goto err_res;
1072 }
1073
1074 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
1075 omap_des_get_pdev(dd, pdev);
1076 if (err)
1077 goto err_res;
1078
2496be2e
JH		 1079 dd->io_base = devm_ioremap_resource(dev, res);
1080 if (IS_ERR(dd->io_base)) {
1081 err = PTR_ERR(dd->io_base);
e91aa9d5
JF		 1082 goto err_res;
1083 }
1084 dd->phys_base = res->start;
1085
1086 pm_runtime_enable(dev);
50eca256 1087 pm_runtime_irq_safe(dev);
f51f593b
NM		 1088 err = pm_runtime_get_sync(dev);
1089 if (err < 0) {
1090 pm_runtime_put_noidle(dev);
1091 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
1092 goto err_get;
1093 }
e91aa9d5
JF		 1094
1095 omap_des_dma_stop(dd);
1096
1097 reg = omap_des_read(dd, DES_REG_REV(dd));
1098
1099 pm_runtime_put_sync(dev);
1100
1101 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
1102 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1103 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1104
1105 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
1106 tasklet_init(&dd->queue_task, omap_des_queue_task, (unsigned long)dd);
1107
1108 err = omap_des_dma_init(dd);
1109 if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
1110 dd->pio_only = 1;
1111
1112 irq = platform_get_irq(pdev, 0);
1113 if (irq < 0) {
1114 dev_err(dev, "can't get IRQ resource\n");
1115 goto err_irq;
1116 }
1117
1118 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1119 dev_name(dev), dd);
1120 if (err) {
1121 dev_err(dev, "Unable to grab omap-des IRQ\n");
1122 goto err_irq;
1123 }
1124 }
1125
1126
1127 INIT_LIST_HEAD(&dd->list);
1128 spin_lock(&list_lock);
1129 list_add_tail(&dd->list, &dev_list);
1130 spin_unlock(&list_lock);
1131
1132 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1133 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1134 algp = &dd->pdata->algs_info[i].algs_list[j];
1135
1136 pr_debug("reg alg: %s\n", algp->cra_name);
1137 INIT_LIST_HEAD(&algp->cra_list);
1138
1139 err = crypto_register_alg(algp);
1140 if (err)
1141 goto err_algs;
1142
1143 dd->pdata->algs_info[i].registered++;
1144 }
1145 }
1146
1147 return 0;
1148err_algs:
1149 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1150 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1151 crypto_unregister_alg(
1152 &dd->pdata->algs_info[i].algs_list[j]);
1153 if (!dd->pio_only)
1154 omap_des_dma_cleanup(dd);
1155err_irq:
1156 tasklet_kill(&dd->done_task);
1157 tasklet_kill(&dd->queue_task);
f51f593b 1158err_get:
e91aa9d5
JF		 1159 pm_runtime_disable(dev);
1160err_res:
1161 dd = NULL;
1162err_data:
1163 dev_err(dev, "initialization failed.\n");
1164 return err;
1165}
1166
1167static int omap_des_remove(struct platform_device *pdev)
1168{
1169 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1170 int i, j;
1171
1172 if (!dd)
1173 return -ENODEV;
1174
1175 spin_lock(&list_lock);
1176 list_del(&dd->list);
1177 spin_unlock(&list_lock);
1178
1179 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1180 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1181 crypto_unregister_alg(
1182 &dd->pdata->algs_info[i].algs_list[j]);
1183
1184 tasklet_kill(&dd->done_task);
1185 tasklet_kill(&dd->queue_task);
1186 omap_des_dma_cleanup(dd);
1187 pm_runtime_disable(dd->dev);
1188 dd = NULL;
1189
1190 return 0;
1191}
1192
1193#ifdef CONFIG_PM_SLEEP
1194static int omap_des_suspend(struct device *dev)
1195{
1196 pm_runtime_put_sync(dev);
1197 return 0;
1198}
1199
1200static int omap_des_resume(struct device *dev)
1201{
f51f593b
NM		 1202 int err;
1203
1204 err = pm_runtime_get_sync(dev);
1205 if (err < 0) {
1206 pm_runtime_put_noidle(dev);
1207 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1208 return err;
1209 }
e91aa9d5
JF		 1210 return 0;
1211}
1212#endif
1213
e78f9193 1214static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
e91aa9d5
JF		 1215
1216static struct platform_driver omap_des_driver = {
1217 .probe = omap_des_probe,
1218 .remove = omap_des_remove,
1219 .driver = {
1220 .name = "omap-des",
e91aa9d5
JF		 1221 .pm = &omap_des_pm_ops,
1222 .of_match_table = of_match_ptr(omap_des_of_match),
1223 },
1224};
1225
1226module_platform_driver(omap_des_driver);
1227
1228MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1229MODULE_LICENSE("GPL v2");
1230MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");
Linux 6.x block layer and io_uring tree(s)