[linux-2.6-block.git] / drivers / cpufreq / tegra20-cpufreq.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *	Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>

static struct cpufreq_frequency_table freq_table[] = {
	{ .frequency = 216000 },
	{ .frequency = 312000 },
	{ .frequency = 456000 },
	{ .frequency = 608000 },
	{ .frequency = 760000 },
	{ .frequency = 816000 },
	{ .frequency = 912000 },
	{ .frequency = 1000000 },
	{ .frequency = CPUFREQ_TABLE_END },
};

#define NUM_CPUS	2

static struct clk *cpu_clk;
static struct clk *pll_x_clk;
static struct clk *pll_p_clk;
static bool pll_x_prepared;

static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
					   unsigned int index)
{
	unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;

	/*
	 * Don't switch to intermediate freq if:
	 * - we are already at it, i.e. policy->cur == ifreq
	 * - index corresponds to ifreq
	 */
	if ((freq_table[index].frequency == ifreq) || (policy->cur == ifreq))
		return 0;

	return ifreq;
}

static int tegra_target_intermediate(struct cpufreq_policy *policy,
				     unsigned int index)
{
	int ret;

	/*
	 * Take an extra reference to the main pll so it doesn't turn
	 * off when we move the cpu off of it as enabling it again while we
	 * switch to it from tegra_target() would take additional time.
	 *
	 * When target-freq is equal to intermediate freq we don't need to
	 * switch to an intermediate freq and so this routine isn't called.
	 * Also, we wouldn't be using pll_x anymore and must not take extra
	 * reference to it, as it can be disabled now to save some power.
	 */
	clk_prepare_enable(pll_x_clk);

	ret = clk_set_parent(cpu_clk, pll_p_clk);
	if (ret)
		clk_disable_unprepare(pll_x_clk);
	else
		pll_x_prepared = true;

	return ret;
}

static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
{
	unsigned long rate = freq_table[index].frequency;
	unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
	int ret = 0;

	/*
	 * target freq == pll_p, don't need to take extra reference to pll_x_clk
	 * as it isn't used anymore.
	 */
	if (rate == ifreq)
		return clk_set_parent(cpu_clk, pll_p_clk);

	ret = clk_set_rate(pll_x_clk, rate * 1000);
	/* Restore to earlier frequency on error, i.e. pll_x */
	if (ret)
		pr_err("Failed to change pll_x to %lu\n", rate);

	ret = clk_set_parent(cpu_clk, pll_x_clk);
	/* This shouldn't fail while changing or restoring */
	WARN_ON(ret);

	/*
	 * Drop count to pll_x clock only if we switched to intermediate freq
	 * earlier while transitioning to a target frequency.
	 */
	if (pll_x_prepared) {
		clk_disable_unprepare(pll_x_clk);
		pll_x_prepared = false;
	}

	return ret;
}

static int tegra_cpu_init(struct cpufreq_policy *policy)
{
	int ret;

	if (policy->cpu >= NUM_CPUS)
		return -EINVAL;

	clk_prepare_enable(cpu_clk);

	/* FIXME: what's the actual transition time? */
	ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
	if (ret) {
		clk_disable_unprepare(cpu_clk);
		return ret;
	}

	policy->clk = cpu_clk;
	policy->suspend_freq = freq_table[0].frequency;
	return 0;
}

static int tegra_cpu_exit(struct cpufreq_policy *policy)
{
	clk_disable_unprepare(cpu_clk);
	return 0;
}

static struct cpufreq_driver tegra_cpufreq_driver = {
	.flags			= CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify			= cpufreq_generic_frequency_table_verify,
	.get_intermediate	= tegra_get_intermediate,
	.target_intermediate	= tegra_target_intermediate,
	.target_index		= tegra_target,
	.get			= cpufreq_generic_get,
	.init			= tegra_cpu_init,
	.exit			= tegra_cpu_exit,
	.name			= "tegra",
	.attr			= cpufreq_generic_attr,
	.suspend		= cpufreq_generic_suspend,
};

static int __init tegra_cpufreq_init(void)
{
	cpu_clk = clk_get_sys(NULL, "cclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	pll_x_clk = clk_get_sys(NULL, "pll_x");
	if (IS_ERR(pll_x_clk))
		return PTR_ERR(pll_x_clk);

	pll_p_clk = clk_get_sys(NULL, "pll_p");
	if (IS_ERR(pll_p_clk))
		return PTR_ERR(pll_p_clk);

	return cpufreq_register_driver(&tegra_cpufreq_driver);
}

static void __exit tegra_cpufreq_exit(void)
{
	cpufreq_unregister_driver(&tegra_cpufreq_driver);
	clk_put(cpu_clk);
}

MODULE_AUTHOR("Colin Cross <ccross@android.com>");
MODULE_DESCRIPTION("NVIDIA Tegra20 cpufreq driver");
MODULE_LICENSE("GPL");
module_init(tegra_cpufreq_init);
module_exit(tegra_cpufreq_exit);
Commit	Line	Data
7056d423	1	/*
7056d423 CC	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* Author:
	5	* Colin Cross <ccross@google.com>
	6	* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
9a25ba9a	19	#include <linux/clk.h>
7056d423	20	#include <linux/cpufreq.h>
7056d423	21	#include <linux/err.h>
9a25ba9a DO	22	#include <linux/init.h>
	23	#include <linux/module.h>
	24	#include <linux/types.h>
7056d423	25
7056d423	26	static struct cpufreq_frequency_table freq_table[] = {
5d69030d VK	27	{ .frequency = 216000 },
	28	{ .frequency = 312000 },
	29	{ .frequency = 456000 },
	30	{ .frequency = 608000 },
	31	{ .frequency = 760000 },
	32	{ .frequency = 816000 },
	33	{ .frequency = 912000 },
	34	{ .frequency = 1000000 },
	35	{ .frequency = CPUFREQ_TABLE_END },
7056d423 CC	36	};
	37
	38	#define NUM_CPUS 2
	39
	40	static struct clk *cpu_clk;
ce32ddaa SW	41	static struct clk *pll_x_clk;
ce32ddaa SW	42	static struct clk *pll_p_clk;
00917ddc	43	static bool pll_x_prepared;
7056d423	44
00917ddc VK	45	static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
	46	unsigned int index)
	47	{
	48	unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
	49
	50	/*
	51	* Don't switch to intermediate freq if:
	52	* - we are already at it, i.e. policy->cur == ifreq
	53	* - index corresponds to ifreq
	54	*/
	55	if ((freq_table[index].frequency == ifreq) \|\| (policy->cur == ifreq))
	56	return 0;
	57
	58	return ifreq;
	59	}
	60
	61	static int tegra_target_intermediate(struct cpufreq_policy *policy,
	62	unsigned int index)
ce32ddaa SW	63	{
	64	int ret;
	65
	66	/*
	67	* Take an extra reference to the main pll so it doesn't turn
00917ddc	68	* off when we move the cpu off of it as enabling it again while we
40cc5490 VK	69	* switch to it from tegra_target() would take additional time.
	70	*
	71	* When target-freq is equal to intermediate freq we don't need to
	72	* switch to an intermediate freq and so this routine isn't called.
	73	* Also, we wouldn't be using pll_x anymore and must not take extra
	74	* reference to it, as it can be disabled now to save some power.
ce32ddaa SW	75	*/
	76	clk_prepare_enable(pll_x_clk);
	77
	78	ret = clk_set_parent(cpu_clk, pll_p_clk);
00917ddc VK	79	if (ret)
	80	clk_disable_unprepare(pll_x_clk);
	81	else
	82	pll_x_prepared = true;
ce32ddaa	83
ce32ddaa SW	84	return ret;
	85	}
	86
e7b453d3	87	static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
7056d423	88	{
e7b453d3	89	unsigned long rate = freq_table[index].frequency;
00917ddc	90	unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
7056d423	91	int ret = 0;
7056d423	92
00917ddc VK	93	/*
	94	* target freq == pll_p, don't need to take extra reference to pll_x_clk
	95	* as it isn't used anymore.
	96	*/
	97	if (rate == ifreq)
	98	return clk_set_parent(cpu_clk, pll_p_clk);
	99
	100	ret = clk_set_rate(pll_x_clk, rate * 1000);
	101	/* Restore to earlier frequency on error, i.e. pll_x */
d4019f0a	102	if (ret)
00917ddc VK	103	pr_err("Failed to change pll_x to %lu\n", rate);
	104
	105	ret = clk_set_parent(cpu_clk, pll_x_clk);
	106	/* This shouldn't fail while changing or restoring */
	107	WARN_ON(ret);
	108
	109	/*
	110	* Drop count to pll_x clock only if we switched to intermediate freq
	111	* earlier while transitioning to a target frequency.
	112	*/
	113	if (pll_x_prepared) {
	114	clk_disable_unprepare(pll_x_clk);
	115	pll_x_prepared = false;
	116	}
7056d423	117
f56cc99e	118	return ret;
7056d423 CC	119	}
7056d423 CC	120
7056d423 CC	121	static int tegra_cpu_init(struct cpufreq_policy *policy)
7056d423 CC	122	{
99d428cf VK	123	int ret;
99d428cf VK	124
7056d423 CC	125	if (policy->cpu >= NUM_CPUS)
	126	return -EINVAL;
	127
6a5278d0	128	clk_prepare_enable(cpu_clk);
89a5fb84	129
7056d423	130	/* FIXME: what's the actual transition time? */
99d428cf VK	131	ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
	132	if (ret) {
	133	clk_disable_unprepare(cpu_clk);
99d428cf VK	134	return ret;
99d428cf VK	135	}
7056d423	136
652ed95d	137	policy->clk = cpu_clk;
d351cb31	138	policy->suspend_freq = freq_table[0].frequency;
7056d423 CC	139	return 0;
	140	}
	141
	142	static int tegra_cpu_exit(struct cpufreq_policy *policy)
	143	{
99d428cf	144	clk_disable_unprepare(cpu_clk);
7056d423 CC	145	return 0;
	146	}
	147
7056d423	148	static struct cpufreq_driver tegra_cpufreq_driver = {
00917ddc VK	149	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	150	.verify = cpufreq_generic_frequency_table_verify,
	151	.get_intermediate = tegra_get_intermediate,
	152	.target_intermediate = tegra_target_intermediate,
	153	.target_index = tegra_target,
	154	.get = cpufreq_generic_get,
	155	.init = tegra_cpu_init,
	156	.exit = tegra_cpu_exit,
	157	.name = "tegra",
	158	.attr = cpufreq_generic_attr,
00917ddc	159	.suspend = cpufreq_generic_suspend,
7056d423 CC	160	};
	161
	162	static int __init tegra_cpufreq_init(void)
	163	{
b192b910	164	cpu_clk = clk_get_sys(NULL, "cclk");
c26cefd0 RZ	165	if (IS_ERR(cpu_clk))
	166	return PTR_ERR(cpu_clk);
	167
	168	pll_x_clk = clk_get_sys(NULL, "pll_x");
	169	if (IS_ERR(pll_x_clk))
	170	return PTR_ERR(pll_x_clk);
	171
b192b910	172	pll_p_clk = clk_get_sys(NULL, "pll_p");
c26cefd0 RZ	173	if (IS_ERR(pll_p_clk))
	174	return PTR_ERR(pll_p_clk);
	175
7056d423 CC	176	return cpufreq_register_driver(&tegra_cpufreq_driver);
	177	}
	178
	179	static void __exit tegra_cpufreq_exit(void)
	180	{
e08551b8	181	cpufreq_unregister_driver(&tegra_cpufreq_driver);
c26cefd0	182	clk_put(cpu_clk);
7056d423 CC	183	}
7056d423 CC	184
7056d423	185	MODULE_AUTHOR("Colin Cross <ccross@android.com>");
49640277	186	MODULE_DESCRIPTION("NVIDIA Tegra20 cpufreq driver");
7056d423 CC	187	MODULE_LICENSE("GPL");
	188	module_init(tegra_cpufreq_init);
	189	module_exit(tegra_cpufreq_exit);