[linux-2.6-block.git] / drivers / cpufreq / tegra-cpufreq.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *	Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>

static struct cpufreq_frequency_table freq_table[] = {
	{ .frequency = 216000 },
	{ .frequency = 312000 },
	{ .frequency = 456000 },
	{ .frequency = 608000 },
	{ .frequency = 760000 },
	{ .frequency = 816000 },
	{ .frequency = 912000 },
	{ .frequency = 1000000 },
	{ .frequency = CPUFREQ_TABLE_END },
};

#define NUM_CPUS	2

static struct clk *cpu_clk;
static struct clk *pll_x_clk;
static struct clk *pll_p_clk;
static struct clk *emc_clk;

static int tegra_cpu_clk_set_rate(unsigned long rate)
{
	int ret;

	/*
	 * Take an extra reference to the main pll so it doesn't turn
	 * off when we move the cpu off of it
	 */
	clk_prepare_enable(pll_x_clk);

	ret = clk_set_parent(cpu_clk, pll_p_clk);
	if (ret) {
		pr_err("Failed to switch cpu to clock pll_p\n");
		goto out;
	}

	if (rate == clk_get_rate(pll_p_clk))
		goto out;

	ret = clk_set_rate(pll_x_clk, rate);
	if (ret) {
		pr_err("Failed to change pll_x to %lu\n", rate);
		goto out;
	}

	ret = clk_set_parent(cpu_clk, pll_x_clk);
	if (ret) {
		pr_err("Failed to switch cpu to clock pll_x\n");
		goto out;
	}

out:
	clk_disable_unprepare(pll_x_clk);
	return ret;
}

static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
{
	unsigned long rate = freq_table[index].frequency;
	int ret = 0;

	/*
	 * Vote on memory bus frequency based on cpu frequency
	 * This sets the minimum frequency, display or avp may request higher
	 */
	if (rate >= 816000)
		clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	else if (rate >= 456000)
		clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	else
		clk_set_rate(emc_clk, 100000000);  /* emc 50Mhz */

	ret = tegra_cpu_clk_set_rate(rate * 1000);
	if (ret)
		pr_err("cpu-tegra: Failed to set cpu frequency to %lu kHz\n",
			rate);

	return ret;
}

static int tegra_cpu_init(struct cpufreq_policy *policy)
{
	int ret;

	if (policy->cpu >= NUM_CPUS)
		return -EINVAL;

	clk_prepare_enable(emc_clk);
	clk_prepare_enable(cpu_clk);

	/* FIXME: what's the actual transition time? */
	ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
	if (ret) {
		clk_disable_unprepare(cpu_clk);
		clk_disable_unprepare(emc_clk);
		return ret;
	}

	policy->clk = cpu_clk;
	policy->suspend_freq = freq_table[0].frequency;
	return 0;
}

static int tegra_cpu_exit(struct cpufreq_policy *policy)
{
	clk_disable_unprepare(cpu_clk);
	clk_disable_unprepare(emc_clk);
	return 0;
}

static struct cpufreq_driver tegra_cpufreq_driver = {
	.flags		= CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= tegra_target,
	.get		= cpufreq_generic_get,
	.init		= tegra_cpu_init,
	.exit		= tegra_cpu_exit,
	.name		= "tegra",
	.attr		= cpufreq_generic_attr,
#ifdef CONFIG_PM
	.suspend	= cpufreq_generic_suspend,
#endif
};

static int __init tegra_cpufreq_init(void)
{
	cpu_clk = clk_get_sys(NULL, "cclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	pll_x_clk = clk_get_sys(NULL, "pll_x");
	if (IS_ERR(pll_x_clk))
		return PTR_ERR(pll_x_clk);

	pll_p_clk = clk_get_sys(NULL, "pll_p");
	if (IS_ERR(pll_p_clk))
		return PTR_ERR(pll_p_clk);

	emc_clk = clk_get_sys("cpu", "emc");
	if (IS_ERR(emc_clk)) {
		clk_put(cpu_clk);
		return PTR_ERR(emc_clk);
	}

	return cpufreq_register_driver(&tegra_cpufreq_driver);
}

static void __exit tegra_cpufreq_exit(void)
{
        cpufreq_unregister_driver(&tegra_cpufreq_driver);
	clk_put(emc_clk);
	clk_put(cpu_clk);
}


MODULE_AUTHOR("Colin Cross <ccross@android.com>");
MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
MODULE_LICENSE("GPL");
module_init(tegra_cpufreq_init);
module_exit(tegra_cpufreq_exit);
Commit	Line	Data
7056d423	1	/*
7056d423 CC	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* Author:
	5	* Colin Cross <ccross@google.com>
	6	* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/types.h>
	22	#include <linux/sched.h>
	23	#include <linux/cpufreq.h>
	24	#include <linux/delay.h>
	25	#include <linux/init.h>
	26	#include <linux/err.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
	29
7056d423	30	static struct cpufreq_frequency_table freq_table[] = {
5d69030d VK	31	{ .frequency = 216000 },
	32	{ .frequency = 312000 },
	33	{ .frequency = 456000 },
	34	{ .frequency = 608000 },
	35	{ .frequency = 760000 },
	36	{ .frequency = 816000 },
	37	{ .frequency = 912000 },
	38	{ .frequency = 1000000 },
	39	{ .frequency = CPUFREQ_TABLE_END },
7056d423 CC	40	};
	41
	42	#define NUM_CPUS 2
	43
	44	static struct clk *cpu_clk;
ce32ddaa SW	45	static struct clk *pll_x_clk;
ce32ddaa SW	46	static struct clk *pll_p_clk;
7a281284	47	static struct clk *emc_clk;
7056d423	48
ce32ddaa SW	49	static int tegra_cpu_clk_set_rate(unsigned long rate)
	50	{
	51	int ret;
	52
	53	/*
	54	* Take an extra reference to the main pll so it doesn't turn
	55	* off when we move the cpu off of it
	56	*/
	57	clk_prepare_enable(pll_x_clk);
	58
	59	ret = clk_set_parent(cpu_clk, pll_p_clk);
	60	if (ret) {
	61	pr_err("Failed to switch cpu to clock pll_p\n");
	62	goto out;
	63	}
	64
	65	if (rate == clk_get_rate(pll_p_clk))
	66	goto out;
	67
	68	ret = clk_set_rate(pll_x_clk, rate);
	69	if (ret) {
	70	pr_err("Failed to change pll_x to %lu\n", rate);
	71	goto out;
	72	}
	73
	74	ret = clk_set_parent(cpu_clk, pll_x_clk);
	75	if (ret) {
	76	pr_err("Failed to switch cpu to clock pll_x\n");
	77	goto out;
	78	}
	79
	80	out:
	81	clk_disable_unprepare(pll_x_clk);
	82	return ret;
	83	}
	84
e7b453d3	85	static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
7056d423	86	{
e7b453d3	87	unsigned long rate = freq_table[index].frequency;
7056d423	88	int ret = 0;
7056d423	89
7a281284 CC	90	/*
	91	* Vote on memory bus frequency based on cpu frequency
	92	* This sets the minimum frequency, display or avp may request higher
	93	*/
	94	if (rate >= 816000)
	95	clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	96	else if (rate >= 456000)
	97	clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	98	else
	99	clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
	100
d4019f0a VK	101	ret = tegra_cpu_clk_set_rate(rate * 1000);
	102	if (ret)
	103	pr_err("cpu-tegra: Failed to set cpu frequency to %lu kHz\n",
	104	rate);
7056d423	105
f56cc99e	106	return ret;
7056d423 CC	107	}
7056d423 CC	108
7056d423 CC	109	static int tegra_cpu_init(struct cpufreq_policy *policy)
7056d423 CC	110	{
99d428cf VK	111	int ret;
99d428cf VK	112
7056d423 CC	113	if (policy->cpu >= NUM_CPUS)
	114	return -EINVAL;
	115
6a5278d0 PG	116	clk_prepare_enable(emc_clk);
6a5278d0 PG	117	clk_prepare_enable(cpu_clk);
89a5fb84	118
7056d423	119	/* FIXME: what's the actual transition time? */
99d428cf VK	120	ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
	121	if (ret) {
	122	clk_disable_unprepare(cpu_clk);
	123	clk_disable_unprepare(emc_clk);
	124	return ret;
	125	}
7056d423	126
652ed95d	127	policy->clk = cpu_clk;
d351cb31	128	policy->suspend_freq = freq_table[0].frequency;
7056d423 CC	129	return 0;
	130	}
	131
	132	static int tegra_cpu_exit(struct cpufreq_policy *policy)
	133	{
99d428cf	134	clk_disable_unprepare(cpu_clk);
6a5278d0	135	clk_disable_unprepare(emc_clk);
7056d423 CC	136	return 0;
	137	}
	138
7056d423	139	static struct cpufreq_driver tegra_cpufreq_driver = {
ae6b4271	140	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
8e08cf03	141	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	142	.target_index = tegra_target,
652ed95d	143	.get = cpufreq_generic_get,
7056d423 CC	144	.init = tegra_cpu_init,
	145	.exit = tegra_cpu_exit,
	146	.name = "tegra",
8e08cf03	147	.attr = cpufreq_generic_attr,
d351cb31 VK	148	#ifdef CONFIG_PM
	149	.suspend = cpufreq_generic_suspend,
	150	#endif
7056d423 CC	151	};
	152
	153	static int __init tegra_cpufreq_init(void)
	154	{
b192b910	155	cpu_clk = clk_get_sys(NULL, "cclk");
c26cefd0 RZ	156	if (IS_ERR(cpu_clk))
	157	return PTR_ERR(cpu_clk);
	158
	159	pll_x_clk = clk_get_sys(NULL, "pll_x");
	160	if (IS_ERR(pll_x_clk))
	161	return PTR_ERR(pll_x_clk);
	162
b192b910	163	pll_p_clk = clk_get_sys(NULL, "pll_p");
c26cefd0 RZ	164	if (IS_ERR(pll_p_clk))
	165	return PTR_ERR(pll_p_clk);
	166
	167	emc_clk = clk_get_sys("cpu", "emc");
	168	if (IS_ERR(emc_clk)) {
	169	clk_put(cpu_clk);
	170	return PTR_ERR(emc_clk);
	171	}
	172
7056d423 CC	173	return cpufreq_register_driver(&tegra_cpufreq_driver);
	174	}
	175
	176	static void __exit tegra_cpufreq_exit(void)
	177	{
	178	cpufreq_unregister_driver(&tegra_cpufreq_driver);
c26cefd0 RZ	179	clk_put(emc_clk);
c26cefd0 RZ	180	clk_put(cpu_clk);
7056d423 CC	181	}
	182
	183
	184	MODULE_AUTHOR("Colin Cross <ccross@android.com>");
	185	MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
	186	MODULE_LICENSE("GPL");
	187	module_init(tegra_cpufreq_init);
	188	module_exit(tegra_cpufreq_exit);