[linux-2.6-block.git] / drivers / cpufreq / cpufreq-nforce2.c

/*
 * (C) 2004-2006  Sebastian Witt <se.witt@gmx.net>
 *
 *  Licensed under the terms of the GNU GPL License version 2.
 *  Based upon reverse engineered information
 *
 *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/pci.h>
#include <linux/delay.h>

#define NFORCE2_XTAL 25
#define NFORCE2_BOOTFSB 0x48
#define NFORCE2_PLLENABLE 0xa8
#define NFORCE2_PLLREG 0xa4
#define NFORCE2_PLLADR 0xa0
#define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)

#define NFORCE2_MIN_FSB 50
#define NFORCE2_SAFE_DISTANCE 50

/* Delay in ms between FSB changes */
/* #define NFORCE2_DELAY 10 */

/*
 * nforce2_chipset:
 * FSB is changed using the chipset
 */
static struct pci_dev *nforce2_dev;

/* fid:
 * multiplier * 10
 */
static int fid;

/* min_fsb, max_fsb:
 * minimum and maximum FSB (= FSB at boot time)
 */
static int min_fsb;
static int max_fsb;

MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
MODULE_LICENSE("GPL");

module_param(fid, int, 0444);
module_param(min_fsb, int, 0444);

MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
MODULE_PARM_DESC(min_fsb,
		"Minimum FSB to use, if not defined: current FSB - 50");

/**
 * nforce2_calc_fsb - calculate FSB
 * @pll: PLL value
 *
 *   Calculates FSB from PLL value
 */
static int nforce2_calc_fsb(int pll)
{
	unsigned char mul, div;

	mul = (pll >> 8) & 0xff;
	div = pll & 0xff;

	if (div > 0)
		return NFORCE2_XTAL * mul / div;

	return 0;
}

/**
 * nforce2_calc_pll - calculate PLL value
 * @fsb: FSB
 *
 *   Calculate PLL value for given FSB
 */
static int nforce2_calc_pll(unsigned int fsb)
{
	unsigned char xmul, xdiv;
	unsigned char mul = 0, div = 0;
	int tried = 0;

	/* Try to calculate multiplier and divider up to 4 times */
	while (((mul == 0) || (div == 0)) && (tried <= 3)) {
		for (xdiv = 2; xdiv <= 0x80; xdiv++)
			for (xmul = 1; xmul <= 0xfe; xmul++)
				if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
				    fsb + tried) {
					mul = xmul;
					div = xdiv;
				}
		tried++;
	}

	if ((mul == 0) || (div == 0))
		return -1;

	return NFORCE2_PLL(mul, div);
}

/**
 * nforce2_write_pll - write PLL value to chipset
 * @pll: PLL value
 *
 *   Writes new FSB PLL value to chipset
 */
static void nforce2_write_pll(int pll)
{
	int temp;

	/* Set the pll addr. to 0x00 */
	pci_write_config_dword(nforce2_dev, NFORCE2_PLLADR, 0);

	/* Now write the value in all 64 registers */
	for (temp = 0; temp <= 0x3f; temp++)
		pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll);

	return;
}

/**
 * nforce2_fsb_read - Read FSB
 *
 *   Read FSB from chipset
 *   If bootfsb != 0, return FSB at boot-time
 */
static unsigned int nforce2_fsb_read(int bootfsb)
{
	struct pci_dev *nforce2_sub5;
	u32 fsb, temp = 0;

	/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
	nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, 0x01EF,
				PCI_ANY_ID, PCI_ANY_ID, NULL);
	if (!nforce2_sub5)
		return 0;

	pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
	fsb /= 1000000;

	/* Check if PLL register is already set */
	pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);

	if (bootfsb || !temp)
		return fsb;

	/* Use PLL register FSB value */
	pci_read_config_dword(nforce2_dev, NFORCE2_PLLREG, &temp);
	fsb = nforce2_calc_fsb(temp);

	return fsb;
}

/**
 * nforce2_set_fsb - set new FSB
 * @fsb: New FSB
 *
 *   Sets new FSB
 */
static int nforce2_set_fsb(unsigned int fsb)
{
	u32 temp = 0;
	unsigned int tfsb;
	int diff;
	int pll = 0;

	if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
		pr_err("FSB %d is out of range!\n", fsb);
		return -EINVAL;
	}

	tfsb = nforce2_fsb_read(0);
	if (!tfsb) {
		pr_err("Error while reading the FSB\n");
		return -EINVAL;
	}

	/* First write? Then set actual value */
	pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
	if (!temp) {
		pll = nforce2_calc_pll(tfsb);

		if (pll < 0)
			return -EINVAL;

		nforce2_write_pll(pll);
	}

	/* Enable write access */
	temp = 0x01;
	pci_write_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8)temp);

	diff = tfsb - fsb;

	if (!diff)
		return 0;

	while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
		if (diff < 0)
			tfsb++;
		else
			tfsb--;

		/* Calculate the PLL reg. value */
		pll = nforce2_calc_pll(tfsb);
		if (pll == -1)
			return -EINVAL;

		nforce2_write_pll(pll);
#ifdef NFORCE2_DELAY
		mdelay(NFORCE2_DELAY);
#endif
	}

	temp = 0x40;
	pci_write_config_byte(nforce2_dev, NFORCE2_PLLADR, (u8)temp);

	return 0;
}

/**
 * nforce2_get - get the CPU frequency
 * @cpu: CPU number
 *
 * Returns the CPU frequency
 */
static unsigned int nforce2_get(unsigned int cpu)
{
	if (cpu)
		return 0;
	return nforce2_fsb_read(0) * fid * 100;
}

/**
 * nforce2_target - set a new CPUFreq policy
 * @policy: new policy
 * @target_freq: the target frequency
 * @relation: how that frequency relates to achieved frequency
 *  (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 *
 * Sets a new CPUFreq policy.
 */
static int nforce2_target(struct cpufreq_policy *policy,
			  unsigned int target_freq, unsigned int relation)
{
/*        unsigned long         flags; */
	struct cpufreq_freqs freqs;
	unsigned int target_fsb;

	if ((target_freq > policy->max) || (target_freq < policy->min))
		return -EINVAL;

	target_fsb = target_freq / (fid * 100);

	freqs.old = nforce2_get(policy->cpu);
	freqs.new = target_fsb * fid * 100;

	if (freqs.old == freqs.new)
		return 0;

	pr_debug("Old CPU frequency %d kHz, new %d kHz\n",
	       freqs.old, freqs.new);

	cpufreq_freq_transition_begin(policy, &freqs);

	/* Disable IRQs */
	/* local_irq_save(flags); */

	if (nforce2_set_fsb(target_fsb) < 0)
		pr_err("Changing FSB to %d failed\n", target_fsb);
	else
		pr_debug("Changed FSB successfully to %d\n",
			target_fsb);

	/* Enable IRQs */
	/* local_irq_restore(flags); */

	cpufreq_freq_transition_end(policy, &freqs, 0);

	return 0;
}

/**
 * nforce2_verify - verifies a new CPUFreq policy
 * @policy: new policy
 */
static int nforce2_verify(struct cpufreq_policy *policy)
{
	unsigned int fsb_pol_max;

	fsb_pol_max = policy->max / (fid * 100);

	if (policy->min < (fsb_pol_max * fid * 100))
		policy->max = (fsb_pol_max + 1) * fid * 100;

	cpufreq_verify_within_cpu_limits(policy);
	return 0;
}

static int nforce2_cpu_init(struct cpufreq_policy *policy)
{
	unsigned int fsb;
	unsigned int rfid;

	/* capability check */
	if (policy->cpu != 0)
		return -ENODEV;

	/* Get current FSB */
	fsb = nforce2_fsb_read(0);

	if (!fsb)
		return -EIO;

	/* FIX: Get FID from CPU */
	if (!fid) {
		if (!cpu_khz) {
			pr_warn("cpu_khz not set, can't calculate multiplier!\n");
			return -ENODEV;
		}

		fid = cpu_khz / (fsb * 100);
		rfid = fid % 5;

		if (rfid) {
			if (rfid > 2)
				fid += 5 - rfid;
			else
				fid -= rfid;
		}
	}

	pr_info("FSB currently at %i MHz, FID %d.%d\n",
		fsb, fid / 10, fid % 10);

	/* Set maximum FSB to FSB at boot time */
	max_fsb = nforce2_fsb_read(1);

	if (!max_fsb)
		return -EIO;

	if (!min_fsb)
		min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;

	if (min_fsb < NFORCE2_MIN_FSB)
		min_fsb = NFORCE2_MIN_FSB;

	/* cpuinfo and default policy values */
	policy->min = policy->cpuinfo.min_freq = min_fsb * fid * 100;
	policy->max = policy->cpuinfo.max_freq = max_fsb * fid * 100;
	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;

	return 0;
}

static int nforce2_cpu_exit(struct cpufreq_policy *policy)
{
	return 0;
}

static struct cpufreq_driver nforce2_driver = {
	.name = "nforce2",
	.verify = nforce2_verify,
	.target = nforce2_target,
	.get = nforce2_get,
	.init = nforce2_cpu_init,
	.exit = nforce2_cpu_exit,
};

#ifdef MODULE
static const struct pci_device_id nforce2_ids[] = {
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2 },
	{}
};
MODULE_DEVICE_TABLE(pci, nforce2_ids);
#endif

/**
 * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
 *
 * Detects nForce2 A2 and C1 stepping
 *
 */
static int nforce2_detect_chipset(void)
{
	nforce2_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
					PCI_DEVICE_ID_NVIDIA_NFORCE2,
					PCI_ANY_ID, PCI_ANY_ID, NULL);

	if (nforce2_dev == NULL)
		return -ENODEV;

	pr_info("Detected nForce2 chipset revision %X\n",
		nforce2_dev->revision);
	pr_info("FSB changing is maybe unstable and can lead to crashes and data loss\n");

	return 0;
}

/**
 * nforce2_init - initializes the nForce2 CPUFreq driver
 *
 * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
 * devices, -EINVAL on problems during initialization, and zero on
 * success.
 */
static int __init nforce2_init(void)
{
	/* TODO: do we need to detect the processor? */

	/* detect chipset */
	if (nforce2_detect_chipset()) {
		pr_info("No nForce2 chipset\n");
		return -ENODEV;
	}

	return cpufreq_register_driver(&nforce2_driver);
}

/**
 * nforce2_exit - unregisters cpufreq module
 *
 *   Unregisters nForce2 FSB change support.
 */
static void __exit nforce2_exit(void)
{
	cpufreq_unregister_driver(&nforce2_driver);
}

module_init(nforce2_init);
module_exit(nforce2_exit);
Commit	Line	Data
1da177e4	1	/*
6ccf58ab	2	* (C) 2004-2006 Sebastian Witt <se.witt@gmx.net>
1da177e4 LT	3	*
	4	* Licensed under the terms of the GNU GPL License version 2.
	5	* Based upon reverse engineered information
	6	*
	7	* BIG FAT DISCLAIMER: Work in progress code. Possibly dangerous
	8	*/
	9
1c5864e2 JP	10	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
1c5864e2 JP	11
1da177e4 LT	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/moduleparam.h>
	15	#include <linux/init.h>
	16	#include <linux/cpufreq.h>
	17	#include <linux/pci.h>
	18	#include <linux/delay.h>
	19
	20	#define NFORCE2_XTAL 25
	21	#define NFORCE2_BOOTFSB 0x48
	22	#define NFORCE2_PLLENABLE 0xa8
	23	#define NFORCE2_PLLREG 0xa4
	24	#define NFORCE2_PLLADR 0xa0
	25	#define NFORCE2_PLL(mul, div) (0x100000 \| (mul << 8) \| div)
	26
	27	#define NFORCE2_MIN_FSB 50
	28	#define NFORCE2_SAFE_DISTANCE 50
	29
	30	/* Delay in ms between FSB changes */
219835f1	31	/* #define NFORCE2_DELAY 10 */
1da177e4	32
219835f1 PC	33	/*
219835f1 PC	34	* nforce2_chipset:
1da177e4 LT	35	* FSB is changed using the chipset
1da177e4 LT	36	*/
b5c91666	37	static struct pci_dev *nforce2_dev;
1da177e4 LT	38
	39	/* fid:
	40	* multiplier * 10
	41	*/
219835f1	42	static int fid;
1da177e4 LT	43
1da177e4 LT	44	/* min_fsb, max_fsb:
32ee8c3e	45	* minimum and maximum FSB (= FSB at boot time)
1da177e4	46	*/
219835f1 PC	47	static int min_fsb;
219835f1 PC	48	static int max_fsb;
1da177e4 LT	49
	50	MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
	51	MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
	52	MODULE_LICENSE("GPL");
	53
	54	module_param(fid, int, 0444);
	55	module_param(min_fsb, int, 0444);
	56
	57	MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
	58	MODULE_PARM_DESC(min_fsb,
219835f1	59	"Minimum FSB to use, if not defined: current FSB - 50");
1da177e4	60
32ee8c3e	61	/**
1da177e4 LT	62	* nforce2_calc_fsb - calculate FSB
1da177e4 LT	63	* @pll: PLL value
32ee8c3e	64	*
1da177e4 LT	65	* Calculates FSB from PLL value
	66	*/
	67	static int nforce2_calc_fsb(int pll)
	68	{
	69	unsigned char mul, div;
	70
	71	mul = (pll >> 8) & 0xff;
	72	div = pll & 0xff;
	73
	74	if (div > 0)
	75	return NFORCE2_XTAL * mul / div;
	76
	77	return 0;
	78	}
	79
32ee8c3e	80	/**
1da177e4 LT	81	* nforce2_calc_pll - calculate PLL value
1da177e4 LT	82	* @fsb: FSB
32ee8c3e	83	*
1da177e4 LT	84	* Calculate PLL value for given FSB
	85	*/
	86	static int nforce2_calc_pll(unsigned int fsb)
	87	{
	88	unsigned char xmul, xdiv;
	89	unsigned char mul = 0, div = 0;
	90	int tried = 0;
	91
	92	/* Try to calculate multiplier and divider up to 4 times */
	93	while (((mul == 0) \|\| (div == 0)) && (tried <= 3)) {
6ccf58ab	94	for (xdiv = 2; xdiv <= 0x80; xdiv++)
1da177e4 LT	95	for (xmul = 1; xmul <= 0xfe; xmul++)
	96	if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
	97	fsb + tried) {
	98	mul = xmul;
	99	div = xdiv;
	100	}
	101	tried++;
	102	}
	103
	104	if ((mul == 0) \|\| (div == 0))
	105	return -1;
	106
	107	return NFORCE2_PLL(mul, div);
	108	}
	109
32ee8c3e	110	/**
1da177e4 LT	111	* nforce2_write_pll - write PLL value to chipset
1da177e4 LT	112	* @pll: PLL value
32ee8c3e	113	*
1da177e4 LT	114	* Writes new FSB PLL value to chipset
	115	*/
	116	static void nforce2_write_pll(int pll)
	117	{
	118	int temp;
	119
	120	/* Set the pll addr. to 0x00 */
b5c91666	121	pci_write_config_dword(nforce2_dev, NFORCE2_PLLADR, 0);
1da177e4 LT	122
1da177e4 LT	123	/* Now write the value in all 64 registers */
32ee8c3e	124	for (temp = 0; temp <= 0x3f; temp++)
b5c91666	125	pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll);
1da177e4 LT	126
	127	return;
	128	}
	129
32ee8c3e	130	/**
1da177e4 LT	131	* nforce2_fsb_read - Read FSB
	132	*
	133	* Read FSB from chipset
	134	* If bootfsb != 0, return FSB at boot-time
	135	*/
	136	static unsigned int nforce2_fsb_read(int bootfsb)
	137	{
	138	struct pci_dev *nforce2_sub5;
	139	u32 fsb, temp = 0;
	140
1da177e4	141	/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
b5c91666 DJ	142	nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, 0x01EF,
b5c91666 DJ	143	PCI_ANY_ID, PCI_ANY_ID, NULL);
1da177e4 LT	144	if (!nforce2_sub5)
	145	return 0;
	146
	147	pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
	148	fsb /= 1000000;
32ee8c3e	149
1da177e4	150	/* Check if PLL register is already set */
b5c91666	151	pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
32ee8c3e	152
219835f1	153	if (bootfsb \|\| !temp)
1da177e4	154	return fsb;
219835f1	155
1da177e4	156	/* Use PLL register FSB value */
b5c91666	157	pci_read_config_dword(nforce2_dev, NFORCE2_PLLREG, &temp);
1da177e4 LT	158	fsb = nforce2_calc_fsb(temp);
	159
	160	return fsb;
	161	}
	162
32ee8c3e	163	/**
1da177e4 LT	164	* nforce2_set_fsb - set new FSB
1da177e4 LT	165	* @fsb: New FSB
32ee8c3e	166	*
1da177e4 LT	167	* Sets new FSB
	168	*/
	169	static int nforce2_set_fsb(unsigned int fsb)
	170	{
d4921914	171	u32 temp = 0;
1da177e4 LT	172	unsigned int tfsb;
1da177e4 LT	173	int diff;
d4921914	174	int pll = 0;
1da177e4 LT	175
1da177e4 LT	176	if ((fsb > max_fsb) \|\| (fsb < NFORCE2_MIN_FSB)) {
1c5864e2	177	pr_err("FSB %d is out of range!\n", fsb);
1da177e4 LT	178	return -EINVAL;
1da177e4 LT	179	}
32ee8c3e	180
1da177e4 LT	181	tfsb = nforce2_fsb_read(0);
1da177e4 LT	182	if (!tfsb) {
1c5864e2	183	pr_err("Error while reading the FSB\n");
1da177e4 LT	184	return -EINVAL;
	185	}
	186
	187	/* First write? Then set actual value */
b5c91666	188	pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
1da177e4 LT	189	if (!temp) {
	190	pll = nforce2_calc_pll(tfsb);
	191
	192	if (pll < 0)
	193	return -EINVAL;
	194
	195	nforce2_write_pll(pll);
	196	}
	197
	198	/* Enable write access */
	199	temp = 0x01;
b5c91666	200	pci_write_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8)temp);
1da177e4 LT	201
	202	diff = tfsb - fsb;
	203
	204	if (!diff)
	205	return 0;
	206
	207	while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
	208	if (diff < 0)
	209	tfsb++;
	210	else
	211	tfsb--;
	212
	213	/* Calculate the PLL reg. value */
219835f1 PC	214	pll = nforce2_calc_pll(tfsb);
219835f1 PC	215	if (pll == -1)
1da177e4	216	return -EINVAL;
32ee8c3e	217
1da177e4 LT	218	nforce2_write_pll(pll);
	219	#ifdef NFORCE2_DELAY
	220	mdelay(NFORCE2_DELAY);
	221	#endif
	222	}
	223
	224	temp = 0x40;
b5c91666	225	pci_write_config_byte(nforce2_dev, NFORCE2_PLLADR, (u8)temp);
1da177e4 LT	226
	227	return 0;
	228	}
	229
	230	/**
	231	* nforce2_get - get the CPU frequency
	232	* @cpu: CPU number
32ee8c3e	233	*
1da177e4 LT	234	* Returns the CPU frequency
	235	*/
	236	static unsigned int nforce2_get(unsigned int cpu)
	237	{
	238	if (cpu)
	239	return 0;
	240	return nforce2_fsb_read(0) * fid * 100;
	241	}
	242
	243	/**
	244	* nforce2_target - set a new CPUFreq policy
	245	* @policy: new policy
	246	* @target_freq: the target frequency
b5c91666 DJ	247	* @relation: how that frequency relates to achieved frequency
b5c91666 DJ	248	* (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
1da177e4 LT	249	*
	250	* Sets a new CPUFreq policy.
	251	*/
	252	static int nforce2_target(struct cpufreq_policy *policy,
	253	unsigned int target_freq, unsigned int relation)
	254	{
219835f1	255	/* unsigned long flags; */
1da177e4 LT	256	struct cpufreq_freqs freqs;
	257	unsigned int target_fsb;
	258
	259	if ((target_freq > policy->max) \|\| (target_freq < policy->min))
	260	return -EINVAL;
	261
	262	target_fsb = target_freq / (fid * 100);
	263
	264	freqs.old = nforce2_get(policy->cpu);
	265	freqs.new = target_fsb * fid * 100;
1da177e4 LT	266
	267	if (freqs.old == freqs.new)
	268	return 0;
	269
2d06d8c4	270	pr_debug("Old CPU frequency %d kHz, new %d kHz\n",
1da177e4 LT	271	freqs.old, freqs.new);
1da177e4 LT	272
8fec051e	273	cpufreq_freq_transition_begin(policy, &freqs);
1da177e4 LT	274
1da177e4 LT	275	/* Disable IRQs */
219835f1	276	/* local_irq_save(flags); */
1da177e4 LT	277
1da177e4 LT	278	if (nforce2_set_fsb(target_fsb) < 0)
1c5864e2	279	pr_err("Changing FSB to %d failed\n", target_fsb);
1da177e4	280	else
2d06d8c4	281	pr_debug("Changed FSB successfully to %d\n",
219835f1	282	target_fsb);
1da177e4 LT	283
1da177e4 LT	284	/* Enable IRQs */
219835f1	285	/* local_irq_restore(flags); */
1da177e4	286
8fec051e	287	cpufreq_freq_transition_end(policy, &freqs, 0);
1da177e4 LT	288
	289	return 0;
	290	}
	291
	292	/**
	293	* nforce2_verify - verifies a new CPUFreq policy
	294	* @policy: new policy
	295	*/
	296	static int nforce2_verify(struct cpufreq_policy *policy)
	297	{
	298	unsigned int fsb_pol_max;
	299
	300	fsb_pol_max = policy->max / (fid * 100);
	301
	302	if (policy->min < (fsb_pol_max * fid * 100))
	303	policy->max = (fsb_pol_max + 1) * fid * 100;
	304
be49e346	305	cpufreq_verify_within_cpu_limits(policy);
1da177e4 LT	306	return 0;
	307	}
	308
	309	static int nforce2_cpu_init(struct cpufreq_policy *policy)
	310	{
	311	unsigned int fsb;
	312	unsigned int rfid;
	313
	314	/* capability check */
	315	if (policy->cpu != 0)
	316	return -ENODEV;
	317
	318	/* Get current FSB */
	319	fsb = nforce2_fsb_read(0);
	320
	321	if (!fsb)
	322	return -EIO;
	323
	324	/* FIX: Get FID from CPU */
	325	if (!fid) {
	326	if (!cpu_khz) {
1c5864e2	327	pr_warn("cpu_khz not set, can't calculate multiplier!\n");
1da177e4 LT	328	return -ENODEV;
	329	}
	330
	331	fid = cpu_khz / (fsb * 100);
	332	rfid = fid % 5;
	333
	334	if (rfid) {
	335	if (rfid > 2)
	336	fid += 5 - rfid;
	337	else
	338	fid -= rfid;
	339	}
	340	}
	341
1c5864e2	342	pr_info("FSB currently at %i MHz, FID %d.%d\n",
b49c22a6	343	fsb, fid / 10, fid % 10);
32ee8c3e	344
1da177e4 LT	345	/* Set maximum FSB to FSB at boot time */
1da177e4 LT	346	max_fsb = nforce2_fsb_read(1);
32ee8c3e	347
219835f1	348	if (!max_fsb)
1da177e4 LT	349	return -EIO;
	350
	351	if (!min_fsb)
	352	min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;
	353
	354	if (min_fsb < NFORCE2_MIN_FSB)
	355	min_fsb = NFORCE2_MIN_FSB;
	356
	357	/* cpuinfo and default policy values */
eb2f50ff VK	358	policy->min = policy->cpuinfo.min_freq = min_fsb * fid * 100;
eb2f50ff VK	359	policy->max = policy->cpuinfo.max_freq = max_fsb * fid * 100;
1da177e4	360	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
1da177e4 LT	361
	362	return 0;
	363	}
	364
	365	static int nforce2_cpu_exit(struct cpufreq_policy *policy)
	366	{
	367	return 0;
	368	}
	369
221dee28	370	static struct cpufreq_driver nforce2_driver = {
1da177e4 LT	371	.name = "nforce2",
	372	.verify = nforce2_verify,
	373	.target = nforce2_target,
	374	.get = nforce2_get,
	375	.init = nforce2_cpu_init,
	376	.exit = nforce2_cpu_exit,
1da177e4 LT	377	};
1da177e4 LT	378
fa8031ae	379	#ifdef MODULE
dfcb0a54	380	static const struct pci_device_id nforce2_ids[] = {
fa8031ae AK	381	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2 },
	382	{}
	383	};
	384	MODULE_DEVICE_TABLE(pci, nforce2_ids);
	385	#endif
	386
1da177e4 LT	387	/**
	388	* nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
	389	*
	390	* Detects nForce2 A2 and C1 stepping
32ee8c3e	391	*
1da177e4	392	*/
b2a33c17	393	static int nforce2_detect_chipset(void)
1da177e4	394	{
b5c91666	395	nforce2_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
32ee8c3e DJ	396	PCI_DEVICE_ID_NVIDIA_NFORCE2,
32ee8c3e DJ	397	PCI_ANY_ID, PCI_ANY_ID, NULL);
1da177e4	398
b5c91666	399	if (nforce2_dev == NULL)
1da177e4 LT	400	return -ENODEV;
1da177e4 LT	401
1c5864e2	402	pr_info("Detected nForce2 chipset revision %X\n",
b49c22a6	403	nforce2_dev->revision);
1c5864e2	404	pr_info("FSB changing is maybe unstable and can lead to crashes and data loss\n");
1da177e4 LT	405
	406	return 0;
	407	}
	408
	409	/**
	410	* nforce2_init - initializes the nForce2 CPUFreq driver
	411	*
	412	* Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
97155e03	413	* devices, -EINVAL on problems during initialization, and zero on
1da177e4 LT	414	* success.
	415	*/
	416	static int __init nforce2_init(void)
	417	{
	418	/* TODO: do we need to detect the processor? */
	419
	420	/* detect chipset */
	421	if (nforce2_detect_chipset()) {
1c5864e2	422	pr_info("No nForce2 chipset\n");
1da177e4 LT	423	return -ENODEV;
	424	}
	425
	426	return cpufreq_register_driver(&nforce2_driver);
	427	}
	428
	429	/**
	430	* nforce2_exit - unregisters cpufreq module
	431	*
	432	* Unregisters nForce2 FSB change support.
	433	*/
	434	static void __exit nforce2_exit(void)
	435	{
	436	cpufreq_unregister_driver(&nforce2_driver);
	437	}
	438
	439	module_init(nforce2_init);
	440	module_exit(nforce2_exit);
	441