[linux-2.6-block.git] / drivers / cpufreq / cpufreq-dt.c

/*
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * Copyright (C) 2014 Linaro.
 * Viresh Kumar <viresh.kumar@linaro.org>
 *
 * The OPP code in function set_target() is reused from
 * drivers/cpufreq/omap-cpufreq.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpu_cooling.h>
#include <linux/cpufreq.h>
#include <linux/cpufreq-dt.h>
#include <linux/cpumask.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/thermal.h>

struct private_data {
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct thermal_cooling_device *cdev;
	unsigned int voltage_tolerance; /* in percentage */
};

static int set_target(struct cpufreq_policy *policy, unsigned int index)
{
	struct dev_pm_opp *opp;
	struct cpufreq_frequency_table *freq_table = policy->freq_table;
	struct clk *cpu_clk = policy->clk;
	struct private_data *priv = policy->driver_data;
	struct device *cpu_dev = priv->cpu_dev;
	struct regulator *cpu_reg = priv->cpu_reg;
	unsigned long volt = 0, volt_old = 0, tol = 0;
	unsigned int old_freq, new_freq;
	long freq_Hz, freq_exact;
	int ret;

	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
	if (freq_Hz <= 0)
		freq_Hz = freq_table[index].frequency * 1000;

	freq_exact = freq_Hz;
	new_freq = freq_Hz / 1000;
	old_freq = clk_get_rate(cpu_clk) / 1000;

	if (!IS_ERR(cpu_reg)) {
		unsigned long opp_freq;

		rcu_read_lock();
		opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
		if (IS_ERR(opp)) {
			rcu_read_unlock();
			dev_err(cpu_dev, "failed to find OPP for %ld\n",
				freq_Hz);
			return PTR_ERR(opp);
		}
		volt = dev_pm_opp_get_voltage(opp);
		opp_freq = dev_pm_opp_get_freq(opp);
		rcu_read_unlock();
		tol = volt * priv->voltage_tolerance / 100;
		volt_old = regulator_get_voltage(cpu_reg);
		dev_dbg(cpu_dev, "Found OPP: %ld kHz, %ld uV\n",
			opp_freq / 1000, volt);
	}

	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
		old_freq / 1000, (volt_old > 0) ? volt_old / 1000 : -1,
		new_freq / 1000, volt ? volt / 1000 : -1);

	/* scaling up?  scale voltage before frequency */
	if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
		if (ret) {
			dev_err(cpu_dev, "failed to scale voltage up: %d\n",
				ret);
			return ret;
		}
	}

	ret = clk_set_rate(cpu_clk, freq_exact);
	if (ret) {
		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
		if (!IS_ERR(cpu_reg) && volt_old > 0)
			regulator_set_voltage_tol(cpu_reg, volt_old, tol);
		return ret;
	}

	/* scaling down?  scale voltage after frequency */
	if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
		if (ret) {
			dev_err(cpu_dev, "failed to scale voltage down: %d\n",
				ret);
			clk_set_rate(cpu_clk, old_freq * 1000);
		}
	}

	return ret;
}

static int allocate_resources(int cpu, struct device **cdev,
			      struct regulator **creg, struct clk **cclk)
{
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct clk *cpu_clk;
	int ret = 0;
	char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg;

	cpu_dev = get_cpu_device(cpu);
	if (!cpu_dev) {
		pr_err("failed to get cpu%d device\n", cpu);
		return -ENODEV;
	}

	/* Try "cpu0" for older DTs */
	if (!cpu)
		reg = reg_cpu0;
	else
		reg = reg_cpu;

try_again:
	cpu_reg = regulator_get_optional(cpu_dev, reg);
	if (IS_ERR(cpu_reg)) {
		/*
		 * If cpu's regulator supply node is present, but regulator is
		 * not yet registered, we should try defering probe.
		 */
		if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
			dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n",
				cpu);
			return -EPROBE_DEFER;
		}

		/* Try with "cpu-supply" */
		if (reg == reg_cpu0) {
			reg = reg_cpu;
			goto try_again;
		}

		dev_dbg(cpu_dev, "no regulator for cpu%d: %ld\n",
			cpu, PTR_ERR(cpu_reg));
	}

	cpu_clk = clk_get(cpu_dev, NULL);
	if (IS_ERR(cpu_clk)) {
		/* put regulator */
		if (!IS_ERR(cpu_reg))
			regulator_put(cpu_reg);

		ret = PTR_ERR(cpu_clk);

		/*
		 * If cpu's clk node is present, but clock is not yet
		 * registered, we should try defering probe.
		 */
		if (ret == -EPROBE_DEFER)
			dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu);
		else
			dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", cpu,
				ret);
	} else {
		*cdev = cpu_dev;
		*creg = cpu_reg;
		*cclk = cpu_clk;
	}

	return ret;
}

static int cpufreq_init(struct cpufreq_policy *policy)
{
	struct cpufreq_dt_platform_data *pd;
	struct cpufreq_frequency_table *freq_table;
	struct device_node *np;
	struct private_data *priv;
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct clk *cpu_clk;
	unsigned long min_uV = ~0, max_uV = 0;
	unsigned int transition_latency;
	int ret;

	ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk);
	if (ret) {
		pr_err("%s: Failed to allocate resources: %d\n", __func__, ret);
		return ret;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
		ret = -ENOENT;
		goto out_put_reg_clk;
	}

	/* OPPs might be populated at runtime, don't check for error here */
	of_init_opp_table(cpu_dev);

	/*
	 * But we need OPP table to function so if it is not there let's
	 * give platform code chance to provide it for us.
	 */
	ret = dev_pm_opp_get_opp_count(cpu_dev);
	if (ret <= 0) {
		pr_debug("OPP table is not ready, deferring probe\n");
		ret = -EPROBE_DEFER;
		goto out_free_opp;
	}

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		ret = -ENOMEM;
		goto out_free_opp;
	}

	of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	if (!IS_ERR(cpu_reg)) {
		unsigned long opp_freq = 0;

		/*
		 * Disable any OPPs where the connected regulator isn't able to
		 * provide the specified voltage and record minimum and maximum
		 * voltage levels.
		 */
		while (1) {
			struct dev_pm_opp *opp;
			unsigned long opp_uV, tol_uV;

			rcu_read_lock();
			opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq);
			if (IS_ERR(opp)) {
				rcu_read_unlock();
				break;
			}
			opp_uV = dev_pm_opp_get_voltage(opp);
			rcu_read_unlock();

			tol_uV = opp_uV * priv->voltage_tolerance / 100;
			if (regulator_is_supported_voltage(cpu_reg, opp_uV,
							   opp_uV + tol_uV)) {
				if (opp_uV < min_uV)
					min_uV = opp_uV;
				if (opp_uV > max_uV)
					max_uV = opp_uV;
			} else {
				dev_pm_opp_disable(cpu_dev, opp_freq);
			}

			opp_freq++;
		}

		ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		pr_err("failed to init cpufreq table: %d\n", ret);
		goto out_free_priv;
	}

	priv->cpu_dev = cpu_dev;
	priv->cpu_reg = cpu_reg;
	policy->driver_data = priv;

	policy->clk = cpu_clk;
	ret = cpufreq_table_validate_and_show(policy, freq_table);
	if (ret) {
		dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
			ret);
		goto out_free_cpufreq_table;
	}

	policy->cpuinfo.transition_latency = transition_latency;

	pd = cpufreq_get_driver_data();
	if (!pd || !pd->independent_clocks)
		cpumask_setall(policy->cpus);

	of_node_put(np);

	return 0;

out_free_cpufreq_table:
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
out_free_priv:
	kfree(priv);
out_free_opp:
	of_free_opp_table(cpu_dev);
	of_node_put(np);
out_put_reg_clk:
	clk_put(cpu_clk);
	if (!IS_ERR(cpu_reg))
		regulator_put(cpu_reg);

	return ret;
}

static int cpufreq_exit(struct cpufreq_policy *policy)
{
	struct private_data *priv = policy->driver_data;

	if (priv->cdev)
		cpufreq_cooling_unregister(priv->cdev);
	dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
	of_free_opp_table(priv->cpu_dev);
	clk_put(policy->clk);
	if (!IS_ERR(priv->cpu_reg))
		regulator_put(priv->cpu_reg);
	kfree(priv);

	return 0;
}

static void cpufreq_ready(struct cpufreq_policy *policy)
{
	struct private_data *priv = policy->driver_data;
	struct device_node *np = of_node_get(priv->cpu_dev->of_node);

	if (WARN_ON(!np))
		return;

	/*
	 * For now, just loading the cooling device;
	 * thermal DT code takes care of matching them.
	 */
	if (of_find_property(np, "#cooling-cells", NULL)) {
		priv->cdev = of_cpufreq_cooling_register(np,
							 policy->related_cpus);
		if (IS_ERR(priv->cdev)) {
			dev_err(priv->cpu_dev,
				"running cpufreq without cooling device: %ld\n",
				PTR_ERR(priv->cdev));

			priv->cdev = NULL;
		}
	}

	of_node_put(np);
}

static struct cpufreq_driver dt_cpufreq_driver = {
	.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = set_target,
	.get = cpufreq_generic_get,
	.init = cpufreq_init,
	.exit = cpufreq_exit,
	.ready = cpufreq_ready,
	.name = "cpufreq-dt",
	.attr = cpufreq_generic_attr,
};

static int dt_cpufreq_probe(struct platform_device *pdev)
{
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct clk *cpu_clk;
	int ret;

	/*
	 * All per-cluster (CPUs sharing clock/voltages) initialization is done
	 * from ->init(). In probe(), we just need to make sure that clk and
	 * regulators are available. Else defer probe and retry.
	 *
	 * FIXME: Is checking this only for CPU0 sufficient ?
	 */
	ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk);
	if (ret)
		return ret;

	clk_put(cpu_clk);
	if (!IS_ERR(cpu_reg))
		regulator_put(cpu_reg);

	dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev);

	ret = cpufreq_register_driver(&dt_cpufreq_driver);
	if (ret)
		dev_err(cpu_dev, "failed register driver: %d\n", ret);

	return ret;
}

static int dt_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&dt_cpufreq_driver);
	return 0;
}

static struct platform_driver dt_cpufreq_platdrv = {
	.driver = {
		.name	= "cpufreq-dt",
	},
	.probe		= dt_cpufreq_probe,
	.remove		= dt_cpufreq_remove,
};
module_platform_driver(dt_cpufreq_platdrv);

MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Generic cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
95ceafd4 SG	1	/*
	2	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	3	*
748c8766 VK	4	* Copyright (C) 2014 Linaro.
	5	* Viresh Kumar <viresh.kumar@linaro.org>
	6	*
bbcf0719	7	* The OPP code in function set_target() is reused from
95ceafd4 SG	8	* drivers/cpufreq/omap-cpufreq.c
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	16
	17	#include <linux/clk.h>
e1825b25	18	#include <linux/cpu.h>
77cff592	19	#include <linux/cpu_cooling.h>
95ceafd4	20	#include <linux/cpufreq.h>
34e5a527	21	#include <linux/cpufreq-dt.h>
77cff592	22	#include <linux/cpumask.h>
95ceafd4 SG	23	#include <linux/err.h>
	24	#include <linux/module.h>
	25	#include <linux/of.h>
e4db1c74	26	#include <linux/pm_opp.h>
5553f9e2	27	#include <linux/platform_device.h>
95ceafd4 SG	28	#include <linux/regulator/consumer.h>
95ceafd4 SG	29	#include <linux/slab.h>
77cff592	30	#include <linux/thermal.h>
95ceafd4	31
d2f31f1d VK	32	struct private_data {
	33	struct device *cpu_dev;
	34	struct regulator *cpu_reg;
	35	struct thermal_cooling_device *cdev;
	36	unsigned int voltage_tolerance; /* in percentage */
	37	};
95ceafd4	38
bbcf0719	39	static int set_target(struct cpufreq_policy *policy, unsigned int index)
95ceafd4	40	{
47d43ba7	41	struct dev_pm_opp *opp;
d2f31f1d VK	42	struct cpufreq_frequency_table *freq_table = policy->freq_table;
	43	struct clk *cpu_clk = policy->clk;
	44	struct private_data *priv = policy->driver_data;
	45	struct device *cpu_dev = priv->cpu_dev;
	46	struct regulator *cpu_reg = priv->cpu_reg;
5df60559	47	unsigned long volt = 0, volt_old = 0, tol = 0;
d4019f0a	48	unsigned int old_freq, new_freq;
0ca68436	49	long freq_Hz, freq_exact;
95ceafd4 SG	50	int ret;
95ceafd4 SG	51
95ceafd4	52	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
2209b0c9	53	if (freq_Hz <= 0)
95ceafd4	54	freq_Hz = freq_table[index].frequency * 1000;
95ceafd4	55
d4019f0a VK	56	freq_exact = freq_Hz;
	57	new_freq = freq_Hz / 1000;
	58	old_freq = clk_get_rate(cpu_clk) / 1000;
95ceafd4	59
4a511de9	60	if (!IS_ERR(cpu_reg)) {
0a1e879d SW	61	unsigned long opp_freq;
0a1e879d SW	62
78e8eb8f	63	rcu_read_lock();
5d4879cd	64	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
95ceafd4	65	if (IS_ERR(opp)) {
78e8eb8f	66	rcu_read_unlock();
fbd48ca5 VK	67	dev_err(cpu_dev, "failed to find OPP for %ld\n",
fbd48ca5 VK	68	freq_Hz);
d4019f0a	69	return PTR_ERR(opp);
95ceafd4	70	}
5d4879cd	71	volt = dev_pm_opp_get_voltage(opp);
0a1e879d	72	opp_freq = dev_pm_opp_get_freq(opp);
78e8eb8f	73	rcu_read_unlock();
d2f31f1d	74	tol = volt * priv->voltage_tolerance / 100;
95ceafd4	75	volt_old = regulator_get_voltage(cpu_reg);
0a1e879d SW	76	dev_dbg(cpu_dev, "Found OPP: %ld kHz, %ld uV\n",
0a1e879d SW	77	opp_freq / 1000, volt);
95ceafd4 SG	78	}
95ceafd4 SG	79
fbd48ca5	80	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
8197bb1b	81	old_freq / 1000, (volt_old > 0) ? volt_old / 1000 : -1,
fbd48ca5	82	new_freq / 1000, volt ? volt / 1000 : -1);
95ceafd4 SG	83
95ceafd4 SG	84	/* scaling up? scale voltage before frequency */
d4019f0a	85	if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
95ceafd4 SG	86	ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
95ceafd4 SG	87	if (ret) {
fbd48ca5 VK	88	dev_err(cpu_dev, "failed to scale voltage up: %d\n",
fbd48ca5 VK	89	ret);
d4019f0a	90	return ret;
95ceafd4 SG	91	}
	92	}
	93
0ca68436	94	ret = clk_set_rate(cpu_clk, freq_exact);
95ceafd4	95	if (ret) {
fbd48ca5	96	dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
8197bb1b	97	if (!IS_ERR(cpu_reg) && volt_old > 0)
95ceafd4	98	regulator_set_voltage_tol(cpu_reg, volt_old, tol);
d4019f0a	99	return ret;
95ceafd4 SG	100	}
	101
	102	/* scaling down? scale voltage after frequency */
d4019f0a	103	if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
95ceafd4 SG	104	ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
95ceafd4 SG	105	if (ret) {
fbd48ca5 VK	106	dev_err(cpu_dev, "failed to scale voltage down: %d\n",
fbd48ca5 VK	107	ret);
d4019f0a	108	clk_set_rate(cpu_clk, old_freq * 1000);
95ceafd4 SG	109	}
	110	}
	111
fd143b4d	112	return ret;
95ceafd4 SG	113	}
95ceafd4 SG	114
95b61058	115	static int allocate_resources(int cpu, struct device **cdev,
d2f31f1d	116	struct regulator creg, struct clk cclk)
95ceafd4	117	{
d2f31f1d VK	118	struct device *cpu_dev;
	119	struct regulator *cpu_reg;
	120	struct clk *cpu_clk;
	121	int ret = 0;
2d2c5e0e	122	char reg_cpu0 = "cpu0", reg_cpu = "cpu", *reg;
95ceafd4	123
95b61058	124	cpu_dev = get_cpu_device(cpu);
e1825b25	125	if (!cpu_dev) {
95b61058	126	pr_err("failed to get cpu%d device\n", cpu);
e1825b25 SK	127	return -ENODEV;
e1825b25 SK	128	}
6754f556	129
2d2c5e0e	130	/* Try "cpu0" for older DTs */
95b61058 VK	131	if (!cpu)
	132	reg = reg_cpu0;
	133	else
	134	reg = reg_cpu;
2d2c5e0e VK	135
	136	try_again:
	137	cpu_reg = regulator_get_optional(cpu_dev, reg);
fc31d6f5 NM	138	if (IS_ERR(cpu_reg)) {
fc31d6f5 NM	139	/*
95b61058	140	* If cpu's regulator supply node is present, but regulator is
fc31d6f5 NM	141	* not yet registered, we should try defering probe.
	142	*/
	143	if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
95b61058 VK	144	dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n",
95b61058 VK	145	cpu);
d2f31f1d	146	return -EPROBE_DEFER;
fc31d6f5	147	}
2d2c5e0e VK	148
	149	/* Try with "cpu-supply" */
	150	if (reg == reg_cpu0) {
	151	reg = reg_cpu;
	152	goto try_again;
	153	}
	154
a00de1ab TP	155	dev_dbg(cpu_dev, "no regulator for cpu%d: %ld\n",
a00de1ab TP	156	cpu, PTR_ERR(cpu_reg));
fc31d6f5 NM	157	}
fc31d6f5 NM	158
e3beb0ac	159	cpu_clk = clk_get(cpu_dev, NULL);
95ceafd4	160	if (IS_ERR(cpu_clk)) {
d2f31f1d VK	161	/* put regulator */
	162	if (!IS_ERR(cpu_reg))
	163	regulator_put(cpu_reg);
	164
95ceafd4	165	ret = PTR_ERR(cpu_clk);
48a8624b VK	166
	167	/*
	168	* If cpu's clk node is present, but clock is not yet
	169	* registered, we should try defering probe.
	170	*/
	171	if (ret == -EPROBE_DEFER)
95b61058	172	dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu);
48a8624b	173	else
71796210 AK	174	dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", cpu,
71796210 AK	175	ret);
d2f31f1d VK	176	} else {
	177	*cdev = cpu_dev;
	178	*creg = cpu_reg;
	179	*cclk = cpu_clk;
	180	}
	181
	182	return ret;
	183	}
	184
bbcf0719	185	static int cpufreq_init(struct cpufreq_policy *policy)
d2f31f1d	186	{
34e5a527	187	struct cpufreq_dt_platform_data *pd;
d2f31f1d	188	struct cpufreq_frequency_table *freq_table;
d2f31f1d VK	189	struct device_node *np;
	190	struct private_data *priv;
	191	struct device *cpu_dev;
	192	struct regulator *cpu_reg;
	193	struct clk *cpu_clk;
045ee45c	194	unsigned long min_uV = ~0, max_uV = 0;
d2f31f1d VK	195	unsigned int transition_latency;
	196	int ret;
	197
95b61058	198	ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk);
d2f31f1d	199	if (ret) {
edd52b1c	200	pr_err("%s: Failed to allocate resources: %d\n", __func__, ret);
d2f31f1d VK	201	return ret;
d2f31f1d VK	202	}
48a8624b	203
d2f31f1d VK	204	np = of_node_get(cpu_dev->of_node);
	205	if (!np) {
	206	dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
	207	ret = -ENOENT;
	208	goto out_put_reg_clk;
95ceafd4 SG	209	}
95ceafd4 SG	210
1bf8cc3d VK	211	/* OPPs might be populated at runtime, don't check for error here */
1bf8cc3d VK	212	of_init_opp_table(cpu_dev);
95ceafd4	213
62a041a4 DT	214	/*
	215	* But we need OPP table to function so if it is not there let's
	216	* give platform code chance to provide it for us.
	217	*/
	218	ret = dev_pm_opp_get_opp_count(cpu_dev);
	219	if (ret <= 0) {
	220	pr_debug("OPP table is not ready, deferring probe\n");
	221	ret = -EPROBE_DEFER;
	222	goto out_free_opp;
	223	}
	224
d2f31f1d VK	225	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	226	if (!priv) {
	227	ret = -ENOMEM;
2f0f609f	228	goto out_free_opp;
95ceafd4 SG	229	}
95ceafd4 SG	230
d2f31f1d	231	of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
95ceafd4 SG	232
	233	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	234	transition_latency = CPUFREQ_ETERNAL;
	235
43c638e3	236	if (!IS_ERR(cpu_reg)) {
045ee45c	237	unsigned long opp_freq = 0;
95ceafd4 SG	238
95ceafd4 SG	239	/*
045ee45c LS	240	* Disable any OPPs where the connected regulator isn't able to
	241	* provide the specified voltage and record minimum and maximum
	242	* voltage levels.
95ceafd4	243	*/
045ee45c LS	244	while (1) {
	245	struct dev_pm_opp *opp;
	246	unsigned long opp_uV, tol_uV;
	247
	248	rcu_read_lock();
	249	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq);
	250	if (IS_ERR(opp)) {
	251	rcu_read_unlock();
	252	break;
	253	}
	254	opp_uV = dev_pm_opp_get_voltage(opp);
	255	rcu_read_unlock();
	256
	257	tol_uV = opp_uV * priv->voltage_tolerance / 100;
	258	if (regulator_is_supported_voltage(cpu_reg, opp_uV,
	259	opp_uV + tol_uV)) {
	260	if (opp_uV < min_uV)
	261	min_uV = opp_uV;
	262	if (opp_uV > max_uV)
	263	max_uV = opp_uV;
	264	} else {
	265	dev_pm_opp_disable(cpu_dev, opp_freq);
	266	}
	267
	268	opp_freq++;
	269	}
	270
95ceafd4 SG	271	ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
	272	if (ret > 0)
	273	transition_latency += ret * 1000;
	274	}
	275
045ee45c LS	276	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	277	if (ret) {
	278	pr_err("failed to init cpufreq table: %d\n", ret);
	279	goto out_free_priv;
	280	}
	281
d2f31f1d VK	282	priv->cpu_dev = cpu_dev;
	283	priv->cpu_reg = cpu_reg;
	284	policy->driver_data = priv;
	285
	286	policy->clk = cpu_clk;
34e5a527 TP	287	ret = cpufreq_table_validate_and_show(policy, freq_table);
	288	if (ret) {
	289	dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
	290	ret);
9a004428	291	goto out_free_cpufreq_table;
34e5a527 TP	292	}
	293
	294	policy->cpuinfo.transition_latency = transition_latency;
	295
	296	pd = cpufreq_get_driver_data();
c81407fe	297	if (!pd \|\| !pd->independent_clocks)
34e5a527	298	cpumask_setall(policy->cpus);
d2f31f1d	299
f9739d27 LS	300	of_node_put(np);
f9739d27 LS	301
95ceafd4 SG	302	return 0;
95ceafd4 SG	303
9a004428	304	out_free_cpufreq_table:
5d4879cd	305	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
045ee45c LS	306	out_free_priv:
045ee45c LS	307	kfree(priv);
2f0f609f VK	308	out_free_opp:
2f0f609f VK	309	of_free_opp_table(cpu_dev);
d2f31f1d VK	310	of_node_put(np);
d2f31f1d VK	311	out_put_reg_clk:
ed4b053c	312	clk_put(cpu_clk);
e3beb0ac LS	313	if (!IS_ERR(cpu_reg))
e3beb0ac LS	314	regulator_put(cpu_reg);
d2f31f1d VK	315
	316	return ret;
	317	}
	318
bbcf0719	319	static int cpufreq_exit(struct cpufreq_policy *policy)
d2f31f1d VK	320	{
	321	struct private_data *priv = policy->driver_data;
	322
9a004428 VK	323	if (priv->cdev)
9a004428 VK	324	cpufreq_cooling_unregister(priv->cdev);
d2f31f1d	325	dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
2f0f609f	326	of_free_opp_table(priv->cpu_dev);
d2f31f1d VK	327	clk_put(policy->clk);
	328	if (!IS_ERR(priv->cpu_reg))
	329	regulator_put(priv->cpu_reg);
	330	kfree(priv);
	331
	332	return 0;
	333	}
	334
9a004428 VK	335	static void cpufreq_ready(struct cpufreq_policy *policy)
	336	{
	337	struct private_data *priv = policy->driver_data;
	338	struct device_node *np = of_node_get(priv->cpu_dev->of_node);
	339
	340	if (WARN_ON(!np))
	341	return;
	342
	343	/*
	344	* For now, just loading the cooling device;
	345	* thermal DT code takes care of matching them.
	346	*/
	347	if (of_find_property(np, "#cooling-cells", NULL)) {
	348	priv->cdev = of_cpufreq_cooling_register(np,
	349	policy->related_cpus);
	350	if (IS_ERR(priv->cdev)) {
	351	dev_err(priv->cpu_dev,
	352	"running cpufreq without cooling device: %ld\n",
	353	PTR_ERR(priv->cdev));
	354
	355	priv->cdev = NULL;
	356	}
	357	}
	358
	359	of_node_put(np);
	360	}
	361
bbcf0719	362	static struct cpufreq_driver dt_cpufreq_driver = {
d2f31f1d VK	363	.flags = CPUFREQ_STICKY \| CPUFREQ_NEED_INITIAL_FREQ_CHECK,
d2f31f1d VK	364	.verify = cpufreq_generic_frequency_table_verify,
bbcf0719	365	.target_index = set_target,
d2f31f1d	366	.get = cpufreq_generic_get,
bbcf0719 VK	367	.init = cpufreq_init,
bbcf0719 VK	368	.exit = cpufreq_exit,
9a004428	369	.ready = cpufreq_ready,
bbcf0719	370	.name = "cpufreq-dt",
d2f31f1d VK	371	.attr = cpufreq_generic_attr,
	372	};
	373
bbcf0719	374	static int dt_cpufreq_probe(struct platform_device *pdev)
d2f31f1d VK	375	{
	376	struct device *cpu_dev;
	377	struct regulator *cpu_reg;
	378	struct clk *cpu_clk;
	379	int ret;
	380
	381	/*
	382	* All per-cluster (CPUs sharing clock/voltages) initialization is done
	383	* from ->init(). In probe(), we just need to make sure that clk and
	384	* regulators are available. Else defer probe and retry.
	385	*
	386	* FIXME: Is checking this only for CPU0 sufficient ?
	387	*/
95b61058	388	ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk);
d2f31f1d VK	389	if (ret)
	390	return ret;
	391
	392	clk_put(cpu_clk);
	393	if (!IS_ERR(cpu_reg))
	394	regulator_put(cpu_reg);
	395
34e5a527 TP	396	dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev);
34e5a527 TP	397
bbcf0719	398	ret = cpufreq_register_driver(&dt_cpufreq_driver);
d2f31f1d VK	399	if (ret)
	400	dev_err(cpu_dev, "failed register driver: %d\n", ret);
	401
95ceafd4 SG	402	return ret;
95ceafd4 SG	403	}
5553f9e2	404
bbcf0719	405	static int dt_cpufreq_remove(struct platform_device *pdev)
5553f9e2	406	{
bbcf0719	407	cpufreq_unregister_driver(&dt_cpufreq_driver);
5553f9e2 SG	408	return 0;
	409	}
	410
bbcf0719	411	static struct platform_driver dt_cpufreq_platdrv = {
5553f9e2	412	.driver = {
bbcf0719	413	.name = "cpufreq-dt",
5553f9e2	414	},
bbcf0719 VK	415	.probe = dt_cpufreq_probe,
bbcf0719 VK	416	.remove = dt_cpufreq_remove,
5553f9e2	417	};
bbcf0719	418	module_platform_driver(dt_cpufreq_platdrv);
95ceafd4	419
748c8766	420	MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
95ceafd4	421	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
bbcf0719	422	MODULE_DESCRIPTION("Generic cpufreq driver");
95ceafd4	423	MODULE_LICENSE("GPL");