[linux-2.6-block.git] / drivers / cpufreq / cpufreq-dt.c

/*
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * Copyright (C) 2014 Linaro.
 * Viresh Kumar <viresh.kumar@linaro.org>
 *
 * The OPP code in function set_target() is reused from
 * drivers/cpufreq/omap-cpufreq.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpu_cooling.h>
#include <linux/cpufreq.h>
#include <linux/cpufreq-dt.h>
#include <linux/cpumask.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/thermal.h>

struct private_data {
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct thermal_cooling_device *cdev;
	unsigned int voltage_tolerance; /* in percentage */
};

static int set_target(struct cpufreq_policy *policy, unsigned int index)
{
	struct dev_pm_opp *opp;
	struct cpufreq_frequency_table *freq_table = policy->freq_table;
	struct clk *cpu_clk = policy->clk;
	struct private_data *priv = policy->driver_data;
	struct device *cpu_dev = priv->cpu_dev;
	struct regulator *cpu_reg = priv->cpu_reg;
	unsigned long volt = 0, volt_old = 0, tol = 0;
	unsigned int old_freq, new_freq;
	long freq_Hz, freq_exact;
	int ret;

	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
	if (freq_Hz <= 0)
		freq_Hz = freq_table[index].frequency * 1000;

	freq_exact = freq_Hz;
	new_freq = freq_Hz / 1000;
	old_freq = clk_get_rate(cpu_clk) / 1000;

	if (!IS_ERR(cpu_reg)) {
		rcu_read_lock();
		opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
		if (IS_ERR(opp)) {
			rcu_read_unlock();
			dev_err(cpu_dev, "failed to find OPP for %ld\n",
				freq_Hz);
			return PTR_ERR(opp);
		}
		volt = dev_pm_opp_get_voltage(opp);
		rcu_read_unlock();
		tol = volt * priv->voltage_tolerance / 100;
		volt_old = regulator_get_voltage(cpu_reg);
	}

	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
		old_freq / 1000, volt_old ? volt_old / 1000 : -1,
		new_freq / 1000, volt ? volt / 1000 : -1);

	/* scaling up?  scale voltage before frequency */
	if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
		if (ret) {
			dev_err(cpu_dev, "failed to scale voltage up: %d\n",
				ret);
			return ret;
		}
	}

	ret = clk_set_rate(cpu_clk, freq_exact);
	if (ret) {
		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
		if (!IS_ERR(cpu_reg))
			regulator_set_voltage_tol(cpu_reg, volt_old, tol);
		return ret;
	}

	/* scaling down?  scale voltage after frequency */
	if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
		if (ret) {
			dev_err(cpu_dev, "failed to scale voltage down: %d\n",
				ret);
			clk_set_rate(cpu_clk, old_freq * 1000);
		}
	}

	return ret;
}

static int allocate_resources(int cpu, struct device **cdev,
			      struct regulator **creg, struct clk **cclk)
{
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct clk *cpu_clk;
	int ret = 0;
	char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg;

	cpu_dev = get_cpu_device(cpu);
	if (!cpu_dev) {
		pr_err("failed to get cpu%d device\n", cpu);
		return -ENODEV;
	}

	/* Try "cpu0" for older DTs */
	if (!cpu)
		reg = reg_cpu0;
	else
		reg = reg_cpu;

try_again:
	cpu_reg = regulator_get_optional(cpu_dev, reg);
	if (IS_ERR(cpu_reg)) {
		/*
		 * If cpu's regulator supply node is present, but regulator is
		 * not yet registered, we should try defering probe.
		 */
		if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
			dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n",
				cpu);
			return -EPROBE_DEFER;
		}

		/* Try with "cpu-supply" */
		if (reg == reg_cpu0) {
			reg = reg_cpu;
			goto try_again;
		}

		dev_dbg(cpu_dev, "no regulator for cpu%d: %ld\n",
			cpu, PTR_ERR(cpu_reg));
	}

	cpu_clk = clk_get(cpu_dev, NULL);
	if (IS_ERR(cpu_clk)) {
		/* put regulator */
		if (!IS_ERR(cpu_reg))
			regulator_put(cpu_reg);

		ret = PTR_ERR(cpu_clk);

		/*
		 * If cpu's clk node is present, but clock is not yet
		 * registered, we should try defering probe.
		 */
		if (ret == -EPROBE_DEFER)
			dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu);
		else
			dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", ret,
				cpu);
	} else {
		*cdev = cpu_dev;
		*creg = cpu_reg;
		*cclk = cpu_clk;
	}

	return ret;
}

static int cpufreq_init(struct cpufreq_policy *policy)
{
	struct cpufreq_dt_platform_data *pd;
	struct cpufreq_frequency_table *freq_table;
	struct thermal_cooling_device *cdev;
	struct device_node *np;
	struct private_data *priv;
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct clk *cpu_clk;
	unsigned int transition_latency;
	int ret;

	ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk);
	if (ret) {
		pr_err("%s: Failed to allocate resources\n: %d", __func__, ret);
		return ret;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
		ret = -ENOENT;
		goto out_put_reg_clk;
	}

	/* OPPs might be populated at runtime, don't check for error here */
	of_init_opp_table(cpu_dev);

	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
		goto out_put_node;
	}

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		ret = -ENOMEM;
		goto out_free_table;
	}

	of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	if (!IS_ERR(cpu_reg)) {
		struct dev_pm_opp *opp;
		unsigned long min_uV, max_uV;
		int i;

		/*
		 * OPP is maintained in order of increasing frequency, and
		 * freq_table initialised from OPP is therefore sorted in the
		 * same order.
		 */
		for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
			;
		rcu_read_lock();
		opp = dev_pm_opp_find_freq_exact(cpu_dev,
				freq_table[0].frequency * 1000, true);
		min_uV = dev_pm_opp_get_voltage(opp);
		opp = dev_pm_opp_find_freq_exact(cpu_dev,
				freq_table[i-1].frequency * 1000, true);
		max_uV = dev_pm_opp_get_voltage(opp);
		rcu_read_unlock();
		ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	/*
	 * For now, just loading the cooling device;
	 * thermal DT code takes care of matching them.
	 */
	if (of_find_property(np, "#cooling-cells", NULL)) {
		cdev = of_cpufreq_cooling_register(np, cpu_present_mask);
		if (IS_ERR(cdev))
			dev_err(cpu_dev,
				"running cpufreq without cooling device: %ld\n",
				PTR_ERR(cdev));
		else
			priv->cdev = cdev;
	}

	priv->cpu_dev = cpu_dev;
	priv->cpu_reg = cpu_reg;
	policy->driver_data = priv;

	policy->clk = cpu_clk;
	ret = cpufreq_table_validate_and_show(policy, freq_table);
	if (ret) {
		dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
			ret);
		goto out_cooling_unregister;
	}

	policy->cpuinfo.transition_latency = transition_latency;

	pd = cpufreq_get_driver_data();
	if (pd && !pd->independent_clocks)
		cpumask_setall(policy->cpus);

	of_node_put(np);

	return 0;

out_cooling_unregister:
	cpufreq_cooling_unregister(priv->cdev);
	kfree(priv);
out_free_table:
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
out_put_node:
	of_node_put(np);
out_put_reg_clk:
	clk_put(cpu_clk);
	if (!IS_ERR(cpu_reg))
		regulator_put(cpu_reg);

	return ret;
}

static int cpufreq_exit(struct cpufreq_policy *policy)
{
	struct private_data *priv = policy->driver_data;

	cpufreq_cooling_unregister(priv->cdev);
	dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
	clk_put(policy->clk);
	if (!IS_ERR(priv->cpu_reg))
		regulator_put(priv->cpu_reg);
	kfree(priv);

	return 0;
}

static struct cpufreq_driver dt_cpufreq_driver = {
	.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = set_target,
	.get = cpufreq_generic_get,
	.init = cpufreq_init,
	.exit = cpufreq_exit,
	.name = "cpufreq-dt",
	.attr = cpufreq_generic_attr,
};

static int dt_cpufreq_probe(struct platform_device *pdev)
{
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct clk *cpu_clk;
	int ret;

	/*
	 * All per-cluster (CPUs sharing clock/voltages) initialization is done
	 * from ->init(). In probe(), we just need to make sure that clk and
	 * regulators are available. Else defer probe and retry.
	 *
	 * FIXME: Is checking this only for CPU0 sufficient ?
	 */
	ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk);
	if (ret)
		return ret;

	clk_put(cpu_clk);
	if (!IS_ERR(cpu_reg))
		regulator_put(cpu_reg);

	dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev);

	ret = cpufreq_register_driver(&dt_cpufreq_driver);
	if (ret)
		dev_err(cpu_dev, "failed register driver: %d\n", ret);

	return ret;
}

static int dt_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&dt_cpufreq_driver);
	return 0;
}

static struct platform_driver dt_cpufreq_platdrv = {
	.driver = {
		.name	= "cpufreq-dt",
		.owner	= THIS_MODULE,
	},
	.probe		= dt_cpufreq_probe,
	.remove		= dt_cpufreq_remove,
};
module_platform_driver(dt_cpufreq_platdrv);

MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Generic cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
95ceafd4 SG	1	/*
	2	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	3	*
748c8766 VK	4	* Copyright (C) 2014 Linaro.
	5	* Viresh Kumar <viresh.kumar@linaro.org>
	6	*
bbcf0719	7	* The OPP code in function set_target() is reused from
95ceafd4 SG	8	* drivers/cpufreq/omap-cpufreq.c
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	16
	17	#include <linux/clk.h>
e1825b25	18	#include <linux/cpu.h>
77cff592	19	#include <linux/cpu_cooling.h>
95ceafd4	20	#include <linux/cpufreq.h>
34e5a527	21	#include <linux/cpufreq-dt.h>
77cff592	22	#include <linux/cpumask.h>
95ceafd4 SG	23	#include <linux/err.h>
	24	#include <linux/module.h>
	25	#include <linux/of.h>
e4db1c74	26	#include <linux/pm_opp.h>
5553f9e2	27	#include <linux/platform_device.h>
95ceafd4 SG	28	#include <linux/regulator/consumer.h>
95ceafd4 SG	29	#include <linux/slab.h>
77cff592	30	#include <linux/thermal.h>
95ceafd4	31
d2f31f1d VK	32	struct private_data {
	33	struct device *cpu_dev;
	34	struct regulator *cpu_reg;
	35	struct thermal_cooling_device *cdev;
	36	unsigned int voltage_tolerance; /* in percentage */
	37	};
95ceafd4	38
bbcf0719	39	static int set_target(struct cpufreq_policy *policy, unsigned int index)
95ceafd4	40	{
47d43ba7	41	struct dev_pm_opp *opp;
d2f31f1d VK	42	struct cpufreq_frequency_table *freq_table = policy->freq_table;
	43	struct clk *cpu_clk = policy->clk;
	44	struct private_data *priv = policy->driver_data;
	45	struct device *cpu_dev = priv->cpu_dev;
	46	struct regulator *cpu_reg = priv->cpu_reg;
5df60559	47	unsigned long volt = 0, volt_old = 0, tol = 0;
d4019f0a	48	unsigned int old_freq, new_freq;
0ca68436	49	long freq_Hz, freq_exact;
95ceafd4 SG	50	int ret;
95ceafd4 SG	51
95ceafd4	52	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
2209b0c9	53	if (freq_Hz <= 0)
95ceafd4	54	freq_Hz = freq_table[index].frequency * 1000;
95ceafd4	55
d4019f0a VK	56	freq_exact = freq_Hz;
	57	new_freq = freq_Hz / 1000;
	58	old_freq = clk_get_rate(cpu_clk) / 1000;
95ceafd4	59
4a511de9	60	if (!IS_ERR(cpu_reg)) {
78e8eb8f	61	rcu_read_lock();
5d4879cd	62	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
95ceafd4	63	if (IS_ERR(opp)) {
78e8eb8f	64	rcu_read_unlock();
fbd48ca5 VK	65	dev_err(cpu_dev, "failed to find OPP for %ld\n",
fbd48ca5 VK	66	freq_Hz);
d4019f0a	67	return PTR_ERR(opp);
95ceafd4	68	}
5d4879cd	69	volt = dev_pm_opp_get_voltage(opp);
78e8eb8f	70	rcu_read_unlock();
d2f31f1d	71	tol = volt * priv->voltage_tolerance / 100;
95ceafd4 SG	72	volt_old = regulator_get_voltage(cpu_reg);
	73	}
	74
fbd48ca5 VK	75	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
	76	old_freq / 1000, volt_old ? volt_old / 1000 : -1,
	77	new_freq / 1000, volt ? volt / 1000 : -1);
95ceafd4 SG	78
95ceafd4 SG	79	/* scaling up? scale voltage before frequency */
d4019f0a	80	if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
95ceafd4 SG	81	ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
95ceafd4 SG	82	if (ret) {
fbd48ca5 VK	83	dev_err(cpu_dev, "failed to scale voltage up: %d\n",
fbd48ca5 VK	84	ret);
d4019f0a	85	return ret;
95ceafd4 SG	86	}
	87	}
	88
0ca68436	89	ret = clk_set_rate(cpu_clk, freq_exact);
95ceafd4	90	if (ret) {
fbd48ca5	91	dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
4a511de9	92	if (!IS_ERR(cpu_reg))
95ceafd4	93	regulator_set_voltage_tol(cpu_reg, volt_old, tol);
d4019f0a	94	return ret;
95ceafd4 SG	95	}
	96
	97	/* scaling down? scale voltage after frequency */
d4019f0a	98	if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
95ceafd4 SG	99	ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
95ceafd4 SG	100	if (ret) {
fbd48ca5 VK	101	dev_err(cpu_dev, "failed to scale voltage down: %d\n",
fbd48ca5 VK	102	ret);
d4019f0a	103	clk_set_rate(cpu_clk, old_freq * 1000);
95ceafd4 SG	104	}
	105	}
	106
fd143b4d	107	return ret;
95ceafd4 SG	108	}
95ceafd4 SG	109
95b61058	110	static int allocate_resources(int cpu, struct device **cdev,
d2f31f1d	111	struct regulator creg, struct clk cclk)
95ceafd4	112	{
d2f31f1d VK	113	struct device *cpu_dev;
	114	struct regulator *cpu_reg;
	115	struct clk *cpu_clk;
	116	int ret = 0;
2d2c5e0e	117	char reg_cpu0 = "cpu0", reg_cpu = "cpu", *reg;
95ceafd4	118
95b61058	119	cpu_dev = get_cpu_device(cpu);
e1825b25	120	if (!cpu_dev) {
95b61058	121	pr_err("failed to get cpu%d device\n", cpu);
e1825b25 SK	122	return -ENODEV;
e1825b25 SK	123	}
6754f556	124
2d2c5e0e	125	/* Try "cpu0" for older DTs */
95b61058 VK	126	if (!cpu)
	127	reg = reg_cpu0;
	128	else
	129	reg = reg_cpu;
2d2c5e0e VK	130
	131	try_again:
	132	cpu_reg = regulator_get_optional(cpu_dev, reg);
fc31d6f5 NM	133	if (IS_ERR(cpu_reg)) {
fc31d6f5 NM	134	/*
95b61058	135	* If cpu's regulator supply node is present, but regulator is
fc31d6f5 NM	136	* not yet registered, we should try defering probe.
	137	*/
	138	if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
95b61058 VK	139	dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n",
95b61058 VK	140	cpu);
d2f31f1d	141	return -EPROBE_DEFER;
fc31d6f5	142	}
2d2c5e0e VK	143
	144	/* Try with "cpu-supply" */
	145	if (reg == reg_cpu0) {
	146	reg = reg_cpu;
	147	goto try_again;
	148	}
	149
a00de1ab TP	150	dev_dbg(cpu_dev, "no regulator for cpu%d: %ld\n",
a00de1ab TP	151	cpu, PTR_ERR(cpu_reg));
fc31d6f5 NM	152	}
fc31d6f5 NM	153
e3beb0ac	154	cpu_clk = clk_get(cpu_dev, NULL);
95ceafd4	155	if (IS_ERR(cpu_clk)) {
d2f31f1d VK	156	/* put regulator */
	157	if (!IS_ERR(cpu_reg))
	158	regulator_put(cpu_reg);
	159
95ceafd4	160	ret = PTR_ERR(cpu_clk);
48a8624b VK	161
	162	/*
	163	* If cpu's clk node is present, but clock is not yet
	164	* registered, we should try defering probe.
	165	*/
	166	if (ret == -EPROBE_DEFER)
95b61058	167	dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu);
48a8624b	168	else
95b61058 VK	169	dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", ret,
95b61058 VK	170	cpu);
d2f31f1d VK	171	} else {
	172	*cdev = cpu_dev;
	173	*creg = cpu_reg;
	174	*cclk = cpu_clk;
	175	}
	176
	177	return ret;
	178	}
	179
bbcf0719	180	static int cpufreq_init(struct cpufreq_policy *policy)
d2f31f1d	181	{
34e5a527	182	struct cpufreq_dt_platform_data *pd;
d2f31f1d VK	183	struct cpufreq_frequency_table *freq_table;
	184	struct thermal_cooling_device *cdev;
	185	struct device_node *np;
	186	struct private_data *priv;
	187	struct device *cpu_dev;
	188	struct regulator *cpu_reg;
	189	struct clk *cpu_clk;
	190	unsigned int transition_latency;
	191	int ret;
	192
95b61058	193	ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk);
d2f31f1d VK	194	if (ret) {
	195	pr_err("%s: Failed to allocate resources\n: %d", __func__, ret);
	196	return ret;
	197	}
48a8624b	198
d2f31f1d VK	199	np = of_node_get(cpu_dev->of_node);
	200	if (!np) {
	201	dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
	202	ret = -ENOENT;
	203	goto out_put_reg_clk;
95ceafd4 SG	204	}
95ceafd4 SG	205
1bf8cc3d VK	206	/* OPPs might be populated at runtime, don't check for error here */
1bf8cc3d VK	207	of_init_opp_table(cpu_dev);
95ceafd4	208
5d4879cd	209	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
95ceafd4	210	if (ret) {
fbd48ca5	211	dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
d2f31f1d VK	212	goto out_put_node;
	213	}
	214
	215	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	216	if (!priv) {
	217	ret = -ENOMEM;
	218	goto out_free_table;
95ceafd4 SG	219	}
95ceafd4 SG	220
d2f31f1d	221	of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
95ceafd4 SG	222
	223	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	224	transition_latency = CPUFREQ_ETERNAL;
	225
43c638e3	226	if (!IS_ERR(cpu_reg)) {
47d43ba7	227	struct dev_pm_opp *opp;
95ceafd4 SG	228	unsigned long min_uV, max_uV;
	229	int i;
	230
	231	/*
	232	* OPP is maintained in order of increasing frequency, and
	233	* freq_table initialised from OPP is therefore sorted in the
	234	* same order.
	235	*/
	236	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
	237	;
78e8eb8f	238	rcu_read_lock();
5d4879cd	239	opp = dev_pm_opp_find_freq_exact(cpu_dev,
95ceafd4	240	freq_table[0].frequency * 1000, true);
5d4879cd NM	241	min_uV = dev_pm_opp_get_voltage(opp);
5d4879cd NM	242	opp = dev_pm_opp_find_freq_exact(cpu_dev,
95ceafd4	243	freq_table[i-1].frequency * 1000, true);
5d4879cd	244	max_uV = dev_pm_opp_get_voltage(opp);
78e8eb8f	245	rcu_read_unlock();
95ceafd4 SG	246	ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
	247	if (ret > 0)
	248	transition_latency += ret * 1000;
	249	}
	250
77cff592 EV	251	/*
	252	* For now, just loading the cooling device;
	253	* thermal DT code takes care of matching them.
	254	*/
	255	if (of_find_property(np, "#cooling-cells", NULL)) {
	256	cdev = of_cpufreq_cooling_register(np, cpu_present_mask);
	257	if (IS_ERR(cdev))
fbd48ca5 VK	258	dev_err(cpu_dev,
	259	"running cpufreq without cooling device: %ld\n",
	260	PTR_ERR(cdev));
d2f31f1d VK	261	else
d2f31f1d VK	262	priv->cdev = cdev;
77cff592	263	}
d2f31f1d VK	264
	265	priv->cpu_dev = cpu_dev;
	266	priv->cpu_reg = cpu_reg;
	267	policy->driver_data = priv;
	268
	269	policy->clk = cpu_clk;
34e5a527 TP	270	ret = cpufreq_table_validate_and_show(policy, freq_table);
	271	if (ret) {
	272	dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
	273	ret);
d2f31f1d	274	goto out_cooling_unregister;
34e5a527 TP	275	}
	276
	277	policy->cpuinfo.transition_latency = transition_latency;
	278
	279	pd = cpufreq_get_driver_data();
	280	if (pd && !pd->independent_clocks)
	281	cpumask_setall(policy->cpus);
d2f31f1d	282
f9739d27 LS	283	of_node_put(np);
f9739d27 LS	284
95ceafd4 SG	285	return 0;
95ceafd4 SG	286
d2f31f1d VK	287	out_cooling_unregister:
	288	cpufreq_cooling_unregister(priv->cdev);
	289	kfree(priv);
95ceafd4	290	out_free_table:
5d4879cd	291	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
d2f31f1d VK	292	out_put_node:
	293	of_node_put(np);
	294	out_put_reg_clk:
ed4b053c	295	clk_put(cpu_clk);
e3beb0ac LS	296	if (!IS_ERR(cpu_reg))
e3beb0ac LS	297	regulator_put(cpu_reg);
d2f31f1d VK	298
	299	return ret;
	300	}
	301
bbcf0719	302	static int cpufreq_exit(struct cpufreq_policy *policy)
d2f31f1d VK	303	{
	304	struct private_data *priv = policy->driver_data;
	305
	306	cpufreq_cooling_unregister(priv->cdev);
	307	dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
	308	clk_put(policy->clk);
	309	if (!IS_ERR(priv->cpu_reg))
	310	regulator_put(priv->cpu_reg);
	311	kfree(priv);
	312
	313	return 0;
	314	}
	315
bbcf0719	316	static struct cpufreq_driver dt_cpufreq_driver = {
d2f31f1d VK	317	.flags = CPUFREQ_STICKY \| CPUFREQ_NEED_INITIAL_FREQ_CHECK,
d2f31f1d VK	318	.verify = cpufreq_generic_frequency_table_verify,
bbcf0719	319	.target_index = set_target,
d2f31f1d	320	.get = cpufreq_generic_get,
bbcf0719 VK	321	.init = cpufreq_init,
	322	.exit = cpufreq_exit,
	323	.name = "cpufreq-dt",
d2f31f1d VK	324	.attr = cpufreq_generic_attr,
	325	};
	326
bbcf0719	327	static int dt_cpufreq_probe(struct platform_device *pdev)
d2f31f1d VK	328	{
	329	struct device *cpu_dev;
	330	struct regulator *cpu_reg;
	331	struct clk *cpu_clk;
	332	int ret;
	333
	334	/*
	335	* All per-cluster (CPUs sharing clock/voltages) initialization is done
	336	* from ->init(). In probe(), we just need to make sure that clk and
	337	* regulators are available. Else defer probe and retry.
	338	*
	339	* FIXME: Is checking this only for CPU0 sufficient ?
	340	*/
95b61058	341	ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk);
d2f31f1d VK	342	if (ret)
	343	return ret;
	344
	345	clk_put(cpu_clk);
	346	if (!IS_ERR(cpu_reg))
	347	regulator_put(cpu_reg);
	348
34e5a527 TP	349	dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev);
34e5a527 TP	350
bbcf0719	351	ret = cpufreq_register_driver(&dt_cpufreq_driver);
d2f31f1d VK	352	if (ret)
	353	dev_err(cpu_dev, "failed register driver: %d\n", ret);
	354
95ceafd4 SG	355	return ret;
95ceafd4 SG	356	}
5553f9e2	357
bbcf0719	358	static int dt_cpufreq_remove(struct platform_device *pdev)
5553f9e2	359	{
bbcf0719	360	cpufreq_unregister_driver(&dt_cpufreq_driver);
5553f9e2 SG	361	return 0;
	362	}
	363
bbcf0719	364	static struct platform_driver dt_cpufreq_platdrv = {
5553f9e2	365	.driver = {
bbcf0719	366	.name = "cpufreq-dt",
5553f9e2 SG	367	.owner = THIS_MODULE,
5553f9e2 SG	368	},
bbcf0719 VK	369	.probe = dt_cpufreq_probe,
bbcf0719 VK	370	.remove = dt_cpufreq_remove,
5553f9e2	371	};
bbcf0719	372	module_platform_driver(dt_cpufreq_platdrv);
95ceafd4	373
748c8766	374	MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
95ceafd4	375	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
bbcf0719	376	MODULE_DESCRIPTION("Generic cpufreq driver");
95ceafd4	377	MODULE_LICENSE("GPL");