Commit | Line | Data |
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95ceafd4 SG |
1 | /* |
2 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
3 | * | |
748c8766 VK |
4 | * Copyright (C) 2014 Linaro. |
5 | * Viresh Kumar <viresh.kumar@linaro.org> | |
6 | * | |
bbcf0719 | 7 | * The OPP code in function set_target() is reused from |
95ceafd4 SG |
8 | * drivers/cpufreq/omap-cpufreq.c |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
16 | ||
17 | #include <linux/clk.h> | |
e1825b25 | 18 | #include <linux/cpu.h> |
77cff592 | 19 | #include <linux/cpu_cooling.h> |
95ceafd4 | 20 | #include <linux/cpufreq.h> |
34e5a527 | 21 | #include <linux/cpufreq-dt.h> |
77cff592 | 22 | #include <linux/cpumask.h> |
95ceafd4 SG |
23 | #include <linux/err.h> |
24 | #include <linux/module.h> | |
25 | #include <linux/of.h> | |
e4db1c74 | 26 | #include <linux/pm_opp.h> |
5553f9e2 | 27 | #include <linux/platform_device.h> |
95ceafd4 SG |
28 | #include <linux/regulator/consumer.h> |
29 | #include <linux/slab.h> | |
77cff592 | 30 | #include <linux/thermal.h> |
95ceafd4 | 31 | |
d2f31f1d VK |
32 | struct private_data { |
33 | struct device *cpu_dev; | |
34 | struct regulator *cpu_reg; | |
35 | struct thermal_cooling_device *cdev; | |
36 | unsigned int voltage_tolerance; /* in percentage */ | |
050794aa | 37 | const char *reg_name; |
d2f31f1d | 38 | }; |
95ceafd4 | 39 | |
21c36d35 BZ |
40 | static struct freq_attr *cpufreq_dt_attr[] = { |
41 | &cpufreq_freq_attr_scaling_available_freqs, | |
42 | NULL, /* Extra space for boost-attr if required */ | |
43 | NULL, | |
44 | }; | |
45 | ||
bbcf0719 | 46 | static int set_target(struct cpufreq_policy *policy, unsigned int index) |
95ceafd4 | 47 | { |
47d43ba7 | 48 | struct dev_pm_opp *opp; |
d2f31f1d VK |
49 | struct cpufreq_frequency_table *freq_table = policy->freq_table; |
50 | struct clk *cpu_clk = policy->clk; | |
51 | struct private_data *priv = policy->driver_data; | |
52 | struct device *cpu_dev = priv->cpu_dev; | |
53 | struct regulator *cpu_reg = priv->cpu_reg; | |
929ca89c AH |
54 | unsigned long volt = 0, tol = 0; |
55 | int volt_old = 0; | |
d4019f0a | 56 | unsigned int old_freq, new_freq; |
0ca68436 | 57 | long freq_Hz, freq_exact; |
95ceafd4 SG |
58 | int ret; |
59 | ||
95ceafd4 | 60 | freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); |
2209b0c9 | 61 | if (freq_Hz <= 0) |
95ceafd4 | 62 | freq_Hz = freq_table[index].frequency * 1000; |
95ceafd4 | 63 | |
d4019f0a VK |
64 | freq_exact = freq_Hz; |
65 | new_freq = freq_Hz / 1000; | |
66 | old_freq = clk_get_rate(cpu_clk) / 1000; | |
95ceafd4 | 67 | |
4a511de9 | 68 | if (!IS_ERR(cpu_reg)) { |
0a1e879d SW |
69 | unsigned long opp_freq; |
70 | ||
78e8eb8f | 71 | rcu_read_lock(); |
5d4879cd | 72 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); |
95ceafd4 | 73 | if (IS_ERR(opp)) { |
78e8eb8f | 74 | rcu_read_unlock(); |
fbd48ca5 VK |
75 | dev_err(cpu_dev, "failed to find OPP for %ld\n", |
76 | freq_Hz); | |
d4019f0a | 77 | return PTR_ERR(opp); |
95ceafd4 | 78 | } |
5d4879cd | 79 | volt = dev_pm_opp_get_voltage(opp); |
0a1e879d | 80 | opp_freq = dev_pm_opp_get_freq(opp); |
78e8eb8f | 81 | rcu_read_unlock(); |
d2f31f1d | 82 | tol = volt * priv->voltage_tolerance / 100; |
95ceafd4 | 83 | volt_old = regulator_get_voltage(cpu_reg); |
0a1e879d SW |
84 | dev_dbg(cpu_dev, "Found OPP: %ld kHz, %ld uV\n", |
85 | opp_freq / 1000, volt); | |
95ceafd4 SG |
86 | } |
87 | ||
929ca89c | 88 | dev_dbg(cpu_dev, "%u MHz, %d mV --> %u MHz, %ld mV\n", |
8197bb1b | 89 | old_freq / 1000, (volt_old > 0) ? volt_old / 1000 : -1, |
fbd48ca5 | 90 | new_freq / 1000, volt ? volt / 1000 : -1); |
95ceafd4 SG |
91 | |
92 | /* scaling up? scale voltage before frequency */ | |
d4019f0a | 93 | if (!IS_ERR(cpu_reg) && new_freq > old_freq) { |
95ceafd4 SG |
94 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
95 | if (ret) { | |
fbd48ca5 VK |
96 | dev_err(cpu_dev, "failed to scale voltage up: %d\n", |
97 | ret); | |
d4019f0a | 98 | return ret; |
95ceafd4 SG |
99 | } |
100 | } | |
101 | ||
0ca68436 | 102 | ret = clk_set_rate(cpu_clk, freq_exact); |
95ceafd4 | 103 | if (ret) { |
fbd48ca5 | 104 | dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); |
8197bb1b | 105 | if (!IS_ERR(cpu_reg) && volt_old > 0) |
95ceafd4 | 106 | regulator_set_voltage_tol(cpu_reg, volt_old, tol); |
d4019f0a | 107 | return ret; |
95ceafd4 SG |
108 | } |
109 | ||
110 | /* scaling down? scale voltage after frequency */ | |
d4019f0a | 111 | if (!IS_ERR(cpu_reg) && new_freq < old_freq) { |
95ceafd4 SG |
112 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
113 | if (ret) { | |
fbd48ca5 VK |
114 | dev_err(cpu_dev, "failed to scale voltage down: %d\n", |
115 | ret); | |
d4019f0a | 116 | clk_set_rate(cpu_clk, old_freq * 1000); |
95ceafd4 SG |
117 | } |
118 | } | |
119 | ||
fd143b4d | 120 | return ret; |
95ceafd4 SG |
121 | } |
122 | ||
050794aa VK |
123 | /* |
124 | * An earlier version of opp-v1 bindings used to name the regulator | |
125 | * "cpu0-supply", we still need to handle that for backwards compatibility. | |
126 | */ | |
127 | static const char *find_supply_name(struct device *dev, struct device_node *np) | |
128 | { | |
129 | struct property *pp; | |
130 | int cpu = dev->id; | |
131 | ||
132 | /* Try "cpu0" for older DTs */ | |
133 | if (!cpu) { | |
134 | pp = of_find_property(np, "cpu0-supply", NULL); | |
135 | if (pp) | |
136 | return "cpu0"; | |
137 | } | |
138 | ||
139 | pp = of_find_property(np, "cpu-supply", NULL); | |
140 | if (pp) | |
141 | return "cpu"; | |
142 | ||
143 | dev_dbg(dev, "no regulator for cpu%d\n", cpu); | |
144 | return NULL; | |
145 | } | |
146 | ||
95b61058 | 147 | static int allocate_resources(int cpu, struct device **cdev, |
d2f31f1d | 148 | struct regulator **creg, struct clk **cclk) |
95ceafd4 | 149 | { |
d2f31f1d VK |
150 | struct device *cpu_dev; |
151 | struct regulator *cpu_reg; | |
152 | struct clk *cpu_clk; | |
153 | int ret = 0; | |
2d2c5e0e | 154 | char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg; |
95ceafd4 | 155 | |
95b61058 | 156 | cpu_dev = get_cpu_device(cpu); |
e1825b25 | 157 | if (!cpu_dev) { |
95b61058 | 158 | pr_err("failed to get cpu%d device\n", cpu); |
e1825b25 SK |
159 | return -ENODEV; |
160 | } | |
6754f556 | 161 | |
2d2c5e0e | 162 | /* Try "cpu0" for older DTs */ |
95b61058 VK |
163 | if (!cpu) |
164 | reg = reg_cpu0; | |
165 | else | |
166 | reg = reg_cpu; | |
2d2c5e0e VK |
167 | |
168 | try_again: | |
169 | cpu_reg = regulator_get_optional(cpu_dev, reg); | |
b331bc20 AB |
170 | ret = PTR_ERR_OR_ZERO(cpu_reg); |
171 | if (ret) { | |
fc31d6f5 | 172 | /* |
95b61058 | 173 | * If cpu's regulator supply node is present, but regulator is |
fc31d6f5 NM |
174 | * not yet registered, we should try defering probe. |
175 | */ | |
b331bc20 | 176 | if (ret == -EPROBE_DEFER) { |
95b61058 VK |
177 | dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n", |
178 | cpu); | |
b331bc20 | 179 | return ret; |
fc31d6f5 | 180 | } |
2d2c5e0e VK |
181 | |
182 | /* Try with "cpu-supply" */ | |
183 | if (reg == reg_cpu0) { | |
184 | reg = reg_cpu; | |
185 | goto try_again; | |
186 | } | |
187 | ||
b331bc20 | 188 | dev_dbg(cpu_dev, "no regulator for cpu%d: %d\n", cpu, ret); |
fc31d6f5 NM |
189 | } |
190 | ||
e3beb0ac | 191 | cpu_clk = clk_get(cpu_dev, NULL); |
b331bc20 AB |
192 | ret = PTR_ERR_OR_ZERO(cpu_clk); |
193 | if (ret) { | |
d2f31f1d VK |
194 | /* put regulator */ |
195 | if (!IS_ERR(cpu_reg)) | |
196 | regulator_put(cpu_reg); | |
197 | ||
48a8624b VK |
198 | /* |
199 | * If cpu's clk node is present, but clock is not yet | |
200 | * registered, we should try defering probe. | |
201 | */ | |
202 | if (ret == -EPROBE_DEFER) | |
95b61058 | 203 | dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu); |
48a8624b | 204 | else |
71796210 AK |
205 | dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", cpu, |
206 | ret); | |
d2f31f1d VK |
207 | } else { |
208 | *cdev = cpu_dev; | |
209 | *creg = cpu_reg; | |
210 | *cclk = cpu_clk; | |
211 | } | |
212 | ||
213 | return ret; | |
214 | } | |
215 | ||
bbcf0719 | 216 | static int cpufreq_init(struct cpufreq_policy *policy) |
d2f31f1d VK |
217 | { |
218 | struct cpufreq_frequency_table *freq_table; | |
d2f31f1d VK |
219 | struct device_node *np; |
220 | struct private_data *priv; | |
221 | struct device *cpu_dev; | |
222 | struct regulator *cpu_reg; | |
223 | struct clk *cpu_clk; | |
953ba9ff | 224 | struct dev_pm_opp *suspend_opp; |
045ee45c | 225 | unsigned long min_uV = ~0, max_uV = 0; |
d2f31f1d | 226 | unsigned int transition_latency; |
457e99e6 | 227 | bool opp_v1 = false; |
050794aa | 228 | const char *name; |
d2f31f1d VK |
229 | int ret; |
230 | ||
95b61058 | 231 | ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk); |
d2f31f1d | 232 | if (ret) { |
edd52b1c | 233 | pr_err("%s: Failed to allocate resources: %d\n", __func__, ret); |
d2f31f1d VK |
234 | return ret; |
235 | } | |
48a8624b | 236 | |
d2f31f1d VK |
237 | np = of_node_get(cpu_dev->of_node); |
238 | if (!np) { | |
239 | dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu); | |
240 | ret = -ENOENT; | |
241 | goto out_put_reg_clk; | |
95ceafd4 SG |
242 | } |
243 | ||
2e02d872 | 244 | /* Get OPP-sharing information from "operating-points-v2" bindings */ |
8f8d37b2 | 245 | ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, policy->cpus); |
2e02d872 VK |
246 | if (ret) { |
247 | /* | |
248 | * operating-points-v2 not supported, fallback to old method of | |
249 | * finding shared-OPPs for backward compatibility. | |
250 | */ | |
251 | if (ret == -ENOENT) | |
457e99e6 | 252 | opp_v1 = true; |
2e02d872 VK |
253 | else |
254 | goto out_node_put; | |
255 | } | |
256 | ||
050794aa VK |
257 | /* |
258 | * OPP layer will be taking care of regulators now, but it needs to know | |
259 | * the name of the regulator first. | |
260 | */ | |
261 | name = find_supply_name(cpu_dev, np); | |
262 | if (name) { | |
263 | ret = dev_pm_opp_set_regulator(cpu_dev, name); | |
264 | if (ret) { | |
265 | dev_err(cpu_dev, "Failed to set regulator for cpu%d: %d\n", | |
266 | policy->cpu, ret); | |
267 | goto out_node_put; | |
268 | } | |
269 | } | |
270 | ||
2e02d872 VK |
271 | /* |
272 | * Initialize OPP tables for all policy->cpus. They will be shared by | |
273 | * all CPUs which have marked their CPUs shared with OPP bindings. | |
274 | * | |
275 | * For platforms not using operating-points-v2 bindings, we do this | |
276 | * before updating policy->cpus. Otherwise, we will end up creating | |
277 | * duplicate OPPs for policy->cpus. | |
278 | * | |
279 | * OPPs might be populated at runtime, don't check for error here | |
280 | */ | |
8f8d37b2 | 281 | dev_pm_opp_of_cpumask_add_table(policy->cpus); |
2e02d872 | 282 | |
7d5d0c8b VK |
283 | /* |
284 | * But we need OPP table to function so if it is not there let's | |
285 | * give platform code chance to provide it for us. | |
286 | */ | |
287 | ret = dev_pm_opp_get_opp_count(cpu_dev); | |
288 | if (ret <= 0) { | |
896d6a4c | 289 | dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n"); |
7d5d0c8b VK |
290 | ret = -EPROBE_DEFER; |
291 | goto out_free_opp; | |
292 | } | |
293 | ||
457e99e6 | 294 | if (opp_v1) { |
2e02d872 VK |
295 | struct cpufreq_dt_platform_data *pd = cpufreq_get_driver_data(); |
296 | ||
297 | if (!pd || !pd->independent_clocks) | |
298 | cpumask_setall(policy->cpus); | |
299 | ||
300 | /* | |
301 | * OPP tables are initialized only for policy->cpu, do it for | |
302 | * others as well. | |
303 | */ | |
8f8d37b2 | 304 | ret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); |
8bc86284 VK |
305 | if (ret) |
306 | dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n", | |
307 | __func__, ret); | |
2e02d872 | 308 | } |
95ceafd4 | 309 | |
d2f31f1d VK |
310 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
311 | if (!priv) { | |
312 | ret = -ENOMEM; | |
2f0f609f | 313 | goto out_free_opp; |
95ceafd4 SG |
314 | } |
315 | ||
050794aa | 316 | priv->reg_name = name; |
d2f31f1d | 317 | of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance); |
95ceafd4 | 318 | |
391d9aef | 319 | transition_latency = dev_pm_opp_get_max_clock_latency(cpu_dev); |
2e02d872 | 320 | if (!transition_latency) |
95ceafd4 SG |
321 | transition_latency = CPUFREQ_ETERNAL; |
322 | ||
43c638e3 | 323 | if (!IS_ERR(cpu_reg)) { |
045ee45c | 324 | unsigned long opp_freq = 0; |
95ceafd4 SG |
325 | |
326 | /* | |
045ee45c LS |
327 | * Disable any OPPs where the connected regulator isn't able to |
328 | * provide the specified voltage and record minimum and maximum | |
329 | * voltage levels. | |
95ceafd4 | 330 | */ |
045ee45c LS |
331 | while (1) { |
332 | struct dev_pm_opp *opp; | |
333 | unsigned long opp_uV, tol_uV; | |
334 | ||
335 | rcu_read_lock(); | |
336 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq); | |
337 | if (IS_ERR(opp)) { | |
338 | rcu_read_unlock(); | |
339 | break; | |
340 | } | |
341 | opp_uV = dev_pm_opp_get_voltage(opp); | |
342 | rcu_read_unlock(); | |
343 | ||
344 | tol_uV = opp_uV * priv->voltage_tolerance / 100; | |
a2022001 VK |
345 | if (regulator_is_supported_voltage(cpu_reg, |
346 | opp_uV - tol_uV, | |
045ee45c LS |
347 | opp_uV + tol_uV)) { |
348 | if (opp_uV < min_uV) | |
349 | min_uV = opp_uV; | |
350 | if (opp_uV > max_uV) | |
351 | max_uV = opp_uV; | |
045ee45c LS |
352 | } |
353 | ||
354 | opp_freq++; | |
355 | } | |
356 | ||
95ceafd4 SG |
357 | ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV); |
358 | if (ret > 0) | |
359 | transition_latency += ret * 1000; | |
360 | } | |
361 | ||
045ee45c LS |
362 | ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); |
363 | if (ret) { | |
896d6a4c | 364 | dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); |
045ee45c LS |
365 | goto out_free_priv; |
366 | } | |
367 | ||
d2f31f1d VK |
368 | priv->cpu_dev = cpu_dev; |
369 | priv->cpu_reg = cpu_reg; | |
370 | policy->driver_data = priv; | |
371 | ||
372 | policy->clk = cpu_clk; | |
953ba9ff BZ |
373 | |
374 | rcu_read_lock(); | |
375 | suspend_opp = dev_pm_opp_get_suspend_opp(cpu_dev); | |
376 | if (suspend_opp) | |
377 | policy->suspend_freq = dev_pm_opp_get_freq(suspend_opp) / 1000; | |
378 | rcu_read_unlock(); | |
379 | ||
34e5a527 TP |
380 | ret = cpufreq_table_validate_and_show(policy, freq_table); |
381 | if (ret) { | |
382 | dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__, | |
383 | ret); | |
9a004428 | 384 | goto out_free_cpufreq_table; |
d15fa862 VK |
385 | } |
386 | ||
387 | /* Support turbo/boost mode */ | |
388 | if (policy_has_boost_freq(policy)) { | |
389 | /* This gets disabled by core on driver unregister */ | |
390 | ret = cpufreq_enable_boost_support(); | |
391 | if (ret) | |
392 | goto out_free_cpufreq_table; | |
21c36d35 | 393 | cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs; |
34e5a527 TP |
394 | } |
395 | ||
396 | policy->cpuinfo.transition_latency = transition_latency; | |
397 | ||
f9739d27 LS |
398 | of_node_put(np); |
399 | ||
95ceafd4 SG |
400 | return 0; |
401 | ||
9a004428 | 402 | out_free_cpufreq_table: |
5d4879cd | 403 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
045ee45c LS |
404 | out_free_priv: |
405 | kfree(priv); | |
2f0f609f | 406 | out_free_opp: |
8f8d37b2 | 407 | dev_pm_opp_of_cpumask_remove_table(policy->cpus); |
050794aa VK |
408 | if (name) |
409 | dev_pm_opp_put_regulator(cpu_dev); | |
2e02d872 | 410 | out_node_put: |
d2f31f1d VK |
411 | of_node_put(np); |
412 | out_put_reg_clk: | |
ed4b053c | 413 | clk_put(cpu_clk); |
e3beb0ac LS |
414 | if (!IS_ERR(cpu_reg)) |
415 | regulator_put(cpu_reg); | |
d2f31f1d VK |
416 | |
417 | return ret; | |
418 | } | |
419 | ||
bbcf0719 | 420 | static int cpufreq_exit(struct cpufreq_policy *policy) |
d2f31f1d VK |
421 | { |
422 | struct private_data *priv = policy->driver_data; | |
423 | ||
17ad13ba | 424 | cpufreq_cooling_unregister(priv->cdev); |
d2f31f1d | 425 | dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table); |
8f8d37b2 | 426 | dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); |
050794aa VK |
427 | if (priv->reg_name) |
428 | dev_pm_opp_put_regulator(priv->cpu_dev); | |
429 | ||
d2f31f1d VK |
430 | clk_put(policy->clk); |
431 | if (!IS_ERR(priv->cpu_reg)) | |
432 | regulator_put(priv->cpu_reg); | |
433 | kfree(priv); | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
9a004428 VK |
438 | static void cpufreq_ready(struct cpufreq_policy *policy) |
439 | { | |
440 | struct private_data *priv = policy->driver_data; | |
441 | struct device_node *np = of_node_get(priv->cpu_dev->of_node); | |
442 | ||
443 | if (WARN_ON(!np)) | |
444 | return; | |
445 | ||
446 | /* | |
447 | * For now, just loading the cooling device; | |
448 | * thermal DT code takes care of matching them. | |
449 | */ | |
450 | if (of_find_property(np, "#cooling-cells", NULL)) { | |
f8fa8ae0 PA |
451 | u32 power_coefficient = 0; |
452 | ||
453 | of_property_read_u32(np, "dynamic-power-coefficient", | |
454 | &power_coefficient); | |
455 | ||
456 | priv->cdev = of_cpufreq_power_cooling_register(np, | |
457 | policy->related_cpus, power_coefficient, NULL); | |
9a004428 VK |
458 | if (IS_ERR(priv->cdev)) { |
459 | dev_err(priv->cpu_dev, | |
460 | "running cpufreq without cooling device: %ld\n", | |
461 | PTR_ERR(priv->cdev)); | |
462 | ||
463 | priv->cdev = NULL; | |
464 | } | |
465 | } | |
466 | ||
467 | of_node_put(np); | |
468 | } | |
469 | ||
bbcf0719 | 470 | static struct cpufreq_driver dt_cpufreq_driver = { |
d2f31f1d VK |
471 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
472 | .verify = cpufreq_generic_frequency_table_verify, | |
bbcf0719 | 473 | .target_index = set_target, |
d2f31f1d | 474 | .get = cpufreq_generic_get, |
bbcf0719 VK |
475 | .init = cpufreq_init, |
476 | .exit = cpufreq_exit, | |
9a004428 | 477 | .ready = cpufreq_ready, |
bbcf0719 | 478 | .name = "cpufreq-dt", |
21c36d35 | 479 | .attr = cpufreq_dt_attr, |
953ba9ff | 480 | .suspend = cpufreq_generic_suspend, |
d2f31f1d VK |
481 | }; |
482 | ||
bbcf0719 | 483 | static int dt_cpufreq_probe(struct platform_device *pdev) |
d2f31f1d VK |
484 | { |
485 | struct device *cpu_dev; | |
486 | struct regulator *cpu_reg; | |
487 | struct clk *cpu_clk; | |
488 | int ret; | |
489 | ||
490 | /* | |
491 | * All per-cluster (CPUs sharing clock/voltages) initialization is done | |
492 | * from ->init(). In probe(), we just need to make sure that clk and | |
493 | * regulators are available. Else defer probe and retry. | |
494 | * | |
495 | * FIXME: Is checking this only for CPU0 sufficient ? | |
496 | */ | |
95b61058 | 497 | ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk); |
d2f31f1d VK |
498 | if (ret) |
499 | return ret; | |
500 | ||
501 | clk_put(cpu_clk); | |
502 | if (!IS_ERR(cpu_reg)) | |
503 | regulator_put(cpu_reg); | |
504 | ||
34e5a527 TP |
505 | dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev); |
506 | ||
bbcf0719 | 507 | ret = cpufreq_register_driver(&dt_cpufreq_driver); |
d2f31f1d VK |
508 | if (ret) |
509 | dev_err(cpu_dev, "failed register driver: %d\n", ret); | |
510 | ||
95ceafd4 SG |
511 | return ret; |
512 | } | |
5553f9e2 | 513 | |
bbcf0719 | 514 | static int dt_cpufreq_remove(struct platform_device *pdev) |
5553f9e2 | 515 | { |
bbcf0719 | 516 | cpufreq_unregister_driver(&dt_cpufreq_driver); |
5553f9e2 SG |
517 | return 0; |
518 | } | |
519 | ||
bbcf0719 | 520 | static struct platform_driver dt_cpufreq_platdrv = { |
5553f9e2 | 521 | .driver = { |
bbcf0719 | 522 | .name = "cpufreq-dt", |
5553f9e2 | 523 | }, |
bbcf0719 VK |
524 | .probe = dt_cpufreq_probe, |
525 | .remove = dt_cpufreq_remove, | |
5553f9e2 | 526 | }; |
bbcf0719 | 527 | module_platform_driver(dt_cpufreq_platdrv); |
95ceafd4 | 528 | |
07949bf9 | 529 | MODULE_ALIAS("platform:cpufreq-dt"); |
748c8766 | 530 | MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>"); |
95ceafd4 | 531 | MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); |
bbcf0719 | 532 | MODULE_DESCRIPTION("Generic cpufreq driver"); |
95ceafd4 | 533 | MODULE_LICENSE("GPL"); |