cpufreq: dt: OPP layers handles clock-latency for V1 bindings as well
[linux-2.6-block.git] / drivers / cpufreq / cpufreq-dt.c
CommitLineData
95ceafd4
SG
1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
748c8766
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4 * Copyright (C) 2014 Linaro.
5 * Viresh Kumar <viresh.kumar@linaro.org>
6 *
bbcf0719 7 * The OPP code in function set_target() is reused from
95ceafd4
SG
8 * drivers/cpufreq/omap-cpufreq.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/clk.h>
e1825b25 18#include <linux/cpu.h>
77cff592 19#include <linux/cpu_cooling.h>
95ceafd4 20#include <linux/cpufreq.h>
34e5a527 21#include <linux/cpufreq-dt.h>
77cff592 22#include <linux/cpumask.h>
95ceafd4
SG
23#include <linux/err.h>
24#include <linux/module.h>
25#include <linux/of.h>
e4db1c74 26#include <linux/pm_opp.h>
5553f9e2 27#include <linux/platform_device.h>
95ceafd4
SG
28#include <linux/regulator/consumer.h>
29#include <linux/slab.h>
77cff592 30#include <linux/thermal.h>
95ceafd4 31
d2f31f1d
VK
32struct private_data {
33 struct device *cpu_dev;
34 struct regulator *cpu_reg;
35 struct thermal_cooling_device *cdev;
36 unsigned int voltage_tolerance; /* in percentage */
37};
95ceafd4 38
21c36d35
BZ
39static struct freq_attr *cpufreq_dt_attr[] = {
40 &cpufreq_freq_attr_scaling_available_freqs,
41 NULL, /* Extra space for boost-attr if required */
42 NULL,
43};
44
bbcf0719 45static int set_target(struct cpufreq_policy *policy, unsigned int index)
95ceafd4 46{
47d43ba7 47 struct dev_pm_opp *opp;
d2f31f1d
VK
48 struct cpufreq_frequency_table *freq_table = policy->freq_table;
49 struct clk *cpu_clk = policy->clk;
50 struct private_data *priv = policy->driver_data;
51 struct device *cpu_dev = priv->cpu_dev;
52 struct regulator *cpu_reg = priv->cpu_reg;
929ca89c
AH
53 unsigned long volt = 0, tol = 0;
54 int volt_old = 0;
d4019f0a 55 unsigned int old_freq, new_freq;
0ca68436 56 long freq_Hz, freq_exact;
95ceafd4
SG
57 int ret;
58
95ceafd4 59 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
2209b0c9 60 if (freq_Hz <= 0)
95ceafd4 61 freq_Hz = freq_table[index].frequency * 1000;
95ceafd4 62
d4019f0a
VK
63 freq_exact = freq_Hz;
64 new_freq = freq_Hz / 1000;
65 old_freq = clk_get_rate(cpu_clk) / 1000;
95ceafd4 66
4a511de9 67 if (!IS_ERR(cpu_reg)) {
0a1e879d
SW
68 unsigned long opp_freq;
69
78e8eb8f 70 rcu_read_lock();
5d4879cd 71 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
95ceafd4 72 if (IS_ERR(opp)) {
78e8eb8f 73 rcu_read_unlock();
fbd48ca5
VK
74 dev_err(cpu_dev, "failed to find OPP for %ld\n",
75 freq_Hz);
d4019f0a 76 return PTR_ERR(opp);
95ceafd4 77 }
5d4879cd 78 volt = dev_pm_opp_get_voltage(opp);
0a1e879d 79 opp_freq = dev_pm_opp_get_freq(opp);
78e8eb8f 80 rcu_read_unlock();
d2f31f1d 81 tol = volt * priv->voltage_tolerance / 100;
95ceafd4 82 volt_old = regulator_get_voltage(cpu_reg);
0a1e879d
SW
83 dev_dbg(cpu_dev, "Found OPP: %ld kHz, %ld uV\n",
84 opp_freq / 1000, volt);
95ceafd4
SG
85 }
86
929ca89c 87 dev_dbg(cpu_dev, "%u MHz, %d mV --> %u MHz, %ld mV\n",
8197bb1b 88 old_freq / 1000, (volt_old > 0) ? volt_old / 1000 : -1,
fbd48ca5 89 new_freq / 1000, volt ? volt / 1000 : -1);
95ceafd4
SG
90
91 /* scaling up? scale voltage before frequency */
d4019f0a 92 if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
95ceafd4
SG
93 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
94 if (ret) {
fbd48ca5
VK
95 dev_err(cpu_dev, "failed to scale voltage up: %d\n",
96 ret);
d4019f0a 97 return ret;
95ceafd4
SG
98 }
99 }
100
0ca68436 101 ret = clk_set_rate(cpu_clk, freq_exact);
95ceafd4 102 if (ret) {
fbd48ca5 103 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
8197bb1b 104 if (!IS_ERR(cpu_reg) && volt_old > 0)
95ceafd4 105 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
d4019f0a 106 return ret;
95ceafd4
SG
107 }
108
109 /* scaling down? scale voltage after frequency */
d4019f0a 110 if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
95ceafd4
SG
111 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
112 if (ret) {
fbd48ca5
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113 dev_err(cpu_dev, "failed to scale voltage down: %d\n",
114 ret);
d4019f0a 115 clk_set_rate(cpu_clk, old_freq * 1000);
95ceafd4
SG
116 }
117 }
118
fd143b4d 119 return ret;
95ceafd4
SG
120}
121
95b61058 122static int allocate_resources(int cpu, struct device **cdev,
d2f31f1d 123 struct regulator **creg, struct clk **cclk)
95ceafd4 124{
d2f31f1d
VK
125 struct device *cpu_dev;
126 struct regulator *cpu_reg;
127 struct clk *cpu_clk;
128 int ret = 0;
2d2c5e0e 129 char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg;
95ceafd4 130
95b61058 131 cpu_dev = get_cpu_device(cpu);
e1825b25 132 if (!cpu_dev) {
95b61058 133 pr_err("failed to get cpu%d device\n", cpu);
e1825b25
SK
134 return -ENODEV;
135 }
6754f556 136
2d2c5e0e 137 /* Try "cpu0" for older DTs */
95b61058
VK
138 if (!cpu)
139 reg = reg_cpu0;
140 else
141 reg = reg_cpu;
2d2c5e0e
VK
142
143try_again:
144 cpu_reg = regulator_get_optional(cpu_dev, reg);
b331bc20
AB
145 ret = PTR_ERR_OR_ZERO(cpu_reg);
146 if (ret) {
fc31d6f5 147 /*
95b61058 148 * If cpu's regulator supply node is present, but regulator is
fc31d6f5
NM
149 * not yet registered, we should try defering probe.
150 */
b331bc20 151 if (ret == -EPROBE_DEFER) {
95b61058
VK
152 dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n",
153 cpu);
b331bc20 154 return ret;
fc31d6f5 155 }
2d2c5e0e
VK
156
157 /* Try with "cpu-supply" */
158 if (reg == reg_cpu0) {
159 reg = reg_cpu;
160 goto try_again;
161 }
162
b331bc20 163 dev_dbg(cpu_dev, "no regulator for cpu%d: %d\n", cpu, ret);
fc31d6f5
NM
164 }
165
e3beb0ac 166 cpu_clk = clk_get(cpu_dev, NULL);
b331bc20
AB
167 ret = PTR_ERR_OR_ZERO(cpu_clk);
168 if (ret) {
d2f31f1d
VK
169 /* put regulator */
170 if (!IS_ERR(cpu_reg))
171 regulator_put(cpu_reg);
172
48a8624b
VK
173 /*
174 * If cpu's clk node is present, but clock is not yet
175 * registered, we should try defering probe.
176 */
177 if (ret == -EPROBE_DEFER)
95b61058 178 dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu);
48a8624b 179 else
71796210
AK
180 dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", cpu,
181 ret);
d2f31f1d
VK
182 } else {
183 *cdev = cpu_dev;
184 *creg = cpu_reg;
185 *cclk = cpu_clk;
186 }
187
188 return ret;
189}
190
bbcf0719 191static int cpufreq_init(struct cpufreq_policy *policy)
d2f31f1d
VK
192{
193 struct cpufreq_frequency_table *freq_table;
d2f31f1d
VK
194 struct device_node *np;
195 struct private_data *priv;
196 struct device *cpu_dev;
197 struct regulator *cpu_reg;
198 struct clk *cpu_clk;
953ba9ff 199 struct dev_pm_opp *suspend_opp;
045ee45c 200 unsigned long min_uV = ~0, max_uV = 0;
d2f31f1d 201 unsigned int transition_latency;
457e99e6 202 bool opp_v1 = false;
d2f31f1d
VK
203 int ret;
204
95b61058 205 ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk);
d2f31f1d 206 if (ret) {
edd52b1c 207 pr_err("%s: Failed to allocate resources: %d\n", __func__, ret);
d2f31f1d
VK
208 return ret;
209 }
48a8624b 210
d2f31f1d
VK
211 np = of_node_get(cpu_dev->of_node);
212 if (!np) {
213 dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
214 ret = -ENOENT;
215 goto out_put_reg_clk;
95ceafd4
SG
216 }
217
2e02d872 218 /* Get OPP-sharing information from "operating-points-v2" bindings */
8f8d37b2 219 ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, policy->cpus);
2e02d872
VK
220 if (ret) {
221 /*
222 * operating-points-v2 not supported, fallback to old method of
223 * finding shared-OPPs for backward compatibility.
224 */
225 if (ret == -ENOENT)
457e99e6 226 opp_v1 = true;
2e02d872
VK
227 else
228 goto out_node_put;
229 }
230
231 /*
232 * Initialize OPP tables for all policy->cpus. They will be shared by
233 * all CPUs which have marked their CPUs shared with OPP bindings.
234 *
235 * For platforms not using operating-points-v2 bindings, we do this
236 * before updating policy->cpus. Otherwise, we will end up creating
237 * duplicate OPPs for policy->cpus.
238 *
239 * OPPs might be populated at runtime, don't check for error here
240 */
8f8d37b2 241 dev_pm_opp_of_cpumask_add_table(policy->cpus);
2e02d872 242
7d5d0c8b
VK
243 /*
244 * But we need OPP table to function so if it is not there let's
245 * give platform code chance to provide it for us.
246 */
247 ret = dev_pm_opp_get_opp_count(cpu_dev);
248 if (ret <= 0) {
896d6a4c 249 dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n");
7d5d0c8b
VK
250 ret = -EPROBE_DEFER;
251 goto out_free_opp;
252 }
253
457e99e6 254 if (opp_v1) {
2e02d872
VK
255 struct cpufreq_dt_platform_data *pd = cpufreq_get_driver_data();
256
257 if (!pd || !pd->independent_clocks)
258 cpumask_setall(policy->cpus);
259
260 /*
261 * OPP tables are initialized only for policy->cpu, do it for
262 * others as well.
263 */
8f8d37b2 264 ret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
8bc86284
VK
265 if (ret)
266 dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n",
267 __func__, ret);
2e02d872 268 }
95ceafd4 269
d2f31f1d
VK
270 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
271 if (!priv) {
272 ret = -ENOMEM;
2f0f609f 273 goto out_free_opp;
95ceafd4
SG
274 }
275
d2f31f1d 276 of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
95ceafd4 277
391d9aef 278 transition_latency = dev_pm_opp_get_max_clock_latency(cpu_dev);
2e02d872 279 if (!transition_latency)
95ceafd4
SG
280 transition_latency = CPUFREQ_ETERNAL;
281
43c638e3 282 if (!IS_ERR(cpu_reg)) {
045ee45c 283 unsigned long opp_freq = 0;
95ceafd4
SG
284
285 /*
045ee45c
LS
286 * Disable any OPPs where the connected regulator isn't able to
287 * provide the specified voltage and record minimum and maximum
288 * voltage levels.
95ceafd4 289 */
045ee45c
LS
290 while (1) {
291 struct dev_pm_opp *opp;
292 unsigned long opp_uV, tol_uV;
293
294 rcu_read_lock();
295 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq);
296 if (IS_ERR(opp)) {
297 rcu_read_unlock();
298 break;
299 }
300 opp_uV = dev_pm_opp_get_voltage(opp);
301 rcu_read_unlock();
302
303 tol_uV = opp_uV * priv->voltage_tolerance / 100;
a2022001
VK
304 if (regulator_is_supported_voltage(cpu_reg,
305 opp_uV - tol_uV,
045ee45c
LS
306 opp_uV + tol_uV)) {
307 if (opp_uV < min_uV)
308 min_uV = opp_uV;
309 if (opp_uV > max_uV)
310 max_uV = opp_uV;
311 } else {
312 dev_pm_opp_disable(cpu_dev, opp_freq);
313 }
314
315 opp_freq++;
316 }
317
95ceafd4
SG
318 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
319 if (ret > 0)
320 transition_latency += ret * 1000;
321 }
322
045ee45c
LS
323 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
324 if (ret) {
896d6a4c 325 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
045ee45c
LS
326 goto out_free_priv;
327 }
328
d2f31f1d
VK
329 priv->cpu_dev = cpu_dev;
330 priv->cpu_reg = cpu_reg;
331 policy->driver_data = priv;
332
333 policy->clk = cpu_clk;
953ba9ff
BZ
334
335 rcu_read_lock();
336 suspend_opp = dev_pm_opp_get_suspend_opp(cpu_dev);
337 if (suspend_opp)
338 policy->suspend_freq = dev_pm_opp_get_freq(suspend_opp) / 1000;
339 rcu_read_unlock();
340
34e5a527
TP
341 ret = cpufreq_table_validate_and_show(policy, freq_table);
342 if (ret) {
343 dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
344 ret);
9a004428 345 goto out_free_cpufreq_table;
d15fa862
VK
346 }
347
348 /* Support turbo/boost mode */
349 if (policy_has_boost_freq(policy)) {
350 /* This gets disabled by core on driver unregister */
351 ret = cpufreq_enable_boost_support();
352 if (ret)
353 goto out_free_cpufreq_table;
21c36d35 354 cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;
34e5a527
TP
355 }
356
357 policy->cpuinfo.transition_latency = transition_latency;
358
f9739d27
LS
359 of_node_put(np);
360
95ceafd4
SG
361 return 0;
362
9a004428 363out_free_cpufreq_table:
5d4879cd 364 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
045ee45c
LS
365out_free_priv:
366 kfree(priv);
2f0f609f 367out_free_opp:
8f8d37b2 368 dev_pm_opp_of_cpumask_remove_table(policy->cpus);
2e02d872 369out_node_put:
d2f31f1d
VK
370 of_node_put(np);
371out_put_reg_clk:
ed4b053c 372 clk_put(cpu_clk);
e3beb0ac
LS
373 if (!IS_ERR(cpu_reg))
374 regulator_put(cpu_reg);
d2f31f1d
VK
375
376 return ret;
377}
378
bbcf0719 379static int cpufreq_exit(struct cpufreq_policy *policy)
d2f31f1d
VK
380{
381 struct private_data *priv = policy->driver_data;
382
17ad13ba 383 cpufreq_cooling_unregister(priv->cdev);
d2f31f1d 384 dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
8f8d37b2 385 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
d2f31f1d
VK
386 clk_put(policy->clk);
387 if (!IS_ERR(priv->cpu_reg))
388 regulator_put(priv->cpu_reg);
389 kfree(priv);
390
391 return 0;
392}
393
9a004428
VK
394static void cpufreq_ready(struct cpufreq_policy *policy)
395{
396 struct private_data *priv = policy->driver_data;
397 struct device_node *np = of_node_get(priv->cpu_dev->of_node);
398
399 if (WARN_ON(!np))
400 return;
401
402 /*
403 * For now, just loading the cooling device;
404 * thermal DT code takes care of matching them.
405 */
406 if (of_find_property(np, "#cooling-cells", NULL)) {
f8fa8ae0
PA
407 u32 power_coefficient = 0;
408
409 of_property_read_u32(np, "dynamic-power-coefficient",
410 &power_coefficient);
411
412 priv->cdev = of_cpufreq_power_cooling_register(np,
413 policy->related_cpus, power_coefficient, NULL);
9a004428
VK
414 if (IS_ERR(priv->cdev)) {
415 dev_err(priv->cpu_dev,
416 "running cpufreq without cooling device: %ld\n",
417 PTR_ERR(priv->cdev));
418
419 priv->cdev = NULL;
420 }
421 }
422
423 of_node_put(np);
424}
425
bbcf0719 426static struct cpufreq_driver dt_cpufreq_driver = {
d2f31f1d
VK
427 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
428 .verify = cpufreq_generic_frequency_table_verify,
bbcf0719 429 .target_index = set_target,
d2f31f1d 430 .get = cpufreq_generic_get,
bbcf0719
VK
431 .init = cpufreq_init,
432 .exit = cpufreq_exit,
9a004428 433 .ready = cpufreq_ready,
bbcf0719 434 .name = "cpufreq-dt",
21c36d35 435 .attr = cpufreq_dt_attr,
953ba9ff 436 .suspend = cpufreq_generic_suspend,
d2f31f1d
VK
437};
438
bbcf0719 439static int dt_cpufreq_probe(struct platform_device *pdev)
d2f31f1d
VK
440{
441 struct device *cpu_dev;
442 struct regulator *cpu_reg;
443 struct clk *cpu_clk;
444 int ret;
445
446 /*
447 * All per-cluster (CPUs sharing clock/voltages) initialization is done
448 * from ->init(). In probe(), we just need to make sure that clk and
449 * regulators are available. Else defer probe and retry.
450 *
451 * FIXME: Is checking this only for CPU0 sufficient ?
452 */
95b61058 453 ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk);
d2f31f1d
VK
454 if (ret)
455 return ret;
456
457 clk_put(cpu_clk);
458 if (!IS_ERR(cpu_reg))
459 regulator_put(cpu_reg);
460
34e5a527
TP
461 dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev);
462
bbcf0719 463 ret = cpufreq_register_driver(&dt_cpufreq_driver);
d2f31f1d
VK
464 if (ret)
465 dev_err(cpu_dev, "failed register driver: %d\n", ret);
466
95ceafd4
SG
467 return ret;
468}
5553f9e2 469
bbcf0719 470static int dt_cpufreq_remove(struct platform_device *pdev)
5553f9e2 471{
bbcf0719 472 cpufreq_unregister_driver(&dt_cpufreq_driver);
5553f9e2
SG
473 return 0;
474}
475
bbcf0719 476static struct platform_driver dt_cpufreq_platdrv = {
5553f9e2 477 .driver = {
bbcf0719 478 .name = "cpufreq-dt",
5553f9e2 479 },
bbcf0719
VK
480 .probe = dt_cpufreq_probe,
481 .remove = dt_cpufreq_remove,
5553f9e2 482};
bbcf0719 483module_platform_driver(dt_cpufreq_platdrv);
95ceafd4 484
07949bf9 485MODULE_ALIAS("platform:cpufreq-dt");
748c8766 486MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
95ceafd4 487MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
bbcf0719 488MODULE_DESCRIPTION("Generic cpufreq driver");
95ceafd4 489MODULE_LICENSE("GPL");