cpufreq: cpu0: don't validate clock on clk_put()
[linux-2.6-block.git] / drivers / cpufreq / cpufreq-cpu0.c
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1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
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4 * Copyright (C) 2014 Linaro.
5 * Viresh Kumar <viresh.kumar@linaro.org>
6 *
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7 * The OPP code in function cpu0_set_target() is reused from
8 * drivers/cpufreq/omap-cpufreq.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/clk.h>
e1825b25 18#include <linux/cpu.h>
77cff592 19#include <linux/cpu_cooling.h>
95ceafd4 20#include <linux/cpufreq.h>
77cff592 21#include <linux/cpumask.h>
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22#include <linux/err.h>
23#include <linux/module.h>
24#include <linux/of.h>
e4db1c74 25#include <linux/pm_opp.h>
5553f9e2 26#include <linux/platform_device.h>
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27#include <linux/regulator/consumer.h>
28#include <linux/slab.h>
77cff592 29#include <linux/thermal.h>
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30
31static unsigned int transition_latency;
32static unsigned int voltage_tolerance; /* in percentage */
33
34static struct device *cpu_dev;
35static struct clk *cpu_clk;
36static struct regulator *cpu_reg;
37static struct cpufreq_frequency_table *freq_table;
77cff592 38static struct thermal_cooling_device *cdev;
95ceafd4 39
9c0ebcf7 40static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
95ceafd4 41{
47d43ba7 42 struct dev_pm_opp *opp;
5df60559 43 unsigned long volt = 0, volt_old = 0, tol = 0;
d4019f0a 44 unsigned int old_freq, new_freq;
0ca68436 45 long freq_Hz, freq_exact;
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46 int ret;
47
95ceafd4 48 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
2209b0c9 49 if (freq_Hz <= 0)
95ceafd4 50 freq_Hz = freq_table[index].frequency * 1000;
95ceafd4 51
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52 freq_exact = freq_Hz;
53 new_freq = freq_Hz / 1000;
54 old_freq = clk_get_rate(cpu_clk) / 1000;
95ceafd4 55
4a511de9 56 if (!IS_ERR(cpu_reg)) {
78e8eb8f 57 rcu_read_lock();
5d4879cd 58 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
95ceafd4 59 if (IS_ERR(opp)) {
78e8eb8f 60 rcu_read_unlock();
95ceafd4 61 pr_err("failed to find OPP for %ld\n", freq_Hz);
d4019f0a 62 return PTR_ERR(opp);
95ceafd4 63 }
5d4879cd 64 volt = dev_pm_opp_get_voltage(opp);
78e8eb8f 65 rcu_read_unlock();
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66 tol = volt * voltage_tolerance / 100;
67 volt_old = regulator_get_voltage(cpu_reg);
68 }
69
70 pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
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71 old_freq / 1000, volt_old ? volt_old / 1000 : -1,
72 new_freq / 1000, volt ? volt / 1000 : -1);
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73
74 /* scaling up? scale voltage before frequency */
d4019f0a 75 if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
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76 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
77 if (ret) {
78 pr_err("failed to scale voltage up: %d\n", ret);
d4019f0a 79 return ret;
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80 }
81 }
82
0ca68436 83 ret = clk_set_rate(cpu_clk, freq_exact);
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84 if (ret) {
85 pr_err("failed to set clock rate: %d\n", ret);
4a511de9 86 if (!IS_ERR(cpu_reg))
95ceafd4 87 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
d4019f0a 88 return ret;
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89 }
90
91 /* scaling down? scale voltage after frequency */
d4019f0a 92 if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
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93 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
94 if (ret) {
95 pr_err("failed to scale voltage down: %d\n", ret);
d4019f0a 96 clk_set_rate(cpu_clk, old_freq * 1000);
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97 }
98 }
99
fd143b4d 100 return ret;
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101}
102
103static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
104{
652ed95d 105 policy->clk = cpu_clk;
78b3d109 106 return cpufreq_generic_init(policy, freq_table, transition_latency);
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107}
108
95ceafd4 109static struct cpufreq_driver cpu0_cpufreq_driver = {
93575b75 110 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
f793d79f 111 .verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7 112 .target_index = cpu0_set_target,
652ed95d 113 .get = cpufreq_generic_get,
95ceafd4 114 .init = cpu0_cpufreq_init,
95ceafd4 115 .name = "generic_cpu0",
f793d79f 116 .attr = cpufreq_generic_attr,
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117};
118
5553f9e2 119static int cpu0_cpufreq_probe(struct platform_device *pdev)
95ceafd4 120{
f837a9b5 121 struct device_node *np;
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122 int ret;
123
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124 cpu_dev = get_cpu_device(0);
125 if (!cpu_dev) {
126 pr_err("failed to get cpu0 device\n");
127 return -ENODEV;
128 }
6754f556 129
f837a9b5 130 np = of_node_get(cpu_dev->of_node);
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131 if (!np) {
132 pr_err("failed to find cpu0 node\n");
f837a9b5 133 return -ENOENT;
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134 }
135
e3beb0ac 136 cpu_reg = regulator_get_optional(cpu_dev, "cpu0");
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137 if (IS_ERR(cpu_reg)) {
138 /*
139 * If cpu0 regulator supply node is present, but regulator is
140 * not yet registered, we should try defering probe.
141 */
142 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
713a3fa6 143 dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n");
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144 ret = -EPROBE_DEFER;
145 goto out_put_node;
146 }
147 pr_warn("failed to get cpu0 regulator: %ld\n",
148 PTR_ERR(cpu_reg));
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149 }
150
e3beb0ac 151 cpu_clk = clk_get(cpu_dev, NULL);
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152 if (IS_ERR(cpu_clk)) {
153 ret = PTR_ERR(cpu_clk);
154 pr_err("failed to get cpu0 clock: %d\n", ret);
e3beb0ac 155 goto out_put_reg;
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156 }
157
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158 /* OPPs might be populated at runtime, don't check for error here */
159 of_init_opp_table(cpu_dev);
95ceafd4 160
5d4879cd 161 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
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162 if (ret) {
163 pr_err("failed to init cpufreq table: %d\n", ret);
e3beb0ac 164 goto out_put_clk;
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165 }
166
167 of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
168
169 if (of_property_read_u32(np, "clock-latency", &transition_latency))
170 transition_latency = CPUFREQ_ETERNAL;
171
43c638e3 172 if (!IS_ERR(cpu_reg)) {
47d43ba7 173 struct dev_pm_opp *opp;
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174 unsigned long min_uV, max_uV;
175 int i;
176
177 /*
178 * OPP is maintained in order of increasing frequency, and
179 * freq_table initialised from OPP is therefore sorted in the
180 * same order.
181 */
182 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
183 ;
78e8eb8f 184 rcu_read_lock();
5d4879cd 185 opp = dev_pm_opp_find_freq_exact(cpu_dev,
95ceafd4 186 freq_table[0].frequency * 1000, true);
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187 min_uV = dev_pm_opp_get_voltage(opp);
188 opp = dev_pm_opp_find_freq_exact(cpu_dev,
95ceafd4 189 freq_table[i-1].frequency * 1000, true);
5d4879cd 190 max_uV = dev_pm_opp_get_voltage(opp);
78e8eb8f 191 rcu_read_unlock();
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192 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
193 if (ret > 0)
194 transition_latency += ret * 1000;
195 }
196
197 ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
198 if (ret) {
199 pr_err("failed register driver: %d\n", ret);
200 goto out_free_table;
201 }
202
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203 /*
204 * For now, just loading the cooling device;
205 * thermal DT code takes care of matching them.
206 */
207 if (of_find_property(np, "#cooling-cells", NULL)) {
208 cdev = of_cpufreq_cooling_register(np, cpu_present_mask);
209 if (IS_ERR(cdev))
210 pr_err("running cpufreq without cooling device: %ld\n",
211 PTR_ERR(cdev));
212 }
213
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214 of_node_put(np);
215 return 0;
216
217out_free_table:
5d4879cd 218 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
e3beb0ac 219out_put_clk:
ed4b053c 220 clk_put(cpu_clk);
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221out_put_reg:
222 if (!IS_ERR(cpu_reg))
223 regulator_put(cpu_reg);
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224out_put_node:
225 of_node_put(np);
226 return ret;
227}
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228
229static int cpu0_cpufreq_remove(struct platform_device *pdev)
230{
77cff592 231 cpufreq_cooling_unregister(cdev);
5553f9e2 232 cpufreq_unregister_driver(&cpu0_cpufreq_driver);
5d4879cd 233 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
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234
235 return 0;
236}
237
238static struct platform_driver cpu0_cpufreq_platdrv = {
239 .driver = {
240 .name = "cpufreq-cpu0",
241 .owner = THIS_MODULE,
242 },
243 .probe = cpu0_cpufreq_probe,
244 .remove = cpu0_cpufreq_remove,
245};
246module_platform_driver(cpu0_cpufreq_platdrv);
95ceafd4 247
748c8766 248MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
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249MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
250MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
251MODULE_LICENSE("GPL");