cpufreq: Add support for per-policy driver data
[linux-2.6-block.git] / drivers / cpufreq / cpufreq-cpu0.c
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95ceafd4
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1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * The OPP code in function cpu0_set_target() is reused from
5 * drivers/cpufreq/omap-cpufreq.c
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/clk.h>
e1825b25 15#include <linux/cpu.h>
77cff592 16#include <linux/cpu_cooling.h>
95ceafd4 17#include <linux/cpufreq.h>
77cff592 18#include <linux/cpumask.h>
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19#include <linux/err.h>
20#include <linux/module.h>
21#include <linux/of.h>
e4db1c74 22#include <linux/pm_opp.h>
5553f9e2 23#include <linux/platform_device.h>
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24#include <linux/regulator/consumer.h>
25#include <linux/slab.h>
77cff592 26#include <linux/thermal.h>
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27
28static unsigned int transition_latency;
29static unsigned int voltage_tolerance; /* in percentage */
30
31static struct device *cpu_dev;
32static struct clk *cpu_clk;
33static struct regulator *cpu_reg;
34static struct cpufreq_frequency_table *freq_table;
77cff592 35static struct thermal_cooling_device *cdev;
95ceafd4 36
9c0ebcf7 37static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
95ceafd4 38{
47d43ba7 39 struct dev_pm_opp *opp;
5df60559 40 unsigned long volt = 0, volt_old = 0, tol = 0;
d4019f0a 41 unsigned int old_freq, new_freq;
0ca68436 42 long freq_Hz, freq_exact;
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43 int ret;
44
95ceafd4 45 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
2209b0c9 46 if (freq_Hz <= 0)
95ceafd4 47 freq_Hz = freq_table[index].frequency * 1000;
95ceafd4 48
d4019f0a
VK
49 freq_exact = freq_Hz;
50 new_freq = freq_Hz / 1000;
51 old_freq = clk_get_rate(cpu_clk) / 1000;
95ceafd4 52
4a511de9 53 if (!IS_ERR(cpu_reg)) {
78e8eb8f 54 rcu_read_lock();
5d4879cd 55 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
95ceafd4 56 if (IS_ERR(opp)) {
78e8eb8f 57 rcu_read_unlock();
95ceafd4 58 pr_err("failed to find OPP for %ld\n", freq_Hz);
d4019f0a 59 return PTR_ERR(opp);
95ceafd4 60 }
5d4879cd 61 volt = dev_pm_opp_get_voltage(opp);
78e8eb8f 62 rcu_read_unlock();
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63 tol = volt * voltage_tolerance / 100;
64 volt_old = regulator_get_voltage(cpu_reg);
65 }
66
67 pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
d4019f0a
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68 old_freq / 1000, volt_old ? volt_old / 1000 : -1,
69 new_freq / 1000, volt ? volt / 1000 : -1);
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70
71 /* scaling up? scale voltage before frequency */
d4019f0a 72 if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
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73 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
74 if (ret) {
75 pr_err("failed to scale voltage up: %d\n", ret);
d4019f0a 76 return ret;
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77 }
78 }
79
0ca68436 80 ret = clk_set_rate(cpu_clk, freq_exact);
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81 if (ret) {
82 pr_err("failed to set clock rate: %d\n", ret);
4a511de9 83 if (!IS_ERR(cpu_reg))
95ceafd4 84 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
d4019f0a 85 return ret;
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86 }
87
88 /* scaling down? scale voltage after frequency */
d4019f0a 89 if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
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90 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
91 if (ret) {
92 pr_err("failed to scale voltage down: %d\n", ret);
d4019f0a 93 clk_set_rate(cpu_clk, old_freq * 1000);
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94 }
95 }
96
fd143b4d 97 return ret;
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98}
99
100static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
101{
652ed95d 102 policy->clk = cpu_clk;
78b3d109 103 return cpufreq_generic_init(policy, freq_table, transition_latency);
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104}
105
95ceafd4 106static struct cpufreq_driver cpu0_cpufreq_driver = {
93575b75 107 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
f793d79f 108 .verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7 109 .target_index = cpu0_set_target,
652ed95d 110 .get = cpufreq_generic_get,
95ceafd4 111 .init = cpu0_cpufreq_init,
95ceafd4 112 .name = "generic_cpu0",
f793d79f 113 .attr = cpufreq_generic_attr,
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114};
115
5553f9e2 116static int cpu0_cpufreq_probe(struct platform_device *pdev)
95ceafd4 117{
f837a9b5 118 struct device_node *np;
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119 int ret;
120
e1825b25
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121 cpu_dev = get_cpu_device(0);
122 if (!cpu_dev) {
123 pr_err("failed to get cpu0 device\n");
124 return -ENODEV;
125 }
6754f556 126
f837a9b5 127 np = of_node_get(cpu_dev->of_node);
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128 if (!np) {
129 pr_err("failed to find cpu0 node\n");
f837a9b5 130 return -ENOENT;
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131 }
132
e3beb0ac 133 cpu_reg = regulator_get_optional(cpu_dev, "cpu0");
fc31d6f5
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134 if (IS_ERR(cpu_reg)) {
135 /*
136 * If cpu0 regulator supply node is present, but regulator is
137 * not yet registered, we should try defering probe.
138 */
139 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
713a3fa6 140 dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n");
fc31d6f5
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141 ret = -EPROBE_DEFER;
142 goto out_put_node;
143 }
144 pr_warn("failed to get cpu0 regulator: %ld\n",
145 PTR_ERR(cpu_reg));
fc31d6f5
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146 }
147
e3beb0ac 148 cpu_clk = clk_get(cpu_dev, NULL);
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149 if (IS_ERR(cpu_clk)) {
150 ret = PTR_ERR(cpu_clk);
151 pr_err("failed to get cpu0 clock: %d\n", ret);
e3beb0ac 152 goto out_put_reg;
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153 }
154
1bf8cc3d
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155 /* OPPs might be populated at runtime, don't check for error here */
156 of_init_opp_table(cpu_dev);
95ceafd4 157
5d4879cd 158 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
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159 if (ret) {
160 pr_err("failed to init cpufreq table: %d\n", ret);
e3beb0ac 161 goto out_put_clk;
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162 }
163
164 of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
165
166 if (of_property_read_u32(np, "clock-latency", &transition_latency))
167 transition_latency = CPUFREQ_ETERNAL;
168
43c638e3 169 if (!IS_ERR(cpu_reg)) {
47d43ba7 170 struct dev_pm_opp *opp;
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171 unsigned long min_uV, max_uV;
172 int i;
173
174 /*
175 * OPP is maintained in order of increasing frequency, and
176 * freq_table initialised from OPP is therefore sorted in the
177 * same order.
178 */
179 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
180 ;
78e8eb8f 181 rcu_read_lock();
5d4879cd 182 opp = dev_pm_opp_find_freq_exact(cpu_dev,
95ceafd4 183 freq_table[0].frequency * 1000, true);
5d4879cd
NM
184 min_uV = dev_pm_opp_get_voltage(opp);
185 opp = dev_pm_opp_find_freq_exact(cpu_dev,
95ceafd4 186 freq_table[i-1].frequency * 1000, true);
5d4879cd 187 max_uV = dev_pm_opp_get_voltage(opp);
78e8eb8f 188 rcu_read_unlock();
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189 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
190 if (ret > 0)
191 transition_latency += ret * 1000;
192 }
193
194 ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
195 if (ret) {
196 pr_err("failed register driver: %d\n", ret);
197 goto out_free_table;
198 }
199
77cff592
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200 /*
201 * For now, just loading the cooling device;
202 * thermal DT code takes care of matching them.
203 */
204 if (of_find_property(np, "#cooling-cells", NULL)) {
205 cdev = of_cpufreq_cooling_register(np, cpu_present_mask);
206 if (IS_ERR(cdev))
207 pr_err("running cpufreq without cooling device: %ld\n",
208 PTR_ERR(cdev));
209 }
210
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211 of_node_put(np);
212 return 0;
213
214out_free_table:
5d4879cd 215 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
e3beb0ac
LS
216out_put_clk:
217 if (!IS_ERR(cpu_clk))
218 clk_put(cpu_clk);
219out_put_reg:
220 if (!IS_ERR(cpu_reg))
221 regulator_put(cpu_reg);
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222out_put_node:
223 of_node_put(np);
224 return ret;
225}
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226
227static int cpu0_cpufreq_remove(struct platform_device *pdev)
228{
77cff592 229 cpufreq_cooling_unregister(cdev);
5553f9e2 230 cpufreq_unregister_driver(&cpu0_cpufreq_driver);
5d4879cd 231 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
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232
233 return 0;
234}
235
236static struct platform_driver cpu0_cpufreq_platdrv = {
237 .driver = {
238 .name = "cpufreq-cpu0",
239 .owner = THIS_MODULE,
240 },
241 .probe = cpu0_cpufreq_probe,
242 .remove = cpu0_cpufreq_remove,
243};
244module_platform_driver(cpu0_cpufreq_platdrv);
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245
246MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
247MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
248MODULE_LICENSE("GPL");