Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3a58df35 | 2 | * acpi-cpufreq.c - ACPI Processor P-States Driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 7 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
8 | * |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
24 | * | |
25 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
26 | */ | |
27 | ||
1da177e4 LT |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
30 | #include <linux/init.h> | |
fe27cb35 VP |
31 | #include <linux/smp.h> |
32 | #include <linux/sched.h> | |
1da177e4 | 33 | #include <linux/cpufreq.h> |
d395bf12 | 34 | #include <linux/compiler.h> |
8adcc0c6 | 35 | #include <linux/dmi.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
1da177e4 LT |
37 | |
38 | #include <linux/acpi.h> | |
3a58df35 DJ |
39 | #include <linux/io.h> |
40 | #include <linux/delay.h> | |
41 | #include <linux/uaccess.h> | |
42 | ||
1da177e4 LT |
43 | #include <acpi/processor.h> |
44 | ||
dde9f7ba | 45 | #include <asm/msr.h> |
fe27cb35 VP |
46 | #include <asm/processor.h> |
47 | #include <asm/cpufeature.h> | |
fe27cb35 | 48 | |
1da177e4 LT |
49 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); |
50 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
51 | MODULE_LICENSE("GPL"); | |
52 | ||
acd31624 AP |
53 | #define PFX "acpi-cpufreq: " |
54 | ||
dde9f7ba VP |
55 | enum { |
56 | UNDEFINED_CAPABLE = 0, | |
57 | SYSTEM_INTEL_MSR_CAPABLE, | |
3dc9a633 | 58 | SYSTEM_AMD_MSR_CAPABLE, |
dde9f7ba VP |
59 | SYSTEM_IO_CAPABLE, |
60 | }; | |
61 | ||
62 | #define INTEL_MSR_RANGE (0xffff) | |
3dc9a633 | 63 | #define AMD_MSR_RANGE (0x7) |
dde9f7ba | 64 | |
615b7300 AP |
65 | #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) |
66 | ||
fe27cb35 | 67 | struct acpi_cpufreq_data { |
64be7eed VP |
68 | struct cpufreq_frequency_table *freq_table; |
69 | unsigned int resume; | |
70 | unsigned int cpu_feature; | |
8cfcfd39 | 71 | unsigned int acpi_perf_cpu; |
f4fd3797 | 72 | cpumask_var_t freqdomain_cpus; |
ed757a2c RW |
73 | void (*cpu_freq_write)(struct acpi_pct_register *reg, u32 val); |
74 | u32 (*cpu_freq_read)(struct acpi_pct_register *reg); | |
1da177e4 LT |
75 | }; |
76 | ||
50109292 | 77 | /* acpi_perf_data is a pointer to percpu data. */ |
3f6c4df7 | 78 | static struct acpi_processor_performance __percpu *acpi_perf_data; |
1da177e4 | 79 | |
3427616b RW |
80 | static inline struct acpi_processor_performance *to_perf_data(struct acpi_cpufreq_data *data) |
81 | { | |
82 | return per_cpu_ptr(acpi_perf_data, data->acpi_perf_cpu); | |
83 | } | |
84 | ||
1da177e4 LT |
85 | static struct cpufreq_driver acpi_cpufreq_driver; |
86 | ||
d395bf12 | 87 | static unsigned int acpi_pstate_strict; |
615b7300 AP |
88 | static struct msr __percpu *msrs; |
89 | ||
90 | static bool boost_state(unsigned int cpu) | |
91 | { | |
92 | u32 lo, hi; | |
93 | u64 msr; | |
94 | ||
95 | switch (boot_cpu_data.x86_vendor) { | |
96 | case X86_VENDOR_INTEL: | |
97 | rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); | |
98 | msr = lo | ((u64)hi << 32); | |
99 | return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
100 | case X86_VENDOR_AMD: | |
101 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
102 | msr = lo | ((u64)hi << 32); | |
103 | return !(msr & MSR_K7_HWCR_CPB_DIS); | |
104 | } | |
105 | return false; | |
106 | } | |
107 | ||
108 | static void boost_set_msrs(bool enable, const struct cpumask *cpumask) | |
109 | { | |
110 | u32 cpu; | |
111 | u32 msr_addr; | |
112 | u64 msr_mask; | |
113 | ||
114 | switch (boot_cpu_data.x86_vendor) { | |
115 | case X86_VENDOR_INTEL: | |
116 | msr_addr = MSR_IA32_MISC_ENABLE; | |
117 | msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; | |
118 | break; | |
119 | case X86_VENDOR_AMD: | |
120 | msr_addr = MSR_K7_HWCR; | |
121 | msr_mask = MSR_K7_HWCR_CPB_DIS; | |
122 | break; | |
123 | default: | |
124 | return; | |
125 | } | |
126 | ||
127 | rdmsr_on_cpus(cpumask, msr_addr, msrs); | |
128 | ||
129 | for_each_cpu(cpu, cpumask) { | |
130 | struct msr *reg = per_cpu_ptr(msrs, cpu); | |
131 | if (enable) | |
132 | reg->q &= ~msr_mask; | |
133 | else | |
134 | reg->q |= msr_mask; | |
135 | } | |
136 | ||
137 | wrmsr_on_cpus(cpumask, msr_addr, msrs); | |
138 | } | |
139 | ||
17135782 | 140 | static int set_boost(int val) |
615b7300 | 141 | { |
615b7300 | 142 | get_online_cpus(); |
615b7300 | 143 | boost_set_msrs(val, cpu_online_mask); |
615b7300 | 144 | put_online_cpus(); |
615b7300 AP |
145 | pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); |
146 | ||
cfc9c8ed | 147 | return 0; |
615b7300 AP |
148 | } |
149 | ||
f4fd3797 LT |
150 | static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) |
151 | { | |
eb0b3e78 | 152 | struct acpi_cpufreq_data *data = policy->driver_data; |
f4fd3797 | 153 | |
e2530367 SP |
154 | if (unlikely(!data)) |
155 | return -ENODEV; | |
156 | ||
f4fd3797 LT |
157 | return cpufreq_show_cpus(data->freqdomain_cpus, buf); |
158 | } | |
159 | ||
160 | cpufreq_freq_attr_ro(freqdomain_cpus); | |
161 | ||
11269ff5 | 162 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
17135782 RW |
163 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, |
164 | size_t count) | |
cfc9c8ed LM |
165 | { |
166 | int ret; | |
17135782 | 167 | unsigned int val = 0; |
cfc9c8ed | 168 | |
7a6c79f2 | 169 | if (!acpi_cpufreq_driver.set_boost) |
cfc9c8ed LM |
170 | return -EINVAL; |
171 | ||
17135782 RW |
172 | ret = kstrtouint(buf, 10, &val); |
173 | if (ret || val > 1) | |
cfc9c8ed LM |
174 | return -EINVAL; |
175 | ||
17135782 | 176 | set_boost(val); |
cfc9c8ed LM |
177 | |
178 | return count; | |
179 | } | |
180 | ||
11269ff5 AP |
181 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) |
182 | { | |
cfc9c8ed | 183 | return sprintf(buf, "%u\n", acpi_cpufreq_driver.boost_enabled); |
11269ff5 AP |
184 | } |
185 | ||
59027d35 | 186 | cpufreq_freq_attr_rw(cpb); |
11269ff5 AP |
187 | #endif |
188 | ||
dde9f7ba VP |
189 | static int check_est_cpu(unsigned int cpuid) |
190 | { | |
92cb7612 | 191 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); |
dde9f7ba | 192 | |
0de51088 | 193 | return cpu_has(cpu, X86_FEATURE_EST); |
dde9f7ba VP |
194 | } |
195 | ||
3dc9a633 MG |
196 | static int check_amd_hwpstate_cpu(unsigned int cpuid) |
197 | { | |
198 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); | |
199 | ||
200 | return cpu_has(cpu, X86_FEATURE_HW_PSTATE); | |
201 | } | |
202 | ||
dde9f7ba | 203 | static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) |
fe27cb35 | 204 | { |
64be7eed VP |
205 | struct acpi_processor_performance *perf; |
206 | int i; | |
fe27cb35 | 207 | |
3427616b | 208 | perf = to_perf_data(data); |
fe27cb35 | 209 | |
3a58df35 | 210 | for (i = 0; i < perf->state_count; i++) { |
fe27cb35 VP |
211 | if (value == perf->states[i].status) |
212 | return data->freq_table[i].frequency; | |
213 | } | |
214 | return 0; | |
215 | } | |
216 | ||
dde9f7ba VP |
217 | static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) |
218 | { | |
041526f9 | 219 | struct cpufreq_frequency_table *pos; |
a6f6e6e6 | 220 | struct acpi_processor_performance *perf; |
dde9f7ba | 221 | |
3dc9a633 MG |
222 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
223 | msr &= AMD_MSR_RANGE; | |
224 | else | |
225 | msr &= INTEL_MSR_RANGE; | |
226 | ||
3427616b | 227 | perf = to_perf_data(data); |
a6f6e6e6 | 228 | |
041526f9 SK |
229 | cpufreq_for_each_entry(pos, data->freq_table) |
230 | if (msr == perf->states[pos->driver_data].status) | |
231 | return pos->frequency; | |
dde9f7ba VP |
232 | return data->freq_table[0].frequency; |
233 | } | |
234 | ||
dde9f7ba VP |
235 | static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) |
236 | { | |
237 | switch (data->cpu_feature) { | |
64be7eed | 238 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 239 | case SYSTEM_AMD_MSR_CAPABLE: |
dde9f7ba | 240 | return extract_msr(val, data); |
64be7eed | 241 | case SYSTEM_IO_CAPABLE: |
dde9f7ba | 242 | return extract_io(val, data); |
64be7eed | 243 | default: |
dde9f7ba VP |
244 | return 0; |
245 | } | |
246 | } | |
247 | ||
ed757a2c RW |
248 | u32 cpu_freq_read_intel(struct acpi_pct_register *not_used) |
249 | { | |
250 | u32 val, dummy; | |
dde9f7ba | 251 | |
ed757a2c RW |
252 | rdmsr(MSR_IA32_PERF_CTL, val, dummy); |
253 | return val; | |
254 | } | |
255 | ||
256 | void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val) | |
257 | { | |
258 | u32 lo, hi; | |
259 | ||
260 | rdmsr(MSR_IA32_PERF_CTL, lo, hi); | |
261 | lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE); | |
262 | wrmsr(MSR_IA32_PERF_CTL, lo, hi); | |
263 | } | |
264 | ||
265 | u32 cpu_freq_read_amd(struct acpi_pct_register *not_used) | |
266 | { | |
267 | u32 val, dummy; | |
268 | ||
269 | rdmsr(MSR_AMD_PERF_CTL, val, dummy); | |
270 | return val; | |
271 | } | |
272 | ||
273 | void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val) | |
274 | { | |
275 | wrmsr(MSR_AMD_PERF_CTL, val, 0); | |
276 | } | |
277 | ||
278 | u32 cpu_freq_read_io(struct acpi_pct_register *reg) | |
279 | { | |
280 | u32 val; | |
281 | ||
282 | acpi_os_read_port(reg->address, &val, reg->bit_width); | |
283 | return val; | |
284 | } | |
285 | ||
286 | void cpu_freq_write_io(struct acpi_pct_register *reg, u32 val) | |
287 | { | |
288 | acpi_os_write_port(reg->address, val, reg->bit_width); | |
289 | } | |
fe27cb35 VP |
290 | |
291 | struct drv_cmd { | |
ed757a2c | 292 | struct acpi_pct_register *reg; |
fe27cb35 | 293 | u32 val; |
ed757a2c RW |
294 | union { |
295 | void (*write)(struct acpi_pct_register *reg, u32 val); | |
296 | u32 (*read)(struct acpi_pct_register *reg); | |
297 | } func; | |
fe27cb35 VP |
298 | }; |
299 | ||
01599fca AM |
300 | /* Called via smp_call_function_single(), on the target CPU */ |
301 | static void do_drv_read(void *_cmd) | |
1da177e4 | 302 | { |
72859081 | 303 | struct drv_cmd *cmd = _cmd; |
dde9f7ba | 304 | |
ed757a2c | 305 | cmd->val = cmd->func.read(cmd->reg); |
fe27cb35 | 306 | } |
1da177e4 | 307 | |
ed757a2c | 308 | static u32 drv_read(struct acpi_cpufreq_data *data, const struct cpumask *mask) |
fe27cb35 | 309 | { |
ed757a2c RW |
310 | struct acpi_processor_performance *perf = to_perf_data(data); |
311 | struct drv_cmd cmd = { | |
312 | .reg = &perf->control_register, | |
313 | .func.read = data->cpu_freq_read, | |
314 | }; | |
315 | int err; | |
dde9f7ba | 316 | |
ed757a2c RW |
317 | err = smp_call_function_any(mask, do_drv_read, &cmd, 1); |
318 | WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ | |
319 | return cmd.val; | |
fe27cb35 | 320 | } |
1da177e4 | 321 | |
ed757a2c RW |
322 | /* Called via smp_call_function_many(), on the target CPUs */ |
323 | static void do_drv_write(void *_cmd) | |
fe27cb35 | 324 | { |
ed757a2c | 325 | struct drv_cmd *cmd = _cmd; |
fe27cb35 | 326 | |
ed757a2c | 327 | cmd->func.write(cmd->reg, cmd->val); |
fe27cb35 VP |
328 | } |
329 | ||
ed757a2c RW |
330 | static void drv_write(struct acpi_cpufreq_data *data, |
331 | const struct cpumask *mask, u32 val) | |
fe27cb35 | 332 | { |
ed757a2c RW |
333 | struct acpi_processor_performance *perf = to_perf_data(data); |
334 | struct drv_cmd cmd = { | |
335 | .reg = &perf->control_register, | |
336 | .val = val, | |
337 | .func.write = data->cpu_freq_write, | |
338 | }; | |
ea34f43a LT |
339 | int this_cpu; |
340 | ||
341 | this_cpu = get_cpu(); | |
ed757a2c RW |
342 | if (cpumask_test_cpu(this_cpu, mask)) |
343 | do_drv_write(&cmd); | |
344 | ||
345 | smp_call_function_many(mask, do_drv_write, &cmd, 1); | |
ea34f43a | 346 | put_cpu(); |
fe27cb35 | 347 | } |
1da177e4 | 348 | |
ed757a2c | 349 | static u32 get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data) |
fe27cb35 | 350 | { |
ed757a2c | 351 | u32 val; |
1da177e4 | 352 | |
4d8bb537 | 353 | if (unlikely(cpumask_empty(mask))) |
fe27cb35 | 354 | return 0; |
1da177e4 | 355 | |
ed757a2c | 356 | val = drv_read(data, mask); |
1da177e4 | 357 | |
ed757a2c | 358 | pr_debug("get_cur_val = %u\n", val); |
fe27cb35 | 359 | |
ed757a2c | 360 | return val; |
fe27cb35 | 361 | } |
1da177e4 | 362 | |
fe27cb35 VP |
363 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
364 | { | |
eb0b3e78 PX |
365 | struct acpi_cpufreq_data *data; |
366 | struct cpufreq_policy *policy; | |
64be7eed | 367 | unsigned int freq; |
e56a727b | 368 | unsigned int cached_freq; |
fe27cb35 | 369 | |
2d06d8c4 | 370 | pr_debug("get_cur_freq_on_cpu (%d)\n", cpu); |
fe27cb35 | 371 | |
1f0bd44e | 372 | policy = cpufreq_cpu_get_raw(cpu); |
eb0b3e78 PX |
373 | if (unlikely(!policy)) |
374 | return 0; | |
375 | ||
376 | data = policy->driver_data; | |
3427616b | 377 | if (unlikely(!data || !data->freq_table)) |
fe27cb35 | 378 | return 0; |
1da177e4 | 379 | |
3427616b | 380 | cached_freq = data->freq_table[to_perf_data(data)->state].frequency; |
eb0b3e78 | 381 | freq = extract_freq(get_cur_val(cpumask_of(cpu), data), data); |
e56a727b VP |
382 | if (freq != cached_freq) { |
383 | /* | |
384 | * The dreaded BIOS frequency change behind our back. | |
385 | * Force set the frequency on next target call. | |
386 | */ | |
387 | data->resume = 1; | |
388 | } | |
389 | ||
2d06d8c4 | 390 | pr_debug("cur freq = %u\n", freq); |
1da177e4 | 391 | |
fe27cb35 | 392 | return freq; |
1da177e4 LT |
393 | } |
394 | ||
72859081 | 395 | static unsigned int check_freqs(const struct cpumask *mask, unsigned int freq, |
64be7eed | 396 | struct acpi_cpufreq_data *data) |
fe27cb35 | 397 | { |
64be7eed VP |
398 | unsigned int cur_freq; |
399 | unsigned int i; | |
1da177e4 | 400 | |
3a58df35 | 401 | for (i = 0; i < 100; i++) { |
eb0b3e78 | 402 | cur_freq = extract_freq(get_cur_val(mask, data), data); |
fe27cb35 VP |
403 | if (cur_freq == freq) |
404 | return 1; | |
405 | udelay(10); | |
406 | } | |
407 | return 0; | |
408 | } | |
409 | ||
410 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 411 | unsigned int index) |
1da177e4 | 412 | { |
eb0b3e78 | 413 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed | 414 | struct acpi_processor_performance *perf; |
ed757a2c | 415 | const struct cpumask *mask; |
8edc59d9 | 416 | unsigned int next_perf_state = 0; /* Index into perf table */ |
64be7eed | 417 | int result = 0; |
fe27cb35 | 418 | |
3427616b | 419 | if (unlikely(data == NULL || data->freq_table == NULL)) { |
fe27cb35 VP |
420 | return -ENODEV; |
421 | } | |
1da177e4 | 422 | |
3427616b | 423 | perf = to_perf_data(data); |
9c0ebcf7 | 424 | next_perf_state = data->freq_table[index].driver_data; |
7650b281 | 425 | if (perf->state == next_perf_state) { |
fe27cb35 | 426 | if (unlikely(data->resume)) { |
2d06d8c4 | 427 | pr_debug("Called after resume, resetting to P%d\n", |
64be7eed | 428 | next_perf_state); |
fe27cb35 VP |
429 | data->resume = 0; |
430 | } else { | |
2d06d8c4 | 431 | pr_debug("Already at target state (P%d)\n", |
64be7eed | 432 | next_perf_state); |
9a909a14 | 433 | return 0; |
fe27cb35 | 434 | } |
09b4d1ee VP |
435 | } |
436 | ||
ed757a2c RW |
437 | /* |
438 | * The core won't allow CPUs to go away until the governor has been | |
439 | * stopped, so we can rely on the stability of policy->cpus. | |
440 | */ | |
441 | mask = policy->shared_type == CPUFREQ_SHARED_TYPE_ANY ? | |
442 | cpumask_of(policy->cpu) : policy->cpus; | |
09b4d1ee | 443 | |
ed757a2c | 444 | drv_write(data, mask, perf->states[next_perf_state].control); |
09b4d1ee | 445 | |
fe27cb35 | 446 | if (acpi_pstate_strict) { |
ed757a2c | 447 | if (!check_freqs(mask, data->freq_table[index].frequency, |
d4019f0a | 448 | data)) { |
2d06d8c4 | 449 | pr_debug("acpi_cpufreq_target failed (%d)\n", |
64be7eed | 450 | policy->cpu); |
4d8bb537 | 451 | result = -EAGAIN; |
09b4d1ee VP |
452 | } |
453 | } | |
454 | ||
e15d8309 VK |
455 | if (!result) |
456 | perf->state = next_perf_state; | |
fe27cb35 VP |
457 | |
458 | return result; | |
1da177e4 LT |
459 | } |
460 | ||
1da177e4 | 461 | static unsigned long |
64be7eed | 462 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 463 | { |
3427616b | 464 | struct acpi_processor_performance *perf; |
09b4d1ee | 465 | |
3427616b | 466 | perf = to_perf_data(data); |
1da177e4 LT |
467 | if (cpu_khz) { |
468 | /* search the closest match to cpu_khz */ | |
469 | unsigned int i; | |
470 | unsigned long freq; | |
09b4d1ee | 471 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 472 | |
3a58df35 | 473 | for (i = 0; i < (perf->state_count-1); i++) { |
1da177e4 | 474 | freq = freqn; |
95dd7227 | 475 | freqn = perf->states[i+1].core_frequency * 1000; |
1da177e4 | 476 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 477 | perf->state = i; |
64be7eed | 478 | return freq; |
1da177e4 LT |
479 | } |
480 | } | |
95dd7227 | 481 | perf->state = perf->state_count-1; |
64be7eed | 482 | return freqn; |
09b4d1ee | 483 | } else { |
1da177e4 | 484 | /* assume CPU is at P0... */ |
09b4d1ee VP |
485 | perf->state = 0; |
486 | return perf->states[0].core_frequency * 1000; | |
487 | } | |
1da177e4 LT |
488 | } |
489 | ||
2fdf66b4 RR |
490 | static void free_acpi_perf_data(void) |
491 | { | |
492 | unsigned int i; | |
493 | ||
494 | /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ | |
495 | for_each_possible_cpu(i) | |
496 | free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) | |
497 | ->shared_cpu_map); | |
498 | free_percpu(acpi_perf_data); | |
499 | } | |
500 | ||
615b7300 AP |
501 | static int boost_notify(struct notifier_block *nb, unsigned long action, |
502 | void *hcpu) | |
503 | { | |
504 | unsigned cpu = (long)hcpu; | |
505 | const struct cpumask *cpumask; | |
506 | ||
507 | cpumask = get_cpu_mask(cpu); | |
508 | ||
509 | /* | |
510 | * Clear the boost-disable bit on the CPU_DOWN path so that | |
511 | * this cpu cannot block the remaining ones from boosting. On | |
512 | * the CPU_UP path we simply keep the boost-disable flag in | |
513 | * sync with the current global state. | |
514 | */ | |
515 | ||
516 | switch (action) { | |
517 | case CPU_UP_PREPARE: | |
518 | case CPU_UP_PREPARE_FROZEN: | |
cfc9c8ed | 519 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, cpumask); |
615b7300 AP |
520 | break; |
521 | ||
522 | case CPU_DOWN_PREPARE: | |
523 | case CPU_DOWN_PREPARE_FROZEN: | |
524 | boost_set_msrs(1, cpumask); | |
525 | break; | |
526 | ||
527 | default: | |
528 | break; | |
529 | } | |
530 | ||
531 | return NOTIFY_OK; | |
532 | } | |
533 | ||
534 | ||
535 | static struct notifier_block boost_nb = { | |
536 | .notifier_call = boost_notify, | |
537 | }; | |
538 | ||
09b4d1ee VP |
539 | /* |
540 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
541 | * | |
542 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
543 | * in order to determine correct frequency and voltage pairings. We can | |
544 | * do _PDC and _PSD and find out the processor dependency for the | |
545 | * actual init that will happen later... | |
546 | */ | |
50109292 | 547 | static int __init acpi_cpufreq_early_init(void) |
09b4d1ee | 548 | { |
2fdf66b4 | 549 | unsigned int i; |
2d06d8c4 | 550 | pr_debug("acpi_cpufreq_early_init\n"); |
09b4d1ee | 551 | |
50109292 FY |
552 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); |
553 | if (!acpi_perf_data) { | |
2d06d8c4 | 554 | pr_debug("Memory allocation error for acpi_perf_data.\n"); |
50109292 | 555 | return -ENOMEM; |
09b4d1ee | 556 | } |
2fdf66b4 | 557 | for_each_possible_cpu(i) { |
eaa95840 | 558 | if (!zalloc_cpumask_var_node( |
80855f73 MT |
559 | &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, |
560 | GFP_KERNEL, cpu_to_node(i))) { | |
2fdf66b4 RR |
561 | |
562 | /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ | |
563 | free_acpi_perf_data(); | |
564 | return -ENOMEM; | |
565 | } | |
566 | } | |
09b4d1ee VP |
567 | |
568 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
569 | acpi_processor_preregister_performance(acpi_perf_data); |
570 | return 0; | |
09b4d1ee VP |
571 | } |
572 | ||
95625b8f | 573 | #ifdef CONFIG_SMP |
8adcc0c6 VP |
574 | /* |
575 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
576 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
577 | * detected, this has a side effect of making CPU run at a different speed | |
578 | * than OS intended it to run at. Detect it and handle it cleanly. | |
579 | */ | |
580 | static int bios_with_sw_any_bug; | |
581 | ||
1855256c | 582 | static int sw_any_bug_found(const struct dmi_system_id *d) |
8adcc0c6 VP |
583 | { |
584 | bios_with_sw_any_bug = 1; | |
585 | return 0; | |
586 | } | |
587 | ||
1855256c | 588 | static const struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
589 | { |
590 | .callback = sw_any_bug_found, | |
591 | .ident = "Supermicro Server X6DLP", | |
592 | .matches = { | |
593 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
594 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
595 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
596 | }, | |
597 | }, | |
598 | { } | |
599 | }; | |
1a8e42fa PB |
600 | |
601 | static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) | |
602 | { | |
293afe44 JV |
603 | /* Intel Xeon Processor 7100 Series Specification Update |
604 | * http://www.intel.com/Assets/PDF/specupdate/314554.pdf | |
1a8e42fa PB |
605 | * AL30: A Machine Check Exception (MCE) Occurring during an |
606 | * Enhanced Intel SpeedStep Technology Ratio Change May Cause | |
293afe44 | 607 | * Both Processor Cores to Lock Up. */ |
1a8e42fa PB |
608 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
609 | if ((c->x86 == 15) && | |
610 | (c->x86_model == 6) && | |
293afe44 JV |
611 | (c->x86_mask == 8)) { |
612 | printk(KERN_INFO "acpi-cpufreq: Intel(R) " | |
613 | "Xeon(R) 7100 Errata AL30, processors may " | |
614 | "lock up on frequency changes: disabling " | |
615 | "acpi-cpufreq.\n"); | |
1a8e42fa | 616 | return -ENODEV; |
293afe44 | 617 | } |
1a8e42fa PB |
618 | } |
619 | return 0; | |
620 | } | |
95625b8f | 621 | #endif |
8adcc0c6 | 622 | |
64be7eed | 623 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 624 | { |
64be7eed VP |
625 | unsigned int i; |
626 | unsigned int valid_states = 0; | |
627 | unsigned int cpu = policy->cpu; | |
628 | struct acpi_cpufreq_data *data; | |
64be7eed | 629 | unsigned int result = 0; |
92cb7612 | 630 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
64be7eed | 631 | struct acpi_processor_performance *perf; |
293afe44 JV |
632 | #ifdef CONFIG_SMP |
633 | static int blacklisted; | |
634 | #endif | |
1da177e4 | 635 | |
2d06d8c4 | 636 | pr_debug("acpi_cpufreq_cpu_init\n"); |
1da177e4 | 637 | |
1a8e42fa | 638 | #ifdef CONFIG_SMP |
293afe44 JV |
639 | if (blacklisted) |
640 | return blacklisted; | |
641 | blacklisted = acpi_cpufreq_blacklist(c); | |
642 | if (blacklisted) | |
643 | return blacklisted; | |
1a8e42fa PB |
644 | #endif |
645 | ||
d5b73cd8 | 646 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
1da177e4 | 647 | if (!data) |
64be7eed | 648 | return -ENOMEM; |
1da177e4 | 649 | |
f4fd3797 LT |
650 | if (!zalloc_cpumask_var(&data->freqdomain_cpus, GFP_KERNEL)) { |
651 | result = -ENOMEM; | |
652 | goto err_free; | |
653 | } | |
654 | ||
3427616b | 655 | perf = per_cpu_ptr(acpi_perf_data, cpu); |
8cfcfd39 | 656 | data->acpi_perf_cpu = cpu; |
eb0b3e78 | 657 | policy->driver_data = data; |
1da177e4 | 658 | |
95dd7227 | 659 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) |
fe27cb35 | 660 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 661 | |
3427616b | 662 | result = acpi_processor_register_performance(perf, cpu); |
1da177e4 | 663 | if (result) |
f4fd3797 | 664 | goto err_free_mask; |
1da177e4 | 665 | |
09b4d1ee | 666 | policy->shared_type = perf->shared_type; |
95dd7227 | 667 | |
46f18e3a | 668 | /* |
95dd7227 | 669 | * Will let policy->cpus know about dependency only when software |
46f18e3a VP |
670 | * coordination is required. |
671 | */ | |
672 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 673 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
835481d9 | 674 | cpumask_copy(policy->cpus, perf->shared_cpu_map); |
8adcc0c6 | 675 | } |
f4fd3797 | 676 | cpumask_copy(data->freqdomain_cpus, perf->shared_cpu_map); |
8adcc0c6 VP |
677 | |
678 | #ifdef CONFIG_SMP | |
679 | dmi_check_system(sw_any_bug_dmi_table); | |
2624f90c | 680 | if (bios_with_sw_any_bug && !policy_is_shared(policy)) { |
8adcc0c6 | 681 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; |
3280c3c8 | 682 | cpumask_copy(policy->cpus, topology_core_cpumask(cpu)); |
8adcc0c6 | 683 | } |
acd31624 AP |
684 | |
685 | if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { | |
686 | cpumask_clear(policy->cpus); | |
687 | cpumask_set_cpu(cpu, policy->cpus); | |
3280c3c8 BG |
688 | cpumask_copy(data->freqdomain_cpus, |
689 | topology_sibling_cpumask(cpu)); | |
acd31624 AP |
690 | policy->shared_type = CPUFREQ_SHARED_TYPE_HW; |
691 | pr_info_once(PFX "overriding BIOS provided _PSD data\n"); | |
692 | } | |
8adcc0c6 | 693 | #endif |
09b4d1ee | 694 | |
1da177e4 | 695 | /* capability check */ |
09b4d1ee | 696 | if (perf->state_count <= 1) { |
2d06d8c4 | 697 | pr_debug("No P-States\n"); |
1da177e4 LT |
698 | result = -ENODEV; |
699 | goto err_unreg; | |
700 | } | |
09b4d1ee | 701 | |
fe27cb35 VP |
702 | if (perf->control_register.space_id != perf->status_register.space_id) { |
703 | result = -ENODEV; | |
704 | goto err_unreg; | |
705 | } | |
706 | ||
707 | switch (perf->control_register.space_id) { | |
64be7eed | 708 | case ACPI_ADR_SPACE_SYSTEM_IO: |
c40a4518 MG |
709 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
710 | boot_cpu_data.x86 == 0xf) { | |
711 | pr_debug("AMD K8 systems must use native drivers.\n"); | |
712 | result = -ENODEV; | |
713 | goto err_unreg; | |
714 | } | |
2d06d8c4 | 715 | pr_debug("SYSTEM IO addr space\n"); |
dde9f7ba | 716 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
ed757a2c RW |
717 | data->cpu_freq_read = cpu_freq_read_io; |
718 | data->cpu_freq_write = cpu_freq_write_io; | |
dde9f7ba | 719 | break; |
64be7eed | 720 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
2d06d8c4 | 721 | pr_debug("HARDWARE addr space\n"); |
3dc9a633 MG |
722 | if (check_est_cpu(cpu)) { |
723 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
ed757a2c RW |
724 | data->cpu_freq_read = cpu_freq_read_intel; |
725 | data->cpu_freq_write = cpu_freq_write_intel; | |
3dc9a633 | 726 | break; |
dde9f7ba | 727 | } |
3dc9a633 MG |
728 | if (check_amd_hwpstate_cpu(cpu)) { |
729 | data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; | |
ed757a2c RW |
730 | data->cpu_freq_read = cpu_freq_read_amd; |
731 | data->cpu_freq_write = cpu_freq_write_amd; | |
3dc9a633 MG |
732 | break; |
733 | } | |
734 | result = -ENODEV; | |
735 | goto err_unreg; | |
64be7eed | 736 | default: |
2d06d8c4 | 737 | pr_debug("Unknown addr space %d\n", |
64be7eed | 738 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
739 | result = -ENODEV; |
740 | goto err_unreg; | |
741 | } | |
742 | ||
71508a1f | 743 | data->freq_table = kzalloc(sizeof(*data->freq_table) * |
95dd7227 | 744 | (perf->state_count+1), GFP_KERNEL); |
1da177e4 LT |
745 | if (!data->freq_table) { |
746 | result = -ENOMEM; | |
747 | goto err_unreg; | |
748 | } | |
749 | ||
750 | /* detect transition latency */ | |
751 | policy->cpuinfo.transition_latency = 0; | |
3a58df35 | 752 | for (i = 0; i < perf->state_count; i++) { |
64be7eed VP |
753 | if ((perf->states[i].transition_latency * 1000) > |
754 | policy->cpuinfo.transition_latency) | |
755 | policy->cpuinfo.transition_latency = | |
756 | perf->states[i].transition_latency * 1000; | |
1da177e4 | 757 | } |
1da177e4 | 758 | |
a59d1637 PV |
759 | /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ |
760 | if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && | |
761 | policy->cpuinfo.transition_latency > 20 * 1000) { | |
a59d1637 | 762 | policy->cpuinfo.transition_latency = 20 * 1000; |
61c8c67e JP |
763 | printk_once(KERN_INFO |
764 | "P-state transition latency capped at 20 uS\n"); | |
a59d1637 PV |
765 | } |
766 | ||
1da177e4 | 767 | /* table init */ |
3a58df35 DJ |
768 | for (i = 0; i < perf->state_count; i++) { |
769 | if (i > 0 && perf->states[i].core_frequency >= | |
3cdf552b | 770 | data->freq_table[valid_states-1].frequency / 1000) |
fe27cb35 VP |
771 | continue; |
772 | ||
50701588 | 773 | data->freq_table[valid_states].driver_data = i; |
fe27cb35 | 774 | data->freq_table[valid_states].frequency = |
64be7eed | 775 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 776 | valid_states++; |
1da177e4 | 777 | } |
3d4a7ef3 | 778 | data->freq_table[valid_states].frequency = CPUFREQ_TABLE_END; |
8edc59d9 | 779 | perf->state = 0; |
1da177e4 | 780 | |
776b57be | 781 | result = cpufreq_table_validate_and_show(policy, data->freq_table); |
95dd7227 | 782 | if (result) |
1da177e4 | 783 | goto err_freqfree; |
1da177e4 | 784 | |
d876dfbb TR |
785 | if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq) |
786 | printk(KERN_WARNING FW_WARN "P-state 0 is not max freq\n"); | |
787 | ||
a507ac4b | 788 | switch (perf->control_register.space_id) { |
64be7eed | 789 | case ACPI_ADR_SPACE_SYSTEM_IO: |
1bab64d5 VK |
790 | /* |
791 | * The core will not set policy->cur, because | |
792 | * cpufreq_driver->get is NULL, so we need to set it here. | |
793 | * However, we have to guess it, because the current speed is | |
794 | * unknown and not detectable via IO ports. | |
795 | */ | |
dde9f7ba VP |
796 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); |
797 | break; | |
64be7eed | 798 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 799 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba | 800 | break; |
64be7eed | 801 | default: |
dde9f7ba VP |
802 | break; |
803 | } | |
804 | ||
1da177e4 LT |
805 | /* notify BIOS that we exist */ |
806 | acpi_processor_notify_smm(THIS_MODULE); | |
807 | ||
2d06d8c4 | 808 | pr_debug("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 809 | for (i = 0; i < perf->state_count; i++) |
2d06d8c4 | 810 | pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 811 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
812 | (u32) perf->states[i].core_frequency, |
813 | (u32) perf->states[i].power, | |
814 | (u32) perf->states[i].transition_latency); | |
1da177e4 | 815 | |
4b31e774 DB |
816 | /* |
817 | * the first call to ->target() should result in us actually | |
818 | * writing something to the appropriate registers. | |
819 | */ | |
820 | data->resume = 1; | |
64be7eed | 821 | |
fe27cb35 | 822 | return result; |
1da177e4 | 823 | |
95dd7227 | 824 | err_freqfree: |
1da177e4 | 825 | kfree(data->freq_table); |
95dd7227 | 826 | err_unreg: |
b2f8dc4c | 827 | acpi_processor_unregister_performance(cpu); |
f4fd3797 LT |
828 | err_free_mask: |
829 | free_cpumask_var(data->freqdomain_cpus); | |
95dd7227 | 830 | err_free: |
1da177e4 | 831 | kfree(data); |
eb0b3e78 | 832 | policy->driver_data = NULL; |
1da177e4 | 833 | |
64be7eed | 834 | return result; |
1da177e4 LT |
835 | } |
836 | ||
64be7eed | 837 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 838 | { |
eb0b3e78 | 839 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 840 | |
2d06d8c4 | 841 | pr_debug("acpi_cpufreq_cpu_exit\n"); |
1da177e4 LT |
842 | |
843 | if (data) { | |
eb0b3e78 | 844 | policy->driver_data = NULL; |
b2f8dc4c | 845 | acpi_processor_unregister_performance(data->acpi_perf_cpu); |
f4fd3797 | 846 | free_cpumask_var(data->freqdomain_cpus); |
dab5fff1 | 847 | kfree(data->freq_table); |
1da177e4 LT |
848 | kfree(data); |
849 | } | |
850 | ||
64be7eed | 851 | return 0; |
1da177e4 LT |
852 | } |
853 | ||
64be7eed | 854 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 855 | { |
eb0b3e78 | 856 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 857 | |
2d06d8c4 | 858 | pr_debug("acpi_cpufreq_resume\n"); |
1da177e4 LT |
859 | |
860 | data->resume = 1; | |
861 | ||
64be7eed | 862 | return 0; |
1da177e4 LT |
863 | } |
864 | ||
64be7eed | 865 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 | 866 | &cpufreq_freq_attr_scaling_available_freqs, |
f4fd3797 | 867 | &freqdomain_cpus, |
f56c50e3 RW |
868 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
869 | &cpb, | |
870 | #endif | |
1da177e4 LT |
871 | NULL, |
872 | }; | |
873 | ||
874 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
db9be219 | 875 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 876 | .target_index = acpi_cpufreq_target, |
e2f74f35 TR |
877 | .bios_limit = acpi_processor_get_bios_limit, |
878 | .init = acpi_cpufreq_cpu_init, | |
879 | .exit = acpi_cpufreq_cpu_exit, | |
880 | .resume = acpi_cpufreq_resume, | |
881 | .name = "acpi-cpufreq", | |
e2f74f35 | 882 | .attr = acpi_cpufreq_attr, |
1da177e4 LT |
883 | }; |
884 | ||
615b7300 AP |
885 | static void __init acpi_cpufreq_boost_init(void) |
886 | { | |
887 | if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { | |
888 | msrs = msrs_alloc(); | |
889 | ||
890 | if (!msrs) | |
891 | return; | |
892 | ||
7a6c79f2 | 893 | acpi_cpufreq_driver.set_boost = set_boost; |
cfc9c8ed | 894 | acpi_cpufreq_driver.boost_enabled = boost_state(0); |
0197fbd2 SB |
895 | |
896 | cpu_notifier_register_begin(); | |
615b7300 AP |
897 | |
898 | /* Force all MSRs to the same value */ | |
cfc9c8ed LM |
899 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, |
900 | cpu_online_mask); | |
615b7300 | 901 | |
0197fbd2 | 902 | __register_cpu_notifier(&boost_nb); |
615b7300 | 903 | |
0197fbd2 | 904 | cpu_notifier_register_done(); |
cfc9c8ed | 905 | } |
615b7300 AP |
906 | } |
907 | ||
eb8c68ef | 908 | static void acpi_cpufreq_boost_exit(void) |
615b7300 | 909 | { |
615b7300 AP |
910 | if (msrs) { |
911 | unregister_cpu_notifier(&boost_nb); | |
912 | ||
913 | msrs_free(msrs); | |
914 | msrs = NULL; | |
915 | } | |
916 | } | |
917 | ||
64be7eed | 918 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 919 | { |
50109292 FY |
920 | int ret; |
921 | ||
75c07581 RW |
922 | if (acpi_disabled) |
923 | return -ENODEV; | |
924 | ||
8a61e12e YL |
925 | /* don't keep reloading if cpufreq_driver exists */ |
926 | if (cpufreq_get_current_driver()) | |
75c07581 | 927 | return -EEXIST; |
ee297533 | 928 | |
2d06d8c4 | 929 | pr_debug("acpi_cpufreq_init\n"); |
1da177e4 | 930 | |
50109292 FY |
931 | ret = acpi_cpufreq_early_init(); |
932 | if (ret) | |
933 | return ret; | |
09b4d1ee | 934 | |
11269ff5 AP |
935 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
936 | /* this is a sysfs file with a strange name and an even stranger | |
937 | * semantic - per CPU instantiation, but system global effect. | |
938 | * Lets enable it only on AMD CPUs for compatibility reasons and | |
939 | * only if configured. This is considered legacy code, which | |
940 | * will probably be removed at some point in the future. | |
941 | */ | |
f56c50e3 RW |
942 | if (!check_amd_hwpstate_cpu(0)) { |
943 | struct freq_attr **attr; | |
11269ff5 | 944 | |
f56c50e3 | 945 | pr_debug("CPB unsupported, do not expose it\n"); |
11269ff5 | 946 | |
f56c50e3 RW |
947 | for (attr = acpi_cpufreq_attr; *attr; attr++) |
948 | if (*attr == &cpb) { | |
949 | *attr = NULL; | |
950 | break; | |
951 | } | |
11269ff5 AP |
952 | } |
953 | #endif | |
cfc9c8ed | 954 | acpi_cpufreq_boost_init(); |
11269ff5 | 955 | |
847aef6f | 956 | ret = cpufreq_register_driver(&acpi_cpufreq_driver); |
eb8c68ef | 957 | if (ret) { |
2fdf66b4 | 958 | free_acpi_perf_data(); |
eb8c68ef KRW |
959 | acpi_cpufreq_boost_exit(); |
960 | } | |
847aef6f | 961 | return ret; |
1da177e4 LT |
962 | } |
963 | ||
64be7eed | 964 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 965 | { |
2d06d8c4 | 966 | pr_debug("acpi_cpufreq_exit\n"); |
1da177e4 | 967 | |
615b7300 AP |
968 | acpi_cpufreq_boost_exit(); |
969 | ||
1da177e4 LT |
970 | cpufreq_unregister_driver(&acpi_cpufreq_driver); |
971 | ||
50f4ddd4 | 972 | free_acpi_perf_data(); |
1da177e4 LT |
973 | } |
974 | ||
d395bf12 | 975 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed | 976 | MODULE_PARM_DESC(acpi_pstate_strict, |
95dd7227 DJ |
977 | "value 0 or non-zero. non-zero -> strict ACPI checks are " |
978 | "performed during frequency changes."); | |
1da177e4 LT |
979 | |
980 | late_initcall(acpi_cpufreq_init); | |
981 | module_exit(acpi_cpufreq_exit); | |
982 | ||
efa17194 MG |
983 | static const struct x86_cpu_id acpi_cpufreq_ids[] = { |
984 | X86_FEATURE_MATCH(X86_FEATURE_ACPI), | |
985 | X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), | |
986 | {} | |
987 | }; | |
988 | MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); | |
989 | ||
c655affb RW |
990 | static const struct acpi_device_id processor_device_ids[] = { |
991 | {ACPI_PROCESSOR_OBJECT_HID, }, | |
992 | {ACPI_PROCESSOR_DEVICE_HID, }, | |
993 | {}, | |
994 | }; | |
995 | MODULE_DEVICE_TABLE(acpi, processor_device_ids); | |
996 | ||
1da177e4 | 997 | MODULE_ALIAS("acpi"); |