[linux-2.6-block.git] / drivers / clocksource / timer-atlas7.c

/*
 * System timer for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/sched_clock.h>

#define SIRFSOC_TIMER_32COUNTER_0_CTRL			0x0000
#define SIRFSOC_TIMER_32COUNTER_1_CTRL			0x0004
#define SIRFSOC_TIMER_MATCH_0				0x0018
#define SIRFSOC_TIMER_MATCH_1				0x001c
#define SIRFSOC_TIMER_COUNTER_0				0x0048
#define SIRFSOC_TIMER_COUNTER_1				0x004c
#define SIRFSOC_TIMER_INTR_STATUS			0x0060
#define SIRFSOC_TIMER_WATCHDOG_EN			0x0064
#define SIRFSOC_TIMER_64COUNTER_CTRL			0x0068
#define SIRFSOC_TIMER_64COUNTER_LO			0x006c
#define SIRFSOC_TIMER_64COUNTER_HI			0x0070
#define SIRFSOC_TIMER_64COUNTER_LOAD_LO			0x0074
#define SIRFSOC_TIMER_64COUNTER_LOAD_HI			0x0078
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO		0x007c
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI		0x0080

#define SIRFSOC_TIMER_REG_CNT 6

static unsigned long atlas7_timer_rate;

static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	SIRFSOC_TIMER_WATCHDOG_EN,
	SIRFSOC_TIMER_32COUNTER_0_CTRL,
	SIRFSOC_TIMER_32COUNTER_1_CTRL,
	SIRFSOC_TIMER_64COUNTER_CTRL,
	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
};

static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];

static void __iomem *sirfsoc_timer_base;

/* disable count and interrupt */
static inline void sirfsoc_timer_count_disable(int idx)
{
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}

/* enable count and interrupt */
static inline void sirfsoc_timer_count_enable(int idx)
{
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}

/* timer interrupt handler */
static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;
	int cpu = smp_processor_id();

	/* clear timer interrupt */
	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

	if (clockevent_state_oneshot(ce))
		sirfsoc_timer_count_disable(cpu);

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

/* read 64-bit timer counter */
static u64 sirfsoc_timer_read(struct clocksource *cs)
{
	u64 cycles;

	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
			BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);

	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
	cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);

	return cycles;
}

static int sirfsoc_timer_set_next_event(unsigned long delta,
	struct clock_event_device *ce)
{
	int cpu = smp_processor_id();

	/* disable timer first, then modify the related registers */
	sirfsoc_timer_count_disable(cpu);

	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
		4 * cpu);
	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
		4 * cpu);

	/* enable the tick */
	sirfsoc_timer_count_enable(cpu);

	return 0;
}

/* Oneshot is enabled in set_next_event */
static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
{
	sirfsoc_timer_count_disable(smp_processor_id());
	return 0;
}

static void sirfsoc_clocksource_suspend(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
		sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
}

static void sirfsoc_clocksource_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
		writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);

	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
}

static struct clock_event_device __percpu *sirfsoc_clockevent;

static struct clocksource sirfsoc_clocksource = {
	.name = "sirfsoc_clocksource",
	.rating = 200,
	.mask = CLOCKSOURCE_MASK(64),
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	.read = sirfsoc_timer_read,
	.suspend = sirfsoc_clocksource_suspend,
	.resume = sirfsoc_clocksource_resume,
};

static struct irqaction sirfsoc_timer_irq = {
	.name = "sirfsoc_timer0",
	.flags = IRQF_TIMER | IRQF_NOBALANCING,
	.handler = sirfsoc_timer_interrupt,
};

static struct irqaction sirfsoc_timer1_irq = {
	.name = "sirfsoc_timer1",
	.flags = IRQF_TIMER | IRQF_NOBALANCING,
	.handler = sirfsoc_timer_interrupt,
};

static int sirfsoc_local_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu);
	struct irqaction *action;

	if (cpu == 0)
		action = &sirfsoc_timer_irq;
	else
		action = &sirfsoc_timer1_irq;

	ce->irq = action->irq;
	ce->name = "local_timer";
	ce->features = CLOCK_EVT_FEAT_ONESHOT;
	ce->rating = 200;
	ce->set_state_shutdown = sirfsoc_timer_shutdown;
	ce->set_state_oneshot = sirfsoc_timer_shutdown;
	ce->tick_resume = sirfsoc_timer_shutdown;
	ce->set_next_event = sirfsoc_timer_set_next_event;
	clockevents_calc_mult_shift(ce, atlas7_timer_rate, 60);
	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
	ce->max_delta_ticks = (unsigned long)-2;
	ce->min_delta_ns = clockevent_delta2ns(2, ce);
	ce->min_delta_ticks = 2;
	ce->cpumask = cpumask_of(cpu);

	action->dev_id = ce;
	BUG_ON(setup_irq(ce->irq, action));
	irq_force_affinity(action->irq, cpumask_of(cpu));

	clockevents_register_device(ce);
	return 0;
}

static int sirfsoc_local_timer_dying_cpu(unsigned int cpu)
{
	sirfsoc_timer_count_disable(1);

	if (cpu == 0)
		remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	else
		remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
	return 0;
}

static int __init sirfsoc_clockevent_init(void)
{
	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
	BUG_ON(!sirfsoc_clockevent);

	/* Install and invoke hotplug callbacks */
	return cpuhp_setup_state(CPUHP_AP_MARCO_TIMER_STARTING,
				 "clockevents/marco:starting",
				 sirfsoc_local_timer_starting_cpu,
				 sirfsoc_local_timer_dying_cpu);
}

/* initialize the kernel jiffy timer source */
static int __init sirfsoc_atlas7_timer_init(struct device_node *np)
{
	struct clk *clk;

	clk = of_clk_get(np, 0);
	BUG_ON(IS_ERR(clk));

	BUG_ON(clk_prepare_enable(clk));

	atlas7_timer_rate = clk_get_rate(clk);

	/* timer dividers: 0, not divided */
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);

	/* Initialize timer counters to 0 */
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);

	/* Clear all interrupts */
	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, atlas7_timer_rate));

	return sirfsoc_clockevent_init();
}

static int __init sirfsoc_of_timer_init(struct device_node *np)
{
	sirfsoc_timer_base = of_iomap(np, 0);
	if (!sirfsoc_timer_base) {
		pr_err("unable to map timer cpu registers\n");
		return -ENXIO;
	}

	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
	if (!sirfsoc_timer_irq.irq) {
		pr_err("No irq passed for timer0 via DT\n");
		return -EINVAL;
	}

	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
	if (!sirfsoc_timer1_irq.irq) {
		pr_err("No irq passed for timer1 via DT\n");
		return -EINVAL;
	}

	return sirfsoc_atlas7_timer_init(np);
}
TIMER_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);
Commit	Line	Data
4898de3d BS	1	/*
	2	* System timer for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/kernel.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/clocksource.h>
05a65485	13	#include <linux/cpu.h>
4898de3d BS	14	#include <linux/bitops.h>
	15	#include <linux/irq.h>
	16	#include <linux/clk.h>
	17	#include <linux/slab.h>
	18	#include <linux/of.h>
	19	#include <linux/of_irq.h>
	20	#include <linux/of_address.h>
38ff87f7	21	#include <linux/sched_clock.h>
980c51ab	22
4898de3d BS	23	#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
	24	#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
	25	#define SIRFSOC_TIMER_MATCH_0 0x0018
	26	#define SIRFSOC_TIMER_MATCH_1 0x001c
	27	#define SIRFSOC_TIMER_COUNTER_0 0x0048
	28	#define SIRFSOC_TIMER_COUNTER_1 0x004c
	29	#define SIRFSOC_TIMER_INTR_STATUS 0x0060
	30	#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
	31	#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
	32	#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
	33	#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
	34	#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
	35	#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
	36	#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
	37	#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
	38
	39	#define SIRFSOC_TIMER_REG_CNT 6
	40
5833ac98	41	static unsigned long atlas7_timer_rate;
ef89af1f	42
4898de3d BS	43	static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	44	SIRFSOC_TIMER_WATCHDOG_EN,
	45	SIRFSOC_TIMER_32COUNTER_0_CTRL,
	46	SIRFSOC_TIMER_32COUNTER_1_CTRL,
	47	SIRFSOC_TIMER_64COUNTER_CTRL,
	48	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
	49	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
	50	};
	51
	52	static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
	53
	54	static void __iomem *sirfsoc_timer_base;
4898de3d BS	55
	56	/* disable count and interrupt */
	57	static inline void sirfsoc_timer_count_disable(int idx)
	58	{
	59	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
	60	sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
	61	}
	62
	63	/* enable count and interrupt */
	64	static inline void sirfsoc_timer_count_enable(int idx)
	65	{
28cf3567	66	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) \| 0x3,
4898de3d BS	67	sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
	68	}
	69
	70	/* timer interrupt handler */
	71	static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
	72	{
	73	struct clock_event_device *ce = dev_id;
	74	int cpu = smp_processor_id();
	75
	76	/* clear timer interrupt */
	77	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
	78
1e729d37	79	if (clockevent_state_oneshot(ce))
4898de3d BS	80	sirfsoc_timer_count_disable(cpu);
	81
	82	ce->event_handler(ce);
	83
	84	return IRQ_HANDLED;
	85	}
	86
	87	/* read 64-bit timer counter */
a5a1d1c2	88	static u64 sirfsoc_timer_read(struct clocksource *cs)
4898de3d BS	89	{
	90	u64 cycles;
	91
	92	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	93	BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	94
	95	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
	96	cycles = (cycles << 32) \| readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
	97
	98	return cycles;
	99	}
	100
	101	static int sirfsoc_timer_set_next_event(unsigned long delta,
	102	struct clock_event_device *ce)
	103	{
	104	int cpu = smp_processor_id();
	105
28cf3567 HL	106	/* disable timer first, then modify the related registers */
	107	sirfsoc_timer_count_disable(cpu);
	108
4898de3d BS	109	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
	110	4 * cpu);
	111	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
	112	4 * cpu);
	113
	114	/* enable the tick */
	115	sirfsoc_timer_count_enable(cpu);
	116
	117	return 0;
	118	}
	119
1e729d37 VK	120	/* Oneshot is enabled in set_next_event */
1e729d37 VK	121	static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
4898de3d	122	{
4898de3d	123	sirfsoc_timer_count_disable(smp_processor_id());
1e729d37	124	return 0;
4898de3d BS	125	}
	126
	127	static void sirfsoc_clocksource_suspend(struct clocksource *cs)
	128	{
	129	int i;
	130
	131	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
	132	sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
	133	}
	134
	135	static void sirfsoc_clocksource_resume(struct clocksource *cs)
	136	{
	137	int i;
	138
	139	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
	140	writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
	141
	142	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
	143	sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	144	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
	145	sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	146
	147	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	148	BIT(1) \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	149	}
	150
05a65485	151	static struct clock_event_device __percpu *sirfsoc_clockevent;
4898de3d BS	152
	153	static struct clocksource sirfsoc_clocksource = {
	154	.name = "sirfsoc_clocksource",
	155	.rating = 200,
	156	.mask = CLOCKSOURCE_MASK(64),
	157	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	158	.read = sirfsoc_timer_read,
	159	.suspend = sirfsoc_clocksource_suspend,
	160	.resume = sirfsoc_clocksource_resume,
	161	};
	162
	163	static struct irqaction sirfsoc_timer_irq = {
	164	.name = "sirfsoc_timer0",
	165	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	166	.handler = sirfsoc_timer_interrupt,
4898de3d BS	167	};
4898de3d BS	168
4898de3d BS	169	static struct irqaction sirfsoc_timer1_irq = {
	170	.name = "sirfsoc_timer1",
	171	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	172	.handler = sirfsoc_timer_interrupt,
	173	};
	174
eb0a9d8c	175	static int sirfsoc_local_timer_starting_cpu(unsigned int cpu)
4898de3d	176	{
eb0a9d8c	177	struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu);
05a65485 SB	178	struct irqaction *action;
	179
	180	if (cpu == 0)
	181	action = &sirfsoc_timer_irq;
	182	else
	183	action = &sirfsoc_timer1_irq;
4898de3d	184
05a65485	185	ce->irq = action->irq;
4898de3d	186	ce->name = "local_timer";
05a65485 SB	187	ce->features = CLOCK_EVT_FEAT_ONESHOT;
05a65485 SB	188	ce->rating = 200;
1e729d37 VK	189	ce->set_state_shutdown = sirfsoc_timer_shutdown;
	190	ce->set_state_oneshot = sirfsoc_timer_shutdown;
	191	ce->tick_resume = sirfsoc_timer_shutdown;
4898de3d	192	ce->set_next_event = sirfsoc_timer_set_next_event;
5833ac98	193	clockevents_calc_mult_shift(ce, atlas7_timer_rate, 60);
05a65485	194	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
547733c5	195	ce->max_delta_ticks = (unsigned long)-2;
05a65485	196	ce->min_delta_ns = clockevent_delta2ns(2, ce);
547733c5	197	ce->min_delta_ticks = 2;
05a65485	198	ce->cpumask = cpumask_of(cpu);
4898de3d	199
05a65485 SB	200	action->dev_id = ce;
05a65485 SB	201	BUG_ON(setup_irq(ce->irq, action));
f214be50	202	irq_force_affinity(action->irq, cpumask_of(cpu));
4898de3d BS	203
	204	clockevents_register_device(ce);
	205	return 0;
	206	}
	207
eb0a9d8c	208	static int sirfsoc_local_timer_dying_cpu(unsigned int cpu)
4898de3d BS	209	{
	210	sirfsoc_timer_count_disable(1);
	211
05a65485 SB	212	if (cpu == 0)
	213	remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	214	else
	215	remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
eb0a9d8c	216	return 0;
4898de3d BS	217	}
4898de3d BS	218
c41c96dd	219	static int __init sirfsoc_clockevent_init(void)
4898de3d	220	{
05a65485 SB	221	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
	222	BUG_ON(!sirfsoc_clockevent);
	223
eb0a9d8c RC	224	/* Install and invoke hotplug callbacks */
eb0a9d8c RC	225	return cpuhp_setup_state(CPUHP_AP_MARCO_TIMER_STARTING,
73c1b41e	226	"clockevents/marco:starting",
eb0a9d8c RC	227	sirfsoc_local_timer_starting_cpu,
eb0a9d8c RC	228	sirfsoc_local_timer_dying_cpu);
4898de3d BS	229	}
	230
	231	/* initialize the kernel jiffy timer source */
c41c96dd	232	static int __init sirfsoc_atlas7_timer_init(struct device_node *np)
4898de3d	233	{
4898de3d BS	234	struct clk *clk;
4898de3d BS	235
c7cff54d	236	clk = of_clk_get(np, 0);
4898de3d	237	BUG_ON(IS_ERR(clk));
38941522 ZS	238
	239	BUG_ON(clk_prepare_enable(clk));
	240
5833ac98	241	atlas7_timer_rate = clk_get_rate(clk);
4898de3d	242
ef89af1f YL	243	/* timer dividers: 0, not divided */
	244	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	245	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
	246	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
4898de3d BS	247
	248	/* Initialize timer counters to 0 */
	249	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	250	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	251	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	252	BIT(1) \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	253	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
	254	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
	255
	256	/* Clear all interrupts */
	257	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
	258
5833ac98	259	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, atlas7_timer_rate));
4898de3d	260
c41c96dd	261	return sirfsoc_clockevent_init();
4898de3d BS	262	}
4898de3d BS	263
c41c96dd	264	static int __init sirfsoc_of_timer_init(struct device_node *np)
4898de3d	265	{
4898de3d	266	sirfsoc_timer_base = of_iomap(np, 0);
c41c96dd DL	267	if (!sirfsoc_timer_base) {
	268	pr_err("unable to map timer cpu registers\n");
	269	return -ENXIO;
	270	}
4898de3d BS	271
4898de3d BS	272	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
c41c96dd DL	273	if (!sirfsoc_timer_irq.irq) {
	274	pr_err("No irq passed for timer0 via DT\n");
	275	return -EINVAL;
	276	}
4898de3d	277
4898de3d	278	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
c41c96dd DL	279	if (!sirfsoc_timer1_irq.irq) {
	280	pr_err("No irq passed for timer1 via DT\n");
	281	return -EINVAL;
	282	}
4898de3d	283
c41c96dd	284	return sirfsoc_atlas7_timer_init(np);
4898de3d	285	}
17273395	286	TIMER_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);