Commit | Line | Data |
---|---|---|
3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
3fb1b6ad MD |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/irq.h> | |
28 | #include <linux/err.h> | |
3f7e5e24 | 29 | #include <linux/delay.h> |
3fb1b6ad MD |
30 | #include <linux/clocksource.h> |
31 | #include <linux/clockchips.h> | |
46a12f74 | 32 | #include <linux/sh_timer.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
7deeab5d | 34 | #include <linux/module.h> |
615a445f | 35 | #include <linux/pm_domain.h> |
bad81383 | 36 | #include <linux/pm_runtime.h> |
3fb1b6ad MD |
37 | |
38 | struct sh_cmt_priv { | |
39 | void __iomem *mapbase; | |
40 | struct clk *clk; | |
41 | unsigned long width; /* 16 or 32 bit version of hardware block */ | |
42 | unsigned long overflow_bit; | |
43 | unsigned long clear_bits; | |
44 | struct irqaction irqaction; | |
45 | struct platform_device *pdev; | |
46 | ||
47 | unsigned long flags; | |
48 | unsigned long match_value; | |
49 | unsigned long next_match_value; | |
50 | unsigned long max_match_value; | |
51 | unsigned long rate; | |
7d0c399f | 52 | raw_spinlock_t lock; |
3fb1b6ad | 53 | struct clock_event_device ced; |
19bdc9d0 | 54 | struct clocksource cs; |
3fb1b6ad | 55 | unsigned long total_cycles; |
bad81383 | 56 | bool cs_enabled; |
3fb1b6ad MD |
57 | }; |
58 | ||
587acb3d MD |
59 | static inline unsigned long sh_cmt_read16(void __iomem *base, |
60 | unsigned long offs) | |
61 | { | |
62 | return ioread16(base + (offs << 1)); | |
63 | } | |
64 | ||
65 | static inline void sh_cmt_write16(void __iomem *base, unsigned long offs, | |
66 | unsigned long value) | |
67 | { | |
68 | iowrite16(value, base + (offs << 1)); | |
69 | } | |
3fb1b6ad | 70 | |
3fb1b6ad MD |
71 | #define CMCSR 0 /* channel register */ |
72 | #define CMCNT 1 /* channel register */ | |
73 | #define CMCOR 2 /* channel register */ | |
74 | ||
75 | static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr) | |
76 | { | |
3fb1b6ad | 77 | void __iomem *base = p->mapbase; |
587acb3d | 78 | unsigned long offs = reg_nr; |
3fb1b6ad | 79 | |
587acb3d | 80 | if (p->width == 16) { |
3fb1b6ad | 81 | offs <<= 1; |
587acb3d MD |
82 | return ioread16(base + offs); |
83 | } else { | |
3fb1b6ad | 84 | offs <<= 2; |
587acb3d | 85 | return ioread32(base + offs); |
3fb1b6ad | 86 | } |
3fb1b6ad MD |
87 | } |
88 | ||
1b56b96b MD |
89 | static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_priv *p) |
90 | { | |
587acb3d MD |
91 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
92 | ||
93 | return sh_cmt_read16(p->mapbase - cfg->channel_offset, 0); | |
1b56b96b MD |
94 | } |
95 | ||
96 | static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_priv *p) | |
97 | { | |
587acb3d | 98 | return sh_cmt_read16(p->mapbase, CMCSR); |
1b56b96b MD |
99 | } |
100 | ||
101 | static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_priv *p) | |
102 | { | |
103 | return sh_cmt_read(p, CMCNT); | |
104 | } | |
105 | ||
3fb1b6ad MD |
106 | static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr, |
107 | unsigned long value) | |
108 | { | |
3fb1b6ad | 109 | void __iomem *base = p->mapbase; |
587acb3d | 110 | unsigned long offs = reg_nr; |
3fb1b6ad | 111 | |
587acb3d | 112 | if (p->width == 16) { |
3fb1b6ad | 113 | offs <<= 1; |
587acb3d MD |
114 | iowrite16(value, base + offs); |
115 | } else { | |
3fb1b6ad | 116 | offs <<= 2; |
587acb3d | 117 | iowrite32(value, base + offs); |
3fb1b6ad | 118 | } |
3fb1b6ad MD |
119 | } |
120 | ||
1b56b96b MD |
121 | static inline void sh_cmt_write_cmstr(struct sh_cmt_priv *p, |
122 | unsigned long value) | |
123 | { | |
587acb3d MD |
124 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
125 | ||
126 | sh_cmt_write16(p->mapbase - cfg->channel_offset, 0, value); | |
1b56b96b MD |
127 | } |
128 | ||
129 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_priv *p, | |
130 | unsigned long value) | |
131 | { | |
587acb3d | 132 | sh_cmt_write16(p->mapbase, CMCSR, value); |
1b56b96b MD |
133 | } |
134 | ||
135 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_priv *p, | |
136 | unsigned long value) | |
137 | { | |
138 | sh_cmt_write(p, CMCNT, value); | |
139 | } | |
140 | ||
141 | static inline void sh_cmt_write_cmcor(struct sh_cmt_priv *p, | |
142 | unsigned long value) | |
143 | { | |
144 | sh_cmt_write(p, CMCOR, value); | |
145 | } | |
146 | ||
3fb1b6ad MD |
147 | static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p, |
148 | int *has_wrapped) | |
149 | { | |
150 | unsigned long v1, v2, v3; | |
5b644c7a MD |
151 | int o1, o2; |
152 | ||
1b56b96b | 153 | o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit; |
3fb1b6ad MD |
154 | |
155 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
156 | do { | |
5b644c7a | 157 | o2 = o1; |
1b56b96b MD |
158 | v1 = sh_cmt_read_cmcnt(p); |
159 | v2 = sh_cmt_read_cmcnt(p); | |
160 | v3 = sh_cmt_read_cmcnt(p); | |
161 | o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit; | |
5b644c7a MD |
162 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
163 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 164 | |
5b644c7a | 165 | *has_wrapped = o1; |
3fb1b6ad MD |
166 | return v2; |
167 | } | |
168 | ||
587acb3d | 169 | static DEFINE_RAW_SPINLOCK(sh_cmt_lock); |
3fb1b6ad MD |
170 | |
171 | static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start) | |
172 | { | |
46a12f74 | 173 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
3fb1b6ad MD |
174 | unsigned long flags, value; |
175 | ||
176 | /* start stop register shared by multiple timer channels */ | |
7d0c399f | 177 | raw_spin_lock_irqsave(&sh_cmt_lock, flags); |
1b56b96b | 178 | value = sh_cmt_read_cmstr(p); |
3fb1b6ad MD |
179 | |
180 | if (start) | |
181 | value |= 1 << cfg->timer_bit; | |
182 | else | |
183 | value &= ~(1 << cfg->timer_bit); | |
184 | ||
1b56b96b | 185 | sh_cmt_write_cmstr(p, value); |
7d0c399f | 186 | raw_spin_unlock_irqrestore(&sh_cmt_lock, flags); |
3fb1b6ad MD |
187 | } |
188 | ||
189 | static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate) | |
190 | { | |
3f7e5e24 | 191 | int k, ret; |
3fb1b6ad | 192 | |
bad81383 RW |
193 | pm_runtime_get_sync(&p->pdev->dev); |
194 | dev_pm_syscore_device(&p->pdev->dev, true); | |
195 | ||
9436b4ab | 196 | /* enable clock */ |
3fb1b6ad MD |
197 | ret = clk_enable(p->clk); |
198 | if (ret) { | |
214a607a | 199 | dev_err(&p->pdev->dev, "cannot enable clock\n"); |
3f7e5e24 | 200 | goto err0; |
3fb1b6ad | 201 | } |
3fb1b6ad MD |
202 | |
203 | /* make sure channel is disabled */ | |
204 | sh_cmt_start_stop_ch(p, 0); | |
205 | ||
206 | /* configure channel, periodic mode and maximum timeout */ | |
3014f474 MD |
207 | if (p->width == 16) { |
208 | *rate = clk_get_rate(p->clk) / 512; | |
1b56b96b | 209 | sh_cmt_write_cmcsr(p, 0x43); |
3014f474 MD |
210 | } else { |
211 | *rate = clk_get_rate(p->clk) / 8; | |
1b56b96b | 212 | sh_cmt_write_cmcsr(p, 0x01a4); |
3014f474 | 213 | } |
3fb1b6ad | 214 | |
1b56b96b MD |
215 | sh_cmt_write_cmcor(p, 0xffffffff); |
216 | sh_cmt_write_cmcnt(p, 0); | |
3fb1b6ad | 217 | |
3f7e5e24 MD |
218 | /* |
219 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
220 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
221 | * modifying CMCNT register; two RCLK cycles are necessary before | |
222 | * this register is either read or any modification of the value | |
223 | * it holds is reflected in the LSI's actual operation. | |
224 | * | |
225 | * While at it, we're supposed to clear out the CMCNT as of this | |
226 | * moment, so make sure it's processed properly here. This will | |
227 | * take RCLKx2 at maximum. | |
228 | */ | |
229 | for (k = 0; k < 100; k++) { | |
1b56b96b | 230 | if (!sh_cmt_read_cmcnt(p)) |
3f7e5e24 MD |
231 | break; |
232 | udelay(1); | |
233 | } | |
234 | ||
1b56b96b | 235 | if (sh_cmt_read_cmcnt(p)) { |
3f7e5e24 MD |
236 | dev_err(&p->pdev->dev, "cannot clear CMCNT\n"); |
237 | ret = -ETIMEDOUT; | |
238 | goto err1; | |
239 | } | |
240 | ||
3fb1b6ad MD |
241 | /* enable channel */ |
242 | sh_cmt_start_stop_ch(p, 1); | |
243 | return 0; | |
3f7e5e24 MD |
244 | err1: |
245 | /* stop clock */ | |
246 | clk_disable(p->clk); | |
247 | ||
248 | err0: | |
249 | return ret; | |
3fb1b6ad MD |
250 | } |
251 | ||
252 | static void sh_cmt_disable(struct sh_cmt_priv *p) | |
253 | { | |
254 | /* disable channel */ | |
255 | sh_cmt_start_stop_ch(p, 0); | |
256 | ||
be890a1a | 257 | /* disable interrupts in CMT block */ |
1b56b96b | 258 | sh_cmt_write_cmcsr(p, 0); |
be890a1a | 259 | |
9436b4ab | 260 | /* stop clock */ |
3fb1b6ad | 261 | clk_disable(p->clk); |
bad81383 RW |
262 | |
263 | dev_pm_syscore_device(&p->pdev->dev, false); | |
264 | pm_runtime_put(&p->pdev->dev); | |
3fb1b6ad MD |
265 | } |
266 | ||
267 | /* private flags */ | |
268 | #define FLAG_CLOCKEVENT (1 << 0) | |
269 | #define FLAG_CLOCKSOURCE (1 << 1) | |
270 | #define FLAG_REPROGRAM (1 << 2) | |
271 | #define FLAG_SKIPEVENT (1 << 3) | |
272 | #define FLAG_IRQCONTEXT (1 << 4) | |
273 | ||
274 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p, | |
275 | int absolute) | |
276 | { | |
277 | unsigned long new_match; | |
278 | unsigned long value = p->next_match_value; | |
279 | unsigned long delay = 0; | |
280 | unsigned long now = 0; | |
281 | int has_wrapped; | |
282 | ||
283 | now = sh_cmt_get_counter(p, &has_wrapped); | |
284 | p->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
285 | ||
286 | if (has_wrapped) { | |
287 | /* we're competing with the interrupt handler. | |
288 | * -> let the interrupt handler reprogram the timer. | |
289 | * -> interrupt number two handles the event. | |
290 | */ | |
291 | p->flags |= FLAG_SKIPEVENT; | |
292 | return; | |
293 | } | |
294 | ||
295 | if (absolute) | |
296 | now = 0; | |
297 | ||
298 | do { | |
299 | /* reprogram the timer hardware, | |
300 | * but don't save the new match value yet. | |
301 | */ | |
302 | new_match = now + value + delay; | |
303 | if (new_match > p->max_match_value) | |
304 | new_match = p->max_match_value; | |
305 | ||
1b56b96b | 306 | sh_cmt_write_cmcor(p, new_match); |
3fb1b6ad MD |
307 | |
308 | now = sh_cmt_get_counter(p, &has_wrapped); | |
309 | if (has_wrapped && (new_match > p->match_value)) { | |
310 | /* we are changing to a greater match value, | |
311 | * so this wrap must be caused by the counter | |
312 | * matching the old value. | |
313 | * -> first interrupt reprograms the timer. | |
314 | * -> interrupt number two handles the event. | |
315 | */ | |
316 | p->flags |= FLAG_SKIPEVENT; | |
317 | break; | |
318 | } | |
319 | ||
320 | if (has_wrapped) { | |
321 | /* we are changing to a smaller match value, | |
322 | * so the wrap must be caused by the counter | |
323 | * matching the new value. | |
324 | * -> save programmed match value. | |
325 | * -> let isr handle the event. | |
326 | */ | |
327 | p->match_value = new_match; | |
328 | break; | |
329 | } | |
330 | ||
331 | /* be safe: verify hardware settings */ | |
332 | if (now < new_match) { | |
333 | /* timer value is below match value, all good. | |
334 | * this makes sure we won't miss any match events. | |
335 | * -> save programmed match value. | |
336 | * -> let isr handle the event. | |
337 | */ | |
338 | p->match_value = new_match; | |
339 | break; | |
340 | } | |
341 | ||
342 | /* the counter has reached a value greater | |
343 | * than our new match value. and since the | |
344 | * has_wrapped flag isn't set we must have | |
345 | * programmed a too close event. | |
346 | * -> increase delay and retry. | |
347 | */ | |
348 | if (delay) | |
349 | delay <<= 1; | |
350 | else | |
351 | delay = 1; | |
352 | ||
353 | if (!delay) | |
214a607a | 354 | dev_warn(&p->pdev->dev, "too long delay\n"); |
3fb1b6ad MD |
355 | |
356 | } while (delay); | |
357 | } | |
358 | ||
65ada547 | 359 | static void __sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta) |
3fb1b6ad | 360 | { |
3fb1b6ad | 361 | if (delta > p->max_match_value) |
214a607a | 362 | dev_warn(&p->pdev->dev, "delta out of range\n"); |
3fb1b6ad | 363 | |
3fb1b6ad MD |
364 | p->next_match_value = delta; |
365 | sh_cmt_clock_event_program_verify(p, 0); | |
65ada547 TY |
366 | } |
367 | ||
368 | static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta) | |
369 | { | |
370 | unsigned long flags; | |
371 | ||
7d0c399f | 372 | raw_spin_lock_irqsave(&p->lock, flags); |
65ada547 | 373 | __sh_cmt_set_next(p, delta); |
7d0c399f | 374 | raw_spin_unlock_irqrestore(&p->lock, flags); |
3fb1b6ad MD |
375 | } |
376 | ||
377 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
378 | { | |
379 | struct sh_cmt_priv *p = dev_id; | |
380 | ||
381 | /* clear flags */ | |
1b56b96b | 382 | sh_cmt_write_cmcsr(p, sh_cmt_read_cmcsr(p) & p->clear_bits); |
3fb1b6ad MD |
383 | |
384 | /* update clock source counter to begin with if enabled | |
385 | * the wrap flag should be cleared by the timer specific | |
386 | * isr before we end up here. | |
387 | */ | |
388 | if (p->flags & FLAG_CLOCKSOURCE) | |
43809473 | 389 | p->total_cycles += p->match_value + 1; |
3fb1b6ad MD |
390 | |
391 | if (!(p->flags & FLAG_REPROGRAM)) | |
392 | p->next_match_value = p->max_match_value; | |
393 | ||
394 | p->flags |= FLAG_IRQCONTEXT; | |
395 | ||
396 | if (p->flags & FLAG_CLOCKEVENT) { | |
397 | if (!(p->flags & FLAG_SKIPEVENT)) { | |
398 | if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) { | |
399 | p->next_match_value = p->max_match_value; | |
400 | p->flags |= FLAG_REPROGRAM; | |
401 | } | |
402 | ||
403 | p->ced.event_handler(&p->ced); | |
404 | } | |
405 | } | |
406 | ||
407 | p->flags &= ~FLAG_SKIPEVENT; | |
408 | ||
409 | if (p->flags & FLAG_REPROGRAM) { | |
410 | p->flags &= ~FLAG_REPROGRAM; | |
411 | sh_cmt_clock_event_program_verify(p, 1); | |
412 | ||
413 | if (p->flags & FLAG_CLOCKEVENT) | |
414 | if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) | |
415 | || (p->match_value == p->next_match_value)) | |
416 | p->flags &= ~FLAG_REPROGRAM; | |
417 | } | |
418 | ||
419 | p->flags &= ~FLAG_IRQCONTEXT; | |
420 | ||
421 | return IRQ_HANDLED; | |
422 | } | |
423 | ||
424 | static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag) | |
425 | { | |
426 | int ret = 0; | |
427 | unsigned long flags; | |
428 | ||
7d0c399f | 429 | raw_spin_lock_irqsave(&p->lock, flags); |
3fb1b6ad MD |
430 | |
431 | if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) | |
432 | ret = sh_cmt_enable(p, &p->rate); | |
433 | ||
434 | if (ret) | |
435 | goto out; | |
436 | p->flags |= flag; | |
437 | ||
438 | /* setup timeout if no clockevent */ | |
439 | if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT))) | |
65ada547 | 440 | __sh_cmt_set_next(p, p->max_match_value); |
3fb1b6ad | 441 | out: |
7d0c399f | 442 | raw_spin_unlock_irqrestore(&p->lock, flags); |
3fb1b6ad MD |
443 | |
444 | return ret; | |
445 | } | |
446 | ||
447 | static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag) | |
448 | { | |
449 | unsigned long flags; | |
450 | unsigned long f; | |
451 | ||
7d0c399f | 452 | raw_spin_lock_irqsave(&p->lock, flags); |
3fb1b6ad MD |
453 | |
454 | f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); | |
455 | p->flags &= ~flag; | |
456 | ||
457 | if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) | |
458 | sh_cmt_disable(p); | |
459 | ||
460 | /* adjust the timeout to maximum if only clocksource left */ | |
461 | if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE)) | |
65ada547 | 462 | __sh_cmt_set_next(p, p->max_match_value); |
3fb1b6ad | 463 | |
7d0c399f | 464 | raw_spin_unlock_irqrestore(&p->lock, flags); |
3fb1b6ad MD |
465 | } |
466 | ||
19bdc9d0 MD |
467 | static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs) |
468 | { | |
469 | return container_of(cs, struct sh_cmt_priv, cs); | |
470 | } | |
471 | ||
472 | static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) | |
473 | { | |
474 | struct sh_cmt_priv *p = cs_to_sh_cmt(cs); | |
475 | unsigned long flags, raw; | |
476 | unsigned long value; | |
477 | int has_wrapped; | |
478 | ||
7d0c399f | 479 | raw_spin_lock_irqsave(&p->lock, flags); |
19bdc9d0 MD |
480 | value = p->total_cycles; |
481 | raw = sh_cmt_get_counter(p, &has_wrapped); | |
482 | ||
483 | if (unlikely(has_wrapped)) | |
43809473 | 484 | raw += p->match_value + 1; |
7d0c399f | 485 | raw_spin_unlock_irqrestore(&p->lock, flags); |
19bdc9d0 MD |
486 | |
487 | return value + raw; | |
488 | } | |
489 | ||
490 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
491 | { | |
3593f5fe | 492 | int ret; |
19bdc9d0 | 493 | struct sh_cmt_priv *p = cs_to_sh_cmt(cs); |
19bdc9d0 | 494 | |
bad81383 RW |
495 | WARN_ON(p->cs_enabled); |
496 | ||
19bdc9d0 MD |
497 | p->total_cycles = 0; |
498 | ||
3593f5fe | 499 | ret = sh_cmt_start(p, FLAG_CLOCKSOURCE); |
bad81383 | 500 | if (!ret) { |
3593f5fe | 501 | __clocksource_updatefreq_hz(cs, p->rate); |
bad81383 RW |
502 | p->cs_enabled = true; |
503 | } | |
3593f5fe | 504 | return ret; |
19bdc9d0 MD |
505 | } |
506 | ||
507 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
508 | { | |
bad81383 RW |
509 | struct sh_cmt_priv *p = cs_to_sh_cmt(cs); |
510 | ||
511 | WARN_ON(!p->cs_enabled); | |
512 | ||
513 | sh_cmt_stop(p, FLAG_CLOCKSOURCE); | |
514 | p->cs_enabled = false; | |
19bdc9d0 MD |
515 | } |
516 | ||
9bb5ec88 RW |
517 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
518 | { | |
519 | struct sh_cmt_priv *p = cs_to_sh_cmt(cs); | |
520 | ||
521 | sh_cmt_stop(p, FLAG_CLOCKSOURCE); | |
522 | pm_genpd_syscore_poweroff(&p->pdev->dev); | |
523 | } | |
524 | ||
c8162884 MD |
525 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
526 | { | |
9bb5ec88 RW |
527 | struct sh_cmt_priv *p = cs_to_sh_cmt(cs); |
528 | ||
529 | pm_genpd_syscore_poweron(&p->pdev->dev); | |
530 | sh_cmt_start(p, FLAG_CLOCKSOURCE); | |
c8162884 MD |
531 | } |
532 | ||
19bdc9d0 MD |
533 | static int sh_cmt_register_clocksource(struct sh_cmt_priv *p, |
534 | char *name, unsigned long rating) | |
535 | { | |
536 | struct clocksource *cs = &p->cs; | |
537 | ||
538 | cs->name = name; | |
539 | cs->rating = rating; | |
540 | cs->read = sh_cmt_clocksource_read; | |
541 | cs->enable = sh_cmt_clocksource_enable; | |
542 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 543 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 544 | cs->resume = sh_cmt_clocksource_resume; |
19bdc9d0 MD |
545 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
546 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 547 | |
214a607a | 548 | dev_info(&p->pdev->dev, "used as clock source\n"); |
f4d7c356 | 549 | |
3593f5fe MD |
550 | /* Register with dummy 1 Hz value, gets updated in ->enable() */ |
551 | clocksource_register_hz(cs, 1); | |
19bdc9d0 MD |
552 | return 0; |
553 | } | |
554 | ||
3fb1b6ad MD |
555 | static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced) |
556 | { | |
557 | return container_of(ced, struct sh_cmt_priv, ced); | |
558 | } | |
559 | ||
560 | static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic) | |
561 | { | |
562 | struct clock_event_device *ced = &p->ced; | |
563 | ||
564 | sh_cmt_start(p, FLAG_CLOCKEVENT); | |
565 | ||
566 | /* TODO: calculate good shift from rate and counter bit width */ | |
567 | ||
568 | ced->shift = 32; | |
569 | ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift); | |
570 | ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced); | |
571 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); | |
572 | ||
573 | if (periodic) | |
43809473 | 574 | sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1); |
3fb1b6ad MD |
575 | else |
576 | sh_cmt_set_next(p, p->max_match_value); | |
577 | } | |
578 | ||
579 | static void sh_cmt_clock_event_mode(enum clock_event_mode mode, | |
580 | struct clock_event_device *ced) | |
581 | { | |
582 | struct sh_cmt_priv *p = ced_to_sh_cmt(ced); | |
583 | ||
584 | /* deal with old setting first */ | |
585 | switch (ced->mode) { | |
586 | case CLOCK_EVT_MODE_PERIODIC: | |
587 | case CLOCK_EVT_MODE_ONESHOT: | |
588 | sh_cmt_stop(p, FLAG_CLOCKEVENT); | |
589 | break; | |
590 | default: | |
591 | break; | |
592 | } | |
593 | ||
594 | switch (mode) { | |
595 | case CLOCK_EVT_MODE_PERIODIC: | |
214a607a | 596 | dev_info(&p->pdev->dev, "used for periodic clock events\n"); |
3fb1b6ad MD |
597 | sh_cmt_clock_event_start(p, 1); |
598 | break; | |
599 | case CLOCK_EVT_MODE_ONESHOT: | |
214a607a | 600 | dev_info(&p->pdev->dev, "used for oneshot clock events\n"); |
3fb1b6ad MD |
601 | sh_cmt_clock_event_start(p, 0); |
602 | break; | |
603 | case CLOCK_EVT_MODE_SHUTDOWN: | |
604 | case CLOCK_EVT_MODE_UNUSED: | |
605 | sh_cmt_stop(p, FLAG_CLOCKEVENT); | |
606 | break; | |
607 | default: | |
608 | break; | |
609 | } | |
610 | } | |
611 | ||
612 | static int sh_cmt_clock_event_next(unsigned long delta, | |
613 | struct clock_event_device *ced) | |
614 | { | |
615 | struct sh_cmt_priv *p = ced_to_sh_cmt(ced); | |
616 | ||
617 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
618 | if (likely(p->flags & FLAG_IRQCONTEXT)) | |
43809473 | 619 | p->next_match_value = delta - 1; |
3fb1b6ad | 620 | else |
43809473 | 621 | sh_cmt_set_next(p, delta - 1); |
3fb1b6ad MD |
622 | |
623 | return 0; | |
624 | } | |
625 | ||
9bb5ec88 RW |
626 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
627 | { | |
628 | pm_genpd_syscore_poweroff(&ced_to_sh_cmt(ced)->pdev->dev); | |
629 | } | |
630 | ||
631 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
632 | { | |
633 | pm_genpd_syscore_poweron(&ced_to_sh_cmt(ced)->pdev->dev); | |
634 | } | |
635 | ||
3fb1b6ad MD |
636 | static void sh_cmt_register_clockevent(struct sh_cmt_priv *p, |
637 | char *name, unsigned long rating) | |
638 | { | |
639 | struct clock_event_device *ced = &p->ced; | |
640 | ||
641 | memset(ced, 0, sizeof(*ced)); | |
642 | ||
643 | ced->name = name; | |
644 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
645 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
646 | ced->rating = rating; | |
647 | ced->cpumask = cpumask_of(0); | |
648 | ced->set_next_event = sh_cmt_clock_event_next; | |
649 | ced->set_mode = sh_cmt_clock_event_mode; | |
9bb5ec88 RW |
650 | ced->suspend = sh_cmt_clock_event_suspend; |
651 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 652 | |
214a607a | 653 | dev_info(&p->pdev->dev, "used for clock events\n"); |
3fb1b6ad MD |
654 | clockevents_register_device(ced); |
655 | } | |
656 | ||
d1fcc0a8 PM |
657 | static int sh_cmt_register(struct sh_cmt_priv *p, char *name, |
658 | unsigned long clockevent_rating, | |
659 | unsigned long clocksource_rating) | |
3fb1b6ad | 660 | { |
3fb1b6ad MD |
661 | if (clockevent_rating) |
662 | sh_cmt_register_clockevent(p, name, clockevent_rating); | |
663 | ||
19bdc9d0 MD |
664 | if (clocksource_rating) |
665 | sh_cmt_register_clocksource(p, name, clocksource_rating); | |
666 | ||
3fb1b6ad MD |
667 | return 0; |
668 | } | |
669 | ||
670 | static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev) | |
671 | { | |
46a12f74 | 672 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
3fb1b6ad MD |
673 | struct resource *res; |
674 | int irq, ret; | |
675 | ret = -ENXIO; | |
676 | ||
677 | memset(p, 0, sizeof(*p)); | |
678 | p->pdev = pdev; | |
679 | ||
680 | if (!cfg) { | |
681 | dev_err(&p->pdev->dev, "missing platform data\n"); | |
682 | goto err0; | |
683 | } | |
684 | ||
3fb1b6ad MD |
685 | res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0); |
686 | if (!res) { | |
687 | dev_err(&p->pdev->dev, "failed to get I/O memory\n"); | |
688 | goto err0; | |
689 | } | |
690 | ||
691 | irq = platform_get_irq(p->pdev, 0); | |
692 | if (irq < 0) { | |
693 | dev_err(&p->pdev->dev, "failed to get irq\n"); | |
694 | goto err0; | |
695 | } | |
696 | ||
697 | /* map memory, let mapbase point to our channel */ | |
698 | p->mapbase = ioremap_nocache(res->start, resource_size(res)); | |
699 | if (p->mapbase == NULL) { | |
214a607a | 700 | dev_err(&p->pdev->dev, "failed to remap I/O memory\n"); |
3fb1b6ad MD |
701 | goto err0; |
702 | } | |
703 | ||
704 | /* request irq using setup_irq() (too early for request_irq()) */ | |
214a607a | 705 | p->irqaction.name = dev_name(&p->pdev->dev); |
3fb1b6ad MD |
706 | p->irqaction.handler = sh_cmt_interrupt; |
707 | p->irqaction.dev_id = p; | |
fecf066c PM |
708 | p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \ |
709 | IRQF_IRQPOLL | IRQF_NOBALANCING; | |
3fb1b6ad MD |
710 | |
711 | /* get hold of clock */ | |
c2a25e81 | 712 | p->clk = clk_get(&p->pdev->dev, "cmt_fck"); |
3fb1b6ad | 713 | if (IS_ERR(p->clk)) { |
03ff858c MD |
714 | dev_err(&p->pdev->dev, "cannot get clock\n"); |
715 | ret = PTR_ERR(p->clk); | |
716 | goto err1; | |
3fb1b6ad MD |
717 | } |
718 | ||
719 | if (resource_size(res) == 6) { | |
720 | p->width = 16; | |
721 | p->overflow_bit = 0x80; | |
3014f474 | 722 | p->clear_bits = ~0x80; |
3fb1b6ad MD |
723 | } else { |
724 | p->width = 32; | |
725 | p->overflow_bit = 0x8000; | |
726 | p->clear_bits = ~0xc000; | |
727 | } | |
728 | ||
44a10f94 MD |
729 | if (p->width == (sizeof(p->max_match_value) * 8)) |
730 | p->max_match_value = ~0; | |
731 | else | |
732 | p->max_match_value = (1 << p->width) - 1; | |
733 | ||
734 | p->match_value = p->max_match_value; | |
735 | raw_spin_lock_init(&p->lock); | |
736 | ||
214a607a | 737 | ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev), |
da64c2a8 PM |
738 | cfg->clockevent_rating, |
739 | cfg->clocksource_rating); | |
740 | if (ret) { | |
214a607a | 741 | dev_err(&p->pdev->dev, "registration failed\n"); |
2fd61b32 | 742 | goto err2; |
da64c2a8 | 743 | } |
bad81383 | 744 | p->cs_enabled = false; |
da64c2a8 PM |
745 | |
746 | ret = setup_irq(irq, &p->irqaction); | |
747 | if (ret) { | |
214a607a | 748 | dev_err(&p->pdev->dev, "failed to request irq %d\n", irq); |
2fd61b32 | 749 | goto err2; |
da64c2a8 PM |
750 | } |
751 | ||
adccc69e MD |
752 | platform_set_drvdata(pdev, p); |
753 | ||
da64c2a8 | 754 | return 0; |
2fd61b32 MD |
755 | err2: |
756 | clk_put(p->clk); | |
da64c2a8 PM |
757 | |
758 | err1: | |
3fb1b6ad | 759 | iounmap(p->mapbase); |
da64c2a8 | 760 | err0: |
3fb1b6ad MD |
761 | return ret; |
762 | } | |
763 | ||
1850514b | 764 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad MD |
765 | { |
766 | struct sh_cmt_priv *p = platform_get_drvdata(pdev); | |
bad81383 | 767 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
3fb1b6ad MD |
768 | int ret; |
769 | ||
9bb5ec88 | 770 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
771 | pm_runtime_set_active(&pdev->dev); |
772 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 773 | } |
615a445f | 774 | |
e475eedb | 775 | if (p) { |
214a607a | 776 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 777 | goto out; |
e475eedb MD |
778 | } |
779 | ||
8e0b8429 | 780 | p = kmalloc(sizeof(*p), GFP_KERNEL); |
3fb1b6ad MD |
781 | if (p == NULL) { |
782 | dev_err(&pdev->dev, "failed to allocate driver data\n"); | |
783 | return -ENOMEM; | |
784 | } | |
785 | ||
786 | ret = sh_cmt_setup(p, pdev); | |
787 | if (ret) { | |
8e0b8429 | 788 | kfree(p); |
bad81383 RW |
789 | pm_runtime_idle(&pdev->dev); |
790 | return ret; | |
3fb1b6ad | 791 | } |
bad81383 RW |
792 | if (is_early_platform_device(pdev)) |
793 | return 0; | |
794 | ||
795 | out: | |
796 | if (cfg->clockevent_rating || cfg->clocksource_rating) | |
797 | pm_runtime_irq_safe(&pdev->dev); | |
798 | else | |
799 | pm_runtime_idle(&pdev->dev); | |
800 | ||
801 | return 0; | |
3fb1b6ad MD |
802 | } |
803 | ||
1850514b | 804 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
805 | { |
806 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
807 | } | |
808 | ||
809 | static struct platform_driver sh_cmt_device_driver = { | |
810 | .probe = sh_cmt_probe, | |
1850514b | 811 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
812 | .driver = { |
813 | .name = "sh_cmt", | |
814 | } | |
815 | }; | |
816 | ||
817 | static int __init sh_cmt_init(void) | |
818 | { | |
819 | return platform_driver_register(&sh_cmt_device_driver); | |
820 | } | |
821 | ||
822 | static void __exit sh_cmt_exit(void) | |
823 | { | |
824 | platform_driver_unregister(&sh_cmt_device_driver); | |
825 | } | |
826 | ||
e475eedb | 827 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
3fb1b6ad MD |
828 | module_init(sh_cmt_init); |
829 | module_exit(sh_cmt_exit); | |
830 | ||
831 | MODULE_AUTHOR("Magnus Damm"); | |
832 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
833 | MODULE_LICENSE("GPL v2"); |