[linux-2.6-block.git] / drivers / clocksource / qcom-timer.c

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <asm/delay.h>

#define TIMER_MATCH_VAL			0x0000
#define TIMER_COUNT_VAL			0x0004
#define TIMER_ENABLE			0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN	BIT(1)
#define TIMER_ENABLE_EN			BIT(0)
#define TIMER_CLEAR			0x000C
#define DGT_CLK_CTL			0x10
#define DGT_CLK_CTL_DIV_4		0x3
#define TIMER_STS_GPT0_CLR_PEND		BIT(10)

#define GPT_HZ 32768

static void __iomem *event_base;
static void __iomem *sts_base;

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	/* Stop the timer tick */
	if (clockevent_state_oneshot(evt)) {
		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
		ctrl &= ~TIMER_ENABLE_EN;
		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	}
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);

	ctrl &= ~TIMER_ENABLE_EN;
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);

	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);

	if (sts_base)
		while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
			cpu_relax();

	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
	return 0;
}

static int msm_timer_shutdown(struct clock_event_device *evt)
{
	u32 ctrl;

	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	return 0;
}

static struct clock_event_device __percpu *msm_evt;

static void __iomem *source_base;

static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
{
	return readl_relaxed(source_base + TIMER_COUNT_VAL);
}

static struct clocksource msm_clocksource = {
	.name	= "dg_timer",
	.rating	= 300,
	.read	= msm_read_timer_count,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static int msm_timer_irq;
static int msm_timer_has_ppi;

static int msm_local_timer_setup(struct clock_event_device *evt)
{
	int cpu = smp_processor_id();
	int err;

	evt->irq = msm_timer_irq;
	evt->name = "msm_timer";
	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 200;
	evt->set_state_shutdown = msm_timer_shutdown;
	evt->set_state_oneshot = msm_timer_shutdown;
	evt->tick_resume = msm_timer_shutdown;
	evt->set_next_event = msm_timer_set_next_event;
	evt->cpumask = cpumask_of(cpu);

	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);

	if (msm_timer_has_ppi) {
		enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	} else {
		err = request_irq(evt->irq, msm_timer_interrupt,
				IRQF_TIMER | IRQF_NOBALANCING |
				IRQF_TRIGGER_RISING, "gp_timer", evt);
		if (err)
			pr_err("request_irq failed\n");
	}

	return 0;
}

static void msm_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_state_shutdown(evt);
	disable_percpu_irq(evt->irq);
}

static int msm_timer_cpu_notify(struct notifier_block *self,
					   unsigned long action, void *hcpu)
{
	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		msm_local_timer_setup(this_cpu_ptr(msm_evt));
		break;
	case CPU_DYING:
		msm_local_timer_stop(this_cpu_ptr(msm_evt));
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block msm_timer_cpu_nb = {
	.notifier_call = msm_timer_cpu_notify,
};

static u64 notrace msm_sched_clock_read(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static unsigned long msm_read_current_timer(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static struct delay_timer msm_delay_timer = {
	.read_current_timer = msm_read_current_timer,
};

static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
				  bool percpu)
{
	struct clocksource *cs = &msm_clocksource;
	int res = 0;

	msm_timer_irq = irq;
	msm_timer_has_ppi = percpu;

	msm_evt = alloc_percpu(struct clock_event_device);
	if (!msm_evt) {
		pr_err("memory allocation failed for clockevents\n");
		goto err;
	}

	if (percpu)
		res = request_percpu_irq(irq, msm_timer_interrupt,
					 "gp_timer", msm_evt);

	if (res) {
		pr_err("request_percpu_irq failed\n");
	} else {
		res = register_cpu_notifier(&msm_timer_cpu_nb);
		if (res) {
			free_percpu_irq(irq, msm_evt);
			goto err;
		}

		/* Immediately configure the timer on the boot CPU */
		msm_local_timer_setup(raw_cpu_ptr(msm_evt));
	}

err:
	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
	res = clocksource_register_hz(cs, dgt_hz);
	if (res)
		pr_err("clocksource_register failed\n");
	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
	msm_delay_timer.freq = dgt_hz;
	register_current_timer_delay(&msm_delay_timer);
}

static void __init msm_dt_timer_init(struct device_node *np)
{
	u32 freq;
	int irq;
	struct resource res;
	u32 percpu_offset;
	void __iomem *base;
	void __iomem *cpu0_base;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("Failed to map event base\n");
		return;
	}

	/* We use GPT0 for the clockevent */
	irq = irq_of_parse_and_map(np, 1);
	if (irq <= 0) {
		pr_err("Can't get irq\n");
		return;
	}

	/* We use CPU0's DGT for the clocksource */
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	if (of_address_to_resource(np, 0, &res)) {
		pr_err("Failed to parse DGT resource\n");
		return;
	}

	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
	if (!cpu0_base) {
		pr_err("Failed to map source base\n");
		return;
	}

	if (of_property_read_u32(np, "clock-frequency", &freq)) {
		pr_err("Unknown frequency\n");
		return;
	}

	event_base = base + 0x4;
	sts_base = base + 0x88;
	source_base = cpu0_base + 0x24;
	freq /= 4;
	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);

	msm_timer_init(freq, 32, irq, !!percpu_offset);
}
CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
Commit	Line	Data
dd15ab81	1	/*
3e4ea372 AH	2	*
3e4ea372 AH	3	* Copyright (C) 2007 Google, Inc.
3f8e8cee	4	* Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
3e4ea372 AH	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
4a184075 SB	17	#include <linux/clocksource.h>
4a184075 SB	18	#include <linux/clockchips.h>
4d70c59b	19	#include <linux/cpu.h>
3e4ea372	20	#include <linux/init.h>
3e4ea372 AH	21	#include <linux/interrupt.h>
3e4ea372 AH	22	#include <linux/irq.h>
fced80c7	23	#include <linux/io.h>
6e332163 SB	24	#include <linux/of.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_irq.h>
38ff87f7	27	#include <linux/sched_clock.h>
3e4ea372	28
013be5ad SB	29	#include <asm/delay.h>
013be5ad SB	30
e25e3d1f SB	31	#define TIMER_MATCH_VAL 0x0000
	32	#define TIMER_COUNT_VAL 0x0004
	33	#define TIMER_ENABLE 0x0008
	34	#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
	35	#define TIMER_ENABLE_EN BIT(0)
	36	#define TIMER_CLEAR 0x000C
	37	#define DGT_CLK_CTL 0x10
	38	#define DGT_CLK_CTL_DIV_4 0x3
	39	#define TIMER_STS_GPT0_CLR_PEND BIT(10)
3e4ea372 AH	40
3e4ea372 AH	41	#define GPT_HZ 32768
672039f0	42
2a00c106	43	static void __iomem *event_base;
e25e3d1f	44	static void __iomem *sts_base;
a850c3f6	45
3e4ea372 AH	46	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
3e4ea372 AH	47	{
4d70c59b	48	struct clock_event_device *evt = dev_id;
a850c3f6	49	/* Stop the timer tick */
736b2df2	50	if (clockevent_state_oneshot(evt)) {
2a00c106	51	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	52	ctrl &= ~TIMER_ENABLE_EN;
2a00c106	53	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
a850c3f6	54	}
3e4ea372 AH	55	evt->event_handler(evt);
	56	return IRQ_HANDLED;
	57	}
	58
3e4ea372 AH	59	static int msm_timer_set_next_event(unsigned long cycles,
	60	struct clock_event_device *evt)
	61	{
2a00c106	62	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
3e4ea372	63
4080d2d1 SB	64	ctrl &= ~TIMER_ENABLE_EN;
	65	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	66
	67	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
2a00c106	68	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
e25e3d1f SB	69
	70	if (sts_base)
	71	while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
	72	cpu_relax();
	73
2a00c106	74	writel_relaxed(ctrl \| TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
3e4ea372 AH	75	return 0;
	76	}
	77
736b2df2	78	static int msm_timer_shutdown(struct clock_event_device *evt)
3e4ea372	79	{
a850c3f6 SB	80	u32 ctrl;
a850c3f6 SB	81
2a00c106	82	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	83	ctrl &= ~(TIMER_ENABLE_EN \| TIMER_ENABLE_CLR_ON_MATCH_EN);
2a00c106	84	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
736b2df2	85	return 0;
3e4ea372 AH	86	}
3e4ea372 AH	87
4d70c59b	88	static struct clock_event_device __percpu *msm_evt;
2a00c106 SB	89
	90	static void __iomem *source_base;
	91
f8e56c42	92	static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
2081a6b5 SB	93	{
	94	return readl_relaxed(source_base + TIMER_COUNT_VAL);
	95	}
	96
2a00c106 SB	97	static struct clocksource msm_clocksource = {
	98	.name = "dg_timer",
	99	.rating = 300,
	100	.read = msm_read_timer_count,
2081a6b5	101	.mask = CLOCKSOURCE_MASK(32),
2a00c106	102	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	103	};
3e4ea372 AH	104
4d70c59b SB	105	static int msm_timer_irq;
	106	static int msm_timer_has_ppi;
	107
8bd26e3a	108	static int msm_local_timer_setup(struct clock_event_device *evt)
5ca709c1	109	{
4d70c59b SB	110	int cpu = smp_processor_id();
	111	int err;
	112
	113	evt->irq = msm_timer_irq;
	114	evt->name = "msm_timer";
	115	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	116	evt->rating = 200;
736b2df2 VK	117	evt->set_state_shutdown = msm_timer_shutdown;
	118	evt->set_state_oneshot = msm_timer_shutdown;
	119	evt->tick_resume = msm_timer_shutdown;
5ca709c1	120	evt->set_next_event = msm_timer_set_next_event;
4d70c59b SB	121	evt->cpumask = cpumask_of(cpu);
	122
	123	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
	124
	125	if (msm_timer_has_ppi) {
	126	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	127	} else {
	128	err = request_irq(evt->irq, msm_timer_interrupt,
	129	IRQF_TIMER \| IRQF_NOBALANCING \|
	130	IRQF_TRIGGER_RISING, "gp_timer", evt);
	131	if (err)
	132	pr_err("request_irq failed\n");
	133	}
5ca709c1	134
5ca709c1 MZ	135	return 0;
	136	}
	137
	138	static void msm_local_timer_stop(struct clock_event_device *evt)
	139	{
736b2df2	140	evt->set_state_shutdown(evt);
5ca709c1 MZ	141	disable_percpu_irq(evt->irq);
	142	}
	143
47dcd356	144	static int msm_timer_cpu_notify(struct notifier_block *self,
4d70c59b SB	145	unsigned long action, void *hcpu)
	146	{
	147	/*
	148	* Grab cpu pointer in each case to avoid spurious
	149	* preemptible warnings
	150	*/
	151	switch (action & ~CPU_TASKS_FROZEN) {
	152	case CPU_STARTING:
	153	msm_local_timer_setup(this_cpu_ptr(msm_evt));
	154	break;
	155	case CPU_DYING:
	156	msm_local_timer_stop(this_cpu_ptr(msm_evt));
	157	break;
	158	}
	159
	160	return NOTIFY_OK;
	161	}
	162
47dcd356	163	static struct notifier_block msm_timer_cpu_nb = {
4d70c59b	164	.notifier_call = msm_timer_cpu_notify,
5ca709c1	165	};
5ca709c1	166
6aa16a26	167	static u64 notrace msm_sched_clock_read(void)
f8e56c42 SB	168	{
	169	return msm_clocksource.read(&msm_clocksource);
	170	}
	171
013be5ad SB	172	static unsigned long msm_read_current_timer(void)
	173	{
	174	return msm_clocksource.read(&msm_clocksource);
	175	}
	176
	177	static struct delay_timer msm_delay_timer = {
	178	.read_current_timer = msm_read_current_timer,
	179	};
	180
4312a7ef SB	181	static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
4312a7ef SB	182	bool percpu)
3e4ea372	183	{
2a00c106	184	struct clocksource *cs = &msm_clocksource;
4d70c59b SB	185	int res = 0;
	186
	187	msm_timer_irq = irq;
	188	msm_timer_has_ppi = percpu;
	189
	190	msm_evt = alloc_percpu(struct clock_event_device);
	191	if (!msm_evt) {
	192	pr_err("memory allocation failed for clockevents\n");
	193	goto err;
	194	}
3e4ea372	195
4d70c59b SB	196	if (percpu)
	197	res = request_percpu_irq(irq, msm_timer_interrupt,
	198	"gp_timer", msm_evt);
dd15ab81	199
4d70c59b SB	200	if (res) {
	201	pr_err("request_percpu_irq failed\n");
	202	} else {
	203	res = register_cpu_notifier(&msm_timer_cpu_nb);
	204	if (res) {
	205	free_percpu_irq(irq, msm_evt);
dd15ab81	206	goto err;
28af690a	207	}
4d70c59b SB	208
4d70c59b SB	209	/* Immediately configure the timer on the boot CPU */
77422a8f	210	msm_local_timer_setup(raw_cpu_ptr(msm_evt));
3e4ea372	211	}
dd15ab81	212
dd15ab81	213	err:
2a00c106	214	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
2081a6b5	215	res = clocksource_register_hz(cs, dgt_hz);
dd15ab81	216	if (res)
2a00c106	217	pr_err("clocksource_register failed\n");
6aa16a26	218	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
013be5ad SB	219	msm_delay_timer.freq = dgt_hz;
013be5ad SB	220	register_current_timer_delay(&msm_delay_timer);
3e4ea372 AH	221	}
3e4ea372 AH	222
c602520f	223	static void __init msm_dt_timer_init(struct device_node *np)
6e332163	224	{
6e332163 SB	225	u32 freq;
	226	int irq;
	227	struct resource res;
	228	u32 percpu_offset;
eebdb0c1 SB	229	void __iomem *base;
eebdb0c1 SB	230	void __iomem *cpu0_base;
6e332163	231
eebdb0c1 SB	232	base = of_iomap(np, 0);
eebdb0c1 SB	233	if (!base) {
6e332163 SB	234	pr_err("Failed to map event base\n");
	235	return;
	236	}
	237
eebdb0c1 SB	238	/* We use GPT0 for the clockevent */
eebdb0c1 SB	239	irq = irq_of_parse_and_map(np, 1);
6e332163 SB	240	if (irq <= 0) {
	241	pr_err("Can't get irq\n");
	242	return;
	243	}
6e332163	244
eebdb0c1	245	/* We use CPU0's DGT for the clocksource */
6e332163 SB	246	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	247	percpu_offset = 0;
	248
	249	if (of_address_to_resource(np, 0, &res)) {
	250	pr_err("Failed to parse DGT resource\n");
	251	return;
	252	}
	253
eebdb0c1 SB	254	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
eebdb0c1 SB	255	if (!cpu0_base) {
6e332163 SB	256	pr_err("Failed to map source base\n");
	257	return;
	258	}
	259
6e332163 SB	260	if (of_property_read_u32(np, "clock-frequency", &freq)) {
	261	pr_err("Unknown frequency\n");
	262	return;
	263	}
6e332163	264
eebdb0c1	265	event_base = base + 0x4;
e25e3d1f	266	sts_base = base + 0x88;
eebdb0c1 SB	267	source_base = cpu0_base + 0x24;
	268	freq /= 4;
	269	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
	270
6e332163 SB	271	msm_timer_init(freq, 32, irq, !!percpu_offset);
6e332163 SB	272	}
c602520f SB	273	CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
c602520f SB	274	CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);