[linux-2.6-block.git] / drivers / clocksource / qcom-timer.c

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <asm/delay.h>

#define TIMER_MATCH_VAL			0x0000
#define TIMER_COUNT_VAL			0x0004
#define TIMER_ENABLE			0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN	BIT(1)
#define TIMER_ENABLE_EN			BIT(0)
#define TIMER_CLEAR			0x000C
#define DGT_CLK_CTL			0x10
#define DGT_CLK_CTL_DIV_4		0x3
#define TIMER_STS_GPT0_CLR_PEND		BIT(10)

#define GPT_HZ 32768

#define MSM_DGT_SHIFT 5

static void __iomem *event_base;
static void __iomem *sts_base;

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	/* Stop the timer tick */
	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
		ctrl &= ~TIMER_ENABLE_EN;
		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	}
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);

	ctrl &= ~TIMER_ENABLE_EN;
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);

	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);

	if (sts_base)
		while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
			cpu_relax();

	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
	return 0;
}

static void msm_timer_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	u32 ctrl;

	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);

	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Timer is enabled in set_next_event */
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		break;
	}
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
}

static struct clock_event_device __percpu *msm_evt;

static void __iomem *source_base;

static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
{
	return readl_relaxed(source_base + TIMER_COUNT_VAL);
}

static struct clocksource msm_clocksource = {
	.name	= "dg_timer",
	.rating	= 300,
	.read	= msm_read_timer_count,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static int msm_timer_irq;
static int msm_timer_has_ppi;

static int msm_local_timer_setup(struct clock_event_device *evt)
{
	int cpu = smp_processor_id();
	int err;

	evt->irq = msm_timer_irq;
	evt->name = "msm_timer";
	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 200;
	evt->set_mode = msm_timer_set_mode;
	evt->set_next_event = msm_timer_set_next_event;
	evt->cpumask = cpumask_of(cpu);

	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);

	if (msm_timer_has_ppi) {
		enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	} else {
		err = request_irq(evt->irq, msm_timer_interrupt,
				IRQF_TIMER | IRQF_NOBALANCING |
				IRQF_TRIGGER_RISING, "gp_timer", evt);
		if (err)
			pr_err("request_irq failed\n");
	}

	return 0;
}

static void msm_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	disable_percpu_irq(evt->irq);
}

static int msm_timer_cpu_notify(struct notifier_block *self,
					   unsigned long action, void *hcpu)
{
	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		msm_local_timer_setup(this_cpu_ptr(msm_evt));
		break;
	case CPU_DYING:
		msm_local_timer_stop(this_cpu_ptr(msm_evt));
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block msm_timer_cpu_nb = {
	.notifier_call = msm_timer_cpu_notify,
};

static u64 notrace msm_sched_clock_read(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static unsigned long msm_read_current_timer(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static struct delay_timer msm_delay_timer = {
	.read_current_timer = msm_read_current_timer,
};

static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
				  bool percpu)
{
	struct clocksource *cs = &msm_clocksource;
	int res = 0;

	msm_timer_irq = irq;
	msm_timer_has_ppi = percpu;

	msm_evt = alloc_percpu(struct clock_event_device);
	if (!msm_evt) {
		pr_err("memory allocation failed for clockevents\n");
		goto err;
	}

	if (percpu)
		res = request_percpu_irq(irq, msm_timer_interrupt,
					 "gp_timer", msm_evt);

	if (res) {
		pr_err("request_percpu_irq failed\n");
	} else {
		res = register_cpu_notifier(&msm_timer_cpu_nb);
		if (res) {
			free_percpu_irq(irq, msm_evt);
			goto err;
		}

		/* Immediately configure the timer on the boot CPU */
		msm_local_timer_setup(raw_cpu_ptr(msm_evt));
	}

err:
	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
	res = clocksource_register_hz(cs, dgt_hz);
	if (res)
		pr_err("clocksource_register failed\n");
	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
	msm_delay_timer.freq = dgt_hz;
	register_current_timer_delay(&msm_delay_timer);
}

#ifdef CONFIG_ARCH_QCOM
static void __init msm_dt_timer_init(struct device_node *np)
{
	u32 freq;
	int irq;
	struct resource res;
	u32 percpu_offset;
	void __iomem *base;
	void __iomem *cpu0_base;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("Failed to map event base\n");
		return;
	}

	/* We use GPT0 for the clockevent */
	irq = irq_of_parse_and_map(np, 1);
	if (irq <= 0) {
		pr_err("Can't get irq\n");
		return;
	}

	/* We use CPU0's DGT for the clocksource */
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	if (of_address_to_resource(np, 0, &res)) {
		pr_err("Failed to parse DGT resource\n");
		return;
	}

	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
	if (!cpu0_base) {
		pr_err("Failed to map source base\n");
		return;
	}

	if (of_property_read_u32(np, "clock-frequency", &freq)) {
		pr_err("Unknown frequency\n");
		return;
	}

	event_base = base + 0x4;
	sts_base = base + 0x88;
	source_base = cpu0_base + 0x24;
	freq /= 4;
	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);

	msm_timer_init(freq, 32, irq, !!percpu_offset);
}
CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
#else

static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
				u32 sts)
{
	void __iomem *base;

	base = ioremap(addr, SZ_256);
	if (!base) {
		pr_err("Failed to map timer base\n");
		return -ENOMEM;
	}
	event_base = base + event;
	source_base = base + source;
	if (sts)
		sts_base = base + sts;

	return 0;
}

static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
{
	/*
	 * Shift timer count down by a constant due to unreliable lower bits
	 * on some targets.
	 */
	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
}

void __init msm7x01_timer_init(void)
{
	struct clocksource *cs = &msm_clocksource;

	if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
		return;
	cs->read = msm_read_timer_count_shift;
	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	/* 600 KHz */
	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
			false);
}

void __init msm7x30_timer_init(void)
{
	if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
		return;
	msm_timer_init(24576000 / 4, 32, 1, false);
}

void __init qsd8x50_timer_init(void)
{
	if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
		return;
	msm_timer_init(19200000 / 4, 32, 7, false);
}
#endif
Commit	Line	Data
dd15ab81	1	/*
3e4ea372 AH	2	*
3e4ea372 AH	3	* Copyright (C) 2007 Google, Inc.
3f8e8cee	4	* Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
3e4ea372 AH	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
4a184075 SB	17	#include <linux/clocksource.h>
4a184075 SB	18	#include <linux/clockchips.h>
4d70c59b	19	#include <linux/cpu.h>
3e4ea372	20	#include <linux/init.h>
3e4ea372 AH	21	#include <linux/interrupt.h>
3e4ea372 AH	22	#include <linux/irq.h>
fced80c7	23	#include <linux/io.h>
6e332163 SB	24	#include <linux/of.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_irq.h>
38ff87f7	27	#include <linux/sched_clock.h>
3e4ea372	28
013be5ad SB	29	#include <asm/delay.h>
013be5ad SB	30
e25e3d1f SB	31	#define TIMER_MATCH_VAL 0x0000
	32	#define TIMER_COUNT_VAL 0x0004
	33	#define TIMER_ENABLE 0x0008
	34	#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
	35	#define TIMER_ENABLE_EN BIT(0)
	36	#define TIMER_CLEAR 0x000C
	37	#define DGT_CLK_CTL 0x10
	38	#define DGT_CLK_CTL_DIV_4 0x3
	39	#define TIMER_STS_GPT0_CLR_PEND BIT(10)
3e4ea372 AH	40
3e4ea372 AH	41	#define GPT_HZ 32768
672039f0	42
2081a6b5	43	#define MSM_DGT_SHIFT 5
3e4ea372	44
2a00c106	45	static void __iomem *event_base;
e25e3d1f	46	static void __iomem *sts_base;
a850c3f6	47
3e4ea372 AH	48	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
3e4ea372 AH	49	{
4d70c59b	50	struct clock_event_device *evt = dev_id;
a850c3f6 SB	51	/* Stop the timer tick */
a850c3f6 SB	52	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
2a00c106	53	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	54	ctrl &= ~TIMER_ENABLE_EN;
2a00c106	55	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
a850c3f6	56	}
3e4ea372 AH	57	evt->event_handler(evt);
	58	return IRQ_HANDLED;
	59	}
	60
3e4ea372 AH	61	static int msm_timer_set_next_event(unsigned long cycles,
	62	struct clock_event_device *evt)
	63	{
2a00c106	64	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
3e4ea372	65
4080d2d1 SB	66	ctrl &= ~TIMER_ENABLE_EN;
	67	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	68
	69	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
2a00c106	70	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
e25e3d1f SB	71
	72	if (sts_base)
	73	while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
	74	cpu_relax();
	75
2a00c106	76	writel_relaxed(ctrl \| TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
3e4ea372 AH	77	return 0;
	78	}
	79
	80	static void msm_timer_set_mode(enum clock_event_mode mode,
	81	struct clock_event_device *evt)
	82	{
a850c3f6 SB	83	u32 ctrl;
a850c3f6 SB	84
2a00c106	85	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	86	ctrl &= ~(TIMER_ENABLE_EN \| TIMER_ENABLE_CLR_ON_MATCH_EN);
94790ec2	87
3e4ea372 AH	88	switch (mode) {
	89	case CLOCK_EVT_MODE_RESUME:
	90	case CLOCK_EVT_MODE_PERIODIC:
	91	break;
	92	case CLOCK_EVT_MODE_ONESHOT:
a850c3f6	93	/* Timer is enabled in set_next_event */
3e4ea372 AH	94	break;
	95	case CLOCK_EVT_MODE_UNUSED:
	96	case CLOCK_EVT_MODE_SHUTDOWN:
3e4ea372 AH	97	break;
3e4ea372 AH	98	}
2a00c106	99	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
3e4ea372 AH	100	}
3e4ea372 AH	101
4d70c59b	102	static struct clock_event_device __percpu *msm_evt;
2a00c106 SB	103
	104	static void __iomem *source_base;
	105
f8e56c42	106	static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
2081a6b5 SB	107	{
	108	return readl_relaxed(source_base + TIMER_COUNT_VAL);
	109	}
	110
2a00c106 SB	111	static struct clocksource msm_clocksource = {
	112	.name = "dg_timer",
	113	.rating = 300,
	114	.read = msm_read_timer_count,
2081a6b5	115	.mask = CLOCKSOURCE_MASK(32),
2a00c106	116	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	117	};
3e4ea372 AH	118
4d70c59b SB	119	static int msm_timer_irq;
	120	static int msm_timer_has_ppi;
	121
8bd26e3a	122	static int msm_local_timer_setup(struct clock_event_device *evt)
5ca709c1	123	{
4d70c59b SB	124	int cpu = smp_processor_id();
	125	int err;
	126
	127	evt->irq = msm_timer_irq;
	128	evt->name = "msm_timer";
	129	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	130	evt->rating = 200;
5ca709c1 MZ	131	evt->set_mode = msm_timer_set_mode;
5ca709c1 MZ	132	evt->set_next_event = msm_timer_set_next_event;
4d70c59b SB	133	evt->cpumask = cpumask_of(cpu);
	134
	135	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
	136
	137	if (msm_timer_has_ppi) {
	138	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	139	} else {
	140	err = request_irq(evt->irq, msm_timer_interrupt,
	141	IRQF_TIMER \| IRQF_NOBALANCING \|
	142	IRQF_TRIGGER_RISING, "gp_timer", evt);
	143	if (err)
	144	pr_err("request_irq failed\n");
	145	}
5ca709c1	146
5ca709c1 MZ	147	return 0;
	148	}
	149
	150	static void msm_local_timer_stop(struct clock_event_device *evt)
	151	{
	152	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	153	disable_percpu_irq(evt->irq);
	154	}
	155
47dcd356	156	static int msm_timer_cpu_notify(struct notifier_block *self,
4d70c59b SB	157	unsigned long action, void *hcpu)
	158	{
	159	/*
	160	* Grab cpu pointer in each case to avoid spurious
	161	* preemptible warnings
	162	*/
	163	switch (action & ~CPU_TASKS_FROZEN) {
	164	case CPU_STARTING:
	165	msm_local_timer_setup(this_cpu_ptr(msm_evt));
	166	break;
	167	case CPU_DYING:
	168	msm_local_timer_stop(this_cpu_ptr(msm_evt));
	169	break;
	170	}
	171
	172	return NOTIFY_OK;
	173	}
	174
47dcd356	175	static struct notifier_block msm_timer_cpu_nb = {
4d70c59b	176	.notifier_call = msm_timer_cpu_notify,
5ca709c1	177	};
5ca709c1	178
6aa16a26	179	static u64 notrace msm_sched_clock_read(void)
f8e56c42 SB	180	{
	181	return msm_clocksource.read(&msm_clocksource);
	182	}
	183
013be5ad SB	184	static unsigned long msm_read_current_timer(void)
	185	{
	186	return msm_clocksource.read(&msm_clocksource);
	187	}
	188
	189	static struct delay_timer msm_delay_timer = {
	190	.read_current_timer = msm_read_current_timer,
	191	};
	192
4312a7ef SB	193	static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
4312a7ef SB	194	bool percpu)
3e4ea372	195	{
2a00c106	196	struct clocksource *cs = &msm_clocksource;
4d70c59b SB	197	int res = 0;
	198
	199	msm_timer_irq = irq;
	200	msm_timer_has_ppi = percpu;
	201
	202	msm_evt = alloc_percpu(struct clock_event_device);
	203	if (!msm_evt) {
	204	pr_err("memory allocation failed for clockevents\n");
	205	goto err;
	206	}
3e4ea372	207
4d70c59b SB	208	if (percpu)
	209	res = request_percpu_irq(irq, msm_timer_interrupt,
	210	"gp_timer", msm_evt);
dd15ab81	211
4d70c59b SB	212	if (res) {
	213	pr_err("request_percpu_irq failed\n");
	214	} else {
	215	res = register_cpu_notifier(&msm_timer_cpu_nb);
	216	if (res) {
	217	free_percpu_irq(irq, msm_evt);
dd15ab81	218	goto err;
28af690a	219	}
4d70c59b SB	220
4d70c59b SB	221	/* Immediately configure the timer on the boot CPU */
77422a8f	222	msm_local_timer_setup(raw_cpu_ptr(msm_evt));
3e4ea372	223	}
dd15ab81	224
dd15ab81	225	err:
2a00c106	226	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
2081a6b5	227	res = clocksource_register_hz(cs, dgt_hz);
dd15ab81	228	if (res)
2a00c106	229	pr_err("clocksource_register failed\n");
6aa16a26	230	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
013be5ad SB	231	msm_delay_timer.freq = dgt_hz;
013be5ad SB	232	register_current_timer_delay(&msm_delay_timer);
3e4ea372 AH	233	}
3e4ea372 AH	234
7d6d45f8	235	#ifdef CONFIG_ARCH_QCOM
c602520f	236	static void __init msm_dt_timer_init(struct device_node *np)
6e332163	237	{
6e332163 SB	238	u32 freq;
	239	int irq;
	240	struct resource res;
	241	u32 percpu_offset;
eebdb0c1 SB	242	void __iomem *base;
eebdb0c1 SB	243	void __iomem *cpu0_base;
6e332163	244
eebdb0c1 SB	245	base = of_iomap(np, 0);
eebdb0c1 SB	246	if (!base) {
6e332163 SB	247	pr_err("Failed to map event base\n");
	248	return;
	249	}
	250
eebdb0c1 SB	251	/* We use GPT0 for the clockevent */
eebdb0c1 SB	252	irq = irq_of_parse_and_map(np, 1);
6e332163 SB	253	if (irq <= 0) {
	254	pr_err("Can't get irq\n");
	255	return;
	256	}
6e332163	257
eebdb0c1	258	/* We use CPU0's DGT for the clocksource */
6e332163 SB	259	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	260	percpu_offset = 0;
	261
	262	if (of_address_to_resource(np, 0, &res)) {
	263	pr_err("Failed to parse DGT resource\n");
	264	return;
	265	}
	266
eebdb0c1 SB	267	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
eebdb0c1 SB	268	if (!cpu0_base) {
6e332163 SB	269	pr_err("Failed to map source base\n");
	270	return;
	271	}
	272
6e332163 SB	273	if (of_property_read_u32(np, "clock-frequency", &freq)) {
	274	pr_err("Unknown frequency\n");
	275	return;
	276	}
6e332163	277
eebdb0c1	278	event_base = base + 0x4;
e25e3d1f	279	sts_base = base + 0x88;
eebdb0c1 SB	280	source_base = cpu0_base + 0x24;
	281	freq /= 4;
	282	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
	283
6e332163 SB	284	msm_timer_init(freq, 32, irq, !!percpu_offset);
6e332163 SB	285	}
c602520f SB	286	CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
c602520f SB	287	CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
7d6d45f8	288	#else
6e332163	289
e25e3d1f SB	290	static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
e25e3d1f SB	291	u32 sts)
4312a7ef	292	{
eebdb0c1 SB	293	void __iomem *base;
	294
	295	base = ioremap(addr, SZ_256);
	296	if (!base) {
	297	pr_err("Failed to map timer base\n");
	298	return -ENOMEM;
4312a7ef	299	}
eebdb0c1 SB	300	event_base = base + event;
eebdb0c1 SB	301	source_base = base + source;
e25e3d1f SB	302	if (sts)
e25e3d1f SB	303	sts_base = base + sts;
eebdb0c1	304
4312a7ef SB	305	return 0;
	306	}
	307
7d6d45f8 KG	308	static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
	309	{
	310	/*
	311	* Shift timer count down by a constant due to unreliable lower bits
	312	* on some targets.
	313	*/
	314	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
	315	}
	316
6bb27d73	317	void __init msm7x01_timer_init(void)
4312a7ef SB	318	{
	319	struct clocksource *cs = &msm_clocksource;
	320
e25e3d1f	321	if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
4312a7ef SB	322	return;
	323	cs->read = msm_read_timer_count_shift;
	324	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	325	/* 600 KHz */
	326	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
	327	false);
	328	}
	329
6bb27d73	330	void __init msm7x30_timer_init(void)
4312a7ef	331	{
e25e3d1f	332	if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
4312a7ef SB	333	return;
	334	msm_timer_init(24576000 / 4, 32, 1, false);
	335	}
	336
6bb27d73	337	void __init qsd8x50_timer_init(void)
4312a7ef	338	{
e25e3d1f	339	if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
4312a7ef SB	340	return;
	341	msm_timer_init(19200000 / 4, 32, 7, false);
	342	}
7d6d45f8	343	#endif