[linux-2.6-block.git] / drivers / clocksource / mtk_timer.c

/*
 * Mediatek SoCs General-Purpose Timer handling.
 *
 * Copyright (C) 2014 Matthias Brugger
 *
 * Matthias Brugger <matthias.bgg@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>

#define GPT_IRQ_EN_REG		0x00
#define GPT_IRQ_ENABLE(val)	BIT((val) - 1)
#define GPT_IRQ_ACK_REG		0x08
#define GPT_IRQ_ACK(val)	BIT((val) - 1)

#define TIMER_CTRL_REG(val)	(0x10 * (val))
#define TIMER_CTRL_OP(val)	(((val) & 0x3) << 4)
#define TIMER_CTRL_OP_ONESHOT	(0)
#define TIMER_CTRL_OP_REPEAT	(1)
#define TIMER_CTRL_OP_FREERUN	(3)
#define TIMER_CTRL_CLEAR	(2)
#define TIMER_CTRL_ENABLE	(1)
#define TIMER_CTRL_DISABLE	(0)

#define TIMER_CLK_REG(val)	(0x04 + (0x10 * (val)))
#define TIMER_CLK_SRC(val)	(((val) & 0x1) << 4)
#define TIMER_CLK_SRC_SYS13M	(0)
#define TIMER_CLK_SRC_RTC32K	(1)
#define TIMER_CLK_DIV1		(0x0)
#define TIMER_CLK_DIV2		(0x1)

#define TIMER_CNT_REG(val)	(0x08 + (0x10 * (val)))
#define TIMER_CMP_REG(val)	(0x0C + (0x10 * (val)))

#define GPT_CLK_EVT	1
#define GPT_CLK_SRC	2

struct mtk_clock_event_device {
	void __iomem *gpt_base;
	u32 ticks_per_jiffy;
	struct clock_event_device dev;
};

static inline struct mtk_clock_event_device *to_mtk_clk(
				struct clock_event_device *c)
{
	return container_of(c, struct mtk_clock_event_device, dev);
}

static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
{
	u32 val;

	val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
	writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
			TIMER_CTRL_REG(timer));
}

static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
				unsigned long delay, u8 timer)
{
	writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
}

static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
		bool periodic, u8 timer)
{
	u32 val;

	/* Acknowledge interrupt */
	writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);

	val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));

	/* Clear 2 bit timer operation mode field */
	val &= ~TIMER_CTRL_OP(0x3);

	if (periodic)
		val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
	else
		val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);

	writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
	       evt->gpt_base + TIMER_CTRL_REG(timer));
}

static int mtk_clkevt_shutdown(struct clock_event_device *clk)
{
	mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT);
	return 0;
}

static int mtk_clkevt_set_periodic(struct clock_event_device *clk)
{
	struct mtk_clock_event_device *evt = to_mtk_clk(clk);

	mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
	mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
	mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
	return 0;
}

static int mtk_clkevt_next_event(unsigned long event,
				   struct clock_event_device *clk)
{
	struct mtk_clock_event_device *evt = to_mtk_clk(clk);

	mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
	mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
	mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);

	return 0;
}

static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
{
	struct mtk_clock_event_device *evt = dev_id;

	/* Acknowledge timer0 irq */
	writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
	evt->dev.event_handler(&evt->dev);

	return IRQ_HANDLED;
}

static void mtk_timer_global_reset(struct mtk_clock_event_device *evt)
{
	/* Disable all interrupts */
	writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
	/* Acknowledge all interrupts */
	writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
}

static void
mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
{
	writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
		evt->gpt_base + TIMER_CTRL_REG(timer));

	writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
			evt->gpt_base + TIMER_CLK_REG(timer));

	writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));

	writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
			evt->gpt_base + TIMER_CTRL_REG(timer));
}

static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
{
	u32 val;

	val = readl(evt->gpt_base + GPT_IRQ_EN_REG);
	writel(val | GPT_IRQ_ENABLE(timer),
			evt->gpt_base + GPT_IRQ_EN_REG);
}

static void __init mtk_timer_init(struct device_node *node)
{
	struct mtk_clock_event_device *evt;
	struct resource res;
	unsigned long rate = 0;
	struct clk *clk;

	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
	if (!evt) {
		pr_warn("Can't allocate mtk clock event driver struct");
		return;
	}

	evt->dev.name = "mtk_tick";
	evt->dev.rating = 300;
	evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	evt->dev.set_state_shutdown = mtk_clkevt_shutdown;
	evt->dev.set_state_periodic = mtk_clkevt_set_periodic;
	evt->dev.set_state_oneshot = mtk_clkevt_shutdown;
	evt->dev.tick_resume = mtk_clkevt_shutdown;
	evt->dev.set_next_event = mtk_clkevt_next_event;
	evt->dev.cpumask = cpu_possible_mask;

	evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer");
	if (IS_ERR(evt->gpt_base)) {
		pr_warn("Can't get resource\n");
		return;
	}

	evt->dev.irq = irq_of_parse_and_map(node, 0);
	if (evt->dev.irq <= 0) {
		pr_warn("Can't parse IRQ");
		goto err_mem;
	}

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_warn("Can't get timer clock");
		goto err_irq;
	}

	if (clk_prepare_enable(clk)) {
		pr_warn("Can't prepare clock");
		goto err_clk_put;
	}
	rate = clk_get_rate(clk);

	mtk_timer_global_reset(evt);

	if (request_irq(evt->dev.irq, mtk_timer_interrupt,
			IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
		pr_warn("failed to setup irq %d\n", evt->dev.irq);
		goto err_clk_disable;
	}

	evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);

	/* Configure clock source */
	mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
	clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
			node->name, rate, 300, 32, clocksource_mmio_readl_up);

	/* Configure clock event */
	mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
	clockevents_config_and_register(&evt->dev, rate, 0x3,
					0xffffffff);

	mtk_timer_enable_irq(evt, GPT_CLK_EVT);

	return;

err_clk_disable:
	clk_disable_unprepare(clk);
err_clk_put:
	clk_put(clk);
err_irq:
	irq_dispose_mapping(evt->dev.irq);
err_mem:
	iounmap(evt->gpt_base);
	of_address_to_resource(node, 0, &res);
	release_mem_region(res.start, resource_size(&res));
}
CLOCKSOURCE_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);
Commit	Line	Data
ecb3530d MB	1	/*
	2	* Mediatek SoCs General-Purpose Timer handling.
	3	*
	4	* Copyright (C) 2014 Matthias Brugger
	5	*
	6	* Matthias Brugger <matthias.bgg@gmail.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <linux/clk.h>
	20	#include <linux/clockchips.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/irq.h>
	23	#include <linux/irqreturn.h>
	24	#include <linux/of.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_irq.h>
	27	#include <linux/slab.h>
	28
	29	#define GPT_IRQ_EN_REG 0x00
	30	#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
	31	#define GPT_IRQ_ACK_REG 0x08
	32	#define GPT_IRQ_ACK(val) BIT((val) - 1)
	33
	34	#define TIMER_CTRL_REG(val) (0x10 * (val))
	35	#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4)
	36	#define TIMER_CTRL_OP_ONESHOT (0)
	37	#define TIMER_CTRL_OP_REPEAT (1)
	38	#define TIMER_CTRL_OP_FREERUN (3)
	39	#define TIMER_CTRL_CLEAR (2)
	40	#define TIMER_CTRL_ENABLE (1)
	41	#define TIMER_CTRL_DISABLE (0)
	42
	43	#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val)))
	44	#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4)
	45	#define TIMER_CLK_SRC_SYS13M (0)
	46	#define TIMER_CLK_SRC_RTC32K (1)
	47	#define TIMER_CLK_DIV1 (0x0)
	48	#define TIMER_CLK_DIV2 (0x1)
	49
	50	#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val)))
	51	#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val)))
	52
	53	#define GPT_CLK_EVT 1
	54	#define GPT_CLK_SRC 2
	55
	56	struct mtk_clock_event_device {
	57	void __iomem *gpt_base;
	58	u32 ticks_per_jiffy;
	59	struct clock_event_device dev;
	60	};
	61
	62	static inline struct mtk_clock_event_device *to_mtk_clk(
	63	struct clock_event_device *c)
	64	{
65	return container_of(c, struct mtk_clock_event_device, dev);
66	}
67
68	static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
69	{
70	u32 val;
71
72	val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
73	writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
74	TIMER_CTRL_REG(timer));
75	}
76
77	static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
78	unsigned long delay, u8 timer)
79	{
80	writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
81	}
82
83	static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
84	bool periodic, u8 timer)
85	{
86	u32 val;
87
88	/* Acknowledge interrupt */
89	writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
90
91	val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
92
93	/* Clear 2 bit timer operation mode field */
94	val &= ~TIMER_CTRL_OP(0x3);
95
96	if (periodic)
97	val \|= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
98	else
99	val \|= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
100
101	writel(val \| TIMER_CTRL_ENABLE \| TIMER_CTRL_CLEAR,
102	evt->gpt_base + TIMER_CTRL_REG(timer));
103	}
104
a2b7e10d VK	105	static int mtk_clkevt_shutdown(struct clock_event_device *clk)
	106	{
	107	mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT);
	108	return 0;
	109	}
	110
	111	static int mtk_clkevt_set_periodic(struct clock_event_device *clk)
ecb3530d MB	112	{
	113	struct mtk_clock_event_device *evt = to_mtk_clk(clk);
	114
	115	mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
a2b7e10d VK	116	mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
	117	mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
	118	return 0;
ecb3530d MB	119	}
	120
	121	static int mtk_clkevt_next_event(unsigned long event,
	122	struct clock_event_device *clk)
	123	{
	124	struct mtk_clock_event_device *evt = to_mtk_clk(clk);
	125
	126	mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
	127	mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
	128	mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
	129
	130	return 0;
	131	}
	132
	133	static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
	134	{
	135	struct mtk_clock_event_device *evt = dev_id;
	136
	137	/* Acknowledge timer0 irq */
	138	writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
	139	evt->dev.event_handler(&evt->dev);
	140
	141	return IRQ_HANDLED;
	142	}
	143
	144	static void mtk_timer_global_reset(struct mtk_clock_event_device *evt)
	145	{
	146	/* Disable all interrupts */
	147	writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
	148	/* Acknowledge all interrupts */
	149	writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
	150	}
	151
	152	static void
	153	mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
	154	{
	155	writel(TIMER_CTRL_CLEAR \| TIMER_CTRL_DISABLE,
	156	evt->gpt_base + TIMER_CTRL_REG(timer));
	157
	158	writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) \| TIMER_CLK_DIV1,
	159	evt->gpt_base + TIMER_CLK_REG(timer));
	160
	161	writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
	162
	163	writel(TIMER_CTRL_OP(option) \| TIMER_CTRL_ENABLE,
	164	evt->gpt_base + TIMER_CTRL_REG(timer));
	165	}
	166
	167	static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
	168	{
	169	u32 val;
	170
	171	val = readl(evt->gpt_base + GPT_IRQ_EN_REG);
	172	writel(val \| GPT_IRQ_ENABLE(timer),
	173	evt->gpt_base + GPT_IRQ_EN_REG);
	174	}
	175
	176	static void __init mtk_timer_init(struct device_node *node)
	177	{
	178	struct mtk_clock_event_device *evt;
	179	struct resource res;
	180	unsigned long rate = 0;
	181	struct clk *clk;
	182
183	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
184	if (!evt) {
185	pr_warn("Can't allocate mtk clock event driver struct");
186	return;
187	}
188
189	evt->dev.name = "mtk_tick";
190	evt->dev.rating = 300;
191	evt->dev.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
a2b7e10d VK	192	evt->dev.set_state_shutdown = mtk_clkevt_shutdown;
	193	evt->dev.set_state_periodic = mtk_clkevt_set_periodic;
	194	evt->dev.set_state_oneshot = mtk_clkevt_shutdown;
	195	evt->dev.tick_resume = mtk_clkevt_shutdown;
ecb3530d MB	196	evt->dev.set_next_event = mtk_clkevt_next_event;
	197	evt->dev.cpumask = cpu_possible_mask;
	198
	199	evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer");
	200	if (IS_ERR(evt->gpt_base)) {
	201	pr_warn("Can't get resource\n");
	202	return;
	203	}
	204
	205	evt->dev.irq = irq_of_parse_and_map(node, 0);
	206	if (evt->dev.irq <= 0) {
	207	pr_warn("Can't parse IRQ");
	208	goto err_mem;
	209	}
	210
	211	clk = of_clk_get(node, 0);
	212	if (IS_ERR(clk)) {
	213	pr_warn("Can't get timer clock");
	214	goto err_irq;
	215	}
	216
	217	if (clk_prepare_enable(clk)) {
	218	pr_warn("Can't prepare clock");
	219	goto err_clk_put;
	220	}
	221	rate = clk_get_rate(clk);
	222
d4a19eb3 MB	223	mtk_timer_global_reset(evt);
d4a19eb3 MB	224
ecb3530d MB	225	if (request_irq(evt->dev.irq, mtk_timer_interrupt,
	226	IRQF_TIMER \| IRQF_IRQPOLL, "mtk_timer", evt)) {
	227	pr_warn("failed to setup irq %d\n", evt->dev.irq);
	228	goto err_clk_disable;
	229	}
	230
	231	evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
	232
ecb3530d MB	233	/* Configure clock source */
	234	mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
	235	clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
	236	node->name, rate, 300, 32, clocksource_mmio_readl_up);
	237
	238	/* Configure clock event */
	239	mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
ecb3530d MB	240	clockevents_config_and_register(&evt->dev, rate, 0x3,
ecb3530d MB	241	0xffffffff);
d4a19eb3 MB	242
	243	mtk_timer_enable_irq(evt, GPT_CLK_EVT);
	244
ecb3530d MB	245	return;
	246
	247	err_clk_disable:
	248	clk_disable_unprepare(clk);
	249	err_clk_put:
	250	clk_put(clk);
	251	err_irq:
	252	irq_dispose_mapping(evt->dev.irq);
	253	err_mem:
	254	iounmap(evt->gpt_base);
	255	of_address_to_resource(node, 0, &res);
	256	release_mem_region(res.start, resource_size(&res));
	257	}
	258	CLOCKSOURCE_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);