[linux-2.6-block.git] / drivers / clocksource / mips-gic-timer.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irqchip/mips-gic.h>
#include <linux/notifier.h>
#include <linux/of_irq.h>
#include <linux/percpu.h>
#include <linux/smp.h>
#include <linux/time.h>

static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
static int gic_timer_irq;
static unsigned int gic_frequency;

static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
{
	u64 cnt;
	int res;

	cnt = gic_read_count();
	cnt += (u64)delta;
	gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
	res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
	return res;
}

static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *cd = dev_id;

	gic_write_compare(gic_read_compare());
	cd->event_handler(cd);
	return IRQ_HANDLED;
}

struct irqaction gic_compare_irqaction = {
	.handler = gic_compare_interrupt,
	.percpu_dev_id = &gic_clockevent_device,
	.flags = IRQF_PERCPU | IRQF_TIMER,
	.name = "timer",
};

static void gic_clockevent_cpu_init(struct clock_event_device *cd)
{
	unsigned int cpu = smp_processor_id();

	cd->name		= "MIPS GIC";
	cd->features		= CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_C3STOP;

	cd->rating		= 350;
	cd->irq			= gic_timer_irq;
	cd->cpumask		= cpumask_of(cpu);
	cd->set_next_event	= gic_next_event;

	clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);

	enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
}

static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
{
	disable_percpu_irq(gic_timer_irq);
}

static void gic_update_frequency(void *data)
{
	unsigned long rate = (unsigned long)data;

	clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate);
}

static int gic_cpu_notifier(struct notifier_block *nb, unsigned long action,
				void *data)
{
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
		break;
	case CPU_DYING:
		gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
		break;
	}

	return NOTIFY_OK;
}

static int gic_clk_notifier(struct notifier_block *nb, unsigned long action,
			    void *data)
{
	struct clk_notifier_data *cnd = data;

	if (action == POST_RATE_CHANGE)
		on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);

	return NOTIFY_OK;
}


static struct notifier_block gic_cpu_nb = {
	.notifier_call = gic_cpu_notifier,
};

static struct notifier_block gic_clk_nb = {
	.notifier_call = gic_clk_notifier,
};

static int gic_clockevent_init(void)
{
	int ret;

	if (!cpu_has_counter || !gic_frequency)
		return -ENXIO;

	ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
	if (ret < 0)
		return ret;

	ret = register_cpu_notifier(&gic_cpu_nb);
	if (ret < 0)
		pr_warn("GIC: Unable to register CPU notifier\n");

	gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));

	return 0;
}

static cycle_t gic_hpt_read(struct clocksource *cs)
{
	return gic_read_count();
}

static struct clocksource gic_clocksource = {
	.name		= "GIC",
	.read		= gic_hpt_read,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.archdata	= { .vdso_clock_mode = VDSO_CLOCK_GIC },
};

static void __init __gic_clocksource_init(void)
{
	int ret;

	/* Set clocksource mask. */
	gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());

	/* Calculate a somewhat reasonable rating value. */
	gic_clocksource.rating = 200 + gic_frequency / 10000000;

	ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
	if (ret < 0)
		pr_warn("GIC: Unable to register clocksource\n");
}

void __init gic_clocksource_init(unsigned int frequency)
{
	gic_frequency = frequency;
	gic_timer_irq = MIPS_GIC_IRQ_BASE +
		GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);

	__gic_clocksource_init();
	gic_clockevent_init();

	/* And finally start the counter */
	gic_start_count();
}

static void __init gic_clocksource_of_init(struct device_node *node)
{
	struct clk *clk;
	int ret;

	if (WARN_ON(!gic_present || !node->parent ||
		    !of_device_is_compatible(node->parent, "mti,gic")))
		return;

	clk = of_clk_get(node, 0);
	if (!IS_ERR(clk)) {
		if (clk_prepare_enable(clk) < 0) {
			pr_err("GIC failed to enable clock\n");
			clk_put(clk);
			return;
		}

		gic_frequency = clk_get_rate(clk);
	} else if (of_property_read_u32(node, "clock-frequency",
					&gic_frequency)) {
		pr_err("GIC frequency not specified.\n");
		return;
	}
	gic_timer_irq = irq_of_parse_and_map(node, 0);
	if (!gic_timer_irq) {
		pr_err("GIC timer IRQ not specified.\n");
		return;
	}

	__gic_clocksource_init();

	ret = gic_clockevent_init();
	if (!ret && !IS_ERR(clk)) {
		if (clk_notifier_register(clk, &gic_clk_nb) < 0)
			pr_warn("GIC: Unable to register clock notifier\n");
	}

	/* And finally start the counter */
	gic_start_count();
}
CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
		       gic_clocksource_of_init);
Commit	Line	Data
778eeb1b SH	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
	7	*/
5b4e8453	8	#include <linux/clk.h>
a331ce63	9	#include <linux/clockchips.h>
e4752dbb	10	#include <linux/cpu.h>
778eeb1b	11	#include <linux/init.h>
a331ce63	12	#include <linux/interrupt.h>
4060bbe9	13	#include <linux/irqchip/mips-gic.h>
e4752dbb	14	#include <linux/notifier.h>
e12aa828	15	#include <linux/of_irq.h>
a331ce63 AB	16	#include <linux/percpu.h>
a331ce63 AB	17	#include <linux/smp.h>
dfa762e1	18	#include <linux/time.h>
778eeb1b	19
5fee56e0	20	static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
e4752dbb	21	static int gic_timer_irq;
b0854514	22	static unsigned int gic_frequency;
a331ce63 AB	23
	24	static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
	25	{
	26	u64 cnt;
	27	int res;
	28
	29	cnt = gic_read_count();
	30	cnt += (u64)delta;
	31	gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
	32	res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
	33	return res;
	34	}
	35
5fee56e0	36	static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
a331ce63	37	{
f7ea3060	38	struct clock_event_device *cd = dev_id;
a331ce63 AB	39
a331ce63 AB	40	gic_write_compare(gic_read_compare());
a331ce63 AB	41	cd->event_handler(cd);
	42	return IRQ_HANDLED;
	43	}
	44
	45	struct irqaction gic_compare_irqaction = {
	46	.handler = gic_compare_interrupt,
f7ea3060	47	.percpu_dev_id = &gic_clockevent_device,
a331ce63 AB	48	.flags = IRQF_PERCPU \| IRQF_TIMER,
	49	.name = "timer",
	50	};
	51
e4752dbb	52	static void gic_clockevent_cpu_init(struct clock_event_device *cd)
a331ce63 AB	53	{
a331ce63 AB	54	unsigned int cpu = smp_processor_id();
a331ce63 AB	55
	56	cd->name = "MIPS GIC";
	57	cd->features = CLOCK_EVT_FEAT_ONESHOT \|
	58	CLOCK_EVT_FEAT_C3STOP;
	59
a45da565	60	cd->rating = 350;
e4752dbb	61	cd->irq = gic_timer_irq;
a331ce63 AB	62	cd->cpumask = cpumask_of(cpu);
a331ce63 AB	63	cd->set_next_event = gic_next_event;
a331ce63	64
b695d8e6	65	clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
a331ce63	66
e4752dbb AB	67	enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
	68	}
	69
	70	static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
	71	{
	72	disable_percpu_irq(gic_timer_irq);
	73	}
	74
fc6a6772 EG	75	static void gic_update_frequency(void *data)
	76	{
	77	unsigned long rate = (unsigned long)data;
	78
	79	clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate);
	80	}
	81
e4752dbb AB	82	static int gic_cpu_notifier(struct notifier_block *nb, unsigned long action,
	83	void *data)
	84	{
	85	switch (action & ~CPU_TASKS_FROZEN) {
	86	case CPU_STARTING:
	87	gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
	88	break;
	89	case CPU_DYING:
	90	gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
	91	break;
a331ce63 AB	92	}
a331ce63 AB	93
e4752dbb AB	94	return NOTIFY_OK;
	95	}
	96
fc6a6772 EG	97	static int gic_clk_notifier(struct notifier_block *nb, unsigned long action,
	98	void *data)
	99	{
	100	struct clk_notifier_data *cnd = data;
	101
	102	if (action == POST_RATE_CHANGE)
	103	on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);
	104
	105	return NOTIFY_OK;
	106	}
	107
	108
e4752dbb AB	109	static struct notifier_block gic_cpu_nb = {
	110	.notifier_call = gic_cpu_notifier,
	111	};
	112
fc6a6772 EG	113	static struct notifier_block gic_clk_nb = {
	114	.notifier_call = gic_clk_notifier,
	115	};
	116
e4752dbb AB	117	static int gic_clockevent_init(void)
e4752dbb AB	118	{
f95ac855 EG	119	int ret;
f95ac855 EG	120
e4752dbb AB	121	if (!cpu_has_counter \|\| !gic_frequency)
	122	return -ENXIO;
	123
f95ac855 EG	124	ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
	125	if (ret < 0)
	126	return ret;
e4752dbb	127
f95ac855 EG	128	ret = register_cpu_notifier(&gic_cpu_nb);
	129	if (ret < 0)
	130	pr_warn("GIC: Unable to register CPU notifier\n");
e4752dbb AB	131
e4752dbb AB	132	gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
a331ce63 AB	133
	134	return 0;
	135	}
	136
778eeb1b SH	137	static cycle_t gic_hpt_read(struct clocksource *cs)
778eeb1b SH	138	{
dfa762e1	139	return gic_read_count();
778eeb1b SH	140	}
	141
	142	static struct clocksource gic_clocksource = {
a7f4df4e AS	143	.name = "GIC",
	144	.read = gic_hpt_read,
	145	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	146	.archdata = { .vdso_clock_mode = VDSO_CLOCK_GIC },
778eeb1b SH	147	};
778eeb1b SH	148
e12aa828	149	static void __init __gic_clocksource_init(void)
778eeb1b	150	{
f95ac855 EG	151	int ret;
f95ac855 EG	152
778eeb1b	153	/* Set clocksource mask. */
387904ff	154	gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
778eeb1b SH	155
778eeb1b SH	156	/* Calculate a somewhat reasonable rating value. */
e12aa828	157	gic_clocksource.rating = 200 + gic_frequency / 10000000;
778eeb1b	158
f95ac855 EG	159	ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
	160	if (ret < 0)
	161	pr_warn("GIC: Unable to register clocksource\n");
778eeb1b	162	}
e12aa828 AB	163
	164	void __init gic_clocksource_init(unsigned int frequency)
	165	{
	166	gic_frequency = frequency;
	167	gic_timer_irq = MIPS_GIC_IRQ_BASE +
	168	GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
	169
	170	__gic_clocksource_init();
67d4e669 EG	171	gic_clockevent_init();
	172
	173	/* And finally start the counter */
	174	gic_start_count();
e12aa828 AB	175	}
	176
	177	static void __init gic_clocksource_of_init(struct device_node *node)
	178	{
5b4e8453	179	struct clk *clk;
fc6a6772	180	int ret;
5b4e8453	181
e12aa828 AB	182	if (WARN_ON(!gic_present \|\| !node->parent \|\|
	183	!of_device_is_compatible(node->parent, "mti,gic")))
	184	return;
	185
5b4e8453 AB	186	clk = of_clk_get(node, 0);
5b4e8453 AB	187	if (!IS_ERR(clk)) {
eb811c73 EG	188	if (clk_prepare_enable(clk) < 0) {
	189	pr_err("GIC failed to enable clock\n");
	190	clk_put(clk);
	191	return;
	192	}
	193
5b4e8453	194	gic_frequency = clk_get_rate(clk);
5b4e8453 AB	195	} else if (of_property_read_u32(node, "clock-frequency",
5b4e8453 AB	196	&gic_frequency)) {
e12aa828 AB	197	pr_err("GIC frequency not specified.\n");
	198	return;
	199	}
	200	gic_timer_irq = irq_of_parse_and_map(node, 0);
	201	if (!gic_timer_irq) {
	202	pr_err("GIC timer IRQ not specified.\n");
	203	return;
	204	}
	205
	206	__gic_clocksource_init();
fc6a6772 EG	207
	208	ret = gic_clockevent_init();
	209	if (!ret && !IS_ERR(clk)) {
	210	if (clk_notifier_register(clk, &gic_clk_nb) < 0)
	211	pr_warn("GIC: Unable to register clock notifier\n");
	212	}
67d4e669 EG	213
	214	/* And finally start the counter */
	215	gic_start_count();
e12aa828 AB	216	}
	217	CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
	218	gic_clocksource_of_init);