[linux-2.6-block.git] / drivers / clocksource / h8300_tpu.c

/*
 *  H8/300 TPU Driver
 *
 *  Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
 *
 */

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/clocksource.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>

#include <asm/irq.h>

#define TCR	0
#define TMDR	1
#define TIOR	2
#define TER	4
#define TSR	5
#define TCNT	6
#define TGRA	8
#define TGRB	10
#define TGRC	12
#define TGRD	14

struct tpu_priv {
	struct platform_device *pdev;
	struct clocksource cs;
	struct clk *clk;
	unsigned long mapbase1;
	unsigned long mapbase2;
	raw_spinlock_t lock;
	unsigned int cs_enabled;
};

static inline unsigned long read_tcnt32(struct tpu_priv *p)
{
	unsigned long tcnt;

	tcnt = ctrl_inw(p->mapbase1 + TCNT) << 16;
	tcnt |= ctrl_inw(p->mapbase2 + TCNT);
	return tcnt;
}

static int tpu_get_counter(struct tpu_priv *p, unsigned long long *val)
{
	unsigned long v1, v2, v3;
	int o1, o2;

	o1 = ctrl_inb(p->mapbase1 + TSR) & 0x10;

	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	do {
		o2 = o1;
		v1 = read_tcnt32(p);
		v2 = read_tcnt32(p);
		v3 = read_tcnt32(p);
		o1 = ctrl_inb(p->mapbase1 + TSR) & 0x10;
	} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
			  || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));

	*val = v2;
	return o1;
}

static inline struct tpu_priv *cs_to_priv(struct clocksource *cs)
{
	return container_of(cs, struct tpu_priv, cs);
}

static cycle_t tpu_clocksource_read(struct clocksource *cs)
{
	struct tpu_priv *p = cs_to_priv(cs);
	unsigned long flags;
	unsigned long long value;

	raw_spin_lock_irqsave(&p->lock, flags);
	if (tpu_get_counter(p, &value))
		value += 0x100000000;
	raw_spin_unlock_irqrestore(&p->lock, flags);

	return value;
}

static int tpu_clocksource_enable(struct clocksource *cs)
{
	struct tpu_priv *p = cs_to_priv(cs);

	WARN_ON(p->cs_enabled);

	ctrl_outw(0, p->mapbase1 + TCNT);
	ctrl_outw(0, p->mapbase2 + TCNT);
	ctrl_outb(0x0f, p->mapbase1 + TCR);
	ctrl_outb(0x03, p->mapbase2 + TCR);

	p->cs_enabled = true;
	return 0;
}

static void tpu_clocksource_disable(struct clocksource *cs)
{
	struct tpu_priv *p = cs_to_priv(cs);

	WARN_ON(!p->cs_enabled);

	ctrl_outb(0, p->mapbase1 + TCR);
	ctrl_outb(0, p->mapbase2 + TCR);
	p->cs_enabled = false;
}

#define CH_L 0
#define CH_H 1

static int __init tpu_setup(struct tpu_priv *p, struct platform_device *pdev)
{
	struct resource *res[2];

	p->pdev = pdev;

	res[CH_L] = platform_get_resource(p->pdev, IORESOURCE_MEM, CH_L);
	res[CH_H] = platform_get_resource(p->pdev, IORESOURCE_MEM, CH_H);
	if (!res[CH_L] || !res[CH_H]) {
		dev_err(&p->pdev->dev, "failed to get I/O memory\n");
		return -ENXIO;
	}

	p->clk = clk_get(&p->pdev->dev, "fck");
	if (IS_ERR(p->clk)) {
		dev_err(&p->pdev->dev, "can't get clk\n");
		return PTR_ERR(p->clk);
	}

	p->mapbase1 = res[CH_L]->start;
	p->mapbase2 = res[CH_H]->start;

	p->cs.name = pdev->name;
	p->cs.rating = 200;
	p->cs.read = tpu_clocksource_read;
	p->cs.enable = tpu_clocksource_enable;
	p->cs.disable = tpu_clocksource_disable;
	p->cs.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
	p->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	clocksource_register_hz(&p->cs, clk_get_rate(p->clk) / 64);
	platform_set_drvdata(pdev, p);

	return 0;
}

static int tpu_probe(struct platform_device *pdev)
{
	struct tpu_priv *p = platform_get_drvdata(pdev);

	if (p) {
		dev_info(&pdev->dev, "kept as earlytimer\n");
		return 0;
	}

	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
	if (!p)
		return -ENOMEM;

	return tpu_setup(p, pdev);
}

static int tpu_remove(struct platform_device *pdev)
{
	return -EBUSY;
}

static const struct of_device_id tpu_of_table[] = {
	{ .compatible = "renesas,tpu" },
	{ }
};

static struct platform_driver tpu_driver = {
	.probe		= tpu_probe,
	.remove		= tpu_remove,
	.driver		= {
		.name	= "h8s-tpu",
		.of_match_table = of_match_ptr(tpu_of_table),
	}
};

static int __init tpu_init(void)
{
	return platform_driver_register(&tpu_driver);
}

static void __exit tpu_exit(void)
{
	platform_driver_unregister(&tpu_driver);
}

subsys_initcall(tpu_init);
module_exit(tpu_exit);
MODULE_AUTHOR("Yoshinori Sato");
MODULE_DESCRIPTION("H8S Timer Pulse Unit Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
618b902d YS	1	/*
	2	* H8/300 TPU Driver
	3	*
	4	* Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
	5	*
	6	*/
	7
	8	#include <linux/errno.h>
	9	#include <linux/sched.h>
	10	#include <linux/kernel.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/init.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/slab.h>
	15	#include <linux/clocksource.h>
	16	#include <linux/module.h>
	17	#include <linux/clk.h>
	18	#include <linux/io.h>
	19	#include <linux/of.h>
	20
	21	#include <asm/irq.h>
	22
	23	#define TCR 0
	24	#define TMDR 1
	25	#define TIOR 2
	26	#define TER 4
	27	#define TSR 5
	28	#define TCNT 6
	29	#define TGRA 8
	30	#define TGRB 10
	31	#define TGRC 12
	32	#define TGRD 14
	33
	34	struct tpu_priv {
	35	struct platform_device *pdev;
	36	struct clocksource cs;
	37	struct clk *clk;
	38	unsigned long mapbase1;
	39	unsigned long mapbase2;
	40	raw_spinlock_t lock;
	41	unsigned int cs_enabled;
	42	};
	43
	44	static inline unsigned long read_tcnt32(struct tpu_priv *p)
	45	{
	46	unsigned long tcnt;
	47
	48	tcnt = ctrl_inw(p->mapbase1 + TCNT) << 16;
	49	tcnt \|= ctrl_inw(p->mapbase2 + TCNT);
	50	return tcnt;
	51	}
	52
	53	static int tpu_get_counter(struct tpu_priv p, unsigned long long val)
	54	{
	55	unsigned long v1, v2, v3;
	56	int o1, o2;
	57
	58	o1 = ctrl_inb(p->mapbase1 + TSR) & 0x10;
	59
	60	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	61	do {
	62	o2 = o1;
	63	v1 = read_tcnt32(p);
	64	v2 = read_tcnt32(p);
65	v3 = read_tcnt32(p);
66	o1 = ctrl_inb(p->mapbase1 + TSR) & 0x10;
67	} while (unlikely((o1 != o2) \|\| (v1 > v2 && v1 < v3)
68	\|\| (v2 > v3 && v2 < v1) \|\| (v3 > v1 && v3 < v2)));
69
70	*val = v2;
71	return o1;
72	}
73
74	static inline struct tpu_priv cs_to_priv(struct clocksource cs)
75	{
76	return container_of(cs, struct tpu_priv, cs);
77	}
78
79	static cycle_t tpu_clocksource_read(struct clocksource *cs)
80	{
81	struct tpu_priv *p = cs_to_priv(cs);
82	unsigned long flags;
83	unsigned long long value;
84
85	raw_spin_lock_irqsave(&p->lock, flags);
86	if (tpu_get_counter(p, &value))
87	value += 0x100000000;
88	raw_spin_unlock_irqrestore(&p->lock, flags);
89
90	return value;
91	}
92
93	static int tpu_clocksource_enable(struct clocksource *cs)
94	{
95	struct tpu_priv *p = cs_to_priv(cs);
96
97	WARN_ON(p->cs_enabled);
98
99	ctrl_outw(0, p->mapbase1 + TCNT);
100	ctrl_outw(0, p->mapbase2 + TCNT);
101	ctrl_outb(0x0f, p->mapbase1 + TCR);
102	ctrl_outb(0x03, p->mapbase2 + TCR);
103
104	p->cs_enabled = true;
105	return 0;
106	}
107
108	static void tpu_clocksource_disable(struct clocksource *cs)
109	{
110	struct tpu_priv *p = cs_to_priv(cs);
111
112	WARN_ON(!p->cs_enabled);
113
114	ctrl_outb(0, p->mapbase1 + TCR);
115	ctrl_outb(0, p->mapbase2 + TCR);
116	p->cs_enabled = false;
117	}
118
119	#define CH_L 0
120	#define CH_H 1
121
122	static int __init tpu_setup(struct tpu_priv p, struct platform_device pdev)
123	{
124	struct resource *res[2];
125
618b902d YS	126	p->pdev = pdev;
	127
	128	res[CH_L] = platform_get_resource(p->pdev, IORESOURCE_MEM, CH_L);
	129	res[CH_H] = platform_get_resource(p->pdev, IORESOURCE_MEM, CH_H);
	130	if (!res[CH_L] \|\| !res[CH_H]) {
	131	dev_err(&p->pdev->dev, "failed to get I/O memory\n");
	132	return -ENXIO;
	133	}
	134
	135	p->clk = clk_get(&p->pdev->dev, "fck");
	136	if (IS_ERR(p->clk)) {
	137	dev_err(&p->pdev->dev, "can't get clk\n");
	138	return PTR_ERR(p->clk);
	139	}
	140
	141	p->mapbase1 = res[CH_L]->start;
	142	p->mapbase2 = res[CH_H]->start;
	143
	144	p->cs.name = pdev->name;
	145	p->cs.rating = 200;
	146	p->cs.read = tpu_clocksource_read;
	147	p->cs.enable = tpu_clocksource_enable;
	148	p->cs.disable = tpu_clocksource_disable;
	149	p->cs.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
	150	p->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	151	clocksource_register_hz(&p->cs, clk_get_rate(p->clk) / 64);
	152	platform_set_drvdata(pdev, p);
	153
	154	return 0;
	155	}
	156
	157	static int tpu_probe(struct platform_device *pdev)
	158	{
	159	struct tpu_priv *p = platform_get_drvdata(pdev);
	160
	161	if (p) {
	162	dev_info(&pdev->dev, "kept as earlytimer\n");
	163	return 0;
	164	}
	165
	166	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
	167	if (!p)
	168	return -ENOMEM;
	169
	170	return tpu_setup(p, pdev);
	171	}
	172
	173	static int tpu_remove(struct platform_device *pdev)
	174	{
	175	return -EBUSY;
	176	}
	177
	178	static const struct of_device_id tpu_of_table[] = {
	179	{ .compatible = "renesas,tpu" },
	180	{ }
	181	};
	182
	183	static struct platform_driver tpu_driver = {
	184	.probe = tpu_probe,
	185	.remove = tpu_remove,
	186	.driver = {
	187	.name = "h8s-tpu",
	188	.of_match_table = of_match_ptr(tpu_of_table),
	189	}
190	};
191
192	static int __init tpu_init(void)
193	{
194	return platform_driver_register(&tpu_driver);
195	}
196
197	static void __exit tpu_exit(void)
198	{
199	platform_driver_unregister(&tpu_driver);
200	}
201
202	subsys_initcall(tpu_init);
203	module_exit(tpu_exit);
204	MODULE_AUTHOR("Yoshinori Sato");
205	MODULE_DESCRIPTION("H8S Timer Pulse Unit Driver");
206	MODULE_LICENSE("GPL v2");