[linux-2.6-block.git] / drivers / clk / tegra / clk.c

/*
 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/clk/tegra.h>
#include <linux/reset-controller.h>

#include <soc/tegra/fuse.h>

#include "clk.h"

#define CLK_OUT_ENB_L			0x010
#define CLK_OUT_ENB_H			0x014
#define CLK_OUT_ENB_U			0x018
#define CLK_OUT_ENB_V			0x360
#define CLK_OUT_ENB_W			0x364
#define CLK_OUT_ENB_X			0x280
#define CLK_OUT_ENB_Y			0x298
#define CLK_OUT_ENB_SET_L		0x320
#define CLK_OUT_ENB_CLR_L		0x324
#define CLK_OUT_ENB_SET_H		0x328
#define CLK_OUT_ENB_CLR_H		0x32c
#define CLK_OUT_ENB_SET_U		0x330
#define CLK_OUT_ENB_CLR_U		0x334
#define CLK_OUT_ENB_SET_V		0x440
#define CLK_OUT_ENB_CLR_V		0x444
#define CLK_OUT_ENB_SET_W		0x448
#define CLK_OUT_ENB_CLR_W		0x44c
#define CLK_OUT_ENB_SET_X		0x284
#define CLK_OUT_ENB_CLR_X		0x288
#define CLK_OUT_ENB_SET_Y		0x29c
#define CLK_OUT_ENB_CLR_Y		0x2a0

#define RST_DEVICES_L			0x004
#define RST_DEVICES_H			0x008
#define RST_DEVICES_U			0x00C
#define RST_DFLL_DVCO			0x2F4
#define RST_DEVICES_V			0x358
#define RST_DEVICES_W			0x35C
#define RST_DEVICES_X			0x28C
#define RST_DEVICES_Y			0x2a4
#define RST_DEVICES_SET_L		0x300
#define RST_DEVICES_CLR_L		0x304
#define RST_DEVICES_SET_H		0x308
#define RST_DEVICES_CLR_H		0x30c
#define RST_DEVICES_SET_U		0x310
#define RST_DEVICES_CLR_U		0x314
#define RST_DEVICES_SET_V		0x430
#define RST_DEVICES_CLR_V		0x434
#define RST_DEVICES_SET_W		0x438
#define RST_DEVICES_CLR_W		0x43c
#define RST_DEVICES_SET_X		0x290
#define RST_DEVICES_CLR_X		0x294
#define RST_DEVICES_SET_Y		0x2a8
#define RST_DEVICES_CLR_Y		0x2ac

/* Global data of Tegra CPU CAR ops */
static struct tegra_cpu_car_ops dummy_car_ops;
struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;

int *periph_clk_enb_refcnt;
static int periph_banks;
static struct clk **clks;
static int clk_num;
static struct clk_onecell_data clk_data;

static struct tegra_clk_periph_regs periph_regs[] = {
	[0] = {
		.enb_reg = CLK_OUT_ENB_L,
		.enb_set_reg = CLK_OUT_ENB_SET_L,
		.enb_clr_reg = CLK_OUT_ENB_CLR_L,
		.rst_reg = RST_DEVICES_L,
		.rst_set_reg = RST_DEVICES_SET_L,
		.rst_clr_reg = RST_DEVICES_CLR_L,
	},
	[1] = {
		.enb_reg = CLK_OUT_ENB_H,
		.enb_set_reg = CLK_OUT_ENB_SET_H,
		.enb_clr_reg = CLK_OUT_ENB_CLR_H,
		.rst_reg = RST_DEVICES_H,
		.rst_set_reg = RST_DEVICES_SET_H,
		.rst_clr_reg = RST_DEVICES_CLR_H,
	},
	[2] = {
		.enb_reg = CLK_OUT_ENB_U,
		.enb_set_reg = CLK_OUT_ENB_SET_U,
		.enb_clr_reg = CLK_OUT_ENB_CLR_U,
		.rst_reg = RST_DEVICES_U,
		.rst_set_reg = RST_DEVICES_SET_U,
		.rst_clr_reg = RST_DEVICES_CLR_U,
	},
	[3] = {
		.enb_reg = CLK_OUT_ENB_V,
		.enb_set_reg = CLK_OUT_ENB_SET_V,
		.enb_clr_reg = CLK_OUT_ENB_CLR_V,
		.rst_reg = RST_DEVICES_V,
		.rst_set_reg = RST_DEVICES_SET_V,
		.rst_clr_reg = RST_DEVICES_CLR_V,
	},
	[4] = {
		.enb_reg = CLK_OUT_ENB_W,
		.enb_set_reg = CLK_OUT_ENB_SET_W,
		.enb_clr_reg = CLK_OUT_ENB_CLR_W,
		.rst_reg = RST_DEVICES_W,
		.rst_set_reg = RST_DEVICES_SET_W,
		.rst_clr_reg = RST_DEVICES_CLR_W,
	},
	[5] = {
		.enb_reg = CLK_OUT_ENB_X,
		.enb_set_reg = CLK_OUT_ENB_SET_X,
		.enb_clr_reg = CLK_OUT_ENB_CLR_X,
		.rst_reg = RST_DEVICES_X,
		.rst_set_reg = RST_DEVICES_SET_X,
		.rst_clr_reg = RST_DEVICES_CLR_X,
	},
	[6] = {
		.enb_reg = CLK_OUT_ENB_Y,
		.enb_set_reg = CLK_OUT_ENB_SET_Y,
		.enb_clr_reg = CLK_OUT_ENB_CLR_Y,
		.rst_reg = RST_DEVICES_Y,
		.rst_set_reg = RST_DEVICES_SET_Y,
		.rst_clr_reg = RST_DEVICES_CLR_Y,
	},
};

static void __iomem *clk_base;

static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
		unsigned long id)
{
	/*
	 * If peripheral is on the APB bus then we must read the APB bus to
	 * flush the write operation in apb bus. This will avoid peripheral
	 * access after disabling clock. Since the reset driver has no
	 * knowledge of which reset IDs represent which devices, simply do
	 * this all the time.
	 */
	tegra_read_chipid();

	writel_relaxed(BIT(id % 32),
			clk_base + periph_regs[id / 32].rst_set_reg);

	return 0;
}

static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
		unsigned long id)
{
	writel_relaxed(BIT(id % 32),
			clk_base + periph_regs[id / 32].rst_clr_reg);

	return 0;
}

struct tegra_clk_periph_regs *get_reg_bank(int clkid)
{
	int reg_bank = clkid / 32;

	if (reg_bank < periph_banks)
		return &periph_regs[reg_bank];
	else {
		WARN_ON(1);
		return NULL;
	}
}

struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
{
	clk_base = regs;

	if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
		return NULL;

	periph_clk_enb_refcnt = kzalloc(32 * banks *
				sizeof(*periph_clk_enb_refcnt), GFP_KERNEL);
	if (!periph_clk_enb_refcnt)
		return NULL;

	periph_banks = banks;

	clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL);
	if (!clks)
		kfree(periph_clk_enb_refcnt);

	clk_num = num;

	return clks;
}

void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
				struct clk *clks[], int clk_max)
{
	struct clk *clk;

	for (; dup_list->clk_id < clk_max; dup_list++) {
		clk = clks[dup_list->clk_id];
		dup_list->lookup.clk = clk;
		clkdev_add(&dup_list->lookup);
	}
}

void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
				  struct clk *clks[], int clk_max)
{
	struct clk *clk;

	for (; tbl->clk_id < clk_max; tbl++) {
		clk = clks[tbl->clk_id];
		if (IS_ERR_OR_NULL(clk)) {
			pr_err("%s: invalid entry %ld in clks array for id %d\n",
			       __func__, PTR_ERR(clk), tbl->clk_id);
			WARN_ON(1);

			continue;
		}

		if (tbl->parent_id < clk_max) {
			struct clk *parent = clks[tbl->parent_id];
			if (clk_set_parent(clk, parent)) {
				pr_err("%s: Failed to set parent %s of %s\n",
				       __func__, __clk_get_name(parent),
				       __clk_get_name(clk));
				WARN_ON(1);
			}
		}

		if (tbl->rate)
			if (clk_set_rate(clk, tbl->rate)) {
				pr_err("%s: Failed to set rate %lu of %s\n",
				       __func__, tbl->rate,
				       __clk_get_name(clk));
				WARN_ON(1);
			}

		if (tbl->state)
			if (clk_prepare_enable(clk)) {
				pr_err("%s: Failed to enable %s\n", __func__,
				       __clk_get_name(clk));
				WARN_ON(1);
			}
	}
}

static struct reset_control_ops rst_ops = {
	.assert = tegra_clk_rst_assert,
	.deassert = tegra_clk_rst_deassert,
};

static struct reset_controller_dev rst_ctlr = {
	.ops = &rst_ops,
	.owner = THIS_MODULE,
	.of_reset_n_cells = 1,
};

void __init tegra_add_of_provider(struct device_node *np)
{
	int i;

	for (i = 0; i < clk_num; i++) {
		if (IS_ERR(clks[i])) {
			pr_err
			    ("Tegra clk %d: register failed with %ld\n",
			     i, PTR_ERR(clks[i]));
		}
		if (!clks[i])
			clks[i] = ERR_PTR(-EINVAL);
	}

	clk_data.clks = clks;
	clk_data.clk_num = clk_num;
	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

	rst_ctlr.of_node = np;
	rst_ctlr.nr_resets = periph_banks * 32;
	reset_controller_register(&rst_ctlr);
}

void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
{
	int i;

	for (i = 0; i < num; i++, dev_clks++)
		clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
				dev_clks->dev_id);

	for (i = 0; i < clk_num; i++) {
		if (!IS_ERR_OR_NULL(clks[i]))
			clk_register_clkdev(clks[i], __clk_get_name(clks[i]),
				"tegra-clk-debug");
	}
}

struct clk ** __init tegra_lookup_dt_id(int clk_id,
					struct tegra_clk *tegra_clk)
{
	if (tegra_clk[clk_id].present)
		return &clks[tegra_clk[clk_id].dt_id];
	else
		return NULL;
}

tegra_clk_apply_init_table_func tegra_clk_apply_init_table;

static int __init tegra_clocks_apply_init_table(void)
{
	if (!tegra_clk_apply_init_table)
		return 0;

	tegra_clk_apply_init_table();

	return 0;
}
arch_initcall(tegra_clocks_apply_init_table);
Commit	Line	Data
8f8f484b PG	1	/*
	2	* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/clk-provider.h>
61fd290d PG	19	#include <linux/of.h>
61fd290d PG	20	#include <linux/clk/tegra.h>
6d5b988e	21	#include <linux/reset-controller.h>
306a7f91 TR	22
306a7f91 TR	23	#include <soc/tegra/fuse.h>
8f8f484b PG	24
	25	#include "clk.h"
	26
d5ff89a8 PDS	27	#define CLK_OUT_ENB_L 0x010
	28	#define CLK_OUT_ENB_H 0x014
	29	#define CLK_OUT_ENB_U 0x018
	30	#define CLK_OUT_ENB_V 0x360
	31	#define CLK_OUT_ENB_W 0x364
	32	#define CLK_OUT_ENB_X 0x280
699b477a	33	#define CLK_OUT_ENB_Y 0x298
d5ff89a8 PDS	34	#define CLK_OUT_ENB_SET_L 0x320
	35	#define CLK_OUT_ENB_CLR_L 0x324
	36	#define CLK_OUT_ENB_SET_H 0x328
	37	#define CLK_OUT_ENB_CLR_H 0x32c
	38	#define CLK_OUT_ENB_SET_U 0x330
	39	#define CLK_OUT_ENB_CLR_U 0x334
	40	#define CLK_OUT_ENB_SET_V 0x440
	41	#define CLK_OUT_ENB_CLR_V 0x444
	42	#define CLK_OUT_ENB_SET_W 0x448
	43	#define CLK_OUT_ENB_CLR_W 0x44c
	44	#define CLK_OUT_ENB_SET_X 0x284
	45	#define CLK_OUT_ENB_CLR_X 0x288
699b477a TR	46	#define CLK_OUT_ENB_SET_Y 0x29c
699b477a TR	47	#define CLK_OUT_ENB_CLR_Y 0x2a0
d5ff89a8 PDS	48
	49	#define RST_DEVICES_L 0x004
	50	#define RST_DEVICES_H 0x008
	51	#define RST_DEVICES_U 0x00C
	52	#define RST_DFLL_DVCO 0x2F4
	53	#define RST_DEVICES_V 0x358
	54	#define RST_DEVICES_W 0x35C
	55	#define RST_DEVICES_X 0x28C
699b477a	56	#define RST_DEVICES_Y 0x2a4
d5ff89a8 PDS	57	#define RST_DEVICES_SET_L 0x300
	58	#define RST_DEVICES_CLR_L 0x304
	59	#define RST_DEVICES_SET_H 0x308
	60	#define RST_DEVICES_CLR_H 0x30c
	61	#define RST_DEVICES_SET_U 0x310
	62	#define RST_DEVICES_CLR_U 0x314
	63	#define RST_DEVICES_SET_V 0x430
	64	#define RST_DEVICES_CLR_V 0x434
	65	#define RST_DEVICES_SET_W 0x438
	66	#define RST_DEVICES_CLR_W 0x43c
2b239077 PDS	67	#define RST_DEVICES_SET_X 0x290
2b239077 PDS	68	#define RST_DEVICES_CLR_X 0x294
699b477a TR	69	#define RST_DEVICES_SET_Y 0x2a8
699b477a TR	70	#define RST_DEVICES_CLR_Y 0x2ac
d5ff89a8	71
61fd290d	72	/* Global data of Tegra CPU CAR ops */
6a676fa0 PDS	73	static struct tegra_cpu_car_ops dummy_car_ops;
6a676fa0 PDS	74	struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
61fd290d	75
343a607c	76	int *periph_clk_enb_refcnt;
d5ff89a8	77	static int periph_banks;
343a607c PDS	78	static struct clk **clks;
	79	static int clk_num;
	80	static struct clk_onecell_data clk_data;
d5ff89a8 PDS	81
	82	static struct tegra_clk_periph_regs periph_regs[] = {
	83	[0] = {
	84	.enb_reg = CLK_OUT_ENB_L,
	85	.enb_set_reg = CLK_OUT_ENB_SET_L,
	86	.enb_clr_reg = CLK_OUT_ENB_CLR_L,
	87	.rst_reg = RST_DEVICES_L,
	88	.rst_set_reg = RST_DEVICES_SET_L,
	89	.rst_clr_reg = RST_DEVICES_CLR_L,
	90	},
	91	[1] = {
	92	.enb_reg = CLK_OUT_ENB_H,
	93	.enb_set_reg = CLK_OUT_ENB_SET_H,
	94	.enb_clr_reg = CLK_OUT_ENB_CLR_H,
	95	.rst_reg = RST_DEVICES_H,
	96	.rst_set_reg = RST_DEVICES_SET_H,
	97	.rst_clr_reg = RST_DEVICES_CLR_H,
	98	},
	99	[2] = {
	100	.enb_reg = CLK_OUT_ENB_U,
	101	.enb_set_reg = CLK_OUT_ENB_SET_U,
	102	.enb_clr_reg = CLK_OUT_ENB_CLR_U,
	103	.rst_reg = RST_DEVICES_U,
	104	.rst_set_reg = RST_DEVICES_SET_U,
	105	.rst_clr_reg = RST_DEVICES_CLR_U,
	106	},
	107	[3] = {
	108	.enb_reg = CLK_OUT_ENB_V,
	109	.enb_set_reg = CLK_OUT_ENB_SET_V,
	110	.enb_clr_reg = CLK_OUT_ENB_CLR_V,
	111	.rst_reg = RST_DEVICES_V,
	112	.rst_set_reg = RST_DEVICES_SET_V,
	113	.rst_clr_reg = RST_DEVICES_CLR_V,
	114	},
	115	[4] = {
	116	.enb_reg = CLK_OUT_ENB_W,
	117	.enb_set_reg = CLK_OUT_ENB_SET_W,
	118	.enb_clr_reg = CLK_OUT_ENB_CLR_W,
	119	.rst_reg = RST_DEVICES_W,
	120	.rst_set_reg = RST_DEVICES_SET_W,
	121	.rst_clr_reg = RST_DEVICES_CLR_W,
	122	},
2b239077 PDS	123	[5] = {
	124	.enb_reg = CLK_OUT_ENB_X,
	125	.enb_set_reg = CLK_OUT_ENB_SET_X,
	126	.enb_clr_reg = CLK_OUT_ENB_CLR_X,
	127	.rst_reg = RST_DEVICES_X,
	128	.rst_set_reg = RST_DEVICES_SET_X,
	129	.rst_clr_reg = RST_DEVICES_CLR_X,
	130	},
699b477a TR	131	[6] = {
	132	.enb_reg = CLK_OUT_ENB_Y,
	133	.enb_set_reg = CLK_OUT_ENB_SET_Y,
	134	.enb_clr_reg = CLK_OUT_ENB_CLR_Y,
	135	.rst_reg = RST_DEVICES_Y,
	136	.rst_set_reg = RST_DEVICES_SET_Y,
	137	.rst_clr_reg = RST_DEVICES_CLR_Y,
	138	},
d5ff89a8 PDS	139	};
d5ff89a8 PDS	140
6d5b988e SW	141	static void __iomem *clk_base;
	142
	143	static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
	144	unsigned long id)
	145	{
	146	/*
	147	* If peripheral is on the APB bus then we must read the APB bus to
	148	* flush the write operation in apb bus. This will avoid peripheral
	149	* access after disabling clock. Since the reset driver has no
	150	* knowledge of which reset IDs represent which devices, simply do
	151	* this all the time.
	152	*/
	153	tegra_read_chipid();
	154
	155	writel_relaxed(BIT(id % 32),
	156	clk_base + periph_regs[id / 32].rst_set_reg);
	157
	158	return 0;
	159	}
	160
	161	static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
	162	unsigned long id)
	163	{
	164	writel_relaxed(BIT(id % 32),
	165	clk_base + periph_regs[id / 32].rst_clr_reg);
	166
	167	return 0;
	168	}
	169
d5ff89a8 PDS	170	struct tegra_clk_periph_regs *get_reg_bank(int clkid)
	171	{
	172	int reg_bank = clkid / 32;
	173
	174	if (reg_bank < periph_banks)
	175	return &periph_regs[reg_bank];
	176	else {
	177	WARN_ON(1);
	178	return NULL;
	179	}
	180	}
	181
6d5b988e	182	struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
d5ff89a8	183	{
6d5b988e SW	184	clk_base = regs;
6d5b988e SW	185
343a607c PDS	186	if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
	187	return NULL;
	188
	189	periph_clk_enb_refcnt = kzalloc(32 * banks *
	190	sizeof(*periph_clk_enb_refcnt), GFP_KERNEL);
	191	if (!periph_clk_enb_refcnt)
	192	return NULL;
d5ff89a8	193
343a607c	194	periph_banks = banks;
d5ff89a8	195
343a607c PDS	196	clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL);
	197	if (!clks)
	198	kfree(periph_clk_enb_refcnt);
	199
	200	clk_num = num;
	201
	202	return clks;
d5ff89a8 PDS	203	}
d5ff89a8 PDS	204
8f8f484b PG	205	void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
	206	struct clk *clks[], int clk_max)
	207	{
	208	struct clk *clk;
	209
	210	for (; dup_list->clk_id < clk_max; dup_list++) {
	211	clk = clks[dup_list->clk_id];
	212	dup_list->lookup.clk = clk;
	213	clkdev_add(&dup_list->lookup);
	214	}
	215	}
	216
	217	void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
	218	struct clk *clks[], int clk_max)
	219	{
	220	struct clk *clk;
	221
	222	for (; tbl->clk_id < clk_max; tbl++) {
	223	clk = clks[tbl->clk_id];
b9e742c3 TV	224	if (IS_ERR_OR_NULL(clk)) {
	225	pr_err("%s: invalid entry %ld in clks array for id %d\n",
	226	__func__, PTR_ERR(clk), tbl->clk_id);
	227	WARN_ON(1);
	228
	229	continue;
	230	}
8f8f484b PG	231
	232	if (tbl->parent_id < clk_max) {
	233	struct clk *parent = clks[tbl->parent_id];
	234	if (clk_set_parent(clk, parent)) {
	235	pr_err("%s: Failed to set parent %s of %s\n",
	236	__func__, __clk_get_name(parent),
	237	__clk_get_name(clk));
	238	WARN_ON(1);
	239	}
	240	}
	241
	242	if (tbl->rate)
	243	if (clk_set_rate(clk, tbl->rate)) {
	244	pr_err("%s: Failed to set rate %lu of %s\n",
	245	__func__, tbl->rate,
	246	__clk_get_name(clk));
	247	WARN_ON(1);
	248	}
	249
	250	if (tbl->state)
	251	if (clk_prepare_enable(clk)) {
	252	pr_err("%s: Failed to enable %s\n", __func__,
	253	__clk_get_name(clk));
	254	WARN_ON(1);
	255	}
	256	}
	257	}
61fd290d	258
6d5b988e SW	259	static struct reset_control_ops rst_ops = {
	260	.assert = tegra_clk_rst_assert,
	261	.deassert = tegra_clk_rst_deassert,
	262	};
	263
	264	static struct reset_controller_dev rst_ctlr = {
	265	.ops = &rst_ops,
	266	.owner = THIS_MODULE,
	267	.of_reset_n_cells = 1,
	268	};
	269
343a607c PDS	270	void __init tegra_add_of_provider(struct device_node *np)
	271	{
	272	int i;
	273
	274	for (i = 0; i < clk_num; i++) {
	275	if (IS_ERR(clks[i])) {
	276	pr_err
	277	("Tegra clk %d: register failed with %ld\n",
	278	i, PTR_ERR(clks[i]));
	279	}
	280	if (!clks[i])
	281	clks[i] = ERR_PTR(-EINVAL);
	282	}
	283
	284	clk_data.clks = clks;
	285	clk_data.clk_num = clk_num;
	286	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
6d5b988e SW	287
6d5b988e SW	288	rst_ctlr.of_node = np;
5e43e259	289	rst_ctlr.nr_resets = periph_banks * 32;
6d5b988e	290	reset_controller_register(&rst_ctlr);
343a607c PDS	291	}
343a607c PDS	292
73d37e4c PDS	293	void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
	294	{
	295	int i;
	296
	297	for (i = 0; i < num; i++, dev_clks++)
	298	clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
	299	dev_clks->dev_id);
9f0030c8 PDS	300
	301	for (i = 0; i < clk_num; i++) {
	302	if (!IS_ERR_OR_NULL(clks[i]))
	303	clk_register_clkdev(clks[i], __clk_get_name(clks[i]),
	304	"tegra-clk-debug");
	305	}
73d37e4c PDS	306	}
73d37e4c PDS	307
b8700d50 PDS	308	struct clk ** __init tegra_lookup_dt_id(int clk_id,
	309	struct tegra_clk *tegra_clk)
	310	{
	311	if (tegra_clk[clk_id].present)
	312	return &clks[tegra_clk[clk_id].dt_id];
	313	else
	314	return NULL;
	315	}
	316
441f199a SW	317	tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
441f199a SW	318
d0a57bd5	319	static int __init tegra_clocks_apply_init_table(void)
441f199a SW	320	{
441f199a SW	321	if (!tegra_clk_apply_init_table)
d0a57bd5	322	return 0;
441f199a SW	323
441f199a SW	324	tegra_clk_apply_init_table();
d0a57bd5 PDS	325
d0a57bd5 PDS	326	return 0;
441f199a	327	}
d0a57bd5	328	arch_initcall(tegra_clocks_apply_init_table);