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1 | /* |
2 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/clk-provider.h> | |
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19 | #include <linux/of.h> |
20 | #include <linux/clk/tegra.h> | |
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21 | |
22 | #include "clk.h" | |
23 | ||
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24 | /* Global data of Tegra CPU CAR ops */ |
25 | struct tegra_cpu_car_ops *tegra_cpu_car_ops; | |
26 | ||
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27 | void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, |
28 | struct clk *clks[], int clk_max) | |
29 | { | |
30 | struct clk *clk; | |
31 | ||
32 | for (; dup_list->clk_id < clk_max; dup_list++) { | |
33 | clk = clks[dup_list->clk_id]; | |
34 | dup_list->lookup.clk = clk; | |
35 | clkdev_add(&dup_list->lookup); | |
36 | } | |
37 | } | |
38 | ||
39 | void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, | |
40 | struct clk *clks[], int clk_max) | |
41 | { | |
42 | struct clk *clk; | |
43 | ||
44 | for (; tbl->clk_id < clk_max; tbl++) { | |
45 | clk = clks[tbl->clk_id]; | |
46 | if (IS_ERR_OR_NULL(clk)) | |
47 | return; | |
48 | ||
49 | if (tbl->parent_id < clk_max) { | |
50 | struct clk *parent = clks[tbl->parent_id]; | |
51 | if (clk_set_parent(clk, parent)) { | |
52 | pr_err("%s: Failed to set parent %s of %s\n", | |
53 | __func__, __clk_get_name(parent), | |
54 | __clk_get_name(clk)); | |
55 | WARN_ON(1); | |
56 | } | |
57 | } | |
58 | ||
59 | if (tbl->rate) | |
60 | if (clk_set_rate(clk, tbl->rate)) { | |
61 | pr_err("%s: Failed to set rate %lu of %s\n", | |
62 | __func__, tbl->rate, | |
63 | __clk_get_name(clk)); | |
64 | WARN_ON(1); | |
65 | } | |
66 | ||
67 | if (tbl->state) | |
68 | if (clk_prepare_enable(clk)) { | |
69 | pr_err("%s: Failed to enable %s\n", __func__, | |
70 | __clk_get_name(clk)); | |
71 | WARN_ON(1); | |
72 | } | |
73 | } | |
74 | } | |
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75 | |
76 | static const struct of_device_id tegra_dt_clk_match[] = { | |
77 | { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init }, | |
78 | { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init }, | |
79 | { } | |
80 | }; | |
81 | ||
82 | void __init tegra_clocks_init(void) | |
83 | { | |
84 | of_clk_init(tegra_dt_clk_match); | |
85 | } | |
441f199a SW |
86 | |
87 | tegra_clk_apply_init_table_func tegra_clk_apply_init_table; | |
88 | ||
89 | void __init tegra_clocks_apply_init_table(void) | |
90 | { | |
91 | if (!tegra_clk_apply_init_table) | |
92 | return; | |
93 | ||
94 | tegra_clk_apply_init_table(); | |
95 | } |