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Merge branch 'pm-cpufreq'
[linux-2.6-block.git] / drivers / clk / samsung / clk-s3c64xx.c
CommitLineData
06dda9d7
TF		 1/*
2 * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Common Clock Framework support for all S3C64xx SoCs.
9*/
10
6f1ed07a 11#include <linux/slab.h>
06dda9d7
TF		 12#include <linux/clk-provider.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
08c0d829 15#include <linux/syscore_ops.h>
06dda9d7
TF		 16
17#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
18
19#include "clk.h"
20#include "clk-pll.h"
21
22/* S3C64xx clock controller register offsets. */
23#define APLL_LOCK 0x000
24#define MPLL_LOCK 0x004
25#define EPLL_LOCK 0x008
26#define APLL_CON 0x00c
27#define MPLL_CON 0x010
28#define EPLL_CON0 0x014
29#define EPLL_CON1 0x018
30#define CLK_SRC 0x01c
31#define CLK_DIV0 0x020
32#define CLK_DIV1 0x024
33#define CLK_DIV2 0x028
34#define HCLK_GATE 0x030
35#define PCLK_GATE 0x034
36#define SCLK_GATE 0x038
37#define MEM0_GATE 0x03c
38#define CLK_SRC2 0x10c
39#define OTHERS 0x900
40
41/* Helper macros to define clock arrays. */
42#define FIXED_RATE_CLOCKS(name) \
43 static struct samsung_fixed_rate_clock name[]
44#define MUX_CLOCKS(name) \
45 static struct samsung_mux_clock name[]
46#define DIV_CLOCKS(name) \
47 static struct samsung_div_clock name[]
48#define GATE_CLOCKS(name) \
49 static struct samsung_gate_clock name[]
50
51/* Helper macros for gate types present on S3C64xx. */
52#define GATE_BUS(_id, cname, pname, o, b) \
53 GATE(_id, cname, pname, o, b, 0, 0)
54#define GATE_SCLK(_id, cname, pname, o, b) \
55 GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
56#define GATE_ON(_id, cname, pname, o, b) \
57 GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
58
59/* list of PLLs to be registered */
60enum s3c64xx_plls {
61 apll, mpll, epll,
62};
63
08c0d829
TF		 64static void __iomem *reg_base;
65static bool is_s3c6400;
66
67#ifdef CONFIG_PM_SLEEP
68static struct samsung_clk_reg_dump *s3c64xx_save_common;
69static struct samsung_clk_reg_dump *s3c64xx_save_soc;
70
06dda9d7
TF		 71/*
72 * List of controller registers to be saved and restored during
73 * a suspend/resume cycle.
74 */
5b0dde99 75static unsigned long s3c64xx_clk_regs[] __initdata = {
06dda9d7
TF		 76 APLL_LOCK,
77 MPLL_LOCK,
78 EPLL_LOCK,
79 APLL_CON,
80 MPLL_CON,
81 EPLL_CON0,
82 EPLL_CON1,
83 CLK_SRC,
84 CLK_DIV0,
85 CLK_DIV1,
86 CLK_DIV2,
87 HCLK_GATE,
88 PCLK_GATE,
89 SCLK_GATE,
90};
91
5b0dde99 92static unsigned long s3c6410_clk_regs[] __initdata = {
06dda9d7
TF		 93 CLK_SRC2,
94 MEM0_GATE,
95};
96
08c0d829
TF		 97static int s3c64xx_clk_suspend(void)
98{
99 samsung_clk_save(reg_base, s3c64xx_save_common,
100 ARRAY_SIZE(s3c64xx_clk_regs));
101
102 if (!is_s3c6400)
103 samsung_clk_save(reg_base, s3c64xx_save_soc,
104 ARRAY_SIZE(s3c6410_clk_regs));
105
106 return 0;
107}
108
109static void s3c64xx_clk_resume(void)
110{
111 samsung_clk_restore(reg_base, s3c64xx_save_common,
112 ARRAY_SIZE(s3c64xx_clk_regs));
113
114 if (!is_s3c6400)
115 samsung_clk_restore(reg_base, s3c64xx_save_soc,
116 ARRAY_SIZE(s3c6410_clk_regs));
117}
118
119static struct syscore_ops s3c64xx_clk_syscore_ops = {
120 .suspend = s3c64xx_clk_suspend,
121 .resume = s3c64xx_clk_resume,
122};
123
124static void s3c64xx_clk_sleep_init(void)
125{
126 s3c64xx_save_common = samsung_clk_alloc_reg_dump(s3c64xx_clk_regs,
127 ARRAY_SIZE(s3c64xx_clk_regs));
128 if (!s3c64xx_save_common)
129 goto err_warn;
130
131 if (!is_s3c6400) {
132 s3c64xx_save_soc = samsung_clk_alloc_reg_dump(s3c6410_clk_regs,
133 ARRAY_SIZE(s3c6410_clk_regs));
134 if (!s3c64xx_save_soc)
135 goto err_soc;
136 }
137
138 register_syscore_ops(&s3c64xx_clk_syscore_ops);
139 return;
140
141err_soc:
142 kfree(s3c64xx_save_common);
143err_warn:
144 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
145 __func__);
146}
147#else
148static void s3c64xx_clk_sleep_init(void) {}
149#endif
150
06dda9d7
TF		 151/* List of parent clocks common for all S3C64xx SoCs. */
152PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
153PNAME(uart_p) = { "mout_epll", "dout_mpll" };
154PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
155 "pcmcdclk0", "none", "none", "none" };
156PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
157 "pcmcdclk0", "none", "none", "none" };
158PNAME(mfc_p) = { "hclkx2", "mout_epll" };
159PNAME(apll_p) = { "fin_pll", "fout_apll" };
160PNAME(mpll_p) = { "fin_pll", "fout_mpll" };
161PNAME(epll_p) = { "fin_pll", "fout_epll" };
162PNAME(hclkx2_p) = { "mout_mpll", "mout_apll" };
163
164/* S3C6400-specific parent clocks. */
165PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" };
166PNAME(irda_p6400) = { "mout_epll", "dout_mpll", "none", "clk48m" };
167PNAME(uhost_p6400) = { "clk48m", "mout_epll", "dout_mpll", "none" };
168
169/* S3C6410-specific parent clocks. */
170PNAME(clk27_p6410) = { "clk27m", "fin_pll" };
171PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" };
172PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
173PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
174PNAME(audio2_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2",
175 "pcmcdclk1", "none", "none", "none" };
176
177/* Fixed rate clocks generated outside the SoC. */
178FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = {
179 FRATE(0, "fin_pll", NULL, CLK_IS_ROOT, 0),
180 FRATE(0, "xusbxti", NULL, CLK_IS_ROOT, 0),
181};
182
183/* Fixed rate clocks generated inside the SoC. */
184FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = {
185 FRATE(CLK27M, "clk27m", NULL, CLK_IS_ROOT, 27000000),
186 FRATE(CLK48M, "clk48m", NULL, CLK_IS_ROOT, 48000000),
187};
188
189/* List of clock muxes present on all S3C64xx SoCs. */
190MUX_CLOCKS(s3c64xx_mux_clks) __initdata = {
191 MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
192 MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
193 MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
194 MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
195 MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
196 MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3),
197 MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3),
198 MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
199 MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
200 MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
201 MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
202 MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2),
203 MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2),
204};
205
206/* List of clock muxes present on S3C6400. */
207MUX_CLOCKS(s3c6400_mux_clks) __initdata = {
208 MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
209 MUX(MOUT_IRDA, "mout_irda", irda_p6400, CLK_SRC, 24, 2),
210 MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6400, CLK_SRC, 26, 2),
211 MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6400, CLK_SRC, 28, 2),
212};
213
214/* List of clock muxes present on S3C6410. */
215MUX_CLOCKS(s3c6410_mux_clks) __initdata = {
216 MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
217 MUX(MOUT_IRDA, "mout_irda", irda_p6410, CLK_SRC, 24, 2),
218 MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6410, CLK_SRC, 26, 2),
219 MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6410, CLK_SRC, 28, 2),
220 MUX(MOUT_DAC27, "mout_dac27", clk27_p6410, CLK_SRC, 30, 1),
221 MUX(MOUT_TV27, "mout_tv27", clk27_p6410, CLK_SRC, 31, 1),
222 MUX(MOUT_AUDIO2, "mout_audio2", audio2_p6410, CLK_SRC2, 0, 3),
223};
224
225/* List of clock dividers present on all S3C64xx SoCs. */
226DIV_CLOCKS(s3c64xx_div_clks) __initdata = {
227 DIV(DOUT_MPLL, "dout_mpll", "mout_mpll", CLK_DIV0, 4, 1),
228 DIV(HCLKX2, "hclkx2", "mout_syncmux", CLK_DIV0, 9, 3),
229 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
230 DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
231 DIV(DOUT_SECUR, "dout_secur", "hclkx2", CLK_DIV0, 18, 2),
232 DIV(DOUT_CAM, "dout_cam", "hclkx2", CLK_DIV0, 20, 4),
233 DIV(DOUT_JPEG, "dout_jpeg", "hclkx2", CLK_DIV0, 24, 4),
234 DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV0, 28, 4),
235 DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV1, 0, 4),
236 DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV1, 4, 4),
237 DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4),
238 DIV(DOUT_LCD, "dout_lcd", "mout_lcd", CLK_DIV1, 12, 4),
239 DIV(DOUT_SCALER, "dout_scaler", "mout_scaler", CLK_DIV1, 16, 4),
240 DIV(DOUT_UHOST, "dout_uhost", "mout_uhost", CLK_DIV1, 20, 4),
241 DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV2, 0, 4),
242 DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV2, 4, 4),
243 DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4),
244 DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV2, 12, 4),
245 DIV(DOUT_UART, "dout_uart", "mout_uart", CLK_DIV2, 16, 4),
246 DIV(DOUT_IRDA, "dout_irda", "mout_irda", CLK_DIV2, 20, 4),
247};
248
249/* List of clock dividers present on S3C6400. */
250DIV_CLOCKS(s3c6400_div_clks) __initdata = {
251 DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3),
252};
253
254/* List of clock dividers present on S3C6410. */
255DIV_CLOCKS(s3c6410_div_clks) __initdata = {
256 DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4),
257 DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
258 DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4),
259};
260
261/* List of clock gates present on all S3C64xx SoCs. */
262GATE_CLOCKS(s3c64xx_gate_clks) __initdata = {
263 GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
264 GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
265 GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
266 GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
267 GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
268 GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
269 GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
270 GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
271 GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17),
272 GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16),
273 GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15),
274 GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14),
275 GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13),
276 GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12),
277 GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11),
278 GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10),
279 GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9),
280 GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
281 GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7),
282 GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
283 GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4),
284 GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3),
285 GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2),
286 GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1),
287 GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
288 GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
289 GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
290 GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
291 GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
292 GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
293 GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
294 GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
295 GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
296 GATE_BUS(PCLK_IIS0, "pclk_iis0", "pclk", PCLK_GATE, 15),
297 GATE_BUS(PCLK_AC97, "pclk_ac97", "pclk", PCLK_GATE, 14),
298 GATE_BUS(PCLK_TZPC, "pclk_tzpc", "pclk", PCLK_GATE, 13),
299 GATE_BUS(PCLK_TSADC, "pclk_tsadc", "pclk", PCLK_GATE, 12),
300 GATE_BUS(PCLK_KEYPAD, "pclk_keypad", "pclk", PCLK_GATE, 11),
301 GATE_BUS(PCLK_IRDA, "pclk_irda", "pclk", PCLK_GATE, 10),
302 GATE_BUS(PCLK_PCM1, "pclk_pcm1", "pclk", PCLK_GATE, 9),
303 GATE_BUS(PCLK_PCM0, "pclk_pcm0", "pclk", PCLK_GATE, 8),
304 GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7),
305 GATE_BUS(PCLK_RTC, "pclk_rtc", "pclk", PCLK_GATE, 6),
306 GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
307 GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4),
308 GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3),
309 GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
310 GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
311 GATE_BUS(PCLK_MFC, "pclk_mfc", "pclk", PCLK_GATE, 0),
312 GATE_SCLK(SCLK_UHOST, "sclk_uhost", "dout_uhost", SCLK_GATE, 30),
313 GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29),
314 GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28),
315 GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27),
316 GATE_SCLK(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", SCLK_GATE, 26),
317 GATE_SCLK(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", SCLK_GATE, 25),
318 GATE_SCLK(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", SCLK_GATE, 24),
319 GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23),
320 GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22),
321 GATE_SCLK(SCLK_SPI1, "sclk_spi1", "dout_spi1", SCLK_GATE, 21),
322 GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
323 GATE_SCLK(SCLK_DAC27, "sclk_dac27", "mout_dac27", SCLK_GATE, 19),
324 GATE_SCLK(SCLK_TV27, "sclk_tv27", "mout_tv27", SCLK_GATE, 18),
325 GATE_SCLK(SCLK_SCALER27, "sclk_scaler27", "clk27m", SCLK_GATE, 17),
326 GATE_SCLK(SCLK_SCALER, "sclk_scaler", "dout_scaler", SCLK_GATE, 16),
327 GATE_SCLK(SCLK_LCD27, "sclk_lcd27", "clk27m", SCLK_GATE, 15),
328 GATE_SCLK(SCLK_LCD, "sclk_lcd", "dout_lcd", SCLK_GATE, 14),
329 GATE_SCLK(SCLK_POST0_27, "sclk_post0_27", "clk27m", SCLK_GATE, 12),
330 GATE_SCLK(SCLK_POST0, "sclk_post0", "dout_lcd", SCLK_GATE, 10),
331 GATE_SCLK(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", SCLK_GATE, 9),
332 GATE_SCLK(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", SCLK_GATE, 8),
333 GATE_SCLK(SCLK_SECUR, "sclk_secur", "dout_secur", SCLK_GATE, 7),
334 GATE_SCLK(SCLK_IRDA, "sclk_irda", "dout_irda", SCLK_GATE, 6),
335 GATE_SCLK(SCLK_UART, "sclk_uart", "dout_uart", SCLK_GATE, 5),
336 GATE_SCLK(SCLK_MFC, "sclk_mfc", "dout_mfc", SCLK_GATE, 3),
337 GATE_SCLK(SCLK_CAM, "sclk_cam", "dout_cam", SCLK_GATE, 2),
338 GATE_SCLK(SCLK_JPEG, "sclk_jpeg", "dout_jpeg", SCLK_GATE, 1),
339};
340
341/* List of clock gates present on S3C6400. */
342GATE_CLOCKS(s3c6400_gate_clks) __initdata = {
343 GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23),
344 GATE_SCLK(SCLK_ONENAND, "sclk_onenand", "parent", SCLK_GATE, 4),
345};
346
347/* List of clock gates present on S3C6410. */
348GATE_CLOCKS(s3c6410_gate_clks) __initdata = {
349 GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31),
350 GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25),
351 GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22),
352 GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21),
353 GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0),
354 GATE_BUS(PCLK_IIC1, "pclk_iic1", "pclk", PCLK_GATE, 27),
355 GATE_BUS(PCLK_IIS2, "pclk_iis2", "pclk", PCLK_GATE, 26),
356 GATE_SCLK(SCLK_FIMC, "sclk_fimc", "dout_fimc", SCLK_GATE, 13),
357 GATE_SCLK(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", SCLK_GATE, 11),
358 GATE_BUS(MEM0_CFCON, "mem0_cfcon", "hclk_mem0", MEM0_GATE, 5),
359 GATE_BUS(MEM0_ONENAND1, "mem0_onenand1", "hclk_mem0", MEM0_GATE, 4),
360 GATE_BUS(MEM0_ONENAND0, "mem0_onenand0", "hclk_mem0", MEM0_GATE, 3),
361 GATE_BUS(MEM0_NFCON, "mem0_nfcon", "hclk_mem0", MEM0_GATE, 2),
362 GATE_ON(MEM0_SROM, "mem0_srom", "hclk_mem0", MEM0_GATE, 1),
363};
364
365/* List of PLL clocks. */
366static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = {
367 [apll] = PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
368 APLL_LOCK, APLL_CON, NULL),
369 [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
370 MPLL_LOCK, MPLL_CON, NULL),
371 [epll] = PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
372 EPLL_LOCK, EPLL_CON0, NULL),
373};
374
375/* Aliases for common s3c64xx clocks. */
376static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
377 ALIAS(FOUT_APLL, NULL, "fout_apll"),
378 ALIAS(FOUT_MPLL, NULL, "fout_mpll"),
379 ALIAS(FOUT_EPLL, NULL, "fout_epll"),
380 ALIAS(MOUT_EPLL, NULL, "mout_epll"),
381 ALIAS(DOUT_MPLL, NULL, "dout_mpll"),
382 ALIAS(HCLKX2, NULL, "hclk2"),
383 ALIAS(HCLK, NULL, "hclk"),
384 ALIAS(PCLK, NULL, "pclk"),
385 ALIAS(PCLK, NULL, "clk_uart_baud2"),
386 ALIAS(ARMCLK, NULL, "armclk"),
387 ALIAS(HCLK_UHOST, "s3c2410-ohci", "usb-host"),
388 ALIAS(HCLK_USB, "s3c-hsotg", "otg"),
389 ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "hsmmc"),
390 ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "mmc_busclk.0"),
391 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
392 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
393 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
394 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
d37f7617 395 ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
d37f7617 396 ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
06dda9d7
TF		 397 ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
398 ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
399 ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
400 ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"),
401 ALIAS(PCLK_IIC0, "s3c2440-i2c.0", "i2c"),
402 ALIAS(PCLK_IIS1, "samsung-i2s.1", "iis"),
403 ALIAS(PCLK_IIS0, "samsung-i2s.0", "iis"),
404 ALIAS(PCLK_AC97, "samsung-ac97", "ac97"),
405 ALIAS(PCLK_TSADC, "s3c64xx-adc", "adc"),
406 ALIAS(PCLK_KEYPAD, "samsung-keypad", "keypad"),
407 ALIAS(PCLK_PCM1, "samsung-pcm.1", "pcm"),
408 ALIAS(PCLK_PCM0, "samsung-pcm.0", "pcm"),
409 ALIAS(PCLK_PWM, NULL, "timers"),
410 ALIAS(PCLK_RTC, "s3c64xx-rtc", "rtc"),
411 ALIAS(PCLK_WDT, NULL, "watchdog"),
412 ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"),
413 ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"),
414 ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),
415 ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
416 ALIAS(SCLK_UHOST, "s3c2410-ohci", "usb-bus-host"),
417 ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"),
418 ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"),
419 ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"),
a92dda4b
CK		 420 ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi_busclk0"),
421 ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi_busclk2"),
422 ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi_busclk0"),
423 ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
06dda9d7
TF		 424 ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"),
425 ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"),
426 ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"),
427 ALIAS(SCLK_AUDIO0, "samsung-i2s.0", "audio-bus"),
428 ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
429 ALIAS(SCLK_CAM, "s3c-camif", "camera"),
430};
431
432/* Aliases for s3c6400-specific clocks. */
433static struct samsung_clock_alias s3c6400_clock_aliases[] = {
434 /* Nothing to place here yet. */
435};
436
437/* Aliases for s3c6410-specific clocks. */
438static struct samsung_clock_alias s3c6410_clock_aliases[] = {
439 ALIAS(PCLK_IIC1, "s3c2440-i2c.1", "i2c"),
440 ALIAS(PCLK_IIS2, "samsung-i2s.2", "iis"),
441 ALIAS(SCLK_FIMC, "s3c-camif", "fimc"),
442 ALIAS(SCLK_AUDIO2, "samsung-i2s.2", "audio-bus"),
443 ALIAS(MEM0_SROM, NULL, "srom"),
444};
445
976face4
RS		 446static void __init s3c64xx_clk_register_fixed_ext(
447 struct samsung_clk_provider *ctx,
448 unsigned long fin_pll_f,
449 unsigned long xusbxti_f)
06dda9d7
TF		 450{
451 s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
452 s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
976face4 453 samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks,
06dda9d7
TF		 454 ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
455}
456
457/* Register s3c64xx clocks. */
458void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
08c0d829
TF		 459 unsigned long xusbxti_f, bool s3c6400,
460 void __iomem *base)
06dda9d7 461{
976face4
RS		 462 struct samsung_clk_provider *ctx;
463
08c0d829
TF		 464 reg_base = base;
465 is_s3c6400 = s3c6400;
06dda9d7
TF		 466
467 if (np) {
468 reg_base = of_iomap(np, 0);
469 if (!reg_base)
470 panic("%s: failed to map registers\n", __func__);
471 }
472
976face4
RS		 473 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
474 if (!ctx)
475 panic("%s: unable to allocate context.\n", __func__);
06dda9d7
TF		 476
477 /* Register external clocks. */
478 if (!np)
976face4 479 s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);
06dda9d7
TF		 480
481 /* Register PLLs. */
976face4 482 samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
06dda9d7
TF		 483 ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
484
485 /* Register common internal clocks. */
976face4 486 samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
06dda9d7 487 ARRAY_SIZE(s3c64xx_fixed_rate_clks));
976face4 488 samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
06dda9d7 489 ARRAY_SIZE(s3c64xx_mux_clks));
976face4 490 samsung_clk_register_div(ctx, s3c64xx_div_clks,
06dda9d7 491 ARRAY_SIZE(s3c64xx_div_clks));
976face4 492 samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
06dda9d7
TF		 493 ARRAY_SIZE(s3c64xx_gate_clks));
494
495 /* Register SoC-specific clocks. */
496 if (is_s3c6400) {
976face4 497 samsung_clk_register_mux(ctx, s3c6400_mux_clks,
06dda9d7 498 ARRAY_SIZE(s3c6400_mux_clks));
976face4 499 samsung_clk_register_div(ctx, s3c6400_div_clks,
06dda9d7 500 ARRAY_SIZE(s3c6400_div_clks));
976face4 501 samsung_clk_register_gate(ctx, s3c6400_gate_clks,
06dda9d7 502 ARRAY_SIZE(s3c6400_gate_clks));
976face4 503 samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
06dda9d7
TF		 504 ARRAY_SIZE(s3c6400_clock_aliases));
505 } else {
976face4 506 samsung_clk_register_mux(ctx, s3c6410_mux_clks,
06dda9d7 507 ARRAY_SIZE(s3c6410_mux_clks));
976face4 508 samsung_clk_register_div(ctx, s3c6410_div_clks,
06dda9d7 509 ARRAY_SIZE(s3c6410_div_clks));
976face4 510 samsung_clk_register_gate(ctx, s3c6410_gate_clks,
06dda9d7 511 ARRAY_SIZE(s3c6410_gate_clks));
976face4 512 samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
06dda9d7
TF		 513 ARRAY_SIZE(s3c6410_clock_aliases));
514 }
515
976face4 516 samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
06dda9d7 517 ARRAY_SIZE(s3c64xx_clock_aliases));
08c0d829 518 s3c64xx_clk_sleep_init();
06dda9d7 519
d5e136a2
SN		 520 samsung_clk_of_add_provider(np, ctx);
521
06dda9d7
TF		 522 pr_info("%s clocks: apll = %lu, mpll = %lu\n"
523 "\tepll = %lu, arm_clk = %lu\n",
524 is_s3c6400 ? "S3C6400" : "S3C6410",
525 _get_rate("fout_apll"), _get_rate("fout_mpll"),
526 _get_rate("fout_epll"), _get_rate("armclk"));
527}
528
529static void __init s3c6400_clk_init(struct device_node *np)
530{
531 s3c64xx_clk_init(np, 0, 0, true, NULL);
532}
533CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init);
534
535static void __init s3c6410_clk_init(struct device_node *np)
536{
537 s3c64xx_clk_init(np, 0, 0, false, NULL);
538}
539CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init);
Linux 6.x block layer and io_uring tree(s)