[linux-2.6-block.git] / drivers / char / hw_random / mtk-rng.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Driver for Mediatek Hardware Random Number Generator
 *
 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
 */
#define MTK_RNG_DEV KBUILD_MODNAME

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/hw_random.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>

/* Runtime PM autosuspend timeout: */
#define RNG_AUTOSUSPEND_TIMEOUT		100

#define USEC_POLL			2
#define TIMEOUT_POLL			20

#define RNG_CTRL			0x00
#define RNG_EN				BIT(0)
#define RNG_READY			BIT(31)

#define RNG_DATA			0x08

#define to_mtk_rng(p)	container_of(p, struct mtk_rng, rng)

struct mtk_rng {
	void __iomem *base;
	struct clk *clk;
	struct hwrng rng;
};

static int mtk_rng_init(struct hwrng *rng)
{
	struct mtk_rng *priv = to_mtk_rng(rng);
	u32 val;
	int err;

	err = clk_prepare_enable(priv->clk);
	if (err)
		return err;

	val = readl(priv->base + RNG_CTRL);
	val |= RNG_EN;
	writel(val, priv->base + RNG_CTRL);

	return 0;
}

static void mtk_rng_cleanup(struct hwrng *rng)
{
	struct mtk_rng *priv = to_mtk_rng(rng);
	u32 val;

	val = readl(priv->base + RNG_CTRL);
	val &= ~RNG_EN;
	writel(val, priv->base + RNG_CTRL);

	clk_disable_unprepare(priv->clk);
}

static bool mtk_rng_wait_ready(struct hwrng *rng, bool wait)
{
	struct mtk_rng *priv = to_mtk_rng(rng);
	int ready;

	ready = readl(priv->base + RNG_CTRL) & RNG_READY;
	if (!ready && wait)
		readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
					  ready & RNG_READY, USEC_POLL,
					  TIMEOUT_POLL);
	return !!ready;
}

static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
	struct mtk_rng *priv = to_mtk_rng(rng);
	int retval = 0;

	pm_runtime_get_sync((struct device *)priv->rng.priv);

	while (max >= sizeof(u32)) {
		if (!mtk_rng_wait_ready(rng, wait))
			break;

		*(u32 *)buf = readl(priv->base + RNG_DATA);
		retval += sizeof(u32);
		buf += sizeof(u32);
		max -= sizeof(u32);
	}

	pm_runtime_mark_last_busy((struct device *)priv->rng.priv);
	pm_runtime_put_sync_autosuspend((struct device *)priv->rng.priv);

	return retval || !wait ? retval : -EIO;
}

static int mtk_rng_probe(struct platform_device *pdev)
{
	int ret;
	struct mtk_rng *priv;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->rng.name = pdev->name;
#ifndef CONFIG_PM
	priv->rng.init = mtk_rng_init;
	priv->rng.cleanup = mtk_rng_cleanup;
#endif
	priv->rng.read = mtk_rng_read;
	priv->rng.priv = (unsigned long)&pdev->dev;
	priv->rng.quality = 900;

	priv->clk = devm_clk_get(&pdev->dev, "rng");
	if (IS_ERR(priv->clk)) {
		ret = PTR_ERR(priv->clk);
		dev_err(&pdev->dev, "no clock for device: %d\n", ret);
		return ret;
	}

	priv->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	ret = devm_hwrng_register(&pdev->dev, &priv->rng);
	if (ret) {
		dev_err(&pdev->dev, "failed to register rng device: %d\n",
			ret);
		return ret;
	}

	dev_set_drvdata(&pdev->dev, priv);
	pm_runtime_set_autosuspend_delay(&pdev->dev, RNG_AUTOSUSPEND_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

	dev_info(&pdev->dev, "registered RNG driver\n");

	return 0;
}

#ifdef CONFIG_PM
static int mtk_rng_runtime_suspend(struct device *dev)
{
	struct mtk_rng *priv = dev_get_drvdata(dev);

	mtk_rng_cleanup(&priv->rng);

	return 0;
}

static int mtk_rng_runtime_resume(struct device *dev)
{
	struct mtk_rng *priv = dev_get_drvdata(dev);

	return mtk_rng_init(&priv->rng);
}

static UNIVERSAL_DEV_PM_OPS(mtk_rng_pm_ops, mtk_rng_runtime_suspend,
			    mtk_rng_runtime_resume, NULL);
#define MTK_RNG_PM_OPS (&mtk_rng_pm_ops)
#else	/* CONFIG_PM */
#define MTK_RNG_PM_OPS NULL
#endif	/* CONFIG_PM */

static const struct of_device_id mtk_rng_match[] = {
	{ .compatible = "mediatek,mt7623-rng" },
	{},
};
MODULE_DEVICE_TABLE(of, mtk_rng_match);

static struct platform_driver mtk_rng_driver = {
	.probe          = mtk_rng_probe,
	.driver = {
		.name = MTK_RNG_DEV,
		.pm = MTK_RNG_PM_OPS,
		.of_match_table = mtk_rng_match,
	},
};

module_platform_driver(mtk_rng_driver);

MODULE_DESCRIPTION("Mediatek Random Number Generator Driver");
MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
7701d1ff SW	2	/*
	3	* Driver for Mediatek Hardware Random Number Generator
	4	*
	5	* Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
7701d1ff SW	6	*/
	7	#define MTK_RNG_DEV KBUILD_MODNAME
	8
	9	#include <linux/clk.h>
	10	#include <linux/delay.h>
	11	#include <linux/err.h>
	12	#include <linux/hw_random.h>
	13	#include <linux/io.h>
	14	#include <linux/iopoll.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/platform_device.h>
81d2b345 SW	19	#include <linux/pm_runtime.h>
	20
	21	/* Runtime PM autosuspend timeout: */
	22	#define RNG_AUTOSUSPEND_TIMEOUT 100
7701d1ff SW	23
	24	#define USEC_POLL 2
	25	#define TIMEOUT_POLL 20
	26
	27	#define RNG_CTRL 0x00
	28	#define RNG_EN BIT(0)
	29	#define RNG_READY BIT(31)
	30
	31	#define RNG_DATA 0x08
	32
	33	#define to_mtk_rng(p) container_of(p, struct mtk_rng, rng)
	34
	35	struct mtk_rng {
	36	void __iomem *base;
	37	struct clk *clk;
	38	struct hwrng rng;
	39	};
	40
	41	static int mtk_rng_init(struct hwrng *rng)
	42	{
	43	struct mtk_rng *priv = to_mtk_rng(rng);
	44	u32 val;
	45	int err;
	46
	47	err = clk_prepare_enable(priv->clk);
	48	if (err)
	49	return err;
	50
	51	val = readl(priv->base + RNG_CTRL);
	52	val \|= RNG_EN;
	53	writel(val, priv->base + RNG_CTRL);
	54
	55	return 0;
	56	}
	57
	58	static void mtk_rng_cleanup(struct hwrng *rng)
	59	{
	60	struct mtk_rng *priv = to_mtk_rng(rng);
	61	u32 val;
	62
	63	val = readl(priv->base + RNG_CTRL);
	64	val &= ~RNG_EN;
	65	writel(val, priv->base + RNG_CTRL);
	66
	67	clk_disable_unprepare(priv->clk);
	68	}
	69
	70	static bool mtk_rng_wait_ready(struct hwrng *rng, bool wait)
	71	{
	72	struct mtk_rng *priv = to_mtk_rng(rng);
	73	int ready;
	74
	75	ready = readl(priv->base + RNG_CTRL) & RNG_READY;
	76	if (!ready && wait)
	77	readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
	78	ready & RNG_READY, USEC_POLL,
	79	TIMEOUT_POLL);
	80	return !!ready;
	81	}
	82
	83	static int mtk_rng_read(struct hwrng rng, void buf, size_t max, bool wait)
	84	{
	85	struct mtk_rng *priv = to_mtk_rng(rng);
	86	int retval = 0;
87
81d2b345 SW	88	pm_runtime_get_sync((struct device *)priv->rng.priv);
81d2b345 SW	89
7701d1ff SW	90	while (max >= sizeof(u32)) {
	91	if (!mtk_rng_wait_ready(rng, wait))
	92	break;
	93
	94	(u32 )buf = readl(priv->base + RNG_DATA);
	95	retval += sizeof(u32);
	96	buf += sizeof(u32);
	97	max -= sizeof(u32);
	98	}
	99
81d2b345 SW	100	pm_runtime_mark_last_busy((struct device *)priv->rng.priv);
	101	pm_runtime_put_sync_autosuspend((struct device *)priv->rng.priv);
	102
7701d1ff SW	103	return retval \|\| !wait ? retval : -EIO;
	104	}
	105
	106	static int mtk_rng_probe(struct platform_device *pdev)
	107	{
7701d1ff SW	108	int ret;
	109	struct mtk_rng *priv;
	110
7701d1ff SW	111	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	112	if (!priv)
	113	return -ENOMEM;
	114
	115	priv->rng.name = pdev->name;
81d2b345	116	#ifndef CONFIG_PM
7701d1ff SW	117	priv->rng.init = mtk_rng_init;
7701d1ff SW	118	priv->rng.cleanup = mtk_rng_cleanup;
81d2b345	119	#endif
7701d1ff	120	priv->rng.read = mtk_rng_read;
81d2b345	121	priv->rng.priv = (unsigned long)&pdev->dev;
4565da7c	122	priv->rng.quality = 900;
7701d1ff SW	123
	124	priv->clk = devm_clk_get(&pdev->dev, "rng");
	125	if (IS_ERR(priv->clk)) {
	126	ret = PTR_ERR(priv->clk);
	127	dev_err(&pdev->dev, "no clock for device: %d\n", ret);
	128	return ret;
	129	}
	130
0600e9c0	131	priv->base = devm_platform_ioremap_resource(pdev, 0);
7701d1ff SW	132	if (IS_ERR(priv->base))
	133	return PTR_ERR(priv->base);
	134
	135	ret = devm_hwrng_register(&pdev->dev, &priv->rng);
	136	if (ret) {
	137	dev_err(&pdev->dev, "failed to register rng device: %d\n",
	138	ret);
	139	return ret;
	140	}
	141
81d2b345 SW	142	dev_set_drvdata(&pdev->dev, priv);
	143	pm_runtime_set_autosuspend_delay(&pdev->dev, RNG_AUTOSUSPEND_TIMEOUT);
	144	pm_runtime_use_autosuspend(&pdev->dev);
	145	pm_runtime_enable(&pdev->dev);
	146
7701d1ff SW	147	dev_info(&pdev->dev, "registered RNG driver\n");
	148
	149	return 0;
	150	}
	151
81d2b345 SW	152	#ifdef CONFIG_PM
	153	static int mtk_rng_runtime_suspend(struct device *dev)
	154	{
	155	struct mtk_rng *priv = dev_get_drvdata(dev);
	156
	157	mtk_rng_cleanup(&priv->rng);
	158
	159	return 0;
	160	}
	161
	162	static int mtk_rng_runtime_resume(struct device *dev)
	163	{
	164	struct mtk_rng *priv = dev_get_drvdata(dev);
	165
	166	return mtk_rng_init(&priv->rng);
	167	}
	168
	169	static UNIVERSAL_DEV_PM_OPS(mtk_rng_pm_ops, mtk_rng_runtime_suspend,
	170	mtk_rng_runtime_resume, NULL);
	171	#define MTK_RNG_PM_OPS (&mtk_rng_pm_ops)
	172	#else /* CONFIG_PM */
	173	#define MTK_RNG_PM_OPS NULL
	174	#endif /* CONFIG_PM */
	175
7701d1ff SW	176	static const struct of_device_id mtk_rng_match[] = {
	177	{ .compatible = "mediatek,mt7623-rng" },
	178	{},
	179	};
	180	MODULE_DEVICE_TABLE(of, mtk_rng_match);
	181
	182	static struct platform_driver mtk_rng_driver = {
	183	.probe = mtk_rng_probe,
	184	.driver = {
	185	.name = MTK_RNG_DEV,
81d2b345	186	.pm = MTK_RNG_PM_OPS,
7701d1ff SW	187	.of_match_table = mtk_rng_match,
	188	},
	189	};
	190
	191	module_platform_driver(mtk_rng_driver);
	192
	193	MODULE_DESCRIPTION("Mediatek Random Number Generator Driver");
	194	MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
	195	MODULE_LICENSE("GPL");