Commit | Line | Data |
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f26c473c DA |
1 | /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ |
2 | /* | |
1da177e4 LT |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * All Rights Reserved. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the "Software"), | |
9 | * to deal in the Software without restriction, including without limitation | |
10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
11 | * and/or sell copies of the Software, and to permit persons to whom the | |
12 | * Software is furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the next | |
15 | * paragraph) shall be included in all copies or substantial portions of the | |
16 | * Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
24 | * DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | */ | |
30 | ||
31 | #include "drmP.h" | |
32 | #include "drm.h" | |
33 | #include "radeon_drm.h" | |
34 | #include "radeon_drv.h" | |
414ed537 | 35 | #include "r300_reg.h" |
1da177e4 | 36 | |
9f18409e AD |
37 | #include "radeon_microcode.h" |
38 | ||
1da177e4 LT |
39 | #define RADEON_FIFO_DEBUG 0 |
40 | ||
84b1fd10 | 41 | static int radeon_do_cleanup_cp(struct drm_device * dev); |
1da177e4 | 42 | |
3d5e2c13 DA |
43 | static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
44 | { | |
45 | u32 ret; | |
46 | RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); | |
47 | ret = RADEON_READ(R520_MC_IND_DATA); | |
48 | RADEON_WRITE(R520_MC_IND_INDEX, 0); | |
49 | return ret; | |
50 | } | |
51 | ||
60f92683 MC |
52 | static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
53 | { | |
54 | RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); | |
55 | return RADEON_READ(RS690_MC_DATA); | |
56 | } | |
57 | ||
3d5e2c13 DA |
58 | u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) |
59 | { | |
60 | ||
61 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
62 | return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); | |
60f92683 MC |
63 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
64 | return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); | |
3d5e2c13 DA |
65 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
66 | return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); | |
67 | else | |
68 | return RADEON_READ(RADEON_MC_FB_LOCATION); | |
69 | } | |
70 | ||
71 | static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) | |
72 | { | |
73 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
74 | RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); | |
60f92683 MC |
75 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
76 | RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); | |
3d5e2c13 DA |
77 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
78 | RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); | |
79 | else | |
80 | RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); | |
81 | } | |
82 | ||
83 | static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) | |
84 | { | |
85 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
86 | RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); | |
60f92683 MC |
87 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
88 | RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); | |
3d5e2c13 DA |
89 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
90 | RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); | |
91 | else | |
92 | RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); | |
93 | } | |
94 | ||
84b1fd10 | 95 | static int RADEON_READ_PLL(struct drm_device * dev, int addr) |
1da177e4 LT |
96 | { |
97 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
98 | ||
99 | RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); | |
100 | return RADEON_READ(RADEON_CLOCK_CNTL_DATA); | |
101 | } | |
102 | ||
3d5e2c13 | 103 | static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) |
ea98a92f DA |
104 | { |
105 | RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); | |
106 | return RADEON_READ(RADEON_PCIE_DATA); | |
107 | } | |
108 | ||
f2b04cd2 DA |
109 | static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr) |
110 | { | |
111 | u32 ret; | |
112 | RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f); | |
113 | ret = RADEON_READ(RADEON_IGPGART_DATA); | |
114 | RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f); | |
115 | return ret; | |
116 | } | |
117 | ||
1da177e4 | 118 | #if RADEON_FIFO_DEBUG |
b5e89ed5 | 119 | static void radeon_status(drm_radeon_private_t * dev_priv) |
1da177e4 | 120 | { |
bf9d8929 | 121 | printk("%s:\n", __func__); |
b5e89ed5 DA |
122 | printk("RBBM_STATUS = 0x%08x\n", |
123 | (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); | |
124 | printk("CP_RB_RTPR = 0x%08x\n", | |
125 | (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); | |
126 | printk("CP_RB_WTPR = 0x%08x\n", | |
127 | (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); | |
128 | printk("AIC_CNTL = 0x%08x\n", | |
129 | (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); | |
130 | printk("AIC_STAT = 0x%08x\n", | |
131 | (unsigned int)RADEON_READ(RADEON_AIC_STAT)); | |
132 | printk("AIC_PT_BASE = 0x%08x\n", | |
133 | (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); | |
134 | printk("TLB_ADDR = 0x%08x\n", | |
135 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); | |
136 | printk("TLB_DATA = 0x%08x\n", | |
137 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); | |
1da177e4 LT |
138 | } |
139 | #endif | |
140 | ||
1da177e4 LT |
141 | /* ================================================================ |
142 | * Engine, FIFO control | |
143 | */ | |
144 | ||
b5e89ed5 | 145 | static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
146 | { |
147 | u32 tmp; | |
148 | int i; | |
149 | ||
150 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
151 | ||
b9b603dd MD |
152 | tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); |
153 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | |
154 | RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); | |
1da177e4 | 155 | |
b5e89ed5 | 156 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
b9b603dd MD |
157 | if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) |
158 | & RADEON_RB3D_DC_BUSY)) { | |
1da177e4 LT |
159 | return 0; |
160 | } | |
b5e89ed5 | 161 | DRM_UDELAY(1); |
1da177e4 LT |
162 | } |
163 | ||
164 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
165 | DRM_ERROR("failed!\n"); |
166 | radeon_status(dev_priv); | |
1da177e4 | 167 | #endif |
20caafa6 | 168 | return -EBUSY; |
1da177e4 LT |
169 | } |
170 | ||
b5e89ed5 | 171 | static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) |
1da177e4 LT |
172 | { |
173 | int i; | |
174 | ||
175 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
176 | ||
b5e89ed5 DA |
177 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
178 | int slots = (RADEON_READ(RADEON_RBBM_STATUS) | |
179 | & RADEON_RBBM_FIFOCNT_MASK); | |
180 | if (slots >= entries) | |
181 | return 0; | |
182 | DRM_UDELAY(1); | |
1da177e4 LT |
183 | } |
184 | ||
185 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
186 | DRM_ERROR("failed!\n"); |
187 | radeon_status(dev_priv); | |
1da177e4 | 188 | #endif |
20caafa6 | 189 | return -EBUSY; |
1da177e4 LT |
190 | } |
191 | ||
b5e89ed5 | 192 | static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
193 | { |
194 | int i, ret; | |
195 | ||
196 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
197 | ||
b5e89ed5 DA |
198 | ret = radeon_do_wait_for_fifo(dev_priv, 64); |
199 | if (ret) | |
200 | return ret; | |
1da177e4 | 201 | |
b5e89ed5 DA |
202 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
203 | if (!(RADEON_READ(RADEON_RBBM_STATUS) | |
204 | & RADEON_RBBM_ACTIVE)) { | |
205 | radeon_do_pixcache_flush(dev_priv); | |
1da177e4 LT |
206 | return 0; |
207 | } | |
b5e89ed5 | 208 | DRM_UDELAY(1); |
1da177e4 LT |
209 | } |
210 | ||
211 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
212 | DRM_ERROR("failed!\n"); |
213 | radeon_status(dev_priv); | |
1da177e4 | 214 | #endif |
20caafa6 | 215 | return -EBUSY; |
1da177e4 LT |
216 | } |
217 | ||
1da177e4 LT |
218 | /* ================================================================ |
219 | * CP control, initialization | |
220 | */ | |
221 | ||
222 | /* Load the microcode for the CP */ | |
b5e89ed5 | 223 | static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
224 | { |
225 | int i; | |
b5e89ed5 | 226 | DRM_DEBUG("\n"); |
1da177e4 | 227 | |
b5e89ed5 | 228 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 229 | |
b5e89ed5 | 230 | RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); |
9f18409e AD |
231 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || |
232 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || | |
233 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || | |
234 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || | |
235 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { | |
236 | DRM_INFO("Loading R100 Microcode\n"); | |
237 | for (i = 0; i < 256; i++) { | |
238 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
239 | R100_cp_microcode[i][1]); | |
240 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
241 | R100_cp_microcode[i][0]); | |
242 | } | |
243 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || | |
244 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || | |
245 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || | |
246 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { | |
1da177e4 | 247 | DRM_INFO("Loading R200 Microcode\n"); |
b5e89ed5 DA |
248 | for (i = 0; i < 256; i++) { |
249 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
250 | R200_cp_microcode[i][1]); | |
251 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
252 | R200_cp_microcode[i][0]); | |
1da177e4 | 253 | } |
9f18409e AD |
254 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || |
255 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || | |
256 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || | |
257 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || | |
258 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400)) { | |
1da177e4 | 259 | DRM_INFO("Loading R300 Microcode\n"); |
b5e89ed5 DA |
260 | for (i = 0; i < 256; i++) { |
261 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
262 | R300_cp_microcode[i][1]); | |
263 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
264 | R300_cp_microcode[i][0]); | |
1da177e4 | 265 | } |
9f18409e AD |
266 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || |
267 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { | |
268 | DRM_INFO("Loading R400 Microcode\n"); | |
269 | for (i = 0; i < 256; i++) { | |
270 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
271 | R420_cp_microcode[i][1]); | |
272 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
273 | R420_cp_microcode[i][0]); | |
274 | } | |
275 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { | |
276 | DRM_INFO("Loading RS690 Microcode\n"); | |
277 | for (i = 0; i < 256; i++) { | |
278 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
279 | RS690_cp_microcode[i][1]); | |
280 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
281 | RS690_cp_microcode[i][0]); | |
282 | } | |
283 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || | |
284 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || | |
285 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || | |
286 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || | |
287 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || | |
288 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { | |
289 | DRM_INFO("Loading R500 Microcode\n"); | |
b5e89ed5 DA |
290 | for (i = 0; i < 256; i++) { |
291 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
9f18409e | 292 | R520_cp_microcode[i][1]); |
b5e89ed5 | 293 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, |
9f18409e | 294 | R520_cp_microcode[i][0]); |
1da177e4 LT |
295 | } |
296 | } | |
297 | } | |
298 | ||
299 | /* Flush any pending commands to the CP. This should only be used just | |
300 | * prior to a wait for idle, as it informs the engine that the command | |
301 | * stream is ending. | |
302 | */ | |
b5e89ed5 | 303 | static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) |
1da177e4 | 304 | { |
b5e89ed5 | 305 | DRM_DEBUG("\n"); |
1da177e4 LT |
306 | #if 0 |
307 | u32 tmp; | |
308 | ||
b5e89ed5 DA |
309 | tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); |
310 | RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); | |
1da177e4 LT |
311 | #endif |
312 | } | |
313 | ||
314 | /* Wait for the CP to go idle. | |
315 | */ | |
b5e89ed5 | 316 | int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
317 | { |
318 | RING_LOCALS; | |
b5e89ed5 | 319 | DRM_DEBUG("\n"); |
1da177e4 | 320 | |
b5e89ed5 | 321 | BEGIN_RING(6); |
1da177e4 LT |
322 | |
323 | RADEON_PURGE_CACHE(); | |
324 | RADEON_PURGE_ZCACHE(); | |
325 | RADEON_WAIT_UNTIL_IDLE(); | |
326 | ||
327 | ADVANCE_RING(); | |
328 | COMMIT_RING(); | |
329 | ||
b5e89ed5 | 330 | return radeon_do_wait_for_idle(dev_priv); |
1da177e4 LT |
331 | } |
332 | ||
333 | /* Start the Command Processor. | |
334 | */ | |
b5e89ed5 | 335 | static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
336 | { |
337 | RING_LOCALS; | |
b5e89ed5 | 338 | DRM_DEBUG("\n"); |
1da177e4 | 339 | |
b5e89ed5 | 340 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 341 | |
b5e89ed5 | 342 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); |
1da177e4 LT |
343 | |
344 | dev_priv->cp_running = 1; | |
345 | ||
b5e89ed5 | 346 | BEGIN_RING(6); |
1da177e4 LT |
347 | |
348 | RADEON_PURGE_CACHE(); | |
349 | RADEON_PURGE_ZCACHE(); | |
350 | RADEON_WAIT_UNTIL_IDLE(); | |
351 | ||
352 | ADVANCE_RING(); | |
353 | COMMIT_RING(); | |
354 | } | |
355 | ||
356 | /* Reset the Command Processor. This will not flush any pending | |
357 | * commands, so you must wait for the CP command stream to complete | |
358 | * before calling this routine. | |
359 | */ | |
b5e89ed5 | 360 | static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
361 | { |
362 | u32 cur_read_ptr; | |
b5e89ed5 | 363 | DRM_DEBUG("\n"); |
1da177e4 | 364 | |
b5e89ed5 DA |
365 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
366 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); | |
367 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
1da177e4 LT |
368 | dev_priv->ring.tail = cur_read_ptr; |
369 | } | |
370 | ||
371 | /* Stop the Command Processor. This will not flush any pending | |
372 | * commands, so you must flush the command stream and wait for the CP | |
373 | * to go idle before calling this routine. | |
374 | */ | |
b5e89ed5 | 375 | static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) |
1da177e4 | 376 | { |
b5e89ed5 | 377 | DRM_DEBUG("\n"); |
1da177e4 | 378 | |
b5e89ed5 | 379 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); |
1da177e4 LT |
380 | |
381 | dev_priv->cp_running = 0; | |
382 | } | |
383 | ||
384 | /* Reset the engine. This will stop the CP if it is running. | |
385 | */ | |
84b1fd10 | 386 | static int radeon_do_engine_reset(struct drm_device * dev) |
1da177e4 LT |
387 | { |
388 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
389 | u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; | |
b5e89ed5 | 390 | DRM_DEBUG("\n"); |
1da177e4 | 391 | |
b5e89ed5 DA |
392 | radeon_do_pixcache_flush(dev_priv); |
393 | ||
3d5e2c13 DA |
394 | if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { |
395 | clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); | |
396 | mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); | |
397 | ||
398 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | | |
399 | RADEON_FORCEON_MCLKA | | |
400 | RADEON_FORCEON_MCLKB | | |
401 | RADEON_FORCEON_YCLKA | | |
402 | RADEON_FORCEON_YCLKB | | |
403 | RADEON_FORCEON_MC | | |
404 | RADEON_FORCEON_AIC)); | |
405 | ||
406 | rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
407 | ||
408 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | | |
409 | RADEON_SOFT_RESET_CP | | |
410 | RADEON_SOFT_RESET_HI | | |
411 | RADEON_SOFT_RESET_SE | | |
412 | RADEON_SOFT_RESET_RE | | |
413 | RADEON_SOFT_RESET_PP | | |
414 | RADEON_SOFT_RESET_E2 | | |
415 | RADEON_SOFT_RESET_RB)); | |
416 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
417 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & | |
418 | ~(RADEON_SOFT_RESET_CP | | |
419 | RADEON_SOFT_RESET_HI | | |
420 | RADEON_SOFT_RESET_SE | | |
421 | RADEON_SOFT_RESET_RE | | |
422 | RADEON_SOFT_RESET_PP | | |
423 | RADEON_SOFT_RESET_E2 | | |
424 | RADEON_SOFT_RESET_RB))); | |
425 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
426 | ||
427 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); | |
428 | RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); | |
429 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); | |
430 | } | |
1da177e4 LT |
431 | |
432 | /* Reset the CP ring */ | |
b5e89ed5 | 433 | radeon_do_cp_reset(dev_priv); |
1da177e4 LT |
434 | |
435 | /* The CP is no longer running after an engine reset */ | |
436 | dev_priv->cp_running = 0; | |
437 | ||
438 | /* Reset any pending vertex, indirect buffers */ | |
b5e89ed5 | 439 | radeon_freelist_reset(dev); |
1da177e4 LT |
440 | |
441 | return 0; | |
442 | } | |
443 | ||
84b1fd10 | 444 | static void radeon_cp_init_ring_buffer(struct drm_device * dev, |
b5e89ed5 | 445 | drm_radeon_private_t * dev_priv) |
1da177e4 LT |
446 | { |
447 | u32 ring_start, cur_read_ptr; | |
448 | u32 tmp; | |
bc5f4523 | 449 | |
d5ea702f DA |
450 | /* Initialize the memory controller. With new memory map, the fb location |
451 | * is not changed, it should have been properly initialized already. Part | |
452 | * of the problem is that the code below is bogus, assuming the GART is | |
453 | * always appended to the fb which is not necessarily the case | |
454 | */ | |
455 | if (!dev_priv->new_memmap) | |
3d5e2c13 | 456 | radeon_write_fb_location(dev_priv, |
d5ea702f DA |
457 | ((dev_priv->gart_vm_start - 1) & 0xffff0000) |
458 | | (dev_priv->fb_location >> 16)); | |
1da177e4 LT |
459 | |
460 | #if __OS_HAS_AGP | |
54a56ac5 | 461 | if (dev_priv->flags & RADEON_IS_AGP) { |
d5ea702f | 462 | RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); |
3d5e2c13 | 463 | radeon_write_agp_location(dev_priv, |
b5e89ed5 DA |
464 | (((dev_priv->gart_vm_start - 1 + |
465 | dev_priv->gart_size) & 0xffff0000) | | |
466 | (dev_priv->gart_vm_start >> 16))); | |
1da177e4 LT |
467 | |
468 | ring_start = (dev_priv->cp_ring->offset | |
469 | - dev->agp->base | |
470 | + dev_priv->gart_vm_start); | |
b0917bd9 | 471 | } else |
1da177e4 LT |
472 | #endif |
473 | ring_start = (dev_priv->cp_ring->offset | |
b0917bd9 | 474 | - (unsigned long)dev->sg->virtual |
1da177e4 LT |
475 | + dev_priv->gart_vm_start); |
476 | ||
b5e89ed5 | 477 | RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); |
1da177e4 LT |
478 | |
479 | /* Set the write pointer delay */ | |
b5e89ed5 | 480 | RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); |
1da177e4 LT |
481 | |
482 | /* Initialize the ring buffer's read and write pointers */ | |
b5e89ed5 DA |
483 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
484 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); | |
485 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
1da177e4 LT |
486 | dev_priv->ring.tail = cur_read_ptr; |
487 | ||
488 | #if __OS_HAS_AGP | |
54a56ac5 | 489 | if (dev_priv->flags & RADEON_IS_AGP) { |
b5e89ed5 DA |
490 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, |
491 | dev_priv->ring_rptr->offset | |
492 | - dev->agp->base + dev_priv->gart_vm_start); | |
1da177e4 LT |
493 | } else |
494 | #endif | |
495 | { | |
55910517 | 496 | struct drm_sg_mem *entry = dev->sg; |
1da177e4 LT |
497 | unsigned long tmp_ofs, page_ofs; |
498 | ||
b0917bd9 IK |
499 | tmp_ofs = dev_priv->ring_rptr->offset - |
500 | (unsigned long)dev->sg->virtual; | |
1da177e4 LT |
501 | page_ofs = tmp_ofs >> PAGE_SHIFT; |
502 | ||
b5e89ed5 DA |
503 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); |
504 | DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", | |
505 | (unsigned long)entry->busaddr[page_ofs], | |
506 | entry->handle + tmp_ofs); | |
1da177e4 LT |
507 | } |
508 | ||
d5ea702f DA |
509 | /* Set ring buffer size */ |
510 | #ifdef __BIG_ENDIAN | |
511 | RADEON_WRITE(RADEON_CP_RB_CNTL, | |
576cc458 RS |
512 | RADEON_BUF_SWAP_32BIT | |
513 | (dev_priv->ring.fetch_size_l2ow << 18) | | |
514 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
515 | dev_priv->ring.size_l2qw); | |
d5ea702f | 516 | #else |
576cc458 RS |
517 | RADEON_WRITE(RADEON_CP_RB_CNTL, |
518 | (dev_priv->ring.fetch_size_l2ow << 18) | | |
519 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
520 | dev_priv->ring.size_l2qw); | |
d5ea702f DA |
521 | #endif |
522 | ||
523 | /* Start with assuming that writeback doesn't work */ | |
524 | dev_priv->writeback_works = 0; | |
525 | ||
1da177e4 LT |
526 | /* Initialize the scratch register pointer. This will cause |
527 | * the scratch register values to be written out to memory | |
528 | * whenever they are updated. | |
529 | * | |
530 | * We simply put this behind the ring read pointer, this works | |
531 | * with PCI GART as well as (whatever kind of) AGP GART | |
532 | */ | |
b5e89ed5 DA |
533 | RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) |
534 | + RADEON_SCRATCH_REG_OFFSET); | |
1da177e4 LT |
535 | |
536 | dev_priv->scratch = ((__volatile__ u32 *) | |
537 | dev_priv->ring_rptr->handle + | |
538 | (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); | |
539 | ||
b5e89ed5 | 540 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); |
1da177e4 | 541 | |
d5ea702f DA |
542 | /* Turn on bus mastering */ |
543 | tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; | |
544 | RADEON_WRITE(RADEON_BUS_CNTL, tmp); | |
1da177e4 LT |
545 | |
546 | dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; | |
b5e89ed5 | 547 | RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); |
1da177e4 LT |
548 | |
549 | dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; | |
b5e89ed5 DA |
550 | RADEON_WRITE(RADEON_LAST_DISPATCH_REG, |
551 | dev_priv->sarea_priv->last_dispatch); | |
1da177e4 LT |
552 | |
553 | dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; | |
b5e89ed5 | 554 | RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); |
1da177e4 | 555 | |
b5e89ed5 | 556 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 557 | |
1da177e4 | 558 | /* Sync everything up */ |
b5e89ed5 DA |
559 | RADEON_WRITE(RADEON_ISYNC_CNTL, |
560 | (RADEON_ISYNC_ANY2D_IDLE3D | | |
561 | RADEON_ISYNC_ANY3D_IDLE2D | | |
562 | RADEON_ISYNC_WAIT_IDLEGUI | | |
563 | RADEON_ISYNC_CPSCRATCH_IDLEGUI)); | |
d5ea702f DA |
564 | |
565 | } | |
566 | ||
567 | static void radeon_test_writeback(drm_radeon_private_t * dev_priv) | |
568 | { | |
569 | u32 tmp; | |
570 | ||
571 | /* Writeback doesn't seem to work everywhere, test it here and possibly | |
572 | * enable it if it appears to work | |
573 | */ | |
574 | DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); | |
575 | RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); | |
576 | ||
577 | for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { | |
578 | if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == | |
579 | 0xdeadbeef) | |
580 | break; | |
581 | DRM_UDELAY(1); | |
582 | } | |
583 | ||
584 | if (tmp < dev_priv->usec_timeout) { | |
585 | dev_priv->writeback_works = 1; | |
586 | DRM_INFO("writeback test succeeded in %d usecs\n", tmp); | |
587 | } else { | |
588 | dev_priv->writeback_works = 0; | |
589 | DRM_INFO("writeback test failed\n"); | |
590 | } | |
591 | if (radeon_no_wb == 1) { | |
592 | dev_priv->writeback_works = 0; | |
593 | DRM_INFO("writeback forced off\n"); | |
594 | } | |
ae1b1a48 MD |
595 | |
596 | if (!dev_priv->writeback_works) { | |
597 | /* Disable writeback to avoid unnecessary bus master transfer */ | |
598 | RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | | |
599 | RADEON_RB_NO_UPDATE); | |
600 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); | |
601 | } | |
1da177e4 LT |
602 | } |
603 | ||
f2b04cd2 DA |
604 | /* Enable or disable IGP GART on the chip */ |
605 | static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) | |
606 | { | |
607 | u32 temp, tmp; | |
608 | ||
609 | tmp = RADEON_READ(RADEON_AIC_CNTL); | |
610 | if (on) { | |
611 | DRM_DEBUG("programming igpgart %08X %08lX %08X\n", | |
612 | dev_priv->gart_vm_start, | |
613 | (long)dev_priv->gart_info.bus_addr, | |
614 | dev_priv->gart_size); | |
615 | ||
616 | RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000); | |
617 | RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1); | |
618 | RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800); | |
619 | RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR, | |
620 | dev_priv->gart_info.bus_addr); | |
621 | ||
622 | temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39); | |
623 | RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp); | |
624 | ||
625 | RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start); | |
626 | dev_priv->gart_size = 32*1024*1024; | |
3d5e2c13 | 627 | radeon_write_agp_location(dev_priv, |
f2b04cd2 DA |
628 | (((dev_priv->gart_vm_start - 1 + |
629 | dev_priv->gart_size) & 0xffff0000) | | |
630 | (dev_priv->gart_vm_start >> 16))); | |
631 | ||
632 | temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE); | |
633 | RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp); | |
634 | ||
635 | RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); | |
636 | RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1); | |
637 | RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); | |
638 | RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0); | |
639 | } | |
640 | } | |
641 | ||
60f92683 MC |
642 | /* Enable or disable RS690 GART on the chip */ |
643 | static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on) | |
644 | { | |
645 | u32 temp; | |
646 | ||
647 | if (on) { | |
648 | DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n", | |
649 | dev_priv->gart_vm_start, | |
650 | (long)dev_priv->gart_info.bus_addr, | |
651 | dev_priv->gart_size); | |
652 | ||
653 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL); | |
654 | RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000); | |
655 | ||
656 | RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, | |
657 | RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); | |
658 | ||
659 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID); | |
660 | RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800); | |
661 | ||
fa0d71b9 DA |
662 | temp = dev_priv->gart_info.bus_addr & 0xfffff000; |
663 | temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; | |
664 | RS690_WRITE_MCIND(RS690_MC_GART_BASE, temp); | |
60f92683 MC |
665 | |
666 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL); | |
667 | RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000); | |
668 | ||
669 | RS690_WRITE_MCIND(RS690_MC_AGP_BASE, | |
670 | (unsigned int)dev_priv->gart_vm_start); | |
671 | ||
672 | dev_priv->gart_size = 32*1024*1024; | |
673 | temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & | |
674 | 0xffff0000) | (dev_priv->gart_vm_start >> 16)); | |
675 | ||
676 | RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp); | |
677 | ||
678 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE); | |
679 | RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, | |
680 | RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); | |
681 | ||
682 | do { | |
683 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); | |
684 | if ((temp & RS690_MC_GART_CLEAR_STATUS) == | |
685 | RS690_MC_GART_CLEAR_DONE) | |
686 | break; | |
687 | DRM_UDELAY(1); | |
688 | } while (1); | |
689 | ||
690 | RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, | |
691 | RS690_MC_GART_CC_CLEAR); | |
692 | do { | |
693 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); | |
694 | if ((temp & RS690_MC_GART_CLEAR_STATUS) == | |
695 | RS690_MC_GART_CLEAR_DONE) | |
696 | break; | |
697 | DRM_UDELAY(1); | |
698 | } while (1); | |
699 | ||
700 | RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, | |
701 | RS690_MC_GART_CC_NO_CHANGE); | |
702 | } else { | |
703 | RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS); | |
704 | } | |
705 | } | |
706 | ||
ea98a92f DA |
707 | static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) |
708 | { | |
709 | u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); | |
710 | if (on) { | |
711 | ||
712 | DRM_DEBUG("programming pcie %08X %08lX %08X\n", | |
b5e89ed5 DA |
713 | dev_priv->gart_vm_start, |
714 | (long)dev_priv->gart_info.bus_addr, | |
ea98a92f | 715 | dev_priv->gart_size); |
b5e89ed5 DA |
716 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, |
717 | dev_priv->gart_vm_start); | |
718 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, | |
719 | dev_priv->gart_info.bus_addr); | |
720 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, | |
721 | dev_priv->gart_vm_start); | |
722 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, | |
723 | dev_priv->gart_vm_start + | |
724 | dev_priv->gart_size - 1); | |
725 | ||
3d5e2c13 | 726 | radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ |
b5e89ed5 DA |
727 | |
728 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, | |
729 | RADEON_PCIE_TX_GART_EN); | |
ea98a92f | 730 | } else { |
b5e89ed5 DA |
731 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
732 | tmp & ~RADEON_PCIE_TX_GART_EN); | |
ea98a92f | 733 | } |
1da177e4 LT |
734 | } |
735 | ||
736 | /* Enable or disable PCI GART on the chip */ | |
b5e89ed5 | 737 | static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) |
1da177e4 | 738 | { |
d985c108 | 739 | u32 tmp; |
1da177e4 | 740 | |
60f92683 MC |
741 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { |
742 | radeon_set_rs690gart(dev_priv, on); | |
743 | return; | |
744 | } | |
745 | ||
f2b04cd2 DA |
746 | if (dev_priv->flags & RADEON_IS_IGPGART) { |
747 | radeon_set_igpgart(dev_priv, on); | |
748 | return; | |
749 | } | |
750 | ||
54a56ac5 | 751 | if (dev_priv->flags & RADEON_IS_PCIE) { |
ea98a92f DA |
752 | radeon_set_pciegart(dev_priv, on); |
753 | return; | |
754 | } | |
1da177e4 | 755 | |
bc5f4523 | 756 | tmp = RADEON_READ(RADEON_AIC_CNTL); |
d985c108 | 757 | |
b5e89ed5 DA |
758 | if (on) { |
759 | RADEON_WRITE(RADEON_AIC_CNTL, | |
760 | tmp | RADEON_PCIGART_TRANSLATE_EN); | |
1da177e4 LT |
761 | |
762 | /* set PCI GART page-table base address | |
763 | */ | |
ea98a92f | 764 | RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); |
1da177e4 LT |
765 | |
766 | /* set address range for PCI address translate | |
767 | */ | |
b5e89ed5 DA |
768 | RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); |
769 | RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start | |
770 | + dev_priv->gart_size - 1); | |
1da177e4 LT |
771 | |
772 | /* Turn off AGP aperture -- is this required for PCI GART? | |
773 | */ | |
3d5e2c13 | 774 | radeon_write_agp_location(dev_priv, 0xffffffc0); |
b5e89ed5 | 775 | RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
1da177e4 | 776 | } else { |
b5e89ed5 DA |
777 | RADEON_WRITE(RADEON_AIC_CNTL, |
778 | tmp & ~RADEON_PCIGART_TRANSLATE_EN); | |
1da177e4 LT |
779 | } |
780 | } | |
781 | ||
84b1fd10 | 782 | static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) |
1da177e4 | 783 | { |
d985c108 DA |
784 | drm_radeon_private_t *dev_priv = dev->dev_private; |
785 | ||
b5e89ed5 | 786 | DRM_DEBUG("\n"); |
1da177e4 | 787 | |
f3dd5c37 | 788 | /* if we require new memory map but we don't have it fail */ |
54a56ac5 | 789 | if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { |
b15ec368 | 790 | DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); |
f3dd5c37 | 791 | radeon_do_cleanup_cp(dev); |
20caafa6 | 792 | return -EINVAL; |
f3dd5c37 DA |
793 | } |
794 | ||
54a56ac5 | 795 | if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { |
d985c108 | 796 | DRM_DEBUG("Forcing AGP card to PCI mode\n"); |
54a56ac5 DA |
797 | dev_priv->flags &= ~RADEON_IS_AGP; |
798 | } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) | |
b15ec368 DA |
799 | && !init->is_pci) { |
800 | DRM_DEBUG("Restoring AGP flag\n"); | |
54a56ac5 | 801 | dev_priv->flags |= RADEON_IS_AGP; |
d985c108 | 802 | } |
1da177e4 | 803 | |
54a56ac5 | 804 | if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { |
b5e89ed5 | 805 | DRM_ERROR("PCI GART memory not allocated!\n"); |
1da177e4 | 806 | radeon_do_cleanup_cp(dev); |
20caafa6 | 807 | return -EINVAL; |
1da177e4 LT |
808 | } |
809 | ||
810 | dev_priv->usec_timeout = init->usec_timeout; | |
b5e89ed5 DA |
811 | if (dev_priv->usec_timeout < 1 || |
812 | dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { | |
813 | DRM_DEBUG("TIMEOUT problem!\n"); | |
1da177e4 | 814 | radeon_do_cleanup_cp(dev); |
20caafa6 | 815 | return -EINVAL; |
1da177e4 LT |
816 | } |
817 | ||
ddbee333 DA |
818 | /* Enable vblank on CRTC1 for older X servers |
819 | */ | |
820 | dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; | |
821 | ||
d985c108 | 822 | switch(init->func) { |
1da177e4 | 823 | case RADEON_INIT_R200_CP: |
b5e89ed5 | 824 | dev_priv->microcode_version = UCODE_R200; |
1da177e4 LT |
825 | break; |
826 | case RADEON_INIT_R300_CP: | |
b5e89ed5 | 827 | dev_priv->microcode_version = UCODE_R300; |
1da177e4 LT |
828 | break; |
829 | default: | |
b5e89ed5 | 830 | dev_priv->microcode_version = UCODE_R100; |
1da177e4 | 831 | } |
b5e89ed5 | 832 | |
1da177e4 LT |
833 | dev_priv->do_boxes = 0; |
834 | dev_priv->cp_mode = init->cp_mode; | |
835 | ||
836 | /* We don't support anything other than bus-mastering ring mode, | |
837 | * but the ring can be in either AGP or PCI space for the ring | |
838 | * read pointer. | |
839 | */ | |
b5e89ed5 DA |
840 | if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && |
841 | (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { | |
842 | DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); | |
1da177e4 | 843 | radeon_do_cleanup_cp(dev); |
20caafa6 | 844 | return -EINVAL; |
1da177e4 LT |
845 | } |
846 | ||
b5e89ed5 | 847 | switch (init->fb_bpp) { |
1da177e4 LT |
848 | case 16: |
849 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; | |
850 | break; | |
851 | case 32: | |
852 | default: | |
853 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; | |
854 | break; | |
855 | } | |
b5e89ed5 DA |
856 | dev_priv->front_offset = init->front_offset; |
857 | dev_priv->front_pitch = init->front_pitch; | |
858 | dev_priv->back_offset = init->back_offset; | |
859 | dev_priv->back_pitch = init->back_pitch; | |
1da177e4 | 860 | |
b5e89ed5 | 861 | switch (init->depth_bpp) { |
1da177e4 LT |
862 | case 16: |
863 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; | |
864 | break; | |
865 | case 32: | |
866 | default: | |
867 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; | |
868 | break; | |
869 | } | |
b5e89ed5 DA |
870 | dev_priv->depth_offset = init->depth_offset; |
871 | dev_priv->depth_pitch = init->depth_pitch; | |
1da177e4 LT |
872 | |
873 | /* Hardware state for depth clears. Remove this if/when we no | |
874 | * longer clear the depth buffer with a 3D rectangle. Hard-code | |
875 | * all values to prevent unwanted 3D state from slipping through | |
876 | * and screwing with the clear operation. | |
877 | */ | |
878 | dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | | |
879 | (dev_priv->color_fmt << 10) | | |
b5e89ed5 DA |
880 | (dev_priv->microcode_version == |
881 | UCODE_R100 ? RADEON_ZBLOCK16 : 0)); | |
1da177e4 | 882 | |
b5e89ed5 DA |
883 | dev_priv->depth_clear.rb3d_zstencilcntl = |
884 | (dev_priv->depth_fmt | | |
885 | RADEON_Z_TEST_ALWAYS | | |
886 | RADEON_STENCIL_TEST_ALWAYS | | |
887 | RADEON_STENCIL_S_FAIL_REPLACE | | |
888 | RADEON_STENCIL_ZPASS_REPLACE | | |
889 | RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); | |
1da177e4 LT |
890 | |
891 | dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | | |
892 | RADEON_BFACE_SOLID | | |
893 | RADEON_FFACE_SOLID | | |
894 | RADEON_FLAT_SHADE_VTX_LAST | | |
895 | RADEON_DIFFUSE_SHADE_FLAT | | |
896 | RADEON_ALPHA_SHADE_FLAT | | |
897 | RADEON_SPECULAR_SHADE_FLAT | | |
898 | RADEON_FOG_SHADE_FLAT | | |
899 | RADEON_VTX_PIX_CENTER_OGL | | |
900 | RADEON_ROUND_MODE_TRUNC | | |
901 | RADEON_ROUND_PREC_8TH_PIX); | |
902 | ||
1da177e4 | 903 | |
1da177e4 LT |
904 | dev_priv->ring_offset = init->ring_offset; |
905 | dev_priv->ring_rptr_offset = init->ring_rptr_offset; | |
906 | dev_priv->buffers_offset = init->buffers_offset; | |
907 | dev_priv->gart_textures_offset = init->gart_textures_offset; | |
b5e89ed5 | 908 | |
da509d7a | 909 | dev_priv->sarea = drm_getsarea(dev); |
b5e89ed5 | 910 | if (!dev_priv->sarea) { |
1da177e4 | 911 | DRM_ERROR("could not find sarea!\n"); |
1da177e4 | 912 | radeon_do_cleanup_cp(dev); |
20caafa6 | 913 | return -EINVAL; |
1da177e4 LT |
914 | } |
915 | ||
1da177e4 | 916 | dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); |
b5e89ed5 | 917 | if (!dev_priv->cp_ring) { |
1da177e4 | 918 | DRM_ERROR("could not find cp ring region!\n"); |
1da177e4 | 919 | radeon_do_cleanup_cp(dev); |
20caafa6 | 920 | return -EINVAL; |
1da177e4 LT |
921 | } |
922 | dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); | |
b5e89ed5 | 923 | if (!dev_priv->ring_rptr) { |
1da177e4 | 924 | DRM_ERROR("could not find ring read pointer!\n"); |
1da177e4 | 925 | radeon_do_cleanup_cp(dev); |
20caafa6 | 926 | return -EINVAL; |
1da177e4 | 927 | } |
d1f2b55a | 928 | dev->agp_buffer_token = init->buffers_offset; |
1da177e4 | 929 | dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); |
b5e89ed5 | 930 | if (!dev->agp_buffer_map) { |
1da177e4 | 931 | DRM_ERROR("could not find dma buffer region!\n"); |
1da177e4 | 932 | radeon_do_cleanup_cp(dev); |
20caafa6 | 933 | return -EINVAL; |
1da177e4 LT |
934 | } |
935 | ||
b5e89ed5 DA |
936 | if (init->gart_textures_offset) { |
937 | dev_priv->gart_textures = | |
938 | drm_core_findmap(dev, init->gart_textures_offset); | |
939 | if (!dev_priv->gart_textures) { | |
1da177e4 | 940 | DRM_ERROR("could not find GART texture region!\n"); |
1da177e4 | 941 | radeon_do_cleanup_cp(dev); |
20caafa6 | 942 | return -EINVAL; |
1da177e4 LT |
943 | } |
944 | } | |
945 | ||
946 | dev_priv->sarea_priv = | |
b5e89ed5 DA |
947 | (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + |
948 | init->sarea_priv_offset); | |
1da177e4 LT |
949 | |
950 | #if __OS_HAS_AGP | |
54a56ac5 | 951 | if (dev_priv->flags & RADEON_IS_AGP) { |
b5e89ed5 DA |
952 | drm_core_ioremap(dev_priv->cp_ring, dev); |
953 | drm_core_ioremap(dev_priv->ring_rptr, dev); | |
954 | drm_core_ioremap(dev->agp_buffer_map, dev); | |
955 | if (!dev_priv->cp_ring->handle || | |
956 | !dev_priv->ring_rptr->handle || | |
957 | !dev->agp_buffer_map->handle) { | |
1da177e4 | 958 | DRM_ERROR("could not find ioremap agp regions!\n"); |
1da177e4 | 959 | radeon_do_cleanup_cp(dev); |
20caafa6 | 960 | return -EINVAL; |
1da177e4 LT |
961 | } |
962 | } else | |
963 | #endif | |
964 | { | |
b5e89ed5 | 965 | dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; |
1da177e4 | 966 | dev_priv->ring_rptr->handle = |
b5e89ed5 DA |
967 | (void *)dev_priv->ring_rptr->offset; |
968 | dev->agp_buffer_map->handle = | |
969 | (void *)dev->agp_buffer_map->offset; | |
970 | ||
971 | DRM_DEBUG("dev_priv->cp_ring->handle %p\n", | |
972 | dev_priv->cp_ring->handle); | |
973 | DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", | |
974 | dev_priv->ring_rptr->handle); | |
975 | DRM_DEBUG("dev->agp_buffer_map->handle %p\n", | |
976 | dev->agp_buffer_map->handle); | |
1da177e4 LT |
977 | } |
978 | ||
3d5e2c13 | 979 | dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; |
bc5f4523 | 980 | dev_priv->fb_size = |
3d5e2c13 | 981 | ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) |
d5ea702f | 982 | - dev_priv->fb_location; |
1da177e4 | 983 | |
b5e89ed5 DA |
984 | dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | |
985 | ((dev_priv->front_offset | |
986 | + dev_priv->fb_location) >> 10)); | |
1da177e4 | 987 | |
b5e89ed5 DA |
988 | dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | |
989 | ((dev_priv->back_offset | |
990 | + dev_priv->fb_location) >> 10)); | |
1da177e4 | 991 | |
b5e89ed5 DA |
992 | dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | |
993 | ((dev_priv->depth_offset | |
994 | + dev_priv->fb_location) >> 10)); | |
1da177e4 LT |
995 | |
996 | dev_priv->gart_size = init->gart_size; | |
d5ea702f DA |
997 | |
998 | /* New let's set the memory map ... */ | |
999 | if (dev_priv->new_memmap) { | |
1000 | u32 base = 0; | |
1001 | ||
1002 | DRM_INFO("Setting GART location based on new memory map\n"); | |
1003 | ||
1004 | /* If using AGP, try to locate the AGP aperture at the same | |
1005 | * location in the card and on the bus, though we have to | |
1006 | * align it down. | |
1007 | */ | |
1008 | #if __OS_HAS_AGP | |
54a56ac5 | 1009 | if (dev_priv->flags & RADEON_IS_AGP) { |
d5ea702f DA |
1010 | base = dev->agp->base; |
1011 | /* Check if valid */ | |
80b2c386 MD |
1012 | if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && |
1013 | base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { | |
d5ea702f DA |
1014 | DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", |
1015 | dev->agp->base); | |
1016 | base = 0; | |
1017 | } | |
1018 | } | |
1019 | #endif | |
1020 | /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ | |
1021 | if (base == 0) { | |
1022 | base = dev_priv->fb_location + dev_priv->fb_size; | |
80b2c386 MD |
1023 | if (base < dev_priv->fb_location || |
1024 | ((base + dev_priv->gart_size) & 0xfffffffful) < base) | |
d5ea702f DA |
1025 | base = dev_priv->fb_location |
1026 | - dev_priv->gart_size; | |
bc5f4523 | 1027 | } |
d5ea702f DA |
1028 | dev_priv->gart_vm_start = base & 0xffc00000u; |
1029 | if (dev_priv->gart_vm_start != base) | |
1030 | DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", | |
1031 | base, dev_priv->gart_vm_start); | |
1032 | } else { | |
1033 | DRM_INFO("Setting GART location based on old memory map\n"); | |
1034 | dev_priv->gart_vm_start = dev_priv->fb_location + | |
1035 | RADEON_READ(RADEON_CONFIG_APER_SIZE); | |
1036 | } | |
1da177e4 LT |
1037 | |
1038 | #if __OS_HAS_AGP | |
54a56ac5 | 1039 | if (dev_priv->flags & RADEON_IS_AGP) |
1da177e4 | 1040 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset |
b5e89ed5 DA |
1041 | - dev->agp->base |
1042 | + dev_priv->gart_vm_start); | |
1da177e4 LT |
1043 | else |
1044 | #endif | |
1045 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset | |
b0917bd9 IK |
1046 | - (unsigned long)dev->sg->virtual |
1047 | + dev_priv->gart_vm_start); | |
1da177e4 | 1048 | |
b5e89ed5 DA |
1049 | DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); |
1050 | DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); | |
1051 | DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", | |
1052 | dev_priv->gart_buffers_offset); | |
1da177e4 | 1053 | |
b5e89ed5 DA |
1054 | dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; |
1055 | dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle | |
1da177e4 LT |
1056 | + init->ring_size / sizeof(u32)); |
1057 | dev_priv->ring.size = init->ring_size; | |
b5e89ed5 | 1058 | dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); |
1da177e4 | 1059 | |
576cc458 RS |
1060 | dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; |
1061 | dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); | |
1062 | ||
1063 | dev_priv->ring.fetch_size = /* init->fetch_size */ 32; | |
1064 | dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); | |
b5e89ed5 | 1065 | dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; |
1da177e4 LT |
1066 | |
1067 | dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; | |
1068 | ||
1069 | #if __OS_HAS_AGP | |
54a56ac5 | 1070 | if (dev_priv->flags & RADEON_IS_AGP) { |
1da177e4 | 1071 | /* Turn off PCI GART */ |
b5e89ed5 | 1072 | radeon_set_pcigart(dev_priv, 0); |
1da177e4 LT |
1073 | } else |
1074 | #endif | |
1075 | { | |
b05c2385 | 1076 | dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); |
ea98a92f | 1077 | /* if we have an offset set from userspace */ |
f2b04cd2 | 1078 | if (dev_priv->pcigart_offset_set) { |
b5e89ed5 DA |
1079 | dev_priv->gart_info.bus_addr = |
1080 | dev_priv->pcigart_offset + dev_priv->fb_location; | |
f26c473c | 1081 | dev_priv->gart_info.mapping.offset = |
7fc86860 | 1082 | dev_priv->pcigart_offset + dev_priv->fb_aper_offset; |
f26c473c | 1083 | dev_priv->gart_info.mapping.size = |
f2b04cd2 | 1084 | dev_priv->gart_info.table_size; |
f26c473c DA |
1085 | |
1086 | drm_core_ioremap(&dev_priv->gart_info.mapping, dev); | |
b5e89ed5 | 1087 | dev_priv->gart_info.addr = |
f26c473c | 1088 | dev_priv->gart_info.mapping.handle; |
b5e89ed5 | 1089 | |
f2b04cd2 DA |
1090 | if (dev_priv->flags & RADEON_IS_PCIE) |
1091 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; | |
1092 | else | |
1093 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; | |
b5e89ed5 DA |
1094 | dev_priv->gart_info.gart_table_location = |
1095 | DRM_ATI_GART_FB; | |
1096 | ||
f26c473c | 1097 | DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", |
b5e89ed5 DA |
1098 | dev_priv->gart_info.addr, |
1099 | dev_priv->pcigart_offset); | |
1100 | } else { | |
f2b04cd2 DA |
1101 | if (dev_priv->flags & RADEON_IS_IGPGART) |
1102 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; | |
1103 | else | |
1104 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; | |
b5e89ed5 DA |
1105 | dev_priv->gart_info.gart_table_location = |
1106 | DRM_ATI_GART_MAIN; | |
f26c473c DA |
1107 | dev_priv->gart_info.addr = NULL; |
1108 | dev_priv->gart_info.bus_addr = 0; | |
54a56ac5 | 1109 | if (dev_priv->flags & RADEON_IS_PCIE) { |
b5e89ed5 DA |
1110 | DRM_ERROR |
1111 | ("Cannot use PCI Express without GART in FB memory\n"); | |
ea98a92f | 1112 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1113 | return -EINVAL; |
ea98a92f DA |
1114 | } |
1115 | } | |
1116 | ||
1117 | if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { | |
b5e89ed5 | 1118 | DRM_ERROR("failed to init PCI GART!\n"); |
1da177e4 | 1119 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1120 | return -ENOMEM; |
1da177e4 LT |
1121 | } |
1122 | ||
1123 | /* Turn on PCI GART */ | |
b5e89ed5 | 1124 | radeon_set_pcigart(dev_priv, 1); |
1da177e4 LT |
1125 | } |
1126 | ||
b5e89ed5 DA |
1127 | radeon_cp_load_microcode(dev_priv); |
1128 | radeon_cp_init_ring_buffer(dev, dev_priv); | |
1da177e4 LT |
1129 | |
1130 | dev_priv->last_buf = 0; | |
1131 | ||
b5e89ed5 | 1132 | radeon_do_engine_reset(dev); |
d5ea702f | 1133 | radeon_test_writeback(dev_priv); |
1da177e4 LT |
1134 | |
1135 | return 0; | |
1136 | } | |
1137 | ||
84b1fd10 | 1138 | static int radeon_do_cleanup_cp(struct drm_device * dev) |
1da177e4 LT |
1139 | { |
1140 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1141 | DRM_DEBUG("\n"); |
1da177e4 LT |
1142 | |
1143 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
1144 | * may not have been called from userspace and after dev_private | |
1145 | * is freed, it's too late. | |
1146 | */ | |
b5e89ed5 DA |
1147 | if (dev->irq_enabled) |
1148 | drm_irq_uninstall(dev); | |
1da177e4 LT |
1149 | |
1150 | #if __OS_HAS_AGP | |
54a56ac5 | 1151 | if (dev_priv->flags & RADEON_IS_AGP) { |
d985c108 | 1152 | if (dev_priv->cp_ring != NULL) { |
b5e89ed5 | 1153 | drm_core_ioremapfree(dev_priv->cp_ring, dev); |
d985c108 DA |
1154 | dev_priv->cp_ring = NULL; |
1155 | } | |
1156 | if (dev_priv->ring_rptr != NULL) { | |
b5e89ed5 | 1157 | drm_core_ioremapfree(dev_priv->ring_rptr, dev); |
d985c108 DA |
1158 | dev_priv->ring_rptr = NULL; |
1159 | } | |
b5e89ed5 DA |
1160 | if (dev->agp_buffer_map != NULL) { |
1161 | drm_core_ioremapfree(dev->agp_buffer_map, dev); | |
1da177e4 LT |
1162 | dev->agp_buffer_map = NULL; |
1163 | } | |
1164 | } else | |
1165 | #endif | |
1166 | { | |
d985c108 DA |
1167 | |
1168 | if (dev_priv->gart_info.bus_addr) { | |
1169 | /* Turn off PCI GART */ | |
1170 | radeon_set_pcigart(dev_priv, 0); | |
ea98a92f DA |
1171 | if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) |
1172 | DRM_ERROR("failed to cleanup PCI GART!\n"); | |
d985c108 | 1173 | } |
b5e89ed5 | 1174 | |
d985c108 DA |
1175 | if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) |
1176 | { | |
f26c473c | 1177 | drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); |
f2b04cd2 | 1178 | dev_priv->gart_info.addr = 0; |
ea98a92f | 1179 | } |
1da177e4 | 1180 | } |
1da177e4 LT |
1181 | /* only clear to the start of flags */ |
1182 | memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
b5e89ed5 DA |
1187 | /* This code will reinit the Radeon CP hardware after a resume from disc. |
1188 | * AFAIK, it would be very difficult to pickle the state at suspend time, so | |
1da177e4 LT |
1189 | * here we make sure that all Radeon hardware initialisation is re-done without |
1190 | * affecting running applications. | |
1191 | * | |
1192 | * Charl P. Botha <http://cpbotha.net> | |
1193 | */ | |
84b1fd10 | 1194 | static int radeon_do_resume_cp(struct drm_device * dev) |
1da177e4 LT |
1195 | { |
1196 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1197 | ||
b5e89ed5 DA |
1198 | if (!dev_priv) { |
1199 | DRM_ERROR("Called with no initialization\n"); | |
20caafa6 | 1200 | return -EINVAL; |
1da177e4 LT |
1201 | } |
1202 | ||
1203 | DRM_DEBUG("Starting radeon_do_resume_cp()\n"); | |
1204 | ||
1205 | #if __OS_HAS_AGP | |
54a56ac5 | 1206 | if (dev_priv->flags & RADEON_IS_AGP) { |
1da177e4 | 1207 | /* Turn off PCI GART */ |
b5e89ed5 | 1208 | radeon_set_pcigart(dev_priv, 0); |
1da177e4 LT |
1209 | } else |
1210 | #endif | |
1211 | { | |
1212 | /* Turn on PCI GART */ | |
b5e89ed5 | 1213 | radeon_set_pcigart(dev_priv, 1); |
1da177e4 LT |
1214 | } |
1215 | ||
b5e89ed5 DA |
1216 | radeon_cp_load_microcode(dev_priv); |
1217 | radeon_cp_init_ring_buffer(dev, dev_priv); | |
1da177e4 | 1218 | |
b5e89ed5 | 1219 | radeon_do_engine_reset(dev); |
1da177e4 LT |
1220 | |
1221 | DRM_DEBUG("radeon_do_resume_cp() complete\n"); | |
1222 | ||
1223 | return 0; | |
1224 | } | |
1225 | ||
c153f45f | 1226 | int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1227 | { |
c153f45f | 1228 | drm_radeon_init_t *init = data; |
1da177e4 | 1229 | |
6c340eac | 1230 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1231 | |
c153f45f | 1232 | if (init->func == RADEON_INIT_R300_CP) |
3d5e2c13 | 1233 | r300_init_reg_flags(dev); |
414ed537 | 1234 | |
c153f45f | 1235 | switch (init->func) { |
1da177e4 LT |
1236 | case RADEON_INIT_CP: |
1237 | case RADEON_INIT_R200_CP: | |
1238 | case RADEON_INIT_R300_CP: | |
c153f45f | 1239 | return radeon_do_init_cp(dev, init); |
1da177e4 | 1240 | case RADEON_CLEANUP_CP: |
b5e89ed5 | 1241 | return radeon_do_cleanup_cp(dev); |
1da177e4 LT |
1242 | } |
1243 | ||
20caafa6 | 1244 | return -EINVAL; |
1da177e4 LT |
1245 | } |
1246 | ||
c153f45f | 1247 | int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1248 | { |
1da177e4 | 1249 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1250 | DRM_DEBUG("\n"); |
1da177e4 | 1251 | |
6c340eac | 1252 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1253 | |
b5e89ed5 | 1254 | if (dev_priv->cp_running) { |
3e684eae | 1255 | DRM_DEBUG("while CP running\n"); |
1da177e4 LT |
1256 | return 0; |
1257 | } | |
b5e89ed5 | 1258 | if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { |
3e684eae MN |
1259 | DRM_DEBUG("called with bogus CP mode (%d)\n", |
1260 | dev_priv->cp_mode); | |
1da177e4 LT |
1261 | return 0; |
1262 | } | |
1263 | ||
b5e89ed5 | 1264 | radeon_do_cp_start(dev_priv); |
1da177e4 LT |
1265 | |
1266 | return 0; | |
1267 | } | |
1268 | ||
1269 | /* Stop the CP. The engine must have been idled before calling this | |
1270 | * routine. | |
1271 | */ | |
c153f45f | 1272 | int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1273 | { |
1da177e4 | 1274 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 1275 | drm_radeon_cp_stop_t *stop = data; |
1da177e4 | 1276 | int ret; |
b5e89ed5 | 1277 | DRM_DEBUG("\n"); |
1da177e4 | 1278 | |
6c340eac | 1279 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1280 | |
1da177e4 LT |
1281 | if (!dev_priv->cp_running) |
1282 | return 0; | |
1283 | ||
1284 | /* Flush any pending CP commands. This ensures any outstanding | |
1285 | * commands are exectuted by the engine before we turn it off. | |
1286 | */ | |
c153f45f | 1287 | if (stop->flush) { |
b5e89ed5 | 1288 | radeon_do_cp_flush(dev_priv); |
1da177e4 LT |
1289 | } |
1290 | ||
1291 | /* If we fail to make the engine go idle, we return an error | |
1292 | * code so that the DRM ioctl wrapper can try again. | |
1293 | */ | |
c153f45f | 1294 | if (stop->idle) { |
b5e89ed5 DA |
1295 | ret = radeon_do_cp_idle(dev_priv); |
1296 | if (ret) | |
1297 | return ret; | |
1da177e4 LT |
1298 | } |
1299 | ||
1300 | /* Finally, we can turn off the CP. If the engine isn't idle, | |
1301 | * we will get some dropped triangles as they won't be fully | |
1302 | * rendered before the CP is shut down. | |
1303 | */ | |
b5e89ed5 | 1304 | radeon_do_cp_stop(dev_priv); |
1da177e4 LT |
1305 | |
1306 | /* Reset the engine */ | |
b5e89ed5 | 1307 | radeon_do_engine_reset(dev); |
1da177e4 LT |
1308 | |
1309 | return 0; | |
1310 | } | |
1311 | ||
84b1fd10 | 1312 | void radeon_do_release(struct drm_device * dev) |
1da177e4 LT |
1313 | { |
1314 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1315 | int i, ret; | |
1316 | ||
1317 | if (dev_priv) { | |
1318 | if (dev_priv->cp_running) { | |
1319 | /* Stop the cp */ | |
b5e89ed5 | 1320 | while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { |
1da177e4 LT |
1321 | DRM_DEBUG("radeon_do_cp_idle %d\n", ret); |
1322 | #ifdef __linux__ | |
1323 | schedule(); | |
1324 | #else | |
1325 | tsleep(&ret, PZERO, "rdnrel", 1); | |
1326 | #endif | |
1327 | } | |
b5e89ed5 DA |
1328 | radeon_do_cp_stop(dev_priv); |
1329 | radeon_do_engine_reset(dev); | |
1da177e4 LT |
1330 | } |
1331 | ||
1332 | /* Disable *all* interrupts */ | |
1333 | if (dev_priv->mmio) /* remove this after permanent addmaps */ | |
b5e89ed5 | 1334 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); |
1da177e4 | 1335 | |
b5e89ed5 | 1336 | if (dev_priv->mmio) { /* remove all surfaces */ |
1da177e4 | 1337 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { |
b5e89ed5 DA |
1338 | RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); |
1339 | RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + | |
1340 | 16 * i, 0); | |
1341 | RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + | |
1342 | 16 * i, 0); | |
1da177e4 LT |
1343 | } |
1344 | } | |
1345 | ||
1346 | /* Free memory heap structures */ | |
b5e89ed5 DA |
1347 | radeon_mem_takedown(&(dev_priv->gart_heap)); |
1348 | radeon_mem_takedown(&(dev_priv->fb_heap)); | |
1da177e4 LT |
1349 | |
1350 | /* deallocate kernel resources */ | |
b5e89ed5 | 1351 | radeon_do_cleanup_cp(dev); |
1da177e4 LT |
1352 | } |
1353 | } | |
1354 | ||
1355 | /* Just reset the CP ring. Called as part of an X Server engine reset. | |
1356 | */ | |
c153f45f | 1357 | int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1358 | { |
1da177e4 | 1359 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1360 | DRM_DEBUG("\n"); |
1da177e4 | 1361 | |
6c340eac | 1362 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1363 | |
b5e89ed5 | 1364 | if (!dev_priv) { |
3e684eae | 1365 | DRM_DEBUG("called before init done\n"); |
20caafa6 | 1366 | return -EINVAL; |
1da177e4 LT |
1367 | } |
1368 | ||
b5e89ed5 | 1369 | radeon_do_cp_reset(dev_priv); |
1da177e4 LT |
1370 | |
1371 | /* The CP is no longer running after an engine reset */ | |
1372 | dev_priv->cp_running = 0; | |
1373 | ||
1374 | return 0; | |
1375 | } | |
1376 | ||
c153f45f | 1377 | int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1378 | { |
1da177e4 | 1379 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1380 | DRM_DEBUG("\n"); |
1da177e4 | 1381 | |
6c340eac | 1382 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1383 | |
b5e89ed5 | 1384 | return radeon_do_cp_idle(dev_priv); |
1da177e4 LT |
1385 | } |
1386 | ||
1387 | /* Added by Charl P. Botha to call radeon_do_resume_cp(). | |
1388 | */ | |
c153f45f | 1389 | int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1390 | { |
1da177e4 LT |
1391 | |
1392 | return radeon_do_resume_cp(dev); | |
1393 | } | |
1394 | ||
c153f45f | 1395 | int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1396 | { |
b5e89ed5 | 1397 | DRM_DEBUG("\n"); |
1da177e4 | 1398 | |
6c340eac | 1399 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1400 | |
b5e89ed5 | 1401 | return radeon_do_engine_reset(dev); |
1da177e4 LT |
1402 | } |
1403 | ||
1da177e4 LT |
1404 | /* ================================================================ |
1405 | * Fullscreen mode | |
1406 | */ | |
1407 | ||
1408 | /* KW: Deprecated to say the least: | |
1409 | */ | |
c153f45f | 1410 | int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 LT |
1411 | { |
1412 | return 0; | |
1413 | } | |
1414 | ||
1da177e4 LT |
1415 | /* ================================================================ |
1416 | * Freelist management | |
1417 | */ | |
1418 | ||
1419 | /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through | |
1420 | * bufs until freelist code is used. Note this hides a problem with | |
1421 | * the scratch register * (used to keep track of last buffer | |
1422 | * completed) being written to before * the last buffer has actually | |
b5e89ed5 | 1423 | * completed rendering. |
1da177e4 LT |
1424 | * |
1425 | * KW: It's also a good way to find free buffers quickly. | |
1426 | * | |
1427 | * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't | |
1428 | * sleep. However, bugs in older versions of radeon_accel.c mean that | |
1429 | * we essentially have to do this, else old clients will break. | |
b5e89ed5 | 1430 | * |
1da177e4 LT |
1431 | * However, it does leave open a potential deadlock where all the |
1432 | * buffers are held by other clients, which can't release them because | |
b5e89ed5 | 1433 | * they can't get the lock. |
1da177e4 LT |
1434 | */ |
1435 | ||
056219e2 | 1436 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
1da177e4 | 1437 | { |
cdd55a29 | 1438 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1439 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1440 | drm_radeon_buf_priv_t *buf_priv; | |
056219e2 | 1441 | struct drm_buf *buf; |
1da177e4 LT |
1442 | int i, t; |
1443 | int start; | |
1444 | ||
b5e89ed5 | 1445 | if (++dev_priv->last_buf >= dma->buf_count) |
1da177e4 LT |
1446 | dev_priv->last_buf = 0; |
1447 | ||
1448 | start = dev_priv->last_buf; | |
1449 | ||
b5e89ed5 DA |
1450 | for (t = 0; t < dev_priv->usec_timeout; t++) { |
1451 | u32 done_age = GET_SCRATCH(1); | |
1452 | DRM_DEBUG("done_age = %d\n", done_age); | |
1453 | for (i = start; i < dma->buf_count; i++) { | |
1da177e4 LT |
1454 | buf = dma->buflist[i]; |
1455 | buf_priv = buf->dev_private; | |
6c340eac EA |
1456 | if (buf->file_priv == NULL || (buf->pending && |
1457 | buf_priv->age <= | |
1458 | done_age)) { | |
1da177e4 LT |
1459 | dev_priv->stats.requested_bufs++; |
1460 | buf->pending = 0; | |
1461 | return buf; | |
1462 | } | |
1463 | start = 0; | |
1464 | } | |
1465 | ||
1466 | if (t) { | |
b5e89ed5 | 1467 | DRM_UDELAY(1); |
1da177e4 LT |
1468 | dev_priv->stats.freelist_loops++; |
1469 | } | |
1470 | } | |
1471 | ||
b5e89ed5 | 1472 | DRM_DEBUG("returning NULL!\n"); |
1da177e4 LT |
1473 | return NULL; |
1474 | } | |
b5e89ed5 | 1475 | |
1da177e4 | 1476 | #if 0 |
056219e2 | 1477 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
1da177e4 | 1478 | { |
cdd55a29 | 1479 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1480 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1481 | drm_radeon_buf_priv_t *buf_priv; | |
056219e2 | 1482 | struct drm_buf *buf; |
1da177e4 LT |
1483 | int i, t; |
1484 | int start; | |
1485 | u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); | |
1486 | ||
b5e89ed5 | 1487 | if (++dev_priv->last_buf >= dma->buf_count) |
1da177e4 LT |
1488 | dev_priv->last_buf = 0; |
1489 | ||
1490 | start = dev_priv->last_buf; | |
1491 | dev_priv->stats.freelist_loops++; | |
b5e89ed5 DA |
1492 | |
1493 | for (t = 0; t < 2; t++) { | |
1494 | for (i = start; i < dma->buf_count; i++) { | |
1da177e4 LT |
1495 | buf = dma->buflist[i]; |
1496 | buf_priv = buf->dev_private; | |
6c340eac EA |
1497 | if (buf->file_priv == 0 || (buf->pending && |
1498 | buf_priv->age <= | |
1499 | done_age)) { | |
1da177e4 LT |
1500 | dev_priv->stats.requested_bufs++; |
1501 | buf->pending = 0; | |
1502 | return buf; | |
1503 | } | |
1504 | } | |
1505 | start = 0; | |
1506 | } | |
1507 | ||
1508 | return NULL; | |
1509 | } | |
1510 | #endif | |
1511 | ||
84b1fd10 | 1512 | void radeon_freelist_reset(struct drm_device * dev) |
1da177e4 | 1513 | { |
cdd55a29 | 1514 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1515 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1516 | int i; | |
1517 | ||
1518 | dev_priv->last_buf = 0; | |
b5e89ed5 | 1519 | for (i = 0; i < dma->buf_count; i++) { |
056219e2 | 1520 | struct drm_buf *buf = dma->buflist[i]; |
1da177e4 LT |
1521 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; |
1522 | buf_priv->age = 0; | |
1523 | } | |
1524 | } | |
1525 | ||
1da177e4 LT |
1526 | /* ================================================================ |
1527 | * CP command submission | |
1528 | */ | |
1529 | ||
b5e89ed5 | 1530 | int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) |
1da177e4 LT |
1531 | { |
1532 | drm_radeon_ring_buffer_t *ring = &dev_priv->ring; | |
1533 | int i; | |
b5e89ed5 | 1534 | u32 last_head = GET_RING_HEAD(dev_priv); |
1da177e4 | 1535 | |
b5e89ed5 DA |
1536 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
1537 | u32 head = GET_RING_HEAD(dev_priv); | |
1da177e4 LT |
1538 | |
1539 | ring->space = (head - ring->tail) * sizeof(u32); | |
b5e89ed5 | 1540 | if (ring->space <= 0) |
1da177e4 | 1541 | ring->space += ring->size; |
b5e89ed5 | 1542 | if (ring->space > n) |
1da177e4 | 1543 | return 0; |
b5e89ed5 | 1544 | |
1da177e4 LT |
1545 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
1546 | ||
1547 | if (head != last_head) | |
1548 | i = 0; | |
1549 | last_head = head; | |
1550 | ||
b5e89ed5 | 1551 | DRM_UDELAY(1); |
1da177e4 LT |
1552 | } |
1553 | ||
1554 | /* FIXME: This return value is ignored in the BEGIN_RING macro! */ | |
1555 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
1556 | radeon_status(dev_priv); |
1557 | DRM_ERROR("failed!\n"); | |
1da177e4 | 1558 | #endif |
20caafa6 | 1559 | return -EBUSY; |
1da177e4 LT |
1560 | } |
1561 | ||
6c340eac EA |
1562 | static int radeon_cp_get_buffers(struct drm_device *dev, |
1563 | struct drm_file *file_priv, | |
c60ce623 | 1564 | struct drm_dma * d) |
1da177e4 LT |
1565 | { |
1566 | int i; | |
056219e2 | 1567 | struct drm_buf *buf; |
1da177e4 | 1568 | |
b5e89ed5 DA |
1569 | for (i = d->granted_count; i < d->request_count; i++) { |
1570 | buf = radeon_freelist_get(dev); | |
1571 | if (!buf) | |
20caafa6 | 1572 | return -EBUSY; /* NOTE: broken client */ |
1da177e4 | 1573 | |
6c340eac | 1574 | buf->file_priv = file_priv; |
1da177e4 | 1575 | |
b5e89ed5 DA |
1576 | if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, |
1577 | sizeof(buf->idx))) | |
20caafa6 | 1578 | return -EFAULT; |
b5e89ed5 DA |
1579 | if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, |
1580 | sizeof(buf->total))) | |
20caafa6 | 1581 | return -EFAULT; |
1da177e4 LT |
1582 | |
1583 | d->granted_count++; | |
1584 | } | |
1585 | return 0; | |
1586 | } | |
1587 | ||
c153f45f | 1588 | int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1589 | { |
cdd55a29 | 1590 | struct drm_device_dma *dma = dev->dma; |
1da177e4 | 1591 | int ret = 0; |
c153f45f | 1592 | struct drm_dma *d = data; |
1da177e4 | 1593 | |
6c340eac | 1594 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1595 | |
1da177e4 LT |
1596 | /* Please don't send us buffers. |
1597 | */ | |
c153f45f | 1598 | if (d->send_count != 0) { |
b5e89ed5 | 1599 | DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", |
c153f45f | 1600 | DRM_CURRENTPID, d->send_count); |
20caafa6 | 1601 | return -EINVAL; |
1da177e4 LT |
1602 | } |
1603 | ||
1604 | /* We'll send you buffers. | |
1605 | */ | |
c153f45f | 1606 | if (d->request_count < 0 || d->request_count > dma->buf_count) { |
b5e89ed5 | 1607 | DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", |
c153f45f | 1608 | DRM_CURRENTPID, d->request_count, dma->buf_count); |
20caafa6 | 1609 | return -EINVAL; |
1da177e4 LT |
1610 | } |
1611 | ||
c153f45f | 1612 | d->granted_count = 0; |
1da177e4 | 1613 | |
c153f45f EA |
1614 | if (d->request_count) { |
1615 | ret = radeon_cp_get_buffers(dev, file_priv, d); | |
1da177e4 LT |
1616 | } |
1617 | ||
1da177e4 LT |
1618 | return ret; |
1619 | } | |
1620 | ||
22eae947 | 1621 | int radeon_driver_load(struct drm_device *dev, unsigned long flags) |
1da177e4 LT |
1622 | { |
1623 | drm_radeon_private_t *dev_priv; | |
1624 | int ret = 0; | |
1625 | ||
1626 | dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); | |
1627 | if (dev_priv == NULL) | |
20caafa6 | 1628 | return -ENOMEM; |
1da177e4 LT |
1629 | |
1630 | memset(dev_priv, 0, sizeof(drm_radeon_private_t)); | |
1631 | dev->dev_private = (void *)dev_priv; | |
1632 | dev_priv->flags = flags; | |
1633 | ||
54a56ac5 | 1634 | switch (flags & RADEON_FAMILY_MASK) { |
1da177e4 LT |
1635 | case CHIP_R100: |
1636 | case CHIP_RV200: | |
1637 | case CHIP_R200: | |
1638 | case CHIP_R300: | |
b15ec368 | 1639 | case CHIP_R350: |
414ed537 | 1640 | case CHIP_R420: |
b15ec368 | 1641 | case CHIP_RV410: |
3d5e2c13 DA |
1642 | case CHIP_RV515: |
1643 | case CHIP_R520: | |
1644 | case CHIP_RV570: | |
1645 | case CHIP_R580: | |
54a56ac5 | 1646 | dev_priv->flags |= RADEON_HAS_HIERZ; |
1da177e4 LT |
1647 | break; |
1648 | default: | |
b5e89ed5 | 1649 | /* all other chips have no hierarchical z buffer */ |
1da177e4 LT |
1650 | break; |
1651 | } | |
414ed537 DA |
1652 | |
1653 | if (drm_device_is_agp(dev)) | |
54a56ac5 | 1654 | dev_priv->flags |= RADEON_IS_AGP; |
b15ec368 | 1655 | else if (drm_device_is_pcie(dev)) |
54a56ac5 | 1656 | dev_priv->flags |= RADEON_IS_PCIE; |
b15ec368 | 1657 | else |
54a56ac5 | 1658 | dev_priv->flags |= RADEON_IS_PCI; |
ea98a92f | 1659 | |
414ed537 | 1660 | DRM_DEBUG("%s card detected\n", |
54a56ac5 | 1661 | ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); |
1da177e4 LT |
1662 | return ret; |
1663 | } | |
1664 | ||
22eae947 DA |
1665 | /* Create mappings for registers and framebuffer so userland doesn't necessarily |
1666 | * have to find them. | |
1667 | */ | |
1668 | int radeon_driver_firstopen(struct drm_device *dev) | |
836cf046 DA |
1669 | { |
1670 | int ret; | |
1671 | drm_local_map_t *map; | |
1672 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1673 | ||
f2b04cd2 DA |
1674 | dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; |
1675 | ||
836cf046 DA |
1676 | ret = drm_addmap(dev, drm_get_resource_start(dev, 2), |
1677 | drm_get_resource_len(dev, 2), _DRM_REGISTERS, | |
1678 | _DRM_READ_ONLY, &dev_priv->mmio); | |
1679 | if (ret != 0) | |
1680 | return ret; | |
1681 | ||
7fc86860 DA |
1682 | dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); |
1683 | ret = drm_addmap(dev, dev_priv->fb_aper_offset, | |
836cf046 DA |
1684 | drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, |
1685 | _DRM_WRITE_COMBINING, &map); | |
1686 | if (ret != 0) | |
1687 | return ret; | |
1688 | ||
1689 | return 0; | |
1690 | } | |
1691 | ||
22eae947 | 1692 | int radeon_driver_unload(struct drm_device *dev) |
1da177e4 LT |
1693 | { |
1694 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1695 | ||
1696 | DRM_DEBUG("\n"); | |
1da177e4 LT |
1697 | drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); |
1698 | ||
1699 | dev->dev_private = NULL; | |
1700 | return 0; | |
1701 | } |