Commit | Line | Data |
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f26c473c DA |
1 | /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ |
2 | /* | |
1da177e4 LT |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
45e51905 | 5 | * Copyright 2007 Advanced Micro Devices, Inc. |
1da177e4 LT |
6 | * All Rights Reserved. |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
26 | * | |
27 | * Authors: | |
28 | * Kevin E. Martin <martin@valinux.com> | |
29 | * Gareth Hughes <gareth@valinux.com> | |
30 | */ | |
31 | ||
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "radeon_drm.h" | |
35 | #include "radeon_drv.h" | |
414ed537 | 36 | #include "r300_reg.h" |
1da177e4 | 37 | |
9f18409e AD |
38 | #include "radeon_microcode.h" |
39 | ||
1da177e4 LT |
40 | #define RADEON_FIFO_DEBUG 0 |
41 | ||
84b1fd10 | 42 | static int radeon_do_cleanup_cp(struct drm_device * dev); |
1da177e4 | 43 | |
45e51905 | 44 | static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
3d5e2c13 DA |
45 | { |
46 | u32 ret; | |
47 | RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); | |
48 | ret = RADEON_READ(R520_MC_IND_DATA); | |
49 | RADEON_WRITE(R520_MC_IND_INDEX, 0); | |
50 | return ret; | |
51 | } | |
52 | ||
45e51905 AD |
53 | static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
54 | { | |
55 | u32 ret; | |
56 | RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); | |
57 | ret = RADEON_READ(RS480_NB_MC_DATA); | |
58 | RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); | |
59 | return ret; | |
60 | } | |
61 | ||
60f92683 MC |
62 | static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
63 | { | |
45e51905 | 64 | u32 ret; |
60f92683 | 65 | RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
45e51905 AD |
66 | ret = RADEON_READ(RS690_MC_DATA); |
67 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); | |
68 | return ret; | |
69 | } | |
70 | ||
71 | static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) | |
72 | { | |
73 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) | |
74 | return RS690_READ_MCIND(dev_priv, addr); | |
75 | else | |
76 | return RS480_READ_MCIND(dev_priv, addr); | |
60f92683 MC |
77 | } |
78 | ||
3d5e2c13 DA |
79 | u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) |
80 | { | |
81 | ||
82 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 83 | return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); |
60f92683 MC |
84 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
85 | return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); | |
3d5e2c13 | 86 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 87 | return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); |
3d5e2c13 DA |
88 | else |
89 | return RADEON_READ(RADEON_MC_FB_LOCATION); | |
90 | } | |
91 | ||
92 | static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) | |
93 | { | |
94 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 95 | R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); |
60f92683 MC |
96 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
97 | RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); | |
3d5e2c13 | 98 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 99 | R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); |
3d5e2c13 DA |
100 | else |
101 | RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); | |
102 | } | |
103 | ||
104 | static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) | |
105 | { | |
106 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | |
45e51905 | 107 | R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); |
60f92683 MC |
108 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
109 | RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); | |
3d5e2c13 | 110 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
45e51905 | 111 | R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); |
3d5e2c13 DA |
112 | else |
113 | RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); | |
114 | } | |
115 | ||
84b1fd10 | 116 | static int RADEON_READ_PLL(struct drm_device * dev, int addr) |
1da177e4 LT |
117 | { |
118 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
119 | ||
120 | RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); | |
121 | return RADEON_READ(RADEON_CLOCK_CNTL_DATA); | |
122 | } | |
123 | ||
3d5e2c13 | 124 | static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) |
ea98a92f DA |
125 | { |
126 | RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); | |
127 | return RADEON_READ(RADEON_PCIE_DATA); | |
128 | } | |
129 | ||
1da177e4 | 130 | #if RADEON_FIFO_DEBUG |
b5e89ed5 | 131 | static void radeon_status(drm_radeon_private_t * dev_priv) |
1da177e4 | 132 | { |
bf9d8929 | 133 | printk("%s:\n", __func__); |
b5e89ed5 DA |
134 | printk("RBBM_STATUS = 0x%08x\n", |
135 | (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); | |
136 | printk("CP_RB_RTPR = 0x%08x\n", | |
137 | (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); | |
138 | printk("CP_RB_WTPR = 0x%08x\n", | |
139 | (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); | |
140 | printk("AIC_CNTL = 0x%08x\n", | |
141 | (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); | |
142 | printk("AIC_STAT = 0x%08x\n", | |
143 | (unsigned int)RADEON_READ(RADEON_AIC_STAT)); | |
144 | printk("AIC_PT_BASE = 0x%08x\n", | |
145 | (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); | |
146 | printk("TLB_ADDR = 0x%08x\n", | |
147 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); | |
148 | printk("TLB_DATA = 0x%08x\n", | |
149 | (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); | |
1da177e4 LT |
150 | } |
151 | #endif | |
152 | ||
1da177e4 LT |
153 | /* ================================================================ |
154 | * Engine, FIFO control | |
155 | */ | |
156 | ||
b5e89ed5 | 157 | static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
158 | { |
159 | u32 tmp; | |
160 | int i; | |
161 | ||
162 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
163 | ||
259434ac AD |
164 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { |
165 | tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); | |
166 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | |
167 | RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); | |
168 | ||
169 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
170 | if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) | |
171 | & RADEON_RB3D_DC_BUSY)) { | |
172 | return 0; | |
173 | } | |
174 | DRM_UDELAY(1); | |
175 | } | |
176 | } else { | |
177 | /* 3D */ | |
178 | tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT); | |
179 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | |
180 | RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp); | |
181 | ||
182 | /* 2D */ | |
183 | tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT); | |
184 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | |
185 | RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); | |
186 | ||
187 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
188 | if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT) | |
189 | & RADEON_RB3D_DC_BUSY)) { | |
190 | return 0; | |
191 | } | |
192 | DRM_UDELAY(1); | |
1da177e4 | 193 | } |
1da177e4 LT |
194 | } |
195 | ||
196 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
197 | DRM_ERROR("failed!\n"); |
198 | radeon_status(dev_priv); | |
1da177e4 | 199 | #endif |
20caafa6 | 200 | return -EBUSY; |
1da177e4 LT |
201 | } |
202 | ||
b5e89ed5 | 203 | static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) |
1da177e4 LT |
204 | { |
205 | int i; | |
206 | ||
207 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
208 | ||
b5e89ed5 DA |
209 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
210 | int slots = (RADEON_READ(RADEON_RBBM_STATUS) | |
211 | & RADEON_RBBM_FIFOCNT_MASK); | |
212 | if (slots >= entries) | |
213 | return 0; | |
214 | DRM_UDELAY(1); | |
1da177e4 LT |
215 | } |
216 | ||
217 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
218 | DRM_ERROR("failed!\n"); |
219 | radeon_status(dev_priv); | |
1da177e4 | 220 | #endif |
20caafa6 | 221 | return -EBUSY; |
1da177e4 LT |
222 | } |
223 | ||
b5e89ed5 | 224 | static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
225 | { |
226 | int i, ret; | |
227 | ||
228 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
229 | ||
b5e89ed5 DA |
230 | ret = radeon_do_wait_for_fifo(dev_priv, 64); |
231 | if (ret) | |
232 | return ret; | |
1da177e4 | 233 | |
b5e89ed5 DA |
234 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
235 | if (!(RADEON_READ(RADEON_RBBM_STATUS) | |
236 | & RADEON_RBBM_ACTIVE)) { | |
237 | radeon_do_pixcache_flush(dev_priv); | |
1da177e4 LT |
238 | return 0; |
239 | } | |
b5e89ed5 | 240 | DRM_UDELAY(1); |
1da177e4 LT |
241 | } |
242 | ||
243 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
244 | DRM_ERROR("failed!\n"); |
245 | radeon_status(dev_priv); | |
1da177e4 | 246 | #endif |
20caafa6 | 247 | return -EBUSY; |
1da177e4 LT |
248 | } |
249 | ||
1da177e4 LT |
250 | /* ================================================================ |
251 | * CP control, initialization | |
252 | */ | |
253 | ||
254 | /* Load the microcode for the CP */ | |
b5e89ed5 | 255 | static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
256 | { |
257 | int i; | |
b5e89ed5 | 258 | DRM_DEBUG("\n"); |
1da177e4 | 259 | |
b5e89ed5 | 260 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 261 | |
b5e89ed5 | 262 | RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); |
9f18409e AD |
263 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || |
264 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || | |
265 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || | |
266 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || | |
267 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { | |
268 | DRM_INFO("Loading R100 Microcode\n"); | |
269 | for (i = 0; i < 256; i++) { | |
270 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
271 | R100_cp_microcode[i][1]); | |
272 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
273 | R100_cp_microcode[i][0]); | |
274 | } | |
275 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || | |
276 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || | |
277 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || | |
278 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { | |
1da177e4 | 279 | DRM_INFO("Loading R200 Microcode\n"); |
b5e89ed5 DA |
280 | for (i = 0; i < 256; i++) { |
281 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
282 | R200_cp_microcode[i][1]); | |
283 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
284 | R200_cp_microcode[i][0]); | |
1da177e4 | 285 | } |
9f18409e AD |
286 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || |
287 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || | |
288 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || | |
289 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || | |
45e51905 | 290 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { |
1da177e4 | 291 | DRM_INFO("Loading R300 Microcode\n"); |
b5e89ed5 DA |
292 | for (i = 0; i < 256; i++) { |
293 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
294 | R300_cp_microcode[i][1]); | |
295 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
296 | R300_cp_microcode[i][0]); | |
1da177e4 | 297 | } |
9f18409e AD |
298 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || |
299 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { | |
300 | DRM_INFO("Loading R400 Microcode\n"); | |
301 | for (i = 0; i < 256; i++) { | |
302 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
303 | R420_cp_microcode[i][1]); | |
304 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
305 | R420_cp_microcode[i][0]); | |
306 | } | |
307 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { | |
308 | DRM_INFO("Loading RS690 Microcode\n"); | |
309 | for (i = 0; i < 256; i++) { | |
310 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
311 | RS690_cp_microcode[i][1]); | |
312 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | |
313 | RS690_cp_microcode[i][0]); | |
314 | } | |
315 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || | |
316 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || | |
317 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || | |
318 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || | |
319 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || | |
320 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { | |
321 | DRM_INFO("Loading R500 Microcode\n"); | |
b5e89ed5 DA |
322 | for (i = 0; i < 256; i++) { |
323 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | |
9f18409e | 324 | R520_cp_microcode[i][1]); |
b5e89ed5 | 325 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, |
9f18409e | 326 | R520_cp_microcode[i][0]); |
1da177e4 LT |
327 | } |
328 | } | |
329 | } | |
330 | ||
331 | /* Flush any pending commands to the CP. This should only be used just | |
332 | * prior to a wait for idle, as it informs the engine that the command | |
333 | * stream is ending. | |
334 | */ | |
b5e89ed5 | 335 | static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) |
1da177e4 | 336 | { |
b5e89ed5 | 337 | DRM_DEBUG("\n"); |
1da177e4 LT |
338 | #if 0 |
339 | u32 tmp; | |
340 | ||
b5e89ed5 DA |
341 | tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); |
342 | RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); | |
1da177e4 LT |
343 | #endif |
344 | } | |
345 | ||
346 | /* Wait for the CP to go idle. | |
347 | */ | |
b5e89ed5 | 348 | int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
349 | { |
350 | RING_LOCALS; | |
b5e89ed5 | 351 | DRM_DEBUG("\n"); |
1da177e4 | 352 | |
b5e89ed5 | 353 | BEGIN_RING(6); |
1da177e4 LT |
354 | |
355 | RADEON_PURGE_CACHE(); | |
356 | RADEON_PURGE_ZCACHE(); | |
357 | RADEON_WAIT_UNTIL_IDLE(); | |
358 | ||
359 | ADVANCE_RING(); | |
360 | COMMIT_RING(); | |
361 | ||
b5e89ed5 | 362 | return radeon_do_wait_for_idle(dev_priv); |
1da177e4 LT |
363 | } |
364 | ||
365 | /* Start the Command Processor. | |
366 | */ | |
b5e89ed5 | 367 | static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
368 | { |
369 | RING_LOCALS; | |
b5e89ed5 | 370 | DRM_DEBUG("\n"); |
1da177e4 | 371 | |
b5e89ed5 | 372 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 373 | |
b5e89ed5 | 374 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); |
1da177e4 LT |
375 | |
376 | dev_priv->cp_running = 1; | |
377 | ||
b5e89ed5 | 378 | BEGIN_RING(6); |
1da177e4 LT |
379 | |
380 | RADEON_PURGE_CACHE(); | |
381 | RADEON_PURGE_ZCACHE(); | |
382 | RADEON_WAIT_UNTIL_IDLE(); | |
383 | ||
384 | ADVANCE_RING(); | |
385 | COMMIT_RING(); | |
386 | } | |
387 | ||
388 | /* Reset the Command Processor. This will not flush any pending | |
389 | * commands, so you must wait for the CP command stream to complete | |
390 | * before calling this routine. | |
391 | */ | |
b5e89ed5 | 392 | static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
393 | { |
394 | u32 cur_read_ptr; | |
b5e89ed5 | 395 | DRM_DEBUG("\n"); |
1da177e4 | 396 | |
b5e89ed5 DA |
397 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
398 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); | |
399 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
1da177e4 LT |
400 | dev_priv->ring.tail = cur_read_ptr; |
401 | } | |
402 | ||
403 | /* Stop the Command Processor. This will not flush any pending | |
404 | * commands, so you must flush the command stream and wait for the CP | |
405 | * to go idle before calling this routine. | |
406 | */ | |
b5e89ed5 | 407 | static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) |
1da177e4 | 408 | { |
b5e89ed5 | 409 | DRM_DEBUG("\n"); |
1da177e4 | 410 | |
b5e89ed5 | 411 | RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); |
1da177e4 LT |
412 | |
413 | dev_priv->cp_running = 0; | |
414 | } | |
415 | ||
416 | /* Reset the engine. This will stop the CP if it is running. | |
417 | */ | |
84b1fd10 | 418 | static int radeon_do_engine_reset(struct drm_device * dev) |
1da177e4 LT |
419 | { |
420 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
421 | u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; | |
b5e89ed5 | 422 | DRM_DEBUG("\n"); |
1da177e4 | 423 | |
b5e89ed5 DA |
424 | radeon_do_pixcache_flush(dev_priv); |
425 | ||
3d5e2c13 DA |
426 | if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { |
427 | clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); | |
428 | mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); | |
429 | ||
430 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | | |
431 | RADEON_FORCEON_MCLKA | | |
432 | RADEON_FORCEON_MCLKB | | |
433 | RADEON_FORCEON_YCLKA | | |
434 | RADEON_FORCEON_YCLKB | | |
435 | RADEON_FORCEON_MC | | |
436 | RADEON_FORCEON_AIC)); | |
437 | ||
438 | rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
439 | ||
440 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | | |
441 | RADEON_SOFT_RESET_CP | | |
442 | RADEON_SOFT_RESET_HI | | |
443 | RADEON_SOFT_RESET_SE | | |
444 | RADEON_SOFT_RESET_RE | | |
445 | RADEON_SOFT_RESET_PP | | |
446 | RADEON_SOFT_RESET_E2 | | |
447 | RADEON_SOFT_RESET_RB)); | |
448 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
449 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & | |
450 | ~(RADEON_SOFT_RESET_CP | | |
451 | RADEON_SOFT_RESET_HI | | |
452 | RADEON_SOFT_RESET_SE | | |
453 | RADEON_SOFT_RESET_RE | | |
454 | RADEON_SOFT_RESET_PP | | |
455 | RADEON_SOFT_RESET_E2 | | |
456 | RADEON_SOFT_RESET_RB))); | |
457 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | |
458 | ||
459 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); | |
460 | RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); | |
461 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); | |
462 | } | |
1da177e4 LT |
463 | |
464 | /* Reset the CP ring */ | |
b5e89ed5 | 465 | radeon_do_cp_reset(dev_priv); |
1da177e4 LT |
466 | |
467 | /* The CP is no longer running after an engine reset */ | |
468 | dev_priv->cp_running = 0; | |
469 | ||
470 | /* Reset any pending vertex, indirect buffers */ | |
b5e89ed5 | 471 | radeon_freelist_reset(dev); |
1da177e4 LT |
472 | |
473 | return 0; | |
474 | } | |
475 | ||
84b1fd10 | 476 | static void radeon_cp_init_ring_buffer(struct drm_device * dev, |
b5e89ed5 | 477 | drm_radeon_private_t * dev_priv) |
1da177e4 LT |
478 | { |
479 | u32 ring_start, cur_read_ptr; | |
480 | u32 tmp; | |
bc5f4523 | 481 | |
d5ea702f DA |
482 | /* Initialize the memory controller. With new memory map, the fb location |
483 | * is not changed, it should have been properly initialized already. Part | |
484 | * of the problem is that the code below is bogus, assuming the GART is | |
485 | * always appended to the fb which is not necessarily the case | |
486 | */ | |
487 | if (!dev_priv->new_memmap) | |
3d5e2c13 | 488 | radeon_write_fb_location(dev_priv, |
d5ea702f DA |
489 | ((dev_priv->gart_vm_start - 1) & 0xffff0000) |
490 | | (dev_priv->fb_location >> 16)); | |
1da177e4 LT |
491 | |
492 | #if __OS_HAS_AGP | |
54a56ac5 | 493 | if (dev_priv->flags & RADEON_IS_AGP) { |
d5ea702f | 494 | RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); |
d7463eb4 AD |
495 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) |
496 | RADEON_WRITE(RADEON_AGP_BASE_2, 0); | |
3d5e2c13 | 497 | radeon_write_agp_location(dev_priv, |
b5e89ed5 DA |
498 | (((dev_priv->gart_vm_start - 1 + |
499 | dev_priv->gart_size) & 0xffff0000) | | |
500 | (dev_priv->gart_vm_start >> 16))); | |
1da177e4 LT |
501 | |
502 | ring_start = (dev_priv->cp_ring->offset | |
503 | - dev->agp->base | |
504 | + dev_priv->gart_vm_start); | |
b0917bd9 | 505 | } else |
1da177e4 LT |
506 | #endif |
507 | ring_start = (dev_priv->cp_ring->offset | |
b0917bd9 | 508 | - (unsigned long)dev->sg->virtual |
1da177e4 LT |
509 | + dev_priv->gart_vm_start); |
510 | ||
b5e89ed5 | 511 | RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); |
1da177e4 LT |
512 | |
513 | /* Set the write pointer delay */ | |
b5e89ed5 | 514 | RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); |
1da177e4 LT |
515 | |
516 | /* Initialize the ring buffer's read and write pointers */ | |
b5e89ed5 DA |
517 | cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); |
518 | RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); | |
519 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
1da177e4 LT |
520 | dev_priv->ring.tail = cur_read_ptr; |
521 | ||
522 | #if __OS_HAS_AGP | |
54a56ac5 | 523 | if (dev_priv->flags & RADEON_IS_AGP) { |
b5e89ed5 DA |
524 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, |
525 | dev_priv->ring_rptr->offset | |
526 | - dev->agp->base + dev_priv->gart_vm_start); | |
1da177e4 LT |
527 | } else |
528 | #endif | |
529 | { | |
55910517 | 530 | struct drm_sg_mem *entry = dev->sg; |
1da177e4 LT |
531 | unsigned long tmp_ofs, page_ofs; |
532 | ||
b0917bd9 IK |
533 | tmp_ofs = dev_priv->ring_rptr->offset - |
534 | (unsigned long)dev->sg->virtual; | |
1da177e4 LT |
535 | page_ofs = tmp_ofs >> PAGE_SHIFT; |
536 | ||
b5e89ed5 DA |
537 | RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); |
538 | DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", | |
539 | (unsigned long)entry->busaddr[page_ofs], | |
540 | entry->handle + tmp_ofs); | |
1da177e4 LT |
541 | } |
542 | ||
d5ea702f DA |
543 | /* Set ring buffer size */ |
544 | #ifdef __BIG_ENDIAN | |
545 | RADEON_WRITE(RADEON_CP_RB_CNTL, | |
576cc458 RS |
546 | RADEON_BUF_SWAP_32BIT | |
547 | (dev_priv->ring.fetch_size_l2ow << 18) | | |
548 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
549 | dev_priv->ring.size_l2qw); | |
d5ea702f | 550 | #else |
576cc458 RS |
551 | RADEON_WRITE(RADEON_CP_RB_CNTL, |
552 | (dev_priv->ring.fetch_size_l2ow << 18) | | |
553 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
554 | dev_priv->ring.size_l2qw); | |
d5ea702f DA |
555 | #endif |
556 | ||
557 | /* Start with assuming that writeback doesn't work */ | |
558 | dev_priv->writeback_works = 0; | |
559 | ||
1da177e4 LT |
560 | /* Initialize the scratch register pointer. This will cause |
561 | * the scratch register values to be written out to memory | |
562 | * whenever they are updated. | |
563 | * | |
564 | * We simply put this behind the ring read pointer, this works | |
565 | * with PCI GART as well as (whatever kind of) AGP GART | |
566 | */ | |
b5e89ed5 DA |
567 | RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) |
568 | + RADEON_SCRATCH_REG_OFFSET); | |
1da177e4 LT |
569 | |
570 | dev_priv->scratch = ((__volatile__ u32 *) | |
571 | dev_priv->ring_rptr->handle + | |
572 | (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); | |
573 | ||
b5e89ed5 | 574 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); |
1da177e4 | 575 | |
d5ea702f DA |
576 | /* Turn on bus mastering */ |
577 | tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; | |
578 | RADEON_WRITE(RADEON_BUS_CNTL, tmp); | |
1da177e4 LT |
579 | |
580 | dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; | |
b5e89ed5 | 581 | RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); |
1da177e4 LT |
582 | |
583 | dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; | |
b5e89ed5 DA |
584 | RADEON_WRITE(RADEON_LAST_DISPATCH_REG, |
585 | dev_priv->sarea_priv->last_dispatch); | |
1da177e4 LT |
586 | |
587 | dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; | |
b5e89ed5 | 588 | RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); |
1da177e4 | 589 | |
b5e89ed5 | 590 | radeon_do_wait_for_idle(dev_priv); |
1da177e4 | 591 | |
1da177e4 | 592 | /* Sync everything up */ |
b5e89ed5 DA |
593 | RADEON_WRITE(RADEON_ISYNC_CNTL, |
594 | (RADEON_ISYNC_ANY2D_IDLE3D | | |
595 | RADEON_ISYNC_ANY3D_IDLE2D | | |
596 | RADEON_ISYNC_WAIT_IDLEGUI | | |
597 | RADEON_ISYNC_CPSCRATCH_IDLEGUI)); | |
d5ea702f DA |
598 | |
599 | } | |
600 | ||
601 | static void radeon_test_writeback(drm_radeon_private_t * dev_priv) | |
602 | { | |
603 | u32 tmp; | |
604 | ||
605 | /* Writeback doesn't seem to work everywhere, test it here and possibly | |
606 | * enable it if it appears to work | |
607 | */ | |
608 | DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); | |
609 | RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); | |
610 | ||
611 | for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { | |
612 | if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == | |
613 | 0xdeadbeef) | |
614 | break; | |
615 | DRM_UDELAY(1); | |
616 | } | |
617 | ||
618 | if (tmp < dev_priv->usec_timeout) { | |
619 | dev_priv->writeback_works = 1; | |
620 | DRM_INFO("writeback test succeeded in %d usecs\n", tmp); | |
621 | } else { | |
622 | dev_priv->writeback_works = 0; | |
623 | DRM_INFO("writeback test failed\n"); | |
624 | } | |
625 | if (radeon_no_wb == 1) { | |
626 | dev_priv->writeback_works = 0; | |
627 | DRM_INFO("writeback forced off\n"); | |
628 | } | |
ae1b1a48 MD |
629 | |
630 | if (!dev_priv->writeback_works) { | |
631 | /* Disable writeback to avoid unnecessary bus master transfer */ | |
632 | RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | | |
633 | RADEON_RB_NO_UPDATE); | |
634 | RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); | |
635 | } | |
1da177e4 LT |
636 | } |
637 | ||
f2b04cd2 DA |
638 | /* Enable or disable IGP GART on the chip */ |
639 | static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) | |
60f92683 MC |
640 | { |
641 | u32 temp; | |
642 | ||
643 | if (on) { | |
45e51905 | 644 | DRM_DEBUG("programming igp gart %08X %08lX %08X\n", |
60f92683 MC |
645 | dev_priv->gart_vm_start, |
646 | (long)dev_priv->gart_info.bus_addr, | |
647 | dev_priv->gart_size); | |
648 | ||
45e51905 AD |
649 | temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); |
650 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) | |
651 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | | |
652 | RS690_BLOCK_GFX_D3_EN)); | |
653 | else | |
654 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); | |
60f92683 | 655 | |
45e51905 AD |
656 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | |
657 | RS480_VA_SIZE_32MB)); | |
60f92683 | 658 | |
45e51905 AD |
659 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); |
660 | IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | | |
661 | RS480_TLB_ENABLE | | |
662 | RS480_GTW_LAC_EN | | |
663 | RS480_1LEVEL_GART)); | |
60f92683 | 664 | |
fa0d71b9 DA |
665 | temp = dev_priv->gart_info.bus_addr & 0xfffff000; |
666 | temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; | |
45e51905 AD |
667 | IGP_WRITE_MCIND(RS480_GART_BASE, temp); |
668 | ||
669 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); | |
670 | IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | | |
671 | RS480_REQ_TYPE_SNOOP_DIS)); | |
672 | ||
673 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { | |
674 | IGP_WRITE_MCIND(RS690_MC_AGP_BASE, | |
675 | (unsigned int)dev_priv->gart_vm_start); | |
676 | IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0); | |
677 | } else { | |
678 | RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start); | |
679 | RADEON_WRITE(RS480_AGP_BASE_2, 0); | |
680 | } | |
3722bfc6 | 681 | |
60f92683 MC |
682 | dev_priv->gart_size = 32*1024*1024; |
683 | temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & | |
684 | 0xffff0000) | (dev_priv->gart_vm_start >> 16)); | |
685 | ||
45e51905 | 686 | radeon_write_agp_location(dev_priv, temp); |
60f92683 | 687 | |
45e51905 AD |
688 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); |
689 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | | |
690 | RS480_VA_SIZE_32MB)); | |
60f92683 MC |
691 | |
692 | do { | |
45e51905 AD |
693 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
694 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) | |
60f92683 MC |
695 | break; |
696 | DRM_UDELAY(1); | |
697 | } while (1); | |
698 | ||
45e51905 AD |
699 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, |
700 | RS480_GART_CACHE_INVALIDATE); | |
2735977b | 701 | |
60f92683 | 702 | do { |
45e51905 AD |
703 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
704 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) | |
60f92683 MC |
705 | break; |
706 | DRM_UDELAY(1); | |
707 | } while (1); | |
708 | ||
45e51905 | 709 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); |
60f92683 | 710 | } else { |
45e51905 | 711 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
60f92683 MC |
712 | } |
713 | } | |
714 | ||
ea98a92f DA |
715 | static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) |
716 | { | |
717 | u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); | |
718 | if (on) { | |
719 | ||
720 | DRM_DEBUG("programming pcie %08X %08lX %08X\n", | |
b5e89ed5 DA |
721 | dev_priv->gart_vm_start, |
722 | (long)dev_priv->gart_info.bus_addr, | |
ea98a92f | 723 | dev_priv->gart_size); |
b5e89ed5 DA |
724 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, |
725 | dev_priv->gart_vm_start); | |
726 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, | |
727 | dev_priv->gart_info.bus_addr); | |
728 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, | |
729 | dev_priv->gart_vm_start); | |
730 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, | |
731 | dev_priv->gart_vm_start + | |
732 | dev_priv->gart_size - 1); | |
733 | ||
3d5e2c13 | 734 | radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ |
b5e89ed5 DA |
735 | |
736 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, | |
737 | RADEON_PCIE_TX_GART_EN); | |
ea98a92f | 738 | } else { |
b5e89ed5 DA |
739 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
740 | tmp & ~RADEON_PCIE_TX_GART_EN); | |
ea98a92f | 741 | } |
1da177e4 LT |
742 | } |
743 | ||
744 | /* Enable or disable PCI GART on the chip */ | |
b5e89ed5 | 745 | static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) |
1da177e4 | 746 | { |
d985c108 | 747 | u32 tmp; |
1da177e4 | 748 | |
45e51905 AD |
749 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
750 | (dev_priv->flags & RADEON_IS_IGPGART)) { | |
f2b04cd2 DA |
751 | radeon_set_igpgart(dev_priv, on); |
752 | return; | |
753 | } | |
754 | ||
54a56ac5 | 755 | if (dev_priv->flags & RADEON_IS_PCIE) { |
ea98a92f DA |
756 | radeon_set_pciegart(dev_priv, on); |
757 | return; | |
758 | } | |
1da177e4 | 759 | |
bc5f4523 | 760 | tmp = RADEON_READ(RADEON_AIC_CNTL); |
d985c108 | 761 | |
b5e89ed5 DA |
762 | if (on) { |
763 | RADEON_WRITE(RADEON_AIC_CNTL, | |
764 | tmp | RADEON_PCIGART_TRANSLATE_EN); | |
1da177e4 LT |
765 | |
766 | /* set PCI GART page-table base address | |
767 | */ | |
ea98a92f | 768 | RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); |
1da177e4 LT |
769 | |
770 | /* set address range for PCI address translate | |
771 | */ | |
b5e89ed5 DA |
772 | RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); |
773 | RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start | |
774 | + dev_priv->gart_size - 1); | |
1da177e4 LT |
775 | |
776 | /* Turn off AGP aperture -- is this required for PCI GART? | |
777 | */ | |
3d5e2c13 | 778 | radeon_write_agp_location(dev_priv, 0xffffffc0); |
b5e89ed5 | 779 | RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
1da177e4 | 780 | } else { |
b5e89ed5 DA |
781 | RADEON_WRITE(RADEON_AIC_CNTL, |
782 | tmp & ~RADEON_PCIGART_TRANSLATE_EN); | |
1da177e4 LT |
783 | } |
784 | } | |
785 | ||
84b1fd10 | 786 | static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) |
1da177e4 | 787 | { |
d985c108 DA |
788 | drm_radeon_private_t *dev_priv = dev->dev_private; |
789 | ||
b5e89ed5 | 790 | DRM_DEBUG("\n"); |
1da177e4 | 791 | |
f3dd5c37 | 792 | /* if we require new memory map but we don't have it fail */ |
54a56ac5 | 793 | if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { |
b15ec368 | 794 | DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); |
f3dd5c37 | 795 | radeon_do_cleanup_cp(dev); |
20caafa6 | 796 | return -EINVAL; |
f3dd5c37 DA |
797 | } |
798 | ||
54a56ac5 | 799 | if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { |
d985c108 | 800 | DRM_DEBUG("Forcing AGP card to PCI mode\n"); |
54a56ac5 DA |
801 | dev_priv->flags &= ~RADEON_IS_AGP; |
802 | } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) | |
b15ec368 DA |
803 | && !init->is_pci) { |
804 | DRM_DEBUG("Restoring AGP flag\n"); | |
54a56ac5 | 805 | dev_priv->flags |= RADEON_IS_AGP; |
d985c108 | 806 | } |
1da177e4 | 807 | |
54a56ac5 | 808 | if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { |
b5e89ed5 | 809 | DRM_ERROR("PCI GART memory not allocated!\n"); |
1da177e4 | 810 | radeon_do_cleanup_cp(dev); |
20caafa6 | 811 | return -EINVAL; |
1da177e4 LT |
812 | } |
813 | ||
814 | dev_priv->usec_timeout = init->usec_timeout; | |
b5e89ed5 DA |
815 | if (dev_priv->usec_timeout < 1 || |
816 | dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { | |
817 | DRM_DEBUG("TIMEOUT problem!\n"); | |
1da177e4 | 818 | radeon_do_cleanup_cp(dev); |
20caafa6 | 819 | return -EINVAL; |
1da177e4 LT |
820 | } |
821 | ||
ddbee333 DA |
822 | /* Enable vblank on CRTC1 for older X servers |
823 | */ | |
824 | dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; | |
825 | ||
d985c108 | 826 | switch(init->func) { |
1da177e4 | 827 | case RADEON_INIT_R200_CP: |
b5e89ed5 | 828 | dev_priv->microcode_version = UCODE_R200; |
1da177e4 LT |
829 | break; |
830 | case RADEON_INIT_R300_CP: | |
b5e89ed5 | 831 | dev_priv->microcode_version = UCODE_R300; |
1da177e4 LT |
832 | break; |
833 | default: | |
b5e89ed5 | 834 | dev_priv->microcode_version = UCODE_R100; |
1da177e4 | 835 | } |
b5e89ed5 | 836 | |
1da177e4 LT |
837 | dev_priv->do_boxes = 0; |
838 | dev_priv->cp_mode = init->cp_mode; | |
839 | ||
840 | /* We don't support anything other than bus-mastering ring mode, | |
841 | * but the ring can be in either AGP or PCI space for the ring | |
842 | * read pointer. | |
843 | */ | |
b5e89ed5 DA |
844 | if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && |
845 | (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { | |
846 | DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); | |
1da177e4 | 847 | radeon_do_cleanup_cp(dev); |
20caafa6 | 848 | return -EINVAL; |
1da177e4 LT |
849 | } |
850 | ||
b5e89ed5 | 851 | switch (init->fb_bpp) { |
1da177e4 LT |
852 | case 16: |
853 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; | |
854 | break; | |
855 | case 32: | |
856 | default: | |
857 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; | |
858 | break; | |
859 | } | |
b5e89ed5 DA |
860 | dev_priv->front_offset = init->front_offset; |
861 | dev_priv->front_pitch = init->front_pitch; | |
862 | dev_priv->back_offset = init->back_offset; | |
863 | dev_priv->back_pitch = init->back_pitch; | |
1da177e4 | 864 | |
b5e89ed5 | 865 | switch (init->depth_bpp) { |
1da177e4 LT |
866 | case 16: |
867 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; | |
868 | break; | |
869 | case 32: | |
870 | default: | |
871 | dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; | |
872 | break; | |
873 | } | |
b5e89ed5 DA |
874 | dev_priv->depth_offset = init->depth_offset; |
875 | dev_priv->depth_pitch = init->depth_pitch; | |
1da177e4 LT |
876 | |
877 | /* Hardware state for depth clears. Remove this if/when we no | |
878 | * longer clear the depth buffer with a 3D rectangle. Hard-code | |
879 | * all values to prevent unwanted 3D state from slipping through | |
880 | * and screwing with the clear operation. | |
881 | */ | |
882 | dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | | |
883 | (dev_priv->color_fmt << 10) | | |
b5e89ed5 DA |
884 | (dev_priv->microcode_version == |
885 | UCODE_R100 ? RADEON_ZBLOCK16 : 0)); | |
1da177e4 | 886 | |
b5e89ed5 DA |
887 | dev_priv->depth_clear.rb3d_zstencilcntl = |
888 | (dev_priv->depth_fmt | | |
889 | RADEON_Z_TEST_ALWAYS | | |
890 | RADEON_STENCIL_TEST_ALWAYS | | |
891 | RADEON_STENCIL_S_FAIL_REPLACE | | |
892 | RADEON_STENCIL_ZPASS_REPLACE | | |
893 | RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); | |
1da177e4 LT |
894 | |
895 | dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | | |
896 | RADEON_BFACE_SOLID | | |
897 | RADEON_FFACE_SOLID | | |
898 | RADEON_FLAT_SHADE_VTX_LAST | | |
899 | RADEON_DIFFUSE_SHADE_FLAT | | |
900 | RADEON_ALPHA_SHADE_FLAT | | |
901 | RADEON_SPECULAR_SHADE_FLAT | | |
902 | RADEON_FOG_SHADE_FLAT | | |
903 | RADEON_VTX_PIX_CENTER_OGL | | |
904 | RADEON_ROUND_MODE_TRUNC | | |
905 | RADEON_ROUND_PREC_8TH_PIX); | |
906 | ||
1da177e4 | 907 | |
1da177e4 LT |
908 | dev_priv->ring_offset = init->ring_offset; |
909 | dev_priv->ring_rptr_offset = init->ring_rptr_offset; | |
910 | dev_priv->buffers_offset = init->buffers_offset; | |
911 | dev_priv->gart_textures_offset = init->gart_textures_offset; | |
b5e89ed5 | 912 | |
da509d7a | 913 | dev_priv->sarea = drm_getsarea(dev); |
b5e89ed5 | 914 | if (!dev_priv->sarea) { |
1da177e4 | 915 | DRM_ERROR("could not find sarea!\n"); |
1da177e4 | 916 | radeon_do_cleanup_cp(dev); |
20caafa6 | 917 | return -EINVAL; |
1da177e4 LT |
918 | } |
919 | ||
1da177e4 | 920 | dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); |
b5e89ed5 | 921 | if (!dev_priv->cp_ring) { |
1da177e4 | 922 | DRM_ERROR("could not find cp ring region!\n"); |
1da177e4 | 923 | radeon_do_cleanup_cp(dev); |
20caafa6 | 924 | return -EINVAL; |
1da177e4 LT |
925 | } |
926 | dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); | |
b5e89ed5 | 927 | if (!dev_priv->ring_rptr) { |
1da177e4 | 928 | DRM_ERROR("could not find ring read pointer!\n"); |
1da177e4 | 929 | radeon_do_cleanup_cp(dev); |
20caafa6 | 930 | return -EINVAL; |
1da177e4 | 931 | } |
d1f2b55a | 932 | dev->agp_buffer_token = init->buffers_offset; |
1da177e4 | 933 | dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); |
b5e89ed5 | 934 | if (!dev->agp_buffer_map) { |
1da177e4 | 935 | DRM_ERROR("could not find dma buffer region!\n"); |
1da177e4 | 936 | radeon_do_cleanup_cp(dev); |
20caafa6 | 937 | return -EINVAL; |
1da177e4 LT |
938 | } |
939 | ||
b5e89ed5 DA |
940 | if (init->gart_textures_offset) { |
941 | dev_priv->gart_textures = | |
942 | drm_core_findmap(dev, init->gart_textures_offset); | |
943 | if (!dev_priv->gart_textures) { | |
1da177e4 | 944 | DRM_ERROR("could not find GART texture region!\n"); |
1da177e4 | 945 | radeon_do_cleanup_cp(dev); |
20caafa6 | 946 | return -EINVAL; |
1da177e4 LT |
947 | } |
948 | } | |
949 | ||
950 | dev_priv->sarea_priv = | |
b5e89ed5 DA |
951 | (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + |
952 | init->sarea_priv_offset); | |
1da177e4 LT |
953 | |
954 | #if __OS_HAS_AGP | |
54a56ac5 | 955 | if (dev_priv->flags & RADEON_IS_AGP) { |
b5e89ed5 DA |
956 | drm_core_ioremap(dev_priv->cp_ring, dev); |
957 | drm_core_ioremap(dev_priv->ring_rptr, dev); | |
958 | drm_core_ioremap(dev->agp_buffer_map, dev); | |
959 | if (!dev_priv->cp_ring->handle || | |
960 | !dev_priv->ring_rptr->handle || | |
961 | !dev->agp_buffer_map->handle) { | |
1da177e4 | 962 | DRM_ERROR("could not find ioremap agp regions!\n"); |
1da177e4 | 963 | radeon_do_cleanup_cp(dev); |
20caafa6 | 964 | return -EINVAL; |
1da177e4 LT |
965 | } |
966 | } else | |
967 | #endif | |
968 | { | |
b5e89ed5 | 969 | dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; |
1da177e4 | 970 | dev_priv->ring_rptr->handle = |
b5e89ed5 DA |
971 | (void *)dev_priv->ring_rptr->offset; |
972 | dev->agp_buffer_map->handle = | |
973 | (void *)dev->agp_buffer_map->offset; | |
974 | ||
975 | DRM_DEBUG("dev_priv->cp_ring->handle %p\n", | |
976 | dev_priv->cp_ring->handle); | |
977 | DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", | |
978 | dev_priv->ring_rptr->handle); | |
979 | DRM_DEBUG("dev->agp_buffer_map->handle %p\n", | |
980 | dev->agp_buffer_map->handle); | |
1da177e4 LT |
981 | } |
982 | ||
3d5e2c13 | 983 | dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; |
bc5f4523 | 984 | dev_priv->fb_size = |
3d5e2c13 | 985 | ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) |
d5ea702f | 986 | - dev_priv->fb_location; |
1da177e4 | 987 | |
b5e89ed5 DA |
988 | dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | |
989 | ((dev_priv->front_offset | |
990 | + dev_priv->fb_location) >> 10)); | |
1da177e4 | 991 | |
b5e89ed5 DA |
992 | dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | |
993 | ((dev_priv->back_offset | |
994 | + dev_priv->fb_location) >> 10)); | |
1da177e4 | 995 | |
b5e89ed5 DA |
996 | dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | |
997 | ((dev_priv->depth_offset | |
998 | + dev_priv->fb_location) >> 10)); | |
1da177e4 LT |
999 | |
1000 | dev_priv->gart_size = init->gart_size; | |
d5ea702f DA |
1001 | |
1002 | /* New let's set the memory map ... */ | |
1003 | if (dev_priv->new_memmap) { | |
1004 | u32 base = 0; | |
1005 | ||
1006 | DRM_INFO("Setting GART location based on new memory map\n"); | |
1007 | ||
1008 | /* If using AGP, try to locate the AGP aperture at the same | |
1009 | * location in the card and on the bus, though we have to | |
1010 | * align it down. | |
1011 | */ | |
1012 | #if __OS_HAS_AGP | |
54a56ac5 | 1013 | if (dev_priv->flags & RADEON_IS_AGP) { |
d5ea702f DA |
1014 | base = dev->agp->base; |
1015 | /* Check if valid */ | |
80b2c386 MD |
1016 | if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && |
1017 | base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { | |
d5ea702f DA |
1018 | DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", |
1019 | dev->agp->base); | |
1020 | base = 0; | |
1021 | } | |
1022 | } | |
1023 | #endif | |
1024 | /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ | |
1025 | if (base == 0) { | |
1026 | base = dev_priv->fb_location + dev_priv->fb_size; | |
80b2c386 MD |
1027 | if (base < dev_priv->fb_location || |
1028 | ((base + dev_priv->gart_size) & 0xfffffffful) < base) | |
d5ea702f DA |
1029 | base = dev_priv->fb_location |
1030 | - dev_priv->gart_size; | |
bc5f4523 | 1031 | } |
d5ea702f DA |
1032 | dev_priv->gart_vm_start = base & 0xffc00000u; |
1033 | if (dev_priv->gart_vm_start != base) | |
1034 | DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", | |
1035 | base, dev_priv->gart_vm_start); | |
1036 | } else { | |
1037 | DRM_INFO("Setting GART location based on old memory map\n"); | |
1038 | dev_priv->gart_vm_start = dev_priv->fb_location + | |
1039 | RADEON_READ(RADEON_CONFIG_APER_SIZE); | |
1040 | } | |
1da177e4 LT |
1041 | |
1042 | #if __OS_HAS_AGP | |
54a56ac5 | 1043 | if (dev_priv->flags & RADEON_IS_AGP) |
1da177e4 | 1044 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset |
b5e89ed5 DA |
1045 | - dev->agp->base |
1046 | + dev_priv->gart_vm_start); | |
1da177e4 LT |
1047 | else |
1048 | #endif | |
1049 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset | |
b0917bd9 IK |
1050 | - (unsigned long)dev->sg->virtual |
1051 | + dev_priv->gart_vm_start); | |
1da177e4 | 1052 | |
b5e89ed5 DA |
1053 | DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); |
1054 | DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); | |
1055 | DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", | |
1056 | dev_priv->gart_buffers_offset); | |
1da177e4 | 1057 | |
b5e89ed5 DA |
1058 | dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; |
1059 | dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle | |
1da177e4 LT |
1060 | + init->ring_size / sizeof(u32)); |
1061 | dev_priv->ring.size = init->ring_size; | |
b5e89ed5 | 1062 | dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); |
1da177e4 | 1063 | |
576cc458 RS |
1064 | dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; |
1065 | dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); | |
1066 | ||
1067 | dev_priv->ring.fetch_size = /* init->fetch_size */ 32; | |
1068 | dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); | |
b5e89ed5 | 1069 | dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; |
1da177e4 LT |
1070 | |
1071 | dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; | |
1072 | ||
1073 | #if __OS_HAS_AGP | |
54a56ac5 | 1074 | if (dev_priv->flags & RADEON_IS_AGP) { |
1da177e4 | 1075 | /* Turn off PCI GART */ |
b5e89ed5 | 1076 | radeon_set_pcigart(dev_priv, 0); |
1da177e4 LT |
1077 | } else |
1078 | #endif | |
1079 | { | |
b05c2385 | 1080 | dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); |
ea98a92f | 1081 | /* if we have an offset set from userspace */ |
f2b04cd2 | 1082 | if (dev_priv->pcigart_offset_set) { |
b5e89ed5 DA |
1083 | dev_priv->gart_info.bus_addr = |
1084 | dev_priv->pcigart_offset + dev_priv->fb_location; | |
f26c473c | 1085 | dev_priv->gart_info.mapping.offset = |
7fc86860 | 1086 | dev_priv->pcigart_offset + dev_priv->fb_aper_offset; |
f26c473c | 1087 | dev_priv->gart_info.mapping.size = |
f2b04cd2 | 1088 | dev_priv->gart_info.table_size; |
f26c473c DA |
1089 | |
1090 | drm_core_ioremap(&dev_priv->gart_info.mapping, dev); | |
b5e89ed5 | 1091 | dev_priv->gart_info.addr = |
f26c473c | 1092 | dev_priv->gart_info.mapping.handle; |
b5e89ed5 | 1093 | |
f2b04cd2 DA |
1094 | if (dev_priv->flags & RADEON_IS_PCIE) |
1095 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; | |
1096 | else | |
1097 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; | |
b5e89ed5 DA |
1098 | dev_priv->gart_info.gart_table_location = |
1099 | DRM_ATI_GART_FB; | |
1100 | ||
f26c473c | 1101 | DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", |
b5e89ed5 DA |
1102 | dev_priv->gart_info.addr, |
1103 | dev_priv->pcigart_offset); | |
1104 | } else { | |
f2b04cd2 DA |
1105 | if (dev_priv->flags & RADEON_IS_IGPGART) |
1106 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; | |
1107 | else | |
1108 | dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; | |
b5e89ed5 DA |
1109 | dev_priv->gart_info.gart_table_location = |
1110 | DRM_ATI_GART_MAIN; | |
f26c473c DA |
1111 | dev_priv->gart_info.addr = NULL; |
1112 | dev_priv->gart_info.bus_addr = 0; | |
54a56ac5 | 1113 | if (dev_priv->flags & RADEON_IS_PCIE) { |
b5e89ed5 DA |
1114 | DRM_ERROR |
1115 | ("Cannot use PCI Express without GART in FB memory\n"); | |
ea98a92f | 1116 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1117 | return -EINVAL; |
ea98a92f DA |
1118 | } |
1119 | } | |
1120 | ||
1121 | if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { | |
b5e89ed5 | 1122 | DRM_ERROR("failed to init PCI GART!\n"); |
1da177e4 | 1123 | radeon_do_cleanup_cp(dev); |
20caafa6 | 1124 | return -ENOMEM; |
1da177e4 LT |
1125 | } |
1126 | ||
1127 | /* Turn on PCI GART */ | |
b5e89ed5 | 1128 | radeon_set_pcigart(dev_priv, 1); |
1da177e4 LT |
1129 | } |
1130 | ||
b5e89ed5 DA |
1131 | radeon_cp_load_microcode(dev_priv); |
1132 | radeon_cp_init_ring_buffer(dev, dev_priv); | |
1da177e4 LT |
1133 | |
1134 | dev_priv->last_buf = 0; | |
1135 | ||
b5e89ed5 | 1136 | radeon_do_engine_reset(dev); |
d5ea702f | 1137 | radeon_test_writeback(dev_priv); |
1da177e4 LT |
1138 | |
1139 | return 0; | |
1140 | } | |
1141 | ||
84b1fd10 | 1142 | static int radeon_do_cleanup_cp(struct drm_device * dev) |
1da177e4 LT |
1143 | { |
1144 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1145 | DRM_DEBUG("\n"); |
1da177e4 LT |
1146 | |
1147 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
1148 | * may not have been called from userspace and after dev_private | |
1149 | * is freed, it's too late. | |
1150 | */ | |
b5e89ed5 DA |
1151 | if (dev->irq_enabled) |
1152 | drm_irq_uninstall(dev); | |
1da177e4 LT |
1153 | |
1154 | #if __OS_HAS_AGP | |
54a56ac5 | 1155 | if (dev_priv->flags & RADEON_IS_AGP) { |
d985c108 | 1156 | if (dev_priv->cp_ring != NULL) { |
b5e89ed5 | 1157 | drm_core_ioremapfree(dev_priv->cp_ring, dev); |
d985c108 DA |
1158 | dev_priv->cp_ring = NULL; |
1159 | } | |
1160 | if (dev_priv->ring_rptr != NULL) { | |
b5e89ed5 | 1161 | drm_core_ioremapfree(dev_priv->ring_rptr, dev); |
d985c108 DA |
1162 | dev_priv->ring_rptr = NULL; |
1163 | } | |
b5e89ed5 DA |
1164 | if (dev->agp_buffer_map != NULL) { |
1165 | drm_core_ioremapfree(dev->agp_buffer_map, dev); | |
1da177e4 LT |
1166 | dev->agp_buffer_map = NULL; |
1167 | } | |
1168 | } else | |
1169 | #endif | |
1170 | { | |
d985c108 DA |
1171 | |
1172 | if (dev_priv->gart_info.bus_addr) { | |
1173 | /* Turn off PCI GART */ | |
1174 | radeon_set_pcigart(dev_priv, 0); | |
ea98a92f DA |
1175 | if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) |
1176 | DRM_ERROR("failed to cleanup PCI GART!\n"); | |
d985c108 | 1177 | } |
b5e89ed5 | 1178 | |
d985c108 DA |
1179 | if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) |
1180 | { | |
f26c473c | 1181 | drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); |
f2b04cd2 | 1182 | dev_priv->gart_info.addr = 0; |
ea98a92f | 1183 | } |
1da177e4 | 1184 | } |
1da177e4 LT |
1185 | /* only clear to the start of flags */ |
1186 | memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); | |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
b5e89ed5 DA |
1191 | /* This code will reinit the Radeon CP hardware after a resume from disc. |
1192 | * AFAIK, it would be very difficult to pickle the state at suspend time, so | |
1da177e4 LT |
1193 | * here we make sure that all Radeon hardware initialisation is re-done without |
1194 | * affecting running applications. | |
1195 | * | |
1196 | * Charl P. Botha <http://cpbotha.net> | |
1197 | */ | |
84b1fd10 | 1198 | static int radeon_do_resume_cp(struct drm_device * dev) |
1da177e4 LT |
1199 | { |
1200 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1201 | ||
b5e89ed5 DA |
1202 | if (!dev_priv) { |
1203 | DRM_ERROR("Called with no initialization\n"); | |
20caafa6 | 1204 | return -EINVAL; |
1da177e4 LT |
1205 | } |
1206 | ||
1207 | DRM_DEBUG("Starting radeon_do_resume_cp()\n"); | |
1208 | ||
1209 | #if __OS_HAS_AGP | |
54a56ac5 | 1210 | if (dev_priv->flags & RADEON_IS_AGP) { |
1da177e4 | 1211 | /* Turn off PCI GART */ |
b5e89ed5 | 1212 | radeon_set_pcigart(dev_priv, 0); |
1da177e4 LT |
1213 | } else |
1214 | #endif | |
1215 | { | |
1216 | /* Turn on PCI GART */ | |
b5e89ed5 | 1217 | radeon_set_pcigart(dev_priv, 1); |
1da177e4 LT |
1218 | } |
1219 | ||
b5e89ed5 DA |
1220 | radeon_cp_load_microcode(dev_priv); |
1221 | radeon_cp_init_ring_buffer(dev, dev_priv); | |
1da177e4 | 1222 | |
b5e89ed5 | 1223 | radeon_do_engine_reset(dev); |
1da177e4 LT |
1224 | |
1225 | DRM_DEBUG("radeon_do_resume_cp() complete\n"); | |
1226 | ||
1227 | return 0; | |
1228 | } | |
1229 | ||
c153f45f | 1230 | int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1231 | { |
c153f45f | 1232 | drm_radeon_init_t *init = data; |
1da177e4 | 1233 | |
6c340eac | 1234 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1235 | |
c153f45f | 1236 | if (init->func == RADEON_INIT_R300_CP) |
3d5e2c13 | 1237 | r300_init_reg_flags(dev); |
414ed537 | 1238 | |
c153f45f | 1239 | switch (init->func) { |
1da177e4 LT |
1240 | case RADEON_INIT_CP: |
1241 | case RADEON_INIT_R200_CP: | |
1242 | case RADEON_INIT_R300_CP: | |
c153f45f | 1243 | return radeon_do_init_cp(dev, init); |
1da177e4 | 1244 | case RADEON_CLEANUP_CP: |
b5e89ed5 | 1245 | return radeon_do_cleanup_cp(dev); |
1da177e4 LT |
1246 | } |
1247 | ||
20caafa6 | 1248 | return -EINVAL; |
1da177e4 LT |
1249 | } |
1250 | ||
c153f45f | 1251 | int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1252 | { |
1da177e4 | 1253 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1254 | DRM_DEBUG("\n"); |
1da177e4 | 1255 | |
6c340eac | 1256 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1257 | |
b5e89ed5 | 1258 | if (dev_priv->cp_running) { |
3e684eae | 1259 | DRM_DEBUG("while CP running\n"); |
1da177e4 LT |
1260 | return 0; |
1261 | } | |
b5e89ed5 | 1262 | if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { |
3e684eae MN |
1263 | DRM_DEBUG("called with bogus CP mode (%d)\n", |
1264 | dev_priv->cp_mode); | |
1da177e4 LT |
1265 | return 0; |
1266 | } | |
1267 | ||
b5e89ed5 | 1268 | radeon_do_cp_start(dev_priv); |
1da177e4 LT |
1269 | |
1270 | return 0; | |
1271 | } | |
1272 | ||
1273 | /* Stop the CP. The engine must have been idled before calling this | |
1274 | * routine. | |
1275 | */ | |
c153f45f | 1276 | int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1277 | { |
1da177e4 | 1278 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 1279 | drm_radeon_cp_stop_t *stop = data; |
1da177e4 | 1280 | int ret; |
b5e89ed5 | 1281 | DRM_DEBUG("\n"); |
1da177e4 | 1282 | |
6c340eac | 1283 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1284 | |
1da177e4 LT |
1285 | if (!dev_priv->cp_running) |
1286 | return 0; | |
1287 | ||
1288 | /* Flush any pending CP commands. This ensures any outstanding | |
1289 | * commands are exectuted by the engine before we turn it off. | |
1290 | */ | |
c153f45f | 1291 | if (stop->flush) { |
b5e89ed5 | 1292 | radeon_do_cp_flush(dev_priv); |
1da177e4 LT |
1293 | } |
1294 | ||
1295 | /* If we fail to make the engine go idle, we return an error | |
1296 | * code so that the DRM ioctl wrapper can try again. | |
1297 | */ | |
c153f45f | 1298 | if (stop->idle) { |
b5e89ed5 DA |
1299 | ret = radeon_do_cp_idle(dev_priv); |
1300 | if (ret) | |
1301 | return ret; | |
1da177e4 LT |
1302 | } |
1303 | ||
1304 | /* Finally, we can turn off the CP. If the engine isn't idle, | |
1305 | * we will get some dropped triangles as they won't be fully | |
1306 | * rendered before the CP is shut down. | |
1307 | */ | |
b5e89ed5 | 1308 | radeon_do_cp_stop(dev_priv); |
1da177e4 LT |
1309 | |
1310 | /* Reset the engine */ | |
b5e89ed5 | 1311 | radeon_do_engine_reset(dev); |
1da177e4 LT |
1312 | |
1313 | return 0; | |
1314 | } | |
1315 | ||
84b1fd10 | 1316 | void radeon_do_release(struct drm_device * dev) |
1da177e4 LT |
1317 | { |
1318 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1319 | int i, ret; | |
1320 | ||
1321 | if (dev_priv) { | |
1322 | if (dev_priv->cp_running) { | |
1323 | /* Stop the cp */ | |
b5e89ed5 | 1324 | while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { |
1da177e4 LT |
1325 | DRM_DEBUG("radeon_do_cp_idle %d\n", ret); |
1326 | #ifdef __linux__ | |
1327 | schedule(); | |
1328 | #else | |
1329 | tsleep(&ret, PZERO, "rdnrel", 1); | |
1330 | #endif | |
1331 | } | |
b5e89ed5 DA |
1332 | radeon_do_cp_stop(dev_priv); |
1333 | radeon_do_engine_reset(dev); | |
1da177e4 LT |
1334 | } |
1335 | ||
1336 | /* Disable *all* interrupts */ | |
1337 | if (dev_priv->mmio) /* remove this after permanent addmaps */ | |
b5e89ed5 | 1338 | RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); |
1da177e4 | 1339 | |
b5e89ed5 | 1340 | if (dev_priv->mmio) { /* remove all surfaces */ |
1da177e4 | 1341 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { |
b5e89ed5 DA |
1342 | RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); |
1343 | RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + | |
1344 | 16 * i, 0); | |
1345 | RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + | |
1346 | 16 * i, 0); | |
1da177e4 LT |
1347 | } |
1348 | } | |
1349 | ||
1350 | /* Free memory heap structures */ | |
b5e89ed5 DA |
1351 | radeon_mem_takedown(&(dev_priv->gart_heap)); |
1352 | radeon_mem_takedown(&(dev_priv->fb_heap)); | |
1da177e4 LT |
1353 | |
1354 | /* deallocate kernel resources */ | |
b5e89ed5 | 1355 | radeon_do_cleanup_cp(dev); |
1da177e4 LT |
1356 | } |
1357 | } | |
1358 | ||
1359 | /* Just reset the CP ring. Called as part of an X Server engine reset. | |
1360 | */ | |
c153f45f | 1361 | int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1362 | { |
1da177e4 | 1363 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1364 | DRM_DEBUG("\n"); |
1da177e4 | 1365 | |
6c340eac | 1366 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1367 | |
b5e89ed5 | 1368 | if (!dev_priv) { |
3e684eae | 1369 | DRM_DEBUG("called before init done\n"); |
20caafa6 | 1370 | return -EINVAL; |
1da177e4 LT |
1371 | } |
1372 | ||
b5e89ed5 | 1373 | radeon_do_cp_reset(dev_priv); |
1da177e4 LT |
1374 | |
1375 | /* The CP is no longer running after an engine reset */ | |
1376 | dev_priv->cp_running = 0; | |
1377 | ||
1378 | return 0; | |
1379 | } | |
1380 | ||
c153f45f | 1381 | int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1382 | { |
1da177e4 | 1383 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 | 1384 | DRM_DEBUG("\n"); |
1da177e4 | 1385 | |
6c340eac | 1386 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1387 | |
b5e89ed5 | 1388 | return radeon_do_cp_idle(dev_priv); |
1da177e4 LT |
1389 | } |
1390 | ||
1391 | /* Added by Charl P. Botha to call radeon_do_resume_cp(). | |
1392 | */ | |
c153f45f | 1393 | int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1394 | { |
1da177e4 LT |
1395 | |
1396 | return radeon_do_resume_cp(dev); | |
1397 | } | |
1398 | ||
c153f45f | 1399 | int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1400 | { |
b5e89ed5 | 1401 | DRM_DEBUG("\n"); |
1da177e4 | 1402 | |
6c340eac | 1403 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1404 | |
b5e89ed5 | 1405 | return radeon_do_engine_reset(dev); |
1da177e4 LT |
1406 | } |
1407 | ||
1da177e4 LT |
1408 | /* ================================================================ |
1409 | * Fullscreen mode | |
1410 | */ | |
1411 | ||
1412 | /* KW: Deprecated to say the least: | |
1413 | */ | |
c153f45f | 1414 | int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 LT |
1415 | { |
1416 | return 0; | |
1417 | } | |
1418 | ||
1da177e4 LT |
1419 | /* ================================================================ |
1420 | * Freelist management | |
1421 | */ | |
1422 | ||
1423 | /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through | |
1424 | * bufs until freelist code is used. Note this hides a problem with | |
1425 | * the scratch register * (used to keep track of last buffer | |
1426 | * completed) being written to before * the last buffer has actually | |
b5e89ed5 | 1427 | * completed rendering. |
1da177e4 LT |
1428 | * |
1429 | * KW: It's also a good way to find free buffers quickly. | |
1430 | * | |
1431 | * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't | |
1432 | * sleep. However, bugs in older versions of radeon_accel.c mean that | |
1433 | * we essentially have to do this, else old clients will break. | |
b5e89ed5 | 1434 | * |
1da177e4 LT |
1435 | * However, it does leave open a potential deadlock where all the |
1436 | * buffers are held by other clients, which can't release them because | |
b5e89ed5 | 1437 | * they can't get the lock. |
1da177e4 LT |
1438 | */ |
1439 | ||
056219e2 | 1440 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
1da177e4 | 1441 | { |
cdd55a29 | 1442 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1443 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1444 | drm_radeon_buf_priv_t *buf_priv; | |
056219e2 | 1445 | struct drm_buf *buf; |
1da177e4 LT |
1446 | int i, t; |
1447 | int start; | |
1448 | ||
b5e89ed5 | 1449 | if (++dev_priv->last_buf >= dma->buf_count) |
1da177e4 LT |
1450 | dev_priv->last_buf = 0; |
1451 | ||
1452 | start = dev_priv->last_buf; | |
1453 | ||
b5e89ed5 DA |
1454 | for (t = 0; t < dev_priv->usec_timeout; t++) { |
1455 | u32 done_age = GET_SCRATCH(1); | |
1456 | DRM_DEBUG("done_age = %d\n", done_age); | |
1457 | for (i = start; i < dma->buf_count; i++) { | |
1da177e4 LT |
1458 | buf = dma->buflist[i]; |
1459 | buf_priv = buf->dev_private; | |
6c340eac EA |
1460 | if (buf->file_priv == NULL || (buf->pending && |
1461 | buf_priv->age <= | |
1462 | done_age)) { | |
1da177e4 LT |
1463 | dev_priv->stats.requested_bufs++; |
1464 | buf->pending = 0; | |
1465 | return buf; | |
1466 | } | |
1467 | start = 0; | |
1468 | } | |
1469 | ||
1470 | if (t) { | |
b5e89ed5 | 1471 | DRM_UDELAY(1); |
1da177e4 LT |
1472 | dev_priv->stats.freelist_loops++; |
1473 | } | |
1474 | } | |
1475 | ||
b5e89ed5 | 1476 | DRM_DEBUG("returning NULL!\n"); |
1da177e4 LT |
1477 | return NULL; |
1478 | } | |
b5e89ed5 | 1479 | |
1da177e4 | 1480 | #if 0 |
056219e2 | 1481 | struct drm_buf *radeon_freelist_get(struct drm_device * dev) |
1da177e4 | 1482 | { |
cdd55a29 | 1483 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1484 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1485 | drm_radeon_buf_priv_t *buf_priv; | |
056219e2 | 1486 | struct drm_buf *buf; |
1da177e4 LT |
1487 | int i, t; |
1488 | int start; | |
1489 | u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); | |
1490 | ||
b5e89ed5 | 1491 | if (++dev_priv->last_buf >= dma->buf_count) |
1da177e4 LT |
1492 | dev_priv->last_buf = 0; |
1493 | ||
1494 | start = dev_priv->last_buf; | |
1495 | dev_priv->stats.freelist_loops++; | |
b5e89ed5 DA |
1496 | |
1497 | for (t = 0; t < 2; t++) { | |
1498 | for (i = start; i < dma->buf_count; i++) { | |
1da177e4 LT |
1499 | buf = dma->buflist[i]; |
1500 | buf_priv = buf->dev_private; | |
6c340eac EA |
1501 | if (buf->file_priv == 0 || (buf->pending && |
1502 | buf_priv->age <= | |
1503 | done_age)) { | |
1da177e4 LT |
1504 | dev_priv->stats.requested_bufs++; |
1505 | buf->pending = 0; | |
1506 | return buf; | |
1507 | } | |
1508 | } | |
1509 | start = 0; | |
1510 | } | |
1511 | ||
1512 | return NULL; | |
1513 | } | |
1514 | #endif | |
1515 | ||
84b1fd10 | 1516 | void radeon_freelist_reset(struct drm_device * dev) |
1da177e4 | 1517 | { |
cdd55a29 | 1518 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1519 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1520 | int i; | |
1521 | ||
1522 | dev_priv->last_buf = 0; | |
b5e89ed5 | 1523 | for (i = 0; i < dma->buf_count; i++) { |
056219e2 | 1524 | struct drm_buf *buf = dma->buflist[i]; |
1da177e4 LT |
1525 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; |
1526 | buf_priv->age = 0; | |
1527 | } | |
1528 | } | |
1529 | ||
1da177e4 LT |
1530 | /* ================================================================ |
1531 | * CP command submission | |
1532 | */ | |
1533 | ||
b5e89ed5 | 1534 | int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) |
1da177e4 LT |
1535 | { |
1536 | drm_radeon_ring_buffer_t *ring = &dev_priv->ring; | |
1537 | int i; | |
b5e89ed5 | 1538 | u32 last_head = GET_RING_HEAD(dev_priv); |
1da177e4 | 1539 | |
b5e89ed5 DA |
1540 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
1541 | u32 head = GET_RING_HEAD(dev_priv); | |
1da177e4 LT |
1542 | |
1543 | ring->space = (head - ring->tail) * sizeof(u32); | |
b5e89ed5 | 1544 | if (ring->space <= 0) |
1da177e4 | 1545 | ring->space += ring->size; |
b5e89ed5 | 1546 | if (ring->space > n) |
1da177e4 | 1547 | return 0; |
b5e89ed5 | 1548 | |
1da177e4 LT |
1549 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
1550 | ||
1551 | if (head != last_head) | |
1552 | i = 0; | |
1553 | last_head = head; | |
1554 | ||
b5e89ed5 | 1555 | DRM_UDELAY(1); |
1da177e4 LT |
1556 | } |
1557 | ||
1558 | /* FIXME: This return value is ignored in the BEGIN_RING macro! */ | |
1559 | #if RADEON_FIFO_DEBUG | |
b5e89ed5 DA |
1560 | radeon_status(dev_priv); |
1561 | DRM_ERROR("failed!\n"); | |
1da177e4 | 1562 | #endif |
20caafa6 | 1563 | return -EBUSY; |
1da177e4 LT |
1564 | } |
1565 | ||
6c340eac EA |
1566 | static int radeon_cp_get_buffers(struct drm_device *dev, |
1567 | struct drm_file *file_priv, | |
c60ce623 | 1568 | struct drm_dma * d) |
1da177e4 LT |
1569 | { |
1570 | int i; | |
056219e2 | 1571 | struct drm_buf *buf; |
1da177e4 | 1572 | |
b5e89ed5 DA |
1573 | for (i = d->granted_count; i < d->request_count; i++) { |
1574 | buf = radeon_freelist_get(dev); | |
1575 | if (!buf) | |
20caafa6 | 1576 | return -EBUSY; /* NOTE: broken client */ |
1da177e4 | 1577 | |
6c340eac | 1578 | buf->file_priv = file_priv; |
1da177e4 | 1579 | |
b5e89ed5 DA |
1580 | if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, |
1581 | sizeof(buf->idx))) | |
20caafa6 | 1582 | return -EFAULT; |
b5e89ed5 DA |
1583 | if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, |
1584 | sizeof(buf->total))) | |
20caafa6 | 1585 | return -EFAULT; |
1da177e4 LT |
1586 | |
1587 | d->granted_count++; | |
1588 | } | |
1589 | return 0; | |
1590 | } | |
1591 | ||
c153f45f | 1592 | int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 1593 | { |
cdd55a29 | 1594 | struct drm_device_dma *dma = dev->dma; |
1da177e4 | 1595 | int ret = 0; |
c153f45f | 1596 | struct drm_dma *d = data; |
1da177e4 | 1597 | |
6c340eac | 1598 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 1599 | |
1da177e4 LT |
1600 | /* Please don't send us buffers. |
1601 | */ | |
c153f45f | 1602 | if (d->send_count != 0) { |
b5e89ed5 | 1603 | DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", |
c153f45f | 1604 | DRM_CURRENTPID, d->send_count); |
20caafa6 | 1605 | return -EINVAL; |
1da177e4 LT |
1606 | } |
1607 | ||
1608 | /* We'll send you buffers. | |
1609 | */ | |
c153f45f | 1610 | if (d->request_count < 0 || d->request_count > dma->buf_count) { |
b5e89ed5 | 1611 | DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", |
c153f45f | 1612 | DRM_CURRENTPID, d->request_count, dma->buf_count); |
20caafa6 | 1613 | return -EINVAL; |
1da177e4 LT |
1614 | } |
1615 | ||
c153f45f | 1616 | d->granted_count = 0; |
1da177e4 | 1617 | |
c153f45f EA |
1618 | if (d->request_count) { |
1619 | ret = radeon_cp_get_buffers(dev, file_priv, d); | |
1da177e4 LT |
1620 | } |
1621 | ||
1da177e4 LT |
1622 | return ret; |
1623 | } | |
1624 | ||
22eae947 | 1625 | int radeon_driver_load(struct drm_device *dev, unsigned long flags) |
1da177e4 LT |
1626 | { |
1627 | drm_radeon_private_t *dev_priv; | |
1628 | int ret = 0; | |
1629 | ||
1630 | dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); | |
1631 | if (dev_priv == NULL) | |
20caafa6 | 1632 | return -ENOMEM; |
1da177e4 LT |
1633 | |
1634 | memset(dev_priv, 0, sizeof(drm_radeon_private_t)); | |
1635 | dev->dev_private = (void *)dev_priv; | |
1636 | dev_priv->flags = flags; | |
1637 | ||
54a56ac5 | 1638 | switch (flags & RADEON_FAMILY_MASK) { |
1da177e4 LT |
1639 | case CHIP_R100: |
1640 | case CHIP_RV200: | |
1641 | case CHIP_R200: | |
1642 | case CHIP_R300: | |
b15ec368 | 1643 | case CHIP_R350: |
414ed537 | 1644 | case CHIP_R420: |
b15ec368 | 1645 | case CHIP_RV410: |
3d5e2c13 DA |
1646 | case CHIP_RV515: |
1647 | case CHIP_R520: | |
1648 | case CHIP_RV570: | |
1649 | case CHIP_R580: | |
54a56ac5 | 1650 | dev_priv->flags |= RADEON_HAS_HIERZ; |
1da177e4 LT |
1651 | break; |
1652 | default: | |
b5e89ed5 | 1653 | /* all other chips have no hierarchical z buffer */ |
1da177e4 LT |
1654 | break; |
1655 | } | |
414ed537 DA |
1656 | |
1657 | if (drm_device_is_agp(dev)) | |
54a56ac5 | 1658 | dev_priv->flags |= RADEON_IS_AGP; |
b15ec368 | 1659 | else if (drm_device_is_pcie(dev)) |
54a56ac5 | 1660 | dev_priv->flags |= RADEON_IS_PCIE; |
b15ec368 | 1661 | else |
54a56ac5 | 1662 | dev_priv->flags |= RADEON_IS_PCI; |
ea98a92f | 1663 | |
414ed537 | 1664 | DRM_DEBUG("%s card detected\n", |
54a56ac5 | 1665 | ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); |
1da177e4 LT |
1666 | return ret; |
1667 | } | |
1668 | ||
22eae947 DA |
1669 | /* Create mappings for registers and framebuffer so userland doesn't necessarily |
1670 | * have to find them. | |
1671 | */ | |
1672 | int radeon_driver_firstopen(struct drm_device *dev) | |
836cf046 DA |
1673 | { |
1674 | int ret; | |
1675 | drm_local_map_t *map; | |
1676 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1677 | ||
f2b04cd2 DA |
1678 | dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; |
1679 | ||
836cf046 DA |
1680 | ret = drm_addmap(dev, drm_get_resource_start(dev, 2), |
1681 | drm_get_resource_len(dev, 2), _DRM_REGISTERS, | |
1682 | _DRM_READ_ONLY, &dev_priv->mmio); | |
1683 | if (ret != 0) | |
1684 | return ret; | |
1685 | ||
7fc86860 DA |
1686 | dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); |
1687 | ret = drm_addmap(dev, dev_priv->fb_aper_offset, | |
836cf046 DA |
1688 | drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, |
1689 | _DRM_WRITE_COMBINING, &map); | |
1690 | if (ret != 0) | |
1691 | return ret; | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
22eae947 | 1696 | int radeon_driver_unload(struct drm_device *dev) |
1da177e4 LT |
1697 | { |
1698 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1699 | ||
1700 | DRM_DEBUG("\n"); | |
1da177e4 LT |
1701 | drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); |
1702 | ||
1703 | dev->dev_private = NULL; | |
1704 | return 0; | |
1705 | } |