projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: fixup RV550 chip family
[linux-2.6-block.git] / drivers / char / drm / radeon_cp.c
CommitLineData
f26c473c
DA		 1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*
1da177e4
LT		 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#include "drmP.h"
32#include "drm.h"
33#include "radeon_drm.h"
34#include "radeon_drv.h"
414ed537 35#include "r300_reg.h"
1da177e4
LT		 36
37#define RADEON_FIFO_DEBUG 0
38
84b1fd10 39static int radeon_do_cleanup_cp(struct drm_device * dev);
1da177e4
LT		 40
41/* CP microcode (from ATI) */
c499aeb0 42static const u32 R200_cp_microcode[][2] = {
b5e89ed5
DA		 43 {0x21007000, 0000000000},
44 {0x20007000, 0000000000},
45 {0x000000ab, 0x00000004},
46 {0x000000af, 0x00000004},
47 {0x66544a49, 0000000000},
48 {0x49494174, 0000000000},
49 {0x54517d83, 0000000000},
50 {0x498d8b64, 0000000000},
51 {0x49494949, 0000000000},
52 {0x49da493c, 0000000000},
53 {0x49989898, 0000000000},
54 {0xd34949d5, 0000000000},
55 {0x9dc90e11, 0000000000},
56 {0xce9b9b9b, 0000000000},
57 {0x000f0000, 0x00000016},
58 {0x352e232c, 0000000000},
59 {0x00000013, 0x00000004},
60 {0x000f0000, 0x00000016},
61 {0x352e272c, 0000000000},
62 {0x000f0001, 0x00000016},
63 {0x3239362f, 0000000000},
64 {0x000077ef, 0x00000002},
65 {0x00061000, 0x00000002},
66 {0x00000020, 0x0000001a},
67 {0x00004000, 0x0000001e},
68 {0x00061000, 0x00000002},
69 {0x00000020, 0x0000001a},
70 {0x00004000, 0x0000001e},
71 {0x00061000, 0x00000002},
72 {0x00000020, 0x0000001a},
73 {0x00004000, 0x0000001e},
74 {0x00000016, 0x00000004},
75 {0x0003802a, 0x00000002},
76 {0x040067e0, 0x00000002},
77 {0x00000016, 0x00000004},
78 {0x000077e0, 0x00000002},
79 {0x00065000, 0x00000002},
80 {0x000037e1, 0x00000002},
81 {0x040067e1, 0x00000006},
82 {0x000077e0, 0x00000002},
83 {0x000077e1, 0x00000002},
84 {0x000077e1, 0x00000006},
85 {0xffffffff, 0000000000},
86 {0x10000000, 0000000000},
87 {0x0003802a, 0x00000002},
88 {0x040067e0, 0x00000006},
89 {0x00007675, 0x00000002},
90 {0x00007676, 0x00000002},
91 {0x00007677, 0x00000002},
92 {0x00007678, 0x00000006},
93 {0x0003802b, 0x00000002},
94 {0x04002676, 0x00000002},
95 {0x00007677, 0x00000002},
96 {0x00007678, 0x00000006},
97 {0x0000002e, 0x00000018},
98 {0x0000002e, 0x00000018},
99 {0000000000, 0x00000006},
100 {0x0000002f, 0x00000018},
101 {0x0000002f, 0x00000018},
102 {0000000000, 0x00000006},
103 {0x01605000, 0x00000002},
104 {0x00065000, 0x00000002},
105 {0x00098000, 0x00000002},
106 {0x00061000, 0x00000002},
107 {0x64c0603d, 0x00000004},
108 {0x00080000, 0x00000016},
109 {0000000000, 0000000000},
110 {0x0400251d, 0x00000002},
111 {0x00007580, 0x00000002},
112 {0x00067581, 0x00000002},
113 {0x04002580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x00000046, 0x00000004},
116 {0x00005000, 0000000000},
117 {0x00061000, 0x00000002},
118 {0x0000750e, 0x00000002},
119 {0x00019000, 0x00000002},
120 {0x00011055, 0x00000014},
121 {0x00000055, 0x00000012},
122 {0x0400250f, 0x00000002},
123 {0x0000504a, 0x00000004},
124 {0x00007565, 0x00000002},
125 {0x00007566, 0x00000002},
126 {0x00000051, 0x00000004},
127 {0x01e655b4, 0x00000002},
128 {0x4401b0dc, 0x00000002},
129 {0x01c110dc, 0x00000002},
130 {0x2666705d, 0x00000018},
131 {0x040c2565, 0x00000002},
132 {0x0000005d, 0x00000018},
133 {0x04002564, 0x00000002},
134 {0x00007566, 0x00000002},
135 {0x00000054, 0x00000004},
136 {0x00401060, 0x00000008},
137 {0x00101000, 0x00000002},
138 {0x000d80ff, 0x00000002},
139 {0x00800063, 0x00000008},
140 {0x000f9000, 0x00000002},
141 {0x000e00ff, 0x00000002},
142 {0000000000, 0x00000006},
143 {0x00000080, 0x00000018},
144 {0x00000054, 0x00000004},
145 {0x00007576, 0x00000002},
146 {0x00065000, 0x00000002},
147 {0x00009000, 0x00000002},
148 {0x00041000, 0x00000002},
149 {0x0c00350e, 0x00000002},
150 {0x00049000, 0x00000002},
151 {0x00051000, 0x00000002},
152 {0x01e785f8, 0x00000002},
153 {0x00200000, 0x00000002},
154 {0x00600073, 0x0000000c},
155 {0x00007563, 0x00000002},
156 {0x006075f0, 0x00000021},
157 {0x20007068, 0x00000004},
158 {0x00005068, 0x00000004},
159 {0x00007576, 0x00000002},
160 {0x00007577, 0x00000002},
161 {0x0000750e, 0x00000002},
162 {0x0000750f, 0x00000002},
163 {0x00a05000, 0x00000002},
164 {0x00600076, 0x0000000c},
165 {0x006075f0, 0x00000021},
166 {0x000075f8, 0x00000002},
167 {0x00000076, 0x00000004},
168 {0x000a750e, 0x00000002},
169 {0x0020750f, 0x00000002},
170 {0x00600079, 0x00000004},
171 {0x00007570, 0x00000002},
172 {0x00007571, 0x00000002},
173 {0x00007572, 0x00000006},
174 {0x00005000, 0x00000002},
175 {0x00a05000, 0x00000002},
176 {0x00007568, 0x00000002},
177 {0x00061000, 0x00000002},
178 {0x00000084, 0x0000000c},
179 {0x00058000, 0x00000002},
180 {0x0c607562, 0x00000002},
181 {0x00000086, 0x00000004},
182 {0x00600085, 0x00000004},
183 {0x400070dd, 0000000000},
184 {0x000380dd, 0x00000002},
185 {0x00000093, 0x0000001c},
186 {0x00065095, 0x00000018},
187 {0x040025bb, 0x00000002},
188 {0x00061096, 0x00000018},
189 {0x040075bc, 0000000000},
190 {0x000075bb, 0x00000002},
191 {0x000075bc, 0000000000},
192 {0x00090000, 0x00000006},
193 {0x00090000, 0x00000002},
194 {0x000d8002, 0x00000006},
195 {0x00005000, 0x00000002},
196 {0x00007821, 0x00000002},
197 {0x00007800, 0000000000},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x01665000, 0x00000002},
201 {0x000a0000, 0x00000002},
202 {0x000671cc, 0x00000002},
203 {0x0286f1cd, 0x00000002},
204 {0x000000a3, 0x00000010},
205 {0x21007000, 0000000000},
206 {0x000000aa, 0x0000001c},
207 {0x00065000, 0x00000002},
208 {0x000a0000, 0x00000002},
209 {0x00061000, 0x00000002},
210 {0x000b0000, 0x00000002},
211 {0x38067000, 0x00000002},
212 {0x000a00a6, 0x00000004},
213 {0x20007000, 0000000000},
214 {0x01200000, 0x00000002},
215 {0x20077000, 0x00000002},
216 {0x01200000, 0x00000002},
217 {0x20007000, 0000000000},
218 {0x00061000, 0x00000002},
219 {0x0120751b, 0x00000002},
220 {0x8040750a, 0x00000002},
221 {0x8040750b, 0x00000002},
222 {0x00110000, 0x00000002},
223 {0x000380dd, 0x00000002},
224 {0x000000bd, 0x0000001c},
225 {0x00061096, 0x00000018},
226 {0x844075bd, 0x00000002},
227 {0x00061095, 0x00000018},
228 {0x840075bb, 0x00000002},
229 {0x00061096, 0x00000018},
230 {0x844075bc, 0x00000002},
231 {0x000000c0, 0x00000004},
232 {0x804075bd, 0x00000002},
233 {0x800075bb, 0x00000002},
234 {0x804075bc, 0x00000002},
235 {0x00108000, 0x00000002},
236 {0x01400000, 0x00000002},
237 {0x006000c4, 0x0000000c},
238 {0x20c07000, 0x00000020},
239 {0x000000c6, 0x00000012},
240 {0x00800000, 0x00000006},
241 {0x0080751d, 0x00000006},
242 {0x000025bb, 0x00000002},
243 {0x000040c0, 0x00000004},
244 {0x0000775c, 0x00000002},
245 {0x00a05000, 0x00000002},
246 {0x00661000, 0x00000002},
247 {0x0460275d, 0x00000020},
248 {0x00004000, 0000000000},
249 {0x00007999, 0x00000002},
250 {0x00a05000, 0x00000002},
251 {0x00661000, 0x00000002},
252 {0x0460299b, 0x00000020},
253 {0x00004000, 0000000000},
254 {0x01e00830, 0x00000002},
255 {0x21007000, 0000000000},
256 {0x00005000, 0x00000002},
257 {0x00038042, 0x00000002},
258 {0x040025e0, 0x00000002},
259 {0x000075e1, 0000000000},
260 {0x00000001, 0000000000},
261 {0x000380d9, 0x00000002},
262 {0x04007394, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
1da177e4
LT		 299};
300
c499aeb0 301static const u32 radeon_cp_microcode[][2] = {
b5e89ed5
DA		 302 {0x21007000, 0000000000},
303 {0x20007000, 0000000000},
304 {0x000000b4, 0x00000004},
305 {0x000000b8, 0x00000004},
306 {0x6f5b4d4c, 0000000000},
307 {0x4c4c427f, 0000000000},
308 {0x5b568a92, 0000000000},
309 {0x4ca09c6d, 0000000000},
310 {0xad4c4c4c, 0000000000},
311 {0x4ce1af3d, 0000000000},
312 {0xd8afafaf, 0000000000},
313 {0xd64c4cdc, 0000000000},
314 {0x4cd10d10, 0000000000},
315 {0x000f0000, 0x00000016},
316 {0x362f242d, 0000000000},
317 {0x00000012, 0x00000004},
318 {0x000f0000, 0x00000016},
319 {0x362f282d, 0000000000},
320 {0x000380e7, 0x00000002},
321 {0x04002c97, 0x00000002},
322 {0x000f0001, 0x00000016},
323 {0x333a3730, 0000000000},
324 {0x000077ef, 0x00000002},
325 {0x00061000, 0x00000002},
326 {0x00000021, 0x0000001a},
327 {0x00004000, 0x0000001e},
328 {0x00061000, 0x00000002},
329 {0x00000021, 0x0000001a},
330 {0x00004000, 0x0000001e},
331 {0x00061000, 0x00000002},
332 {0x00000021, 0x0000001a},
333 {0x00004000, 0x0000001e},
334 {0x00000017, 0x00000004},
335 {0x0003802b, 0x00000002},
336 {0x040067e0, 0x00000002},
337 {0x00000017, 0x00000004},
338 {0x000077e0, 0x00000002},
339 {0x00065000, 0x00000002},
340 {0x000037e1, 0x00000002},
341 {0x040067e1, 0x00000006},
342 {0x000077e0, 0x00000002},
343 {0x000077e1, 0x00000002},
344 {0x000077e1, 0x00000006},
345 {0xffffffff, 0000000000},
346 {0x10000000, 0000000000},
347 {0x0003802b, 0x00000002},
348 {0x040067e0, 0x00000006},
349 {0x00007675, 0x00000002},
350 {0x00007676, 0x00000002},
351 {0x00007677, 0x00000002},
352 {0x00007678, 0x00000006},
353 {0x0003802c, 0x00000002},
354 {0x04002676, 0x00000002},
355 {0x00007677, 0x00000002},
356 {0x00007678, 0x00000006},
357 {0x0000002f, 0x00000018},
358 {0x0000002f, 0x00000018},
359 {0000000000, 0x00000006},
360 {0x00000030, 0x00000018},
361 {0x00000030, 0x00000018},
362 {0000000000, 0x00000006},
363 {0x01605000, 0x00000002},
364 {0x00065000, 0x00000002},
365 {0x00098000, 0x00000002},
366 {0x00061000, 0x00000002},
367 {0x64c0603e, 0x00000004},
368 {0x000380e6, 0x00000002},
369 {0x040025c5, 0x00000002},
370 {0x00080000, 0x00000016},
371 {0000000000, 0000000000},
372 {0x0400251d, 0x00000002},
373 {0x00007580, 0x00000002},
374 {0x00067581, 0x00000002},
375 {0x04002580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x00000049, 0x00000004},
378 {0x00005000, 0000000000},
379 {0x000380e6, 0x00000002},
380 {0x040025c5, 0x00000002},
381 {0x00061000, 0x00000002},
382 {0x0000750e, 0x00000002},
383 {0x00019000, 0x00000002},
384 {0x00011055, 0x00000014},
385 {0x00000055, 0x00000012},
386 {0x0400250f, 0x00000002},
387 {0x0000504f, 0x00000004},
388 {0x000380e6, 0x00000002},
389 {0x040025c5, 0x00000002},
390 {0x00007565, 0x00000002},
391 {0x00007566, 0x00000002},
392 {0x00000058, 0x00000004},
393 {0x000380e6, 0x00000002},
394 {0x040025c5, 0x00000002},
395 {0x01e655b4, 0x00000002},
396 {0x4401b0e4, 0x00000002},
397 {0x01c110e4, 0x00000002},
398 {0x26667066, 0x00000018},
399 {0x040c2565, 0x00000002},
400 {0x00000066, 0x00000018},
401 {0x04002564, 0x00000002},
402 {0x00007566, 0x00000002},
403 {0x0000005d, 0x00000004},
404 {0x00401069, 0x00000008},
405 {0x00101000, 0x00000002},
406 {0x000d80ff, 0x00000002},
407 {0x0080006c, 0x00000008},
408 {0x000f9000, 0x00000002},
409 {0x000e00ff, 0x00000002},
410 {0000000000, 0x00000006},
411 {0x0000008f, 0x00000018},
412 {0x0000005b, 0x00000004},
413 {0x000380e6, 0x00000002},
414 {0x040025c5, 0x00000002},
415 {0x00007576, 0x00000002},
416 {0x00065000, 0x00000002},
417 {0x00009000, 0x00000002},
418 {0x00041000, 0x00000002},
419 {0x0c00350e, 0x00000002},
420 {0x00049000, 0x00000002},
421 {0x00051000, 0x00000002},
422 {0x01e785f8, 0x00000002},
423 {0x00200000, 0x00000002},
424 {0x0060007e, 0x0000000c},
425 {0x00007563, 0x00000002},
426 {0x006075f0, 0x00000021},
427 {0x20007073, 0x00000004},
428 {0x00005073, 0x00000004},
429 {0x000380e6, 0x00000002},
430 {0x040025c5, 0x00000002},
431 {0x00007576, 0x00000002},
432 {0x00007577, 0x00000002},
433 {0x0000750e, 0x00000002},
434 {0x0000750f, 0x00000002},
435 {0x00a05000, 0x00000002},
436 {0x00600083, 0x0000000c},
437 {0x006075f0, 0x00000021},
438 {0x000075f8, 0x00000002},
439 {0x00000083, 0x00000004},
440 {0x000a750e, 0x00000002},
441 {0x000380e6, 0x00000002},
442 {0x040025c5, 0x00000002},
443 {0x0020750f, 0x00000002},
444 {0x00600086, 0x00000004},
445 {0x00007570, 0x00000002},
446 {0x00007571, 0x00000002},
447 {0x00007572, 0x00000006},
448 {0x000380e6, 0x00000002},
449 {0x040025c5, 0x00000002},
450 {0x00005000, 0x00000002},
451 {0x00a05000, 0x00000002},
452 {0x00007568, 0x00000002},
453 {0x00061000, 0x00000002},
454 {0x00000095, 0x0000000c},
455 {0x00058000, 0x00000002},
456 {0x0c607562, 0x00000002},
457 {0x00000097, 0x00000004},
458 {0x000380e6, 0x00000002},
459 {0x040025c5, 0x00000002},
460 {0x00600096, 0x00000004},
461 {0x400070e5, 0000000000},
462 {0x000380e6, 0x00000002},
463 {0x040025c5, 0x00000002},
464 {0x000380e5, 0x00000002},
465 {0x000000a8, 0x0000001c},
466 {0x000650aa, 0x00000018},
467 {0x040025bb, 0x00000002},
468 {0x000610ab, 0x00000018},
469 {0x040075bc, 0000000000},
470 {0x000075bb, 0x00000002},
471 {0x000075bc, 0000000000},
472 {0x00090000, 0x00000006},
473 {0x00090000, 0x00000002},
474 {0x000d8002, 0x00000006},
475 {0x00007832, 0x00000002},
476 {0x00005000, 0x00000002},
477 {0x000380e7, 0x00000002},
478 {0x04002c97, 0x00000002},
479 {0x00007820, 0x00000002},
480 {0x00007821, 0x00000002},
481 {0x00007800, 0000000000},
482 {0x01200000, 0x00000002},
483 {0x20077000, 0x00000002},
484 {0x01200000, 0x00000002},
485 {0x20007000, 0x00000002},
486 {0x00061000, 0x00000002},
487 {0x0120751b, 0x00000002},
488 {0x8040750a, 0x00000002},
489 {0x8040750b, 0x00000002},
490 {0x00110000, 0x00000002},
491 {0x000380e5, 0x00000002},
492 {0x000000c6, 0x0000001c},
493 {0x000610ab, 0x00000018},
494 {0x844075bd, 0x00000002},
495 {0x000610aa, 0x00000018},
496 {0x840075bb, 0x00000002},
497 {0x000610ab, 0x00000018},
498 {0x844075bc, 0x00000002},
499 {0x000000c9, 0x00000004},
500 {0x804075bd, 0x00000002},
501 {0x800075bb, 0x00000002},
502 {0x804075bc, 0x00000002},
503 {0x00108000, 0x00000002},
504 {0x01400000, 0x00000002},
505 {0x006000cd, 0x0000000c},
506 {0x20c07000, 0x00000020},
507 {0x000000cf, 0x00000012},
508 {0x00800000, 0x00000006},
509 {0x0080751d, 0x00000006},
510 {0000000000, 0000000000},
511 {0x0000775c, 0x00000002},
512 {0x00a05000, 0x00000002},
513 {0x00661000, 0x00000002},
514 {0x0460275d, 0x00000020},
515 {0x00004000, 0000000000},
516 {0x01e00830, 0x00000002},
517 {0x21007000, 0000000000},
518 {0x6464614d, 0000000000},
519 {0x69687420, 0000000000},
520 {0x00000073, 0000000000},
521 {0000000000, 0000000000},
522 {0x00005000, 0x00000002},
523 {0x000380d0, 0x00000002},
524 {0x040025e0, 0x00000002},
525 {0x000075e1, 0000000000},
526 {0x00000001, 0000000000},
527 {0x000380e0, 0x00000002},
528 {0x04002394, 0x00000002},
529 {0x00005000, 0000000000},
530 {0000000000, 0000000000},
531 {0000000000, 0000000000},
532 {0x00000008, 0000000000},
533 {0x00000004, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
1da177e4
LT		 558};
559
c499aeb0 560static const u32 R300_cp_microcode[][2] = {
b5e89ed5
DA		 561 {0x4200e000, 0000000000},
562 {0x4000e000, 0000000000},
563 {0x000000af, 0x00000008},
564 {0x000000b3, 0x00000008},
565 {0x6c5a504f, 0000000000},
566 {0x4f4f497a, 0000000000},
567 {0x5a578288, 0000000000},
568 {0x4f91906a, 0000000000},
569 {0x4f4f4f4f, 0000000000},
570 {0x4fe24f44, 0000000000},
571 {0x4f9c9c9c, 0000000000},
572 {0xdc4f4fde, 0000000000},
573 {0xa1cd4f4f, 0000000000},
574 {0xd29d9d9d, 0000000000},
575 {0x4f0f9fd7, 0000000000},
576 {0x000ca000, 0x00000004},
577 {0x000d0012, 0x00000038},
578 {0x0000e8b4, 0x00000004},
579 {0x000d0014, 0x00000038},
580 {0x0000e8b6, 0x00000004},
581 {0x000d0016, 0x00000038},
582 {0x0000e854, 0x00000004},
583 {0x000d0018, 0x00000038},
584 {0x0000e855, 0x00000004},
585 {0x000d001a, 0x00000038},
586 {0x0000e856, 0x00000004},
587 {0x000d001c, 0x00000038},
588 {0x0000e857, 0x00000004},
589 {0x000d001e, 0x00000038},
590 {0x0000e824, 0x00000004},
591 {0x000d0020, 0x00000038},
592 {0x0000e825, 0x00000004},
593 {0x000d0022, 0x00000038},
594 {0x0000e830, 0x00000004},
595 {0x000d0024, 0x00000038},
596 {0x0000f0c0, 0x00000004},
597 {0x000d0026, 0x00000038},
598 {0x0000f0c1, 0x00000004},
599 {0x000d0028, 0x00000038},
600 {0x0000f041, 0x00000004},
601 {0x000d002a, 0x00000038},
602 {0x0000f184, 0x00000004},
603 {0x000d002c, 0x00000038},
604 {0x0000f185, 0x00000004},
605 {0x000d002e, 0x00000038},
606 {0x0000f186, 0x00000004},
607 {0x000d0030, 0x00000038},
608 {0x0000f187, 0x00000004},
609 {0x000d0032, 0x00000038},
610 {0x0000f180, 0x00000004},
611 {0x000d0034, 0x00000038},
612 {0x0000f393, 0x00000004},
613 {0x000d0036, 0x00000038},
614 {0x0000f38a, 0x00000004},
615 {0x000d0038, 0x00000038},
616 {0x0000f38e, 0x00000004},
617 {0x0000e821, 0x00000004},
618 {0x0140a000, 0x00000004},
619 {0x00000043, 0x00000018},
620 {0x00cce800, 0x00000004},
621 {0x001b0001, 0x00000004},
622 {0x08004800, 0x00000004},
623 {0x001b0001, 0x00000004},
624 {0x08004800, 0x00000004},
625 {0x001b0001, 0x00000004},
626 {0x08004800, 0x00000004},
627 {0x0000003a, 0x00000008},
628 {0x0000a000, 0000000000},
629 {0x02c0a000, 0x00000004},
630 {0x000ca000, 0x00000004},
631 {0x00130000, 0x00000004},
632 {0x000c2000, 0x00000004},
633 {0xc980c045, 0x00000008},
634 {0x2000451d, 0x00000004},
635 {0x0000e580, 0x00000004},
636 {0x000ce581, 0x00000004},
637 {0x08004580, 0x00000004},
638 {0x000ce581, 0x00000004},
639 {0x0000004c, 0x00000008},
640 {0x0000a000, 0000000000},
641 {0x000c2000, 0x00000004},
642 {0x0000e50e, 0x00000004},
643 {0x00032000, 0x00000004},
644 {0x00022056, 0x00000028},
645 {0x00000056, 0x00000024},
646 {0x0800450f, 0x00000004},
647 {0x0000a050, 0x00000008},
648 {0x0000e565, 0x00000004},
649 {0x0000e566, 0x00000004},
650 {0x00000057, 0x00000008},
651 {0x03cca5b4, 0x00000004},
652 {0x05432000, 0x00000004},
653 {0x00022000, 0x00000004},
654 {0x4ccce063, 0x00000030},
655 {0x08274565, 0x00000004},
656 {0x00000063, 0x00000030},
657 {0x08004564, 0x00000004},
658 {0x0000e566, 0x00000004},
659 {0x0000005a, 0x00000008},
660 {0x00802066, 0x00000010},
661 {0x00202000, 0x00000004},
662 {0x001b00ff, 0x00000004},
663 {0x01000069, 0x00000010},
664 {0x001f2000, 0x00000004},
665 {0x001c00ff, 0x00000004},
666 {0000000000, 0x0000000c},
667 {0x00000085, 0x00000030},
668 {0x0000005a, 0x00000008},
669 {0x0000e576, 0x00000004},
670 {0x000ca000, 0x00000004},
671 {0x00012000, 0x00000004},
672 {0x00082000, 0x00000004},
673 {0x1800650e, 0x00000004},
674 {0x00092000, 0x00000004},
675 {0x000a2000, 0x00000004},
676 {0x000f0000, 0x00000004},
677 {0x00400000, 0x00000004},
678 {0x00000079, 0x00000018},
679 {0x0000e563, 0x00000004},
680 {0x00c0e5f9, 0x000000c2},
681 {0x0000006e, 0x00000008},
682 {0x0000a06e, 0x00000008},
683 {0x0000e576, 0x00000004},
684 {0x0000e577, 0x00000004},
685 {0x0000e50e, 0x00000004},
686 {0x0000e50f, 0x00000004},
687 {0x0140a000, 0x00000004},
688 {0x0000007c, 0x00000018},
689 {0x00c0e5f9, 0x000000c2},
690 {0x0000007c, 0x00000008},
691 {0x0014e50e, 0x00000004},
692 {0x0040e50f, 0x00000004},
693 {0x00c0007f, 0x00000008},
694 {0x0000e570, 0x00000004},
695 {0x0000e571, 0x00000004},
696 {0x0000e572, 0x0000000c},
697 {0x0000a000, 0x00000004},
698 {0x0140a000, 0x00000004},
699 {0x0000e568, 0x00000004},
700 {0x000c2000, 0x00000004},
701 {0x00000089, 0x00000018},
702 {0x000b0000, 0x00000004},
703 {0x18c0e562, 0x00000004},
704 {0x0000008b, 0x00000008},
705 {0x00c0008a, 0x00000008},
706 {0x000700e4, 0x00000004},
707 {0x00000097, 0x00000038},
708 {0x000ca099, 0x00000030},
709 {0x080045bb, 0x00000004},
710 {0x000c209a, 0x00000030},
711 {0x0800e5bc, 0000000000},
712 {0x0000e5bb, 0x00000004},
713 {0x0000e5bc, 0000000000},
714 {0x00120000, 0x0000000c},
715 {0x00120000, 0x00000004},
716 {0x001b0002, 0x0000000c},
717 {0x0000a000, 0x00000004},
718 {0x0000e821, 0x00000004},
719 {0x0000e800, 0000000000},
720 {0x0000e821, 0x00000004},
721 {0x0000e82e, 0000000000},
722 {0x02cca000, 0x00000004},
723 {0x00140000, 0x00000004},
724 {0x000ce1cc, 0x00000004},
725 {0x050de1cd, 0x00000004},
726 {0x000000a7, 0x00000020},
727 {0x4200e000, 0000000000},
728 {0x000000ae, 0x00000038},
729 {0x000ca000, 0x00000004},
730 {0x00140000, 0x00000004},
731 {0x000c2000, 0x00000004},
732 {0x00160000, 0x00000004},
733 {0x700ce000, 0x00000004},
734 {0x001400aa, 0x00000008},
735 {0x4000e000, 0000000000},
736 {0x02400000, 0x00000004},
737 {0x400ee000, 0x00000004},
738 {0x02400000, 0x00000004},
739 {0x4000e000, 0000000000},
740 {0x000c2000, 0x00000004},
741 {0x0240e51b, 0x00000004},
742 {0x0080e50a, 0x00000005},
743 {0x0080e50b, 0x00000005},
744 {0x00220000, 0x00000004},
745 {0x000700e4, 0x00000004},
746 {0x000000c1, 0x00000038},
747 {0x000c209a, 0x00000030},
748 {0x0880e5bd, 0x00000005},
749 {0x000c2099, 0x00000030},
750 {0x0800e5bb, 0x00000005},
751 {0x000c209a, 0x00000030},
752 {0x0880e5bc, 0x00000005},
753 {0x000000c4, 0x00000008},
754 {0x0080e5bd, 0x00000005},
755 {0x0000e5bb, 0x00000005},
756 {0x0080e5bc, 0x00000005},
757 {0x00210000, 0x00000004},
758 {0x02800000, 0x00000004},
759 {0x00c000c8, 0x00000018},
760 {0x4180e000, 0x00000040},
761 {0x000000ca, 0x00000024},
762 {0x01000000, 0x0000000c},
763 {0x0100e51d, 0x0000000c},
764 {0x000045bb, 0x00000004},
765 {0x000080c4, 0x00000008},
766 {0x0000f3ce, 0x00000004},
767 {0x0140a000, 0x00000004},
768 {0x00cc2000, 0x00000004},
769 {0x08c053cf, 0x00000040},
770 {0x00008000, 0000000000},
771 {0x0000f3d2, 0x00000004},
772 {0x0140a000, 0x00000004},
773 {0x00cc2000, 0x00000004},
774 {0x08c053d3, 0x00000040},
775 {0x00008000, 0000000000},
776 {0x0000f39d, 0x00000004},
777 {0x0140a000, 0x00000004},
778 {0x00cc2000, 0x00000004},
779 {0x08c0539e, 0x00000040},
780 {0x00008000, 0000000000},
781 {0x03c00830, 0x00000004},
782 {0x4200e000, 0000000000},
783 {0x0000a000, 0x00000004},
784 {0x200045e0, 0x00000004},
785 {0x0000e5e1, 0000000000},
786 {0x00000001, 0000000000},
787 {0x000700e1, 0x00000004},
788 {0x0800e394, 0000000000},
789 {0000000000, 0000000000},
790 {0000000000, 0000000000},
791 {0000000000, 0000000000},
792 {0000000000, 0000000000},
793 {0000000000, 0000000000},
794 {0000000000, 0000000000},
795 {0000000000, 0000000000},
796 {0000000000, 0000000000},
797 {0000000000, 0000000000},
798 {0000000000, 0000000000},
799 {0000000000, 0000000000},
800 {0000000000, 0000000000},
801 {0000000000, 0000000000},
802 {0000000000, 0000000000},
803 {0000000000, 0000000000},
804 {0000000000, 0000000000},
805 {0000000000, 0000000000},
806 {0000000000, 0000000000},
807 {0000000000, 0000000000},
808 {0000000000, 0000000000},
809 {0000000000, 0000000000},
810 {0000000000, 0000000000},
811 {0000000000, 0000000000},
812 {0000000000, 0000000000},
813 {0000000000, 0000000000},
814 {0000000000, 0000000000},
815 {0000000000, 0000000000},
816 {0000000000, 0000000000},
1da177e4
LT		 817};
818
3d5e2c13
DA		 819static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
820{
821 u32 ret;
822 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
823 ret = RADEON_READ(R520_MC_IND_DATA);
824 RADEON_WRITE(R520_MC_IND_INDEX, 0);
825 return ret;
826}
827
60f92683
MC		 828static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
829{
830 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
831 return RADEON_READ(RS690_MC_DATA);
832}
833
3d5e2c13
DA		 834u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
835{
836
837 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
838 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
60f92683
MC		 839 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
840 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
3d5e2c13
DA		 841 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
842 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
843 else
844 return RADEON_READ(RADEON_MC_FB_LOCATION);
845}
846
847static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
848{
849 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
850 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
60f92683
MC		 851 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
852 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
3d5e2c13
DA		 853 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
854 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
855 else
856 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
857}
858
859static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
860{
861 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
862 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
60f92683
MC		 863 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
864 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
3d5e2c13
DA		 865 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
866 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
867 else
868 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
869}
870
84b1fd10 871static int RADEON_READ_PLL(struct drm_device * dev, int addr)
1da177e4
LT		 872{
873 drm_radeon_private_t *dev_priv = dev->dev_private;
874
875 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
876 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
877}
878
3d5e2c13 879static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
ea98a92f
DA		 880{
881 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
882 return RADEON_READ(RADEON_PCIE_DATA);
883}
884
f2b04cd2
DA		 885static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
886{
887 u32 ret;
888 RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
889 ret = RADEON_READ(RADEON_IGPGART_DATA);
890 RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
891 return ret;
892}
893
1da177e4 894#if RADEON_FIFO_DEBUG
b5e89ed5 895static void radeon_status(drm_radeon_private_t * dev_priv)
1da177e4 896{
b5e89ed5
DA		 897 printk("%s:\n", __FUNCTION__);
898 printk("RBBM_STATUS = 0x%08x\n",
899 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
900 printk("CP_RB_RTPR = 0x%08x\n",
901 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
902 printk("CP_RB_WTPR = 0x%08x\n",
903 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
904 printk("AIC_CNTL = 0x%08x\n",
905 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
906 printk("AIC_STAT = 0x%08x\n",
907 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
908 printk("AIC_PT_BASE = 0x%08x\n",
909 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
910 printk("TLB_ADDR = 0x%08x\n",
911 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
912 printk("TLB_DATA = 0x%08x\n",
913 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
1da177e4
LT		 914}
915#endif
916
1da177e4
LT		 917/* ================================================================
918 * Engine, FIFO control
919 */
920
b5e89ed5 921static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
1da177e4
LT		 922{
923 u32 tmp;
924 int i;
925
926 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
927
b9b603dd
MD		 928 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
929 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
930 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
1da177e4 931
b5e89ed5 932 for (i = 0; i < dev_priv->usec_timeout; i++) {
b9b603dd
MD		 933 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
934 & RADEON_RB3D_DC_BUSY)) {
1da177e4
LT		 935 return 0;
936 }
b5e89ed5 937 DRM_UDELAY(1);
1da177e4
LT		 938 }
939
940#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 941 DRM_ERROR("failed!\n");
942 radeon_status(dev_priv);
1da177e4 943#endif
20caafa6 944 return -EBUSY;
1da177e4
LT		 945}
946
b5e89ed5 947static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
1da177e4
LT		 948{
949 int i;
950
951 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
952
b5e89ed5
DA		 953 for (i = 0; i < dev_priv->usec_timeout; i++) {
954 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
955 & RADEON_RBBM_FIFOCNT_MASK);
956 if (slots >= entries)
957 return 0;
958 DRM_UDELAY(1);
1da177e4
LT		 959 }
960
961#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 962 DRM_ERROR("failed!\n");
963 radeon_status(dev_priv);
1da177e4 964#endif
20caafa6 965 return -EBUSY;
1da177e4
LT		 966}
967
b5e89ed5 968static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 969{
970 int i, ret;
971
972 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
973
b5e89ed5
DA		 974 ret = radeon_do_wait_for_fifo(dev_priv, 64);
975 if (ret)
976 return ret;
1da177e4 977
b5e89ed5
DA		 978 for (i = 0; i < dev_priv->usec_timeout; i++) {
979 if (!(RADEON_READ(RADEON_RBBM_STATUS)
980 & RADEON_RBBM_ACTIVE)) {
981 radeon_do_pixcache_flush(dev_priv);
1da177e4
LT		 982 return 0;
983 }
b5e89ed5 984 DRM_UDELAY(1);
1da177e4
LT		 985 }
986
987#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 988 DRM_ERROR("failed!\n");
989 radeon_status(dev_priv);
1da177e4 990#endif
20caafa6 991 return -EBUSY;
1da177e4
LT		 992}
993
1da177e4
LT		 994/* ================================================================
995 * CP control, initialization
996 */
997
998/* Load the microcode for the CP */
b5e89ed5 999static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1000{
1001 int i;
b5e89ed5 1002 DRM_DEBUG("\n");
1da177e4 1003
b5e89ed5 1004 radeon_do_wait_for_idle(dev_priv);
1da177e4 1005
b5e89ed5 1006 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
1da177e4 1007
b5e89ed5 1008 if (dev_priv->microcode_version == UCODE_R200) {
1da177e4 1009 DRM_INFO("Loading R200 Microcode\n");
b5e89ed5
DA		 1010 for (i = 0; i < 256; i++) {
1011 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1012 R200_cp_microcode[i][1]);
1013 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1014 R200_cp_microcode[i][0]);
1da177e4 1015 }
b5e89ed5 1016 } else if (dev_priv->microcode_version == UCODE_R300) {
1da177e4 1017 DRM_INFO("Loading R300 Microcode\n");
b5e89ed5
DA		 1018 for (i = 0; i < 256; i++) {
1019 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1020 R300_cp_microcode[i][1]);
1021 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1022 R300_cp_microcode[i][0]);
1da177e4
LT		 1023 }
1024 } else {
b5e89ed5
DA		 1025 for (i = 0; i < 256; i++) {
1026 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1027 radeon_cp_microcode[i][1]);
1028 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1029 radeon_cp_microcode[i][0]);
1da177e4
LT		 1030 }
1031 }
1032}
1033
1034/* Flush any pending commands to the CP. This should only be used just
1035 * prior to a wait for idle, as it informs the engine that the command
1036 * stream is ending.
1037 */
b5e89ed5 1038static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
1da177e4 1039{
b5e89ed5 1040 DRM_DEBUG("\n");
1da177e4
LT		 1041#if 0
1042 u32 tmp;
1043
b5e89ed5
DA		 1044 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
1045 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1da177e4
LT		 1046#endif
1047}
1048
1049/* Wait for the CP to go idle.
1050 */
b5e89ed5 1051int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1052{
1053 RING_LOCALS;
b5e89ed5 1054 DRM_DEBUG("\n");
1da177e4 1055
b5e89ed5 1056 BEGIN_RING(6);
1da177e4
LT		 1057
1058 RADEON_PURGE_CACHE();
1059 RADEON_PURGE_ZCACHE();
1060 RADEON_WAIT_UNTIL_IDLE();
1061
1062 ADVANCE_RING();
1063 COMMIT_RING();
1064
b5e89ed5 1065 return radeon_do_wait_for_idle(dev_priv);
1da177e4
LT		 1066}
1067
1068/* Start the Command Processor.
1069 */
b5e89ed5 1070static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1071{
1072 RING_LOCALS;
b5e89ed5 1073 DRM_DEBUG("\n");
1da177e4 1074
b5e89ed5 1075 radeon_do_wait_for_idle(dev_priv);
1da177e4 1076
b5e89ed5 1077 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1da177e4
LT		 1078
1079 dev_priv->cp_running = 1;
1080
b5e89ed5 1081 BEGIN_RING(6);
1da177e4
LT		 1082
1083 RADEON_PURGE_CACHE();
1084 RADEON_PURGE_ZCACHE();
1085 RADEON_WAIT_UNTIL_IDLE();
1086
1087 ADVANCE_RING();
1088 COMMIT_RING();
1089}
1090
1091/* Reset the Command Processor. This will not flush any pending
1092 * commands, so you must wait for the CP command stream to complete
1093 * before calling this routine.
1094 */
b5e89ed5 1095static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1da177e4
LT		 1096{
1097 u32 cur_read_ptr;
b5e89ed5 1098 DRM_DEBUG("\n");
1da177e4 1099
b5e89ed5
DA		 1100 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1101 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1102 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 1103 dev_priv->ring.tail = cur_read_ptr;
1104}
1105
1106/* Stop the Command Processor. This will not flush any pending
1107 * commands, so you must flush the command stream and wait for the CP
1108 * to go idle before calling this routine.
1109 */
b5e89ed5 1110static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1da177e4 1111{
b5e89ed5 1112 DRM_DEBUG("\n");
1da177e4 1113
b5e89ed5 1114 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1da177e4
LT		 1115
1116 dev_priv->cp_running = 0;
1117}
1118
1119/* Reset the engine. This will stop the CP if it is running.
1120 */
84b1fd10 1121static int radeon_do_engine_reset(struct drm_device * dev)
1da177e4
LT		 1122{
1123 drm_radeon_private_t *dev_priv = dev->dev_private;
1124 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
b5e89ed5 1125 DRM_DEBUG("\n");
1da177e4 1126
b5e89ed5
DA		 1127 radeon_do_pixcache_flush(dev_priv);
1128
3d5e2c13
DA		 1129 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1130 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1131 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1132
1133 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1134 RADEON_FORCEON_MCLKA |
1135 RADEON_FORCEON_MCLKB |
1136 RADEON_FORCEON_YCLKA |
1137 RADEON_FORCEON_YCLKB |
1138 RADEON_FORCEON_MC |
1139 RADEON_FORCEON_AIC));
1140
1141 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1142
1143 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1144 RADEON_SOFT_RESET_CP |
1145 RADEON_SOFT_RESET_HI |
1146 RADEON_SOFT_RESET_SE |
1147 RADEON_SOFT_RESET_RE |
1148 RADEON_SOFT_RESET_PP |
1149 RADEON_SOFT_RESET_E2 |
1150 RADEON_SOFT_RESET_RB));
1151 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1152 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1153 ~(RADEON_SOFT_RESET_CP |
1154 RADEON_SOFT_RESET_HI |
1155 RADEON_SOFT_RESET_SE |
1156 RADEON_SOFT_RESET_RE |
1157 RADEON_SOFT_RESET_PP |
1158 RADEON_SOFT_RESET_E2 |
1159 RADEON_SOFT_RESET_RB)));
1160 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1161
1162 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1163 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1164 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1165 }
1da177e4
LT		 1166
1167 /* Reset the CP ring */
b5e89ed5 1168 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 1169
1170 /* The CP is no longer running after an engine reset */
1171 dev_priv->cp_running = 0;
1172
1173 /* Reset any pending vertex, indirect buffers */
b5e89ed5 1174 radeon_freelist_reset(dev);
1da177e4
LT		 1175
1176 return 0;
1177}
1178
84b1fd10 1179static void radeon_cp_init_ring_buffer(struct drm_device * dev,
b5e89ed5 1180 drm_radeon_private_t * dev_priv)
1da177e4
LT		 1181{
1182 u32 ring_start, cur_read_ptr;
1183 u32 tmp;
bc5f4523 1184
d5ea702f
DA		 1185 /* Initialize the memory controller. With new memory map, the fb location
1186 * is not changed, it should have been properly initialized already. Part
1187 * of the problem is that the code below is bogus, assuming the GART is
1188 * always appended to the fb which is not necessarily the case
1189 */
1190 if (!dev_priv->new_memmap)
3d5e2c13 1191 radeon_write_fb_location(dev_priv,
d5ea702f
DA		 1192 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1193 | (dev_priv->fb_location >> 16));
1da177e4
LT		 1194
1195#if __OS_HAS_AGP
54a56ac5 1196 if (dev_priv->flags & RADEON_IS_AGP) {
d5ea702f 1197 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
3d5e2c13 1198 radeon_write_agp_location(dev_priv,
b5e89ed5
DA		 1199 (((dev_priv->gart_vm_start - 1 +
1200 dev_priv->gart_size) & 0xffff0000) |
1201 (dev_priv->gart_vm_start >> 16)));
1da177e4
LT		 1202
1203 ring_start = (dev_priv->cp_ring->offset
1204 - dev->agp->base
1205 + dev_priv->gart_vm_start);
b0917bd9 1206 } else
1da177e4
LT		 1207#endif
1208 ring_start = (dev_priv->cp_ring->offset
b0917bd9 1209 - (unsigned long)dev->sg->virtual
1da177e4
LT		 1210 + dev_priv->gart_vm_start);
1211
b5e89ed5 1212 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1da177e4
LT		 1213
1214 /* Set the write pointer delay */
b5e89ed5 1215 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1da177e4
LT		 1216
1217 /* Initialize the ring buffer's read and write pointers */
b5e89ed5
DA		 1218 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1219 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1220 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 1221 dev_priv->ring.tail = cur_read_ptr;
1222
1223#if __OS_HAS_AGP
54a56ac5 1224 if (dev_priv->flags & RADEON_IS_AGP) {
b5e89ed5
DA		 1225 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1226 dev_priv->ring_rptr->offset
1227 - dev->agp->base + dev_priv->gart_vm_start);
1da177e4
LT		 1228 } else
1229#endif
1230 {
55910517 1231 struct drm_sg_mem *entry = dev->sg;
1da177e4
LT		 1232 unsigned long tmp_ofs, page_ofs;
1233
b0917bd9
IK		 1234 tmp_ofs = dev_priv->ring_rptr->offset -
1235 (unsigned long)dev->sg->virtual;
1da177e4
LT		 1236 page_ofs = tmp_ofs >> PAGE_SHIFT;
1237
b5e89ed5
DA		 1238 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1239 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1240 (unsigned long)entry->busaddr[page_ofs],
1241 entry->handle + tmp_ofs);
1da177e4
LT		 1242 }
1243
d5ea702f
DA		 1244 /* Set ring buffer size */
1245#ifdef __BIG_ENDIAN
1246 RADEON_WRITE(RADEON_CP_RB_CNTL,
576cc458
RS		 1247 RADEON_BUF_SWAP_32BIT |
1248 (dev_priv->ring.fetch_size_l2ow << 18) |
1249 (dev_priv->ring.rptr_update_l2qw << 8) |
1250 dev_priv->ring.size_l2qw);
d5ea702f 1251#else
576cc458
RS		 1252 RADEON_WRITE(RADEON_CP_RB_CNTL,
1253 (dev_priv->ring.fetch_size_l2ow << 18) |
1254 (dev_priv->ring.rptr_update_l2qw << 8) |
1255 dev_priv->ring.size_l2qw);
d5ea702f
DA		 1256#endif
1257
1258 /* Start with assuming that writeback doesn't work */
1259 dev_priv->writeback_works = 0;
1260
1da177e4
LT		 1261 /* Initialize the scratch register pointer. This will cause
1262 * the scratch register values to be written out to memory
1263 * whenever they are updated.
1264 *
1265 * We simply put this behind the ring read pointer, this works
1266 * with PCI GART as well as (whatever kind of) AGP GART
1267 */
b5e89ed5
DA		 1268 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1269 + RADEON_SCRATCH_REG_OFFSET);
1da177e4
LT		 1270
1271 dev_priv->scratch = ((__volatile__ u32 *)
1272 dev_priv->ring_rptr->handle +
1273 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1274
b5e89ed5 1275 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1da177e4 1276
d5ea702f
DA		 1277 /* Turn on bus mastering */
1278 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1279 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1da177e4
LT		 1280
1281 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
b5e89ed5 1282 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1da177e4
LT		 1283
1284 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
b5e89ed5
DA		 1285 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1286 dev_priv->sarea_priv->last_dispatch);
1da177e4
LT		 1287
1288 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
b5e89ed5 1289 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1da177e4 1290
b5e89ed5 1291 radeon_do_wait_for_idle(dev_priv);
1da177e4 1292
1da177e4 1293 /* Sync everything up */
b5e89ed5
DA		 1294 RADEON_WRITE(RADEON_ISYNC_CNTL,
1295 (RADEON_ISYNC_ANY2D_IDLE3D |
1296 RADEON_ISYNC_ANY3D_IDLE2D |
1297 RADEON_ISYNC_WAIT_IDLEGUI |
1298 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
d5ea702f
DA		 1299
1300}
1301
1302static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1303{
1304 u32 tmp;
1305
1306 /* Writeback doesn't seem to work everywhere, test it here and possibly
1307 * enable it if it appears to work
1308 */
1309 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1310 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1311
1312 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1313 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1314 0xdeadbeef)
1315 break;
1316 DRM_UDELAY(1);
1317 }
1318
1319 if (tmp < dev_priv->usec_timeout) {
1320 dev_priv->writeback_works = 1;
1321 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1322 } else {
1323 dev_priv->writeback_works = 0;
1324 DRM_INFO("writeback test failed\n");
1325 }
1326 if (radeon_no_wb == 1) {
1327 dev_priv->writeback_works = 0;
1328 DRM_INFO("writeback forced off\n");
1329 }
ae1b1a48
MD		 1330
1331 if (!dev_priv->writeback_works) {
1332 /* Disable writeback to avoid unnecessary bus master transfer */
1333 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
1334 RADEON_RB_NO_UPDATE);
1335 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
1336 }
1da177e4
LT		 1337}
1338
f2b04cd2
DA		 1339/* Enable or disable IGP GART on the chip */
1340static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1341{
1342 u32 temp, tmp;
1343
1344 tmp = RADEON_READ(RADEON_AIC_CNTL);
1345 if (on) {
1346 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
1347 dev_priv->gart_vm_start,
1348 (long)dev_priv->gart_info.bus_addr,
1349 dev_priv->gart_size);
1350
1351 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
1352 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
1353 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
1354 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
1355 dev_priv->gart_info.bus_addr);
1356
1357 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1358 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
1359
1360 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1361 dev_priv->gart_size = 32*1024*1024;
3d5e2c13 1362 radeon_write_agp_location(dev_priv,
f2b04cd2
DA		 1363 (((dev_priv->gart_vm_start - 1 +
1364 dev_priv->gart_size) & 0xffff0000) |
1365 (dev_priv->gart_vm_start >> 16)));
1366
1367 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1368 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
1369
1370 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1371 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1372 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1373 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1374 }
1375}
1376
60f92683
MC		 1377/* Enable or disable RS690 GART on the chip */
1378static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
1379{
1380 u32 temp;
1381
1382 if (on) {
1383 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
1384 dev_priv->gart_vm_start,
1385 (long)dev_priv->gart_info.bus_addr,
1386 dev_priv->gart_size);
1387
1388 temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
1389 RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
1390
1391 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
1392 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
1393
1394 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
1395 RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
1396
1397 RS690_WRITE_MCIND(RS690_MC_GART_BASE,
1398 dev_priv->gart_info.bus_addr);
1399
1400 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
1401 RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
1402
1403 RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
1404 (unsigned int)dev_priv->gart_vm_start);
1405
1406 dev_priv->gart_size = 32*1024*1024;
1407 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
1408 0xffff0000) | (dev_priv->gart_vm_start >> 16));
1409
1410 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
1411
1412 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE);
1413 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
1414 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
1415
1416 do {
1417 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
1418 if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
1419 RS690_MC_GART_CLEAR_DONE)
1420 break;
1421 DRM_UDELAY(1);
1422 } while (1);
1423
1424 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
1425 RS690_MC_GART_CC_CLEAR);
1426 do {
1427 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
1428 if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
1429 RS690_MC_GART_CLEAR_DONE)
1430 break;
1431 DRM_UDELAY(1);
1432 } while (1);
1433
1434 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
1435 RS690_MC_GART_CC_NO_CHANGE);
1436 } else {
1437 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS);
1438 }
1439}
1440
ea98a92f
DA		 1441static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1442{
1443 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1444 if (on) {
1445
1446 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
b5e89ed5
DA		 1447 dev_priv->gart_vm_start,
1448 (long)dev_priv->gart_info.bus_addr,
ea98a92f 1449 dev_priv->gart_size);
b5e89ed5
DA		 1450 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1451 dev_priv->gart_vm_start);
1452 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1453 dev_priv->gart_info.bus_addr);
1454 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1455 dev_priv->gart_vm_start);
1456 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1457 dev_priv->gart_vm_start +
1458 dev_priv->gart_size - 1);
1459
3d5e2c13 1460 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
b5e89ed5
DA		 1461
1462 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1463 RADEON_PCIE_TX_GART_EN);
ea98a92f 1464 } else {
b5e89ed5
DA		 1465 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1466 tmp & ~RADEON_PCIE_TX_GART_EN);
ea98a92f 1467 }
1da177e4
LT		 1468}
1469
1470/* Enable or disable PCI GART on the chip */
b5e89ed5 1471static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1da177e4 1472{
d985c108 1473 u32 tmp;
1da177e4 1474
60f92683
MC		 1475 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
1476 radeon_set_rs690gart(dev_priv, on);
1477 return;
1478 }
1479
f2b04cd2
DA		 1480 if (dev_priv->flags & RADEON_IS_IGPGART) {
1481 radeon_set_igpgart(dev_priv, on);
1482 return;
1483 }
1484
54a56ac5 1485 if (dev_priv->flags & RADEON_IS_PCIE) {
ea98a92f
DA		 1486 radeon_set_pciegart(dev_priv, on);
1487 return;
1488 }
1da177e4 1489
bc5f4523 1490 tmp = RADEON_READ(RADEON_AIC_CNTL);
d985c108 1491
b5e89ed5
DA		 1492 if (on) {
1493 RADEON_WRITE(RADEON_AIC_CNTL,
1494 tmp | RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 1495
1496 /* set PCI GART page-table base address
1497 */
ea98a92f 1498 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1da177e4
LT		 1499
1500 /* set address range for PCI address translate
1501 */
b5e89ed5
DA		 1502 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1503 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1504 + dev_priv->gart_size - 1);
1da177e4
LT		 1505
1506 /* Turn off AGP aperture -- is this required for PCI GART?
1507 */
3d5e2c13 1508 radeon_write_agp_location(dev_priv, 0xffffffc0);
b5e89ed5 1509 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1da177e4 1510 } else {
b5e89ed5
DA		 1511 RADEON_WRITE(RADEON_AIC_CNTL,
1512 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 1513 }
1514}
1515
84b1fd10 1516static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
1da177e4 1517{
d985c108
DA		 1518 drm_radeon_private_t *dev_priv = dev->dev_private;
1519
b5e89ed5 1520 DRM_DEBUG("\n");
1da177e4 1521
f3dd5c37 1522 /* if we require new memory map but we don't have it fail */
54a56ac5 1523 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
b15ec368 1524 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
f3dd5c37 1525 radeon_do_cleanup_cp(dev);
20caafa6 1526 return -EINVAL;
f3dd5c37
DA		 1527 }
1528
54a56ac5 1529 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
d985c108 1530 DRM_DEBUG("Forcing AGP card to PCI mode\n");
54a56ac5
DA		 1531 dev_priv->flags &= ~RADEON_IS_AGP;
1532 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
b15ec368
DA		 1533 && !init->is_pci) {
1534 DRM_DEBUG("Restoring AGP flag\n");
54a56ac5 1535 dev_priv->flags |= RADEON_IS_AGP;
d985c108 1536 }
1da177e4 1537
54a56ac5 1538 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
b5e89ed5 1539 DRM_ERROR("PCI GART memory not allocated!\n");
1da177e4 1540 radeon_do_cleanup_cp(dev);
20caafa6 1541 return -EINVAL;
1da177e4
LT		 1542 }
1543
1544 dev_priv->usec_timeout = init->usec_timeout;
b5e89ed5
DA		 1545 if (dev_priv->usec_timeout < 1 ||
1546 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1547 DRM_DEBUG("TIMEOUT problem!\n");
1da177e4 1548 radeon_do_cleanup_cp(dev);
20caafa6 1549 return -EINVAL;
1da177e4
LT		 1550 }
1551
ddbee333
DA		 1552 /* Enable vblank on CRTC1 for older X servers
1553 */
1554 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1555
d985c108 1556 switch(init->func) {
1da177e4 1557 case RADEON_INIT_R200_CP:
b5e89ed5 1558 dev_priv->microcode_version = UCODE_R200;
1da177e4
LT		 1559 break;
1560 case RADEON_INIT_R300_CP:
b5e89ed5 1561 dev_priv->microcode_version = UCODE_R300;
1da177e4
LT		 1562 break;
1563 default:
b5e89ed5 1564 dev_priv->microcode_version = UCODE_R100;
1da177e4 1565 }
b5e89ed5 1566
1da177e4
LT		 1567 dev_priv->do_boxes = 0;
1568 dev_priv->cp_mode = init->cp_mode;
1569
1570 /* We don't support anything other than bus-mastering ring mode,
1571 * but the ring can be in either AGP or PCI space for the ring
1572 * read pointer.
1573 */
b5e89ed5
DA		 1574 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1575 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1576 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1da177e4 1577 radeon_do_cleanup_cp(dev);
20caafa6 1578 return -EINVAL;
1da177e4
LT		 1579 }
1580
b5e89ed5 1581 switch (init->fb_bpp) {
1da177e4
LT		 1582 case 16:
1583 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1584 break;
1585 case 32:
1586 default:
1587 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1588 break;
1589 }
b5e89ed5
DA		 1590 dev_priv->front_offset = init->front_offset;
1591 dev_priv->front_pitch = init->front_pitch;
1592 dev_priv->back_offset = init->back_offset;
1593 dev_priv->back_pitch = init->back_pitch;
1da177e4 1594
b5e89ed5 1595 switch (init->depth_bpp) {
1da177e4
LT		 1596 case 16:
1597 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1598 break;
1599 case 32:
1600 default:
1601 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1602 break;
1603 }
b5e89ed5
DA		 1604 dev_priv->depth_offset = init->depth_offset;
1605 dev_priv->depth_pitch = init->depth_pitch;
1da177e4
LT		 1606
1607 /* Hardware state for depth clears. Remove this if/when we no
1608 * longer clear the depth buffer with a 3D rectangle. Hard-code
1609 * all values to prevent unwanted 3D state from slipping through
1610 * and screwing with the clear operation.
1611 */
1612 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1613 (dev_priv->color_fmt << 10) |
b5e89ed5
DA		 1614 (dev_priv->microcode_version ==
1615 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1da177e4 1616
b5e89ed5
DA		 1617 dev_priv->depth_clear.rb3d_zstencilcntl =
1618 (dev_priv->depth_fmt |
1619 RADEON_Z_TEST_ALWAYS |
1620 RADEON_STENCIL_TEST_ALWAYS |
1621 RADEON_STENCIL_S_FAIL_REPLACE |
1622 RADEON_STENCIL_ZPASS_REPLACE |
1623 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1da177e4
LT		 1624
1625 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1626 RADEON_BFACE_SOLID |
1627 RADEON_FFACE_SOLID |
1628 RADEON_FLAT_SHADE_VTX_LAST |
1629 RADEON_DIFFUSE_SHADE_FLAT |
1630 RADEON_ALPHA_SHADE_FLAT |
1631 RADEON_SPECULAR_SHADE_FLAT |
1632 RADEON_FOG_SHADE_FLAT |
1633 RADEON_VTX_PIX_CENTER_OGL |
1634 RADEON_ROUND_MODE_TRUNC |
1635 RADEON_ROUND_PREC_8TH_PIX);
1636
1da177e4 1637
1da177e4
LT		 1638 dev_priv->ring_offset = init->ring_offset;
1639 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1640 dev_priv->buffers_offset = init->buffers_offset;
1641 dev_priv->gart_textures_offset = init->gart_textures_offset;
b5e89ed5 1642
da509d7a 1643 dev_priv->sarea = drm_getsarea(dev);
b5e89ed5 1644 if (!dev_priv->sarea) {
1da177e4 1645 DRM_ERROR("could not find sarea!\n");
1da177e4 1646 radeon_do_cleanup_cp(dev);
20caafa6 1647 return -EINVAL;
1da177e4
LT		 1648 }
1649
1da177e4 1650 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
b5e89ed5 1651 if (!dev_priv->cp_ring) {
1da177e4 1652 DRM_ERROR("could not find cp ring region!\n");
1da177e4 1653 radeon_do_cleanup_cp(dev);
20caafa6 1654 return -EINVAL;
1da177e4
LT		 1655 }
1656 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
b5e89ed5 1657 if (!dev_priv->ring_rptr) {
1da177e4 1658 DRM_ERROR("could not find ring read pointer!\n");
1da177e4 1659 radeon_do_cleanup_cp(dev);
20caafa6 1660 return -EINVAL;
1da177e4 1661 }
d1f2b55a 1662 dev->agp_buffer_token = init->buffers_offset;
1da177e4 1663 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
b5e89ed5 1664 if (!dev->agp_buffer_map) {
1da177e4 1665 DRM_ERROR("could not find dma buffer region!\n");
1da177e4 1666 radeon_do_cleanup_cp(dev);
20caafa6 1667 return -EINVAL;
1da177e4
LT		 1668 }
1669
b5e89ed5
DA		 1670 if (init->gart_textures_offset) {
1671 dev_priv->gart_textures =
1672 drm_core_findmap(dev, init->gart_textures_offset);
1673 if (!dev_priv->gart_textures) {
1da177e4 1674 DRM_ERROR("could not find GART texture region!\n");
1da177e4 1675 radeon_do_cleanup_cp(dev);
20caafa6 1676 return -EINVAL;
1da177e4
LT		 1677 }
1678 }
1679
1680 dev_priv->sarea_priv =
b5e89ed5
DA		 1681 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1682 init->sarea_priv_offset);
1da177e4
LT		 1683
1684#if __OS_HAS_AGP
54a56ac5 1685 if (dev_priv->flags & RADEON_IS_AGP) {
b5e89ed5
DA		 1686 drm_core_ioremap(dev_priv->cp_ring, dev);
1687 drm_core_ioremap(dev_priv->ring_rptr, dev);
1688 drm_core_ioremap(dev->agp_buffer_map, dev);
1689 if (!dev_priv->cp_ring->handle ||
1690 !dev_priv->ring_rptr->handle ||
1691 !dev->agp_buffer_map->handle) {
1da177e4 1692 DRM_ERROR("could not find ioremap agp regions!\n");
1da177e4 1693 radeon_do_cleanup_cp(dev);
20caafa6 1694 return -EINVAL;
1da177e4
LT		 1695 }
1696 } else
1697#endif
1698 {
b5e89ed5 1699 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1da177e4 1700 dev_priv->ring_rptr->handle =
b5e89ed5
DA		 1701 (void *)dev_priv->ring_rptr->offset;
1702 dev->agp_buffer_map->handle =
1703 (void *)dev->agp_buffer_map->offset;
1704
1705 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1706 dev_priv->cp_ring->handle);
1707 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1708 dev_priv->ring_rptr->handle);
1709 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1710 dev->agp_buffer_map->handle);
1da177e4
LT		 1711 }
1712
3d5e2c13 1713 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
bc5f4523 1714 dev_priv->fb_size =
3d5e2c13 1715 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
d5ea702f 1716 - dev_priv->fb_location;
1da177e4 1717
b5e89ed5
DA		 1718 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1719 ((dev_priv->front_offset
1720 + dev_priv->fb_location) >> 10));
1da177e4 1721
b5e89ed5
DA		 1722 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1723 ((dev_priv->back_offset
1724 + dev_priv->fb_location) >> 10));
1da177e4 1725
b5e89ed5
DA		 1726 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1727 ((dev_priv->depth_offset
1728 + dev_priv->fb_location) >> 10));
1da177e4
LT		 1729
1730 dev_priv->gart_size = init->gart_size;
d5ea702f
DA		 1731
1732 /* New let's set the memory map ... */
1733 if (dev_priv->new_memmap) {
1734 u32 base = 0;
1735
1736 DRM_INFO("Setting GART location based on new memory map\n");
1737
1738 /* If using AGP, try to locate the AGP aperture at the same
1739 * location in the card and on the bus, though we have to
1740 * align it down.
1741 */
1742#if __OS_HAS_AGP
54a56ac5 1743 if (dev_priv->flags & RADEON_IS_AGP) {
d5ea702f
DA		 1744 base = dev->agp->base;
1745 /* Check if valid */
80b2c386
MD		 1746 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1747 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
d5ea702f
DA		 1748 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1749 dev->agp->base);
1750 base = 0;
1751 }
1752 }
1753#endif
1754 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1755 if (base == 0) {
1756 base = dev_priv->fb_location + dev_priv->fb_size;
80b2c386
MD		 1757 if (base < dev_priv->fb_location ||
1758 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
d5ea702f
DA		 1759 base = dev_priv->fb_location
1760 - dev_priv->gart_size;
bc5f4523 1761 }
d5ea702f
DA		 1762 dev_priv->gart_vm_start = base & 0xffc00000u;
1763 if (dev_priv->gart_vm_start != base)
1764 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1765 base, dev_priv->gart_vm_start);
1766 } else {
1767 DRM_INFO("Setting GART location based on old memory map\n");
1768 dev_priv->gart_vm_start = dev_priv->fb_location +
1769 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1770 }
1da177e4
LT		 1771
1772#if __OS_HAS_AGP
54a56ac5 1773 if (dev_priv->flags & RADEON_IS_AGP)
1da177e4 1774 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b5e89ed5
DA		 1775 - dev->agp->base
1776 + dev_priv->gart_vm_start);
1da177e4
LT		 1777 else
1778#endif
1779 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b0917bd9
IK		 1780 - (unsigned long)dev->sg->virtual
1781 + dev_priv->gart_vm_start);
1da177e4 1782
b5e89ed5
DA		 1783 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1784 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1785 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1786 dev_priv->gart_buffers_offset);
1da177e4 1787
b5e89ed5
DA		 1788 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1789 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1da177e4
LT		 1790 + init->ring_size / sizeof(u32));
1791 dev_priv->ring.size = init->ring_size;
b5e89ed5 1792 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1da177e4 1793
576cc458
RS		 1794 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1795 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1796
1797 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1798 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
b5e89ed5 1799 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1da177e4
LT		 1800
1801 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1802
1803#if __OS_HAS_AGP
54a56ac5 1804 if (dev_priv->flags & RADEON_IS_AGP) {
1da177e4 1805 /* Turn off PCI GART */
b5e89ed5 1806 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1807 } else
1808#endif
1809 {
ea98a92f 1810 /* if we have an offset set from userspace */
f2b04cd2 1811 if (dev_priv->pcigart_offset_set) {
b5e89ed5
DA		 1812 dev_priv->gart_info.bus_addr =
1813 dev_priv->pcigart_offset + dev_priv->fb_location;
f26c473c 1814 dev_priv->gart_info.mapping.offset =
7fc86860 1815 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
f26c473c 1816 dev_priv->gart_info.mapping.size =
f2b04cd2 1817 dev_priv->gart_info.table_size;
f26c473c
DA		 1818
1819 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
b5e89ed5 1820 dev_priv->gart_info.addr =
f26c473c 1821 dev_priv->gart_info.mapping.handle;
b5e89ed5 1822
f2b04cd2
DA		 1823 if (dev_priv->flags & RADEON_IS_PCIE)
1824 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1825 else
1826 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
b5e89ed5
DA		 1827 dev_priv->gart_info.gart_table_location =
1828 DRM_ATI_GART_FB;
1829
f26c473c 1830 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
b5e89ed5
DA		 1831 dev_priv->gart_info.addr,
1832 dev_priv->pcigart_offset);
1833 } else {
f2b04cd2
DA		 1834 if (dev_priv->flags & RADEON_IS_IGPGART)
1835 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1836 else
1837 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
b5e89ed5
DA		 1838 dev_priv->gart_info.gart_table_location =
1839 DRM_ATI_GART_MAIN;
f26c473c
DA		 1840 dev_priv->gart_info.addr = NULL;
1841 dev_priv->gart_info.bus_addr = 0;
54a56ac5 1842 if (dev_priv->flags & RADEON_IS_PCIE) {
b5e89ed5
DA		 1843 DRM_ERROR
1844 ("Cannot use PCI Express without GART in FB memory\n");
ea98a92f 1845 radeon_do_cleanup_cp(dev);
20caafa6 1846 return -EINVAL;
ea98a92f
DA		 1847 }
1848 }
1849
1850 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
b5e89ed5 1851 DRM_ERROR("failed to init PCI GART!\n");
1da177e4 1852 radeon_do_cleanup_cp(dev);
20caafa6 1853 return -ENOMEM;
1da177e4
LT		 1854 }
1855
1856 /* Turn on PCI GART */
b5e89ed5 1857 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1858 }
1859
b5e89ed5
DA		 1860 radeon_cp_load_microcode(dev_priv);
1861 radeon_cp_init_ring_buffer(dev, dev_priv);
1da177e4
LT		 1862
1863 dev_priv->last_buf = 0;
1864
b5e89ed5 1865 radeon_do_engine_reset(dev);
d5ea702f 1866 radeon_test_writeback(dev_priv);
1da177e4
LT		 1867
1868 return 0;
1869}
1870
84b1fd10 1871static int radeon_do_cleanup_cp(struct drm_device * dev)
1da177e4
LT		 1872{
1873 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1874 DRM_DEBUG("\n");
1da177e4
LT		 1875
1876 /* Make sure interrupts are disabled here because the uninstall ioctl
1877 * may not have been called from userspace and after dev_private
1878 * is freed, it's too late.
1879 */
b5e89ed5
DA		 1880 if (dev->irq_enabled)
1881 drm_irq_uninstall(dev);
1da177e4
LT		 1882
1883#if __OS_HAS_AGP
54a56ac5 1884 if (dev_priv->flags & RADEON_IS_AGP) {
d985c108 1885 if (dev_priv->cp_ring != NULL) {
b5e89ed5 1886 drm_core_ioremapfree(dev_priv->cp_ring, dev);
d985c108
DA		 1887 dev_priv->cp_ring = NULL;
1888 }
1889 if (dev_priv->ring_rptr != NULL) {
b5e89ed5 1890 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
d985c108
DA		 1891 dev_priv->ring_rptr = NULL;
1892 }
b5e89ed5
DA		 1893 if (dev->agp_buffer_map != NULL) {
1894 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1da177e4
LT		 1895 dev->agp_buffer_map = NULL;
1896 }
1897 } else
1898#endif
1899 {
d985c108
DA		 1900
1901 if (dev_priv->gart_info.bus_addr) {
1902 /* Turn off PCI GART */
1903 radeon_set_pcigart(dev_priv, 0);
ea98a92f
DA		 1904 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1905 DRM_ERROR("failed to cleanup PCI GART!\n");
d985c108 1906 }
b5e89ed5 1907
d985c108
DA		 1908 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1909 {
f26c473c 1910 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
f2b04cd2 1911 dev_priv->gart_info.addr = 0;
ea98a92f 1912 }
1da177e4 1913 }
1da177e4
LT		 1914 /* only clear to the start of flags */
1915 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1916
1917 return 0;
1918}
1919
b5e89ed5
DA		 1920/* This code will reinit the Radeon CP hardware after a resume from disc.
1921 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1da177e4
LT		 1922 * here we make sure that all Radeon hardware initialisation is re-done without
1923 * affecting running applications.
1924 *
1925 * Charl P. Botha <http://cpbotha.net>
1926 */
84b1fd10 1927static int radeon_do_resume_cp(struct drm_device * dev)
1da177e4
LT		 1928{
1929 drm_radeon_private_t *dev_priv = dev->dev_private;
1930
b5e89ed5
DA		 1931 if (!dev_priv) {
1932 DRM_ERROR("Called with no initialization\n");
20caafa6 1933 return -EINVAL;
1da177e4
LT		 1934 }
1935
1936 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1937
1938#if __OS_HAS_AGP
54a56ac5 1939 if (dev_priv->flags & RADEON_IS_AGP) {
1da177e4 1940 /* Turn off PCI GART */
b5e89ed5 1941 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1942 } else
1943#endif
1944 {
1945 /* Turn on PCI GART */
b5e89ed5 1946 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1947 }
1948
b5e89ed5
DA		 1949 radeon_cp_load_microcode(dev_priv);
1950 radeon_cp_init_ring_buffer(dev, dev_priv);
1da177e4 1951
b5e89ed5 1952 radeon_do_engine_reset(dev);
1da177e4
LT		 1953
1954 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1955
1956 return 0;
1957}
1958
c153f45f 1959int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1960{
c153f45f 1961 drm_radeon_init_t *init = data;
1da177e4 1962
6c340eac 1963 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1964
c153f45f 1965 if (init->func == RADEON_INIT_R300_CP)
3d5e2c13 1966 r300_init_reg_flags(dev);
414ed537 1967
c153f45f 1968 switch (init->func) {
1da177e4
LT		 1969 case RADEON_INIT_CP:
1970 case RADEON_INIT_R200_CP:
1971 case RADEON_INIT_R300_CP:
c153f45f 1972 return radeon_do_init_cp(dev, init);
1da177e4 1973 case RADEON_CLEANUP_CP:
b5e89ed5 1974 return radeon_do_cleanup_cp(dev);
1da177e4
LT		 1975 }
1976
20caafa6 1977 return -EINVAL;
1da177e4
LT		 1978}
1979
c153f45f 1980int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1981{
1da177e4 1982 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1983 DRM_DEBUG("\n");
1da177e4 1984
6c340eac 1985 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1986
b5e89ed5 1987 if (dev_priv->cp_running) {
3e684eae 1988 DRM_DEBUG("while CP running\n");
1da177e4
LT		 1989 return 0;
1990 }
b5e89ed5 1991 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
3e684eae
MN		 1992 DRM_DEBUG("called with bogus CP mode (%d)\n",
1993 dev_priv->cp_mode);
1da177e4
LT		 1994 return 0;
1995 }
1996
b5e89ed5 1997 radeon_do_cp_start(dev_priv);
1da177e4
LT		 1998
1999 return 0;
2000}
2001
2002/* Stop the CP. The engine must have been idled before calling this
2003 * routine.
2004 */
c153f45f 2005int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2006{
1da177e4 2007 drm_radeon_private_t *dev_priv = dev->dev_private;
c153f45f 2008 drm_radeon_cp_stop_t *stop = data;
1da177e4 2009 int ret;
b5e89ed5 2010 DRM_DEBUG("\n");
1da177e4 2011
6c340eac 2012 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 2013
1da177e4
LT		 2014 if (!dev_priv->cp_running)
2015 return 0;
2016
2017 /* Flush any pending CP commands. This ensures any outstanding
2018 * commands are exectuted by the engine before we turn it off.
2019 */
c153f45f 2020 if (stop->flush) {
b5e89ed5 2021 radeon_do_cp_flush(dev_priv);
1da177e4
LT		 2022 }
2023
2024 /* If we fail to make the engine go idle, we return an error
2025 * code so that the DRM ioctl wrapper can try again.
2026 */
c153f45f 2027 if (stop->idle) {
b5e89ed5
DA		 2028 ret = radeon_do_cp_idle(dev_priv);
2029 if (ret)
2030 return ret;
1da177e4
LT		 2031 }
2032
2033 /* Finally, we can turn off the CP. If the engine isn't idle,
2034 * we will get some dropped triangles as they won't be fully
2035 * rendered before the CP is shut down.
2036 */
b5e89ed5 2037 radeon_do_cp_stop(dev_priv);
1da177e4
LT		 2038
2039 /* Reset the engine */
b5e89ed5 2040 radeon_do_engine_reset(dev);
1da177e4
LT		 2041
2042 return 0;
2043}
2044
84b1fd10 2045void radeon_do_release(struct drm_device * dev)
1da177e4
LT		 2046{
2047 drm_radeon_private_t *dev_priv = dev->dev_private;
2048 int i, ret;
2049
2050 if (dev_priv) {
2051 if (dev_priv->cp_running) {
2052 /* Stop the cp */
b5e89ed5 2053 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1da177e4
LT		 2054 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
2055#ifdef __linux__
2056 schedule();
2057#else
2058 tsleep(&ret, PZERO, "rdnrel", 1);
2059#endif
2060 }
b5e89ed5
DA		 2061 radeon_do_cp_stop(dev_priv);
2062 radeon_do_engine_reset(dev);
1da177e4
LT		 2063 }
2064
2065 /* Disable *all* interrupts */
2066 if (dev_priv->mmio) /* remove this after permanent addmaps */
b5e89ed5 2067 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1da177e4 2068
b5e89ed5 2069 if (dev_priv->mmio) { /* remove all surfaces */
1da177e4 2070 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
b5e89ed5
DA		 2071 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
2072 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
2073 16 * i, 0);
2074 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
2075 16 * i, 0);
1da177e4
LT		 2076 }
2077 }
2078
2079 /* Free memory heap structures */
b5e89ed5
DA		 2080 radeon_mem_takedown(&(dev_priv->gart_heap));
2081 radeon_mem_takedown(&(dev_priv->fb_heap));
1da177e4
LT		 2082
2083 /* deallocate kernel resources */
b5e89ed5 2084 radeon_do_cleanup_cp(dev);
1da177e4
LT		 2085 }
2086}
2087
2088/* Just reset the CP ring. Called as part of an X Server engine reset.
2089 */
c153f45f 2090int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2091{
1da177e4 2092 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 2093 DRM_DEBUG("\n");
1da177e4 2094
6c340eac 2095 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 2096
b5e89ed5 2097 if (!dev_priv) {
3e684eae 2098 DRM_DEBUG("called before init done\n");
20caafa6 2099 return -EINVAL;
1da177e4
LT		 2100 }
2101
b5e89ed5 2102 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 2103
2104 /* The CP is no longer running after an engine reset */
2105 dev_priv->cp_running = 0;
2106
2107 return 0;
2108}
2109
c153f45f 2110int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2111{
1da177e4 2112 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 2113 DRM_DEBUG("\n");
1da177e4 2114
6c340eac 2115 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 2116
b5e89ed5 2117 return radeon_do_cp_idle(dev_priv);
1da177e4
LT		 2118}
2119
2120/* Added by Charl P. Botha to call radeon_do_resume_cp().
2121 */
c153f45f 2122int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2123{
1da177e4
LT		 2124
2125 return radeon_do_resume_cp(dev);
2126}
2127
c153f45f 2128int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2129{
b5e89ed5 2130 DRM_DEBUG("\n");
1da177e4 2131
6c340eac 2132 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 2133
b5e89ed5 2134 return radeon_do_engine_reset(dev);
1da177e4
LT		 2135}
2136
1da177e4
LT		 2137/* ================================================================
2138 * Fullscreen mode
2139 */
2140
2141/* KW: Deprecated to say the least:
2142 */
c153f45f 2143int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4
LT		 2144{
2145 return 0;
2146}
2147
1da177e4
LT		 2148/* ================================================================
2149 * Freelist management
2150 */
2151
2152/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
2153 * bufs until freelist code is used. Note this hides a problem with
2154 * the scratch register * (used to keep track of last buffer
2155 * completed) being written to before * the last buffer has actually
b5e89ed5 2156 * completed rendering.
1da177e4
LT		 2157 *
2158 * KW: It's also a good way to find free buffers quickly.
2159 *
2160 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
2161 * sleep. However, bugs in older versions of radeon_accel.c mean that
2162 * we essentially have to do this, else old clients will break.
b5e89ed5 2163 *
1da177e4
LT		 2164 * However, it does leave open a potential deadlock where all the
2165 * buffers are held by other clients, which can't release them because
b5e89ed5 2166 * they can't get the lock.
1da177e4
LT		 2167 */
2168
056219e2 2169struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1da177e4 2170{
cdd55a29 2171 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 2172 drm_radeon_private_t *dev_priv = dev->dev_private;
2173 drm_radeon_buf_priv_t *buf_priv;
056219e2 2174 struct drm_buf *buf;
1da177e4
LT		 2175 int i, t;
2176 int start;
2177
b5e89ed5 2178 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 2179 dev_priv->last_buf = 0;
2180
2181 start = dev_priv->last_buf;
2182
b5e89ed5
DA		 2183 for (t = 0; t < dev_priv->usec_timeout; t++) {
2184 u32 done_age = GET_SCRATCH(1);
2185 DRM_DEBUG("done_age = %d\n", done_age);
2186 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 2187 buf = dma->buflist[i];
2188 buf_priv = buf->dev_private;
6c340eac
EA		 2189 if (buf->file_priv == NULL || (buf->pending &&
2190 buf_priv->age <=
2191 done_age)) {
1da177e4
LT		 2192 dev_priv->stats.requested_bufs++;
2193 buf->pending = 0;
2194 return buf;
2195 }
2196 start = 0;
2197 }
2198
2199 if (t) {
b5e89ed5 2200 DRM_UDELAY(1);
1da177e4
LT		 2201 dev_priv->stats.freelist_loops++;
2202 }
2203 }
2204
b5e89ed5 2205 DRM_DEBUG("returning NULL!\n");
1da177e4
LT		 2206 return NULL;
2207}
b5e89ed5 2208
1da177e4 2209#if 0
056219e2 2210struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1da177e4 2211{
cdd55a29 2212 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 2213 drm_radeon_private_t *dev_priv = dev->dev_private;
2214 drm_radeon_buf_priv_t *buf_priv;
056219e2 2215 struct drm_buf *buf;
1da177e4
LT		 2216 int i, t;
2217 int start;
2218 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2219
b5e89ed5 2220 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 2221 dev_priv->last_buf = 0;
2222
2223 start = dev_priv->last_buf;
2224 dev_priv->stats.freelist_loops++;
b5e89ed5
DA		 2225
2226 for (t = 0; t < 2; t++) {
2227 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 2228 buf = dma->buflist[i];
2229 buf_priv = buf->dev_private;
6c340eac
EA		 2230 if (buf->file_priv == 0 || (buf->pending &&
2231 buf_priv->age <=
2232 done_age)) {
1da177e4
LT		 2233 dev_priv->stats.requested_bufs++;
2234 buf->pending = 0;
2235 return buf;
2236 }
2237 }
2238 start = 0;
2239 }
2240
2241 return NULL;
2242}
2243#endif
2244
84b1fd10 2245void radeon_freelist_reset(struct drm_device * dev)
1da177e4 2246{
cdd55a29 2247 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 2248 drm_radeon_private_t *dev_priv = dev->dev_private;
2249 int i;
2250
2251 dev_priv->last_buf = 0;
b5e89ed5 2252 for (i = 0; i < dma->buf_count; i++) {
056219e2 2253 struct drm_buf *buf = dma->buflist[i];
1da177e4
LT		 2254 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2255 buf_priv->age = 0;
2256 }
2257}
2258
1da177e4
LT		 2259/* ================================================================
2260 * CP command submission
2261 */
2262
b5e89ed5 2263int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1da177e4
LT		 2264{
2265 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2266 int i;
b5e89ed5 2267 u32 last_head = GET_RING_HEAD(dev_priv);
1da177e4 2268
b5e89ed5
DA		 2269 for (i = 0; i < dev_priv->usec_timeout; i++) {
2270 u32 head = GET_RING_HEAD(dev_priv);
1da177e4
LT		 2271
2272 ring->space = (head - ring->tail) * sizeof(u32);
b5e89ed5 2273 if (ring->space <= 0)
1da177e4 2274 ring->space += ring->size;
b5e89ed5 2275 if (ring->space > n)
1da177e4 2276 return 0;
b5e89ed5 2277
1da177e4
LT		 2278 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2279
2280 if (head != last_head)
2281 i = 0;
2282 last_head = head;
2283
b5e89ed5 2284 DRM_UDELAY(1);
1da177e4
LT		 2285 }
2286
2287 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2288#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 2289 radeon_status(dev_priv);
2290 DRM_ERROR("failed!\n");
1da177e4 2291#endif
20caafa6 2292 return -EBUSY;
1da177e4
LT		 2293}
2294
6c340eac
EA		 2295static int radeon_cp_get_buffers(struct drm_device *dev,
2296 struct drm_file *file_priv,
c60ce623 2297 struct drm_dma * d)
1da177e4
LT		 2298{
2299 int i;
056219e2 2300 struct drm_buf *buf;
1da177e4 2301
b5e89ed5
DA		 2302 for (i = d->granted_count; i < d->request_count; i++) {
2303 buf = radeon_freelist_get(dev);
2304 if (!buf)
20caafa6 2305 return -EBUSY; /* NOTE: broken client */
1da177e4 2306
6c340eac 2307 buf->file_priv = file_priv;
1da177e4 2308
b5e89ed5
DA		 2309 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2310 sizeof(buf->idx)))
20caafa6 2311 return -EFAULT;
b5e89ed5
DA		 2312 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2313 sizeof(buf->total)))
20caafa6 2314 return -EFAULT;
1da177e4
LT		 2315
2316 d->granted_count++;
2317 }
2318 return 0;
2319}
2320
c153f45f 2321int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 2322{
cdd55a29 2323 struct drm_device_dma *dma = dev->dma;
1da177e4 2324 int ret = 0;
c153f45f 2325 struct drm_dma *d = data;
1da177e4 2326
6c340eac 2327 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 2328
1da177e4
LT		 2329 /* Please don't send us buffers.
2330 */
c153f45f 2331 if (d->send_count != 0) {
b5e89ed5 2332 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
c153f45f 2333 DRM_CURRENTPID, d->send_count);
20caafa6 2334 return -EINVAL;
1da177e4
LT		 2335 }
2336
2337 /* We'll send you buffers.
2338 */
c153f45f 2339 if (d->request_count < 0 || d->request_count > dma->buf_count) {
b5e89ed5 2340 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
c153f45f 2341 DRM_CURRENTPID, d->request_count, dma->buf_count);
20caafa6 2342 return -EINVAL;
1da177e4
LT		 2343 }
2344
c153f45f 2345 d->granted_count = 0;
1da177e4 2346
c153f45f
EA		 2347 if (d->request_count) {
2348 ret = radeon_cp_get_buffers(dev, file_priv, d);
1da177e4
LT		 2349 }
2350
1da177e4
LT		 2351 return ret;
2352}
2353
22eae947 2354int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1da177e4
LT		 2355{
2356 drm_radeon_private_t *dev_priv;
2357 int ret = 0;
2358
2359 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2360 if (dev_priv == NULL)
20caafa6 2361 return -ENOMEM;
1da177e4
LT		 2362
2363 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2364 dev->dev_private = (void *)dev_priv;
2365 dev_priv->flags = flags;
2366
54a56ac5 2367 switch (flags & RADEON_FAMILY_MASK) {
1da177e4
LT		 2368 case CHIP_R100:
2369 case CHIP_RV200:
2370 case CHIP_R200:
2371 case CHIP_R300:
b15ec368 2372 case CHIP_R350:
414ed537 2373 case CHIP_R420:
b15ec368 2374 case CHIP_RV410:
3d5e2c13
DA		 2375 case CHIP_RV515:
2376 case CHIP_R520:
2377 case CHIP_RV570:
2378 case CHIP_R580:
54a56ac5 2379 dev_priv->flags |= RADEON_HAS_HIERZ;
1da177e4
LT		 2380 break;
2381 default:
b5e89ed5 2382 /* all other chips have no hierarchical z buffer */
1da177e4
LT		 2383 break;
2384 }
414ed537
DA		 2385
2386 if (drm_device_is_agp(dev))
54a56ac5 2387 dev_priv->flags |= RADEON_IS_AGP;
b15ec368 2388 else if (drm_device_is_pcie(dev))
54a56ac5 2389 dev_priv->flags |= RADEON_IS_PCIE;
b15ec368 2390 else
54a56ac5 2391 dev_priv->flags |= RADEON_IS_PCI;
ea98a92f 2392
414ed537 2393 DRM_DEBUG("%s card detected\n",
54a56ac5 2394 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1da177e4
LT		 2395 return ret;
2396}
2397
22eae947
DA		 2398/* Create mappings for registers and framebuffer so userland doesn't necessarily
2399 * have to find them.
2400 */
2401int radeon_driver_firstopen(struct drm_device *dev)
836cf046
DA		 2402{
2403 int ret;
2404 drm_local_map_t *map;
2405 drm_radeon_private_t *dev_priv = dev->dev_private;
2406
f2b04cd2
DA		 2407 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2408
836cf046
DA		 2409 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2410 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2411 _DRM_READ_ONLY, &dev_priv->mmio);
2412 if (ret != 0)
2413 return ret;
2414
7fc86860
DA		 2415 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2416 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
836cf046
DA		 2417 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2418 _DRM_WRITE_COMBINING, &map);
2419 if (ret != 0)
2420 return ret;
2421
2422 return 0;
2423}
2424
22eae947 2425int radeon_driver_unload(struct drm_device *dev)
1da177e4
LT		 2426{
2427 drm_radeon_private_t *dev_priv = dev->dev_private;
2428
2429 DRM_DEBUG("\n");
1da177e4
LT		 2430 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2431
2432 dev->dev_private = NULL;
2433 return 0;
2434}
Linux 6.x block layer and io_uring tree(s)