[linux-2.6-block.git] / drivers / char / agp / hp-agp.c

/*
 * HP zx1 AGPGART routines.
 *
 * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
 *	Bjorn Helgaas <bjorn.helgaas@hp.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include <linux/log2.h>

#include <asm/acpi-ext.h>

#include "agp.h"

#define HP_ZX1_IOC_OFFSET	0x1000  /* ACPI reports SBA, we want IOC */

/* HP ZX1 IOC registers */
#define HP_ZX1_IBASE		0x300
#define HP_ZX1_IMASK		0x308
#define HP_ZX1_PCOM		0x310
#define HP_ZX1_TCNFG		0x318
#define HP_ZX1_PDIR_BASE	0x320

#define HP_ZX1_IOVA_BASE	GB(1UL)
#define HP_ZX1_IOVA_SIZE	GB(1UL)
#define HP_ZX1_GART_SIZE	(HP_ZX1_IOVA_SIZE / 2)
#define HP_ZX1_SBA_IOMMU_COOKIE	0x0000badbadc0ffeeUL

#define HP_ZX1_PDIR_VALID_BIT	0x8000000000000000UL
#define HP_ZX1_IOVA_TO_PDIR(va)	((va - hp_private.iova_base) >> hp_private.io_tlb_shift)

#define AGP8X_MODE_BIT		3
#define AGP8X_MODE		(1 << AGP8X_MODE_BIT)

/* AGP bridge need not be PCI device, but DRM thinks it is. */
static struct pci_dev fake_bridge_dev;

static int hp_zx1_gart_found;

static struct aper_size_info_fixed hp_zx1_sizes[] =
{
	{0, 0, 0},		/* filled in by hp_zx1_fetch_size() */
};

static struct gatt_mask hp_zx1_masks[] =
{
	{.mask = HP_ZX1_PDIR_VALID_BIT, .type = 0}
};

static struct _hp_private {
	volatile u8 __iomem *ioc_regs;
	volatile u8 __iomem *lba_regs;
	int lba_cap_offset;
	u64 *io_pdir;		// PDIR for entire IOVA
	u64 *gatt;		// PDIR just for GART (subset of above)
	u64 gatt_entries;
	u64 iova_base;
	u64 gart_base;
	u64 gart_size;
	u64 io_pdir_size;
	int io_pdir_owner;	// do we own it, or share it with sba_iommu?
	int io_page_size;
	int io_tlb_shift;
	int io_tlb_ps;		// IOC ps config
	int io_pages_per_kpage;
} hp_private;

static int __init hp_zx1_ioc_shared(void)
{
	struct _hp_private *hp = &hp_private;

	printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR shared with sba_iommu\n");

	/*
	 * IOC already configured by sba_iommu module; just use
	 * its setup.  We assume:
	 *	- IOVA space is 1Gb in size
	 *	- first 512Mb is IOMMU, second 512Mb is GART
	 */
	hp->io_tlb_ps = readq(hp->ioc_regs+HP_ZX1_TCNFG);
	switch (hp->io_tlb_ps) {
		case 0: hp->io_tlb_shift = 12; break;
		case 1: hp->io_tlb_shift = 13; break;
		case 2: hp->io_tlb_shift = 14; break;
		case 3: hp->io_tlb_shift = 16; break;
		default:
			printk(KERN_ERR PFX "Invalid IOTLB page size "
			       "configuration 0x%x\n", hp->io_tlb_ps);
			hp->gatt = NULL;
			hp->gatt_entries = 0;
			return -ENODEV;
	}
	hp->io_page_size = 1 << hp->io_tlb_shift;
	hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;

	hp->iova_base = readq(hp->ioc_regs+HP_ZX1_IBASE) & ~0x1;
	hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - HP_ZX1_GART_SIZE;

	hp->gart_size = HP_ZX1_GART_SIZE;
	hp->gatt_entries = hp->gart_size / hp->io_page_size;

	hp->io_pdir = gart_to_virt(readq(hp->ioc_regs+HP_ZX1_PDIR_BASE));
	hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];

	if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) {
		/* Normal case when no AGP device in system */
		hp->gatt = NULL;
		hp->gatt_entries = 0;
		printk(KERN_ERR PFX "No reserved IO PDIR entry found; "
		       "GART disabled\n");
		return -ENODEV;
	}

	return 0;
}

static int __init
hp_zx1_ioc_owner (void)
{
	struct _hp_private *hp = &hp_private;

	printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR dedicated to GART\n");

	/*
	 * Select an IOV page size no larger than system page size.
	 */
	if (PAGE_SIZE >= KB(64)) {
		hp->io_tlb_shift = 16;
		hp->io_tlb_ps = 3;
	} else if (PAGE_SIZE >= KB(16)) {
		hp->io_tlb_shift = 14;
		hp->io_tlb_ps = 2;
	} else if (PAGE_SIZE >= KB(8)) {
		hp->io_tlb_shift = 13;
		hp->io_tlb_ps = 1;
	} else {
		hp->io_tlb_shift = 12;
		hp->io_tlb_ps = 0;
	}
	hp->io_page_size = 1 << hp->io_tlb_shift;
	hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;

	hp->iova_base = HP_ZX1_IOVA_BASE;
	hp->gart_size = HP_ZX1_GART_SIZE;
	hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - hp->gart_size;

	hp->gatt_entries = hp->gart_size / hp->io_page_size;
	hp->io_pdir_size = (HP_ZX1_IOVA_SIZE / hp->io_page_size) * sizeof(u64);

	return 0;
}

static int __init
hp_zx1_ioc_init (u64 hpa)
{
	struct _hp_private *hp = &hp_private;

	hp->ioc_regs = ioremap(hpa, 1024);
	if (!hp->ioc_regs)
		return -ENOMEM;

	/*
	 * If the IOTLB is currently disabled, we can take it over.
	 * Otherwise, we have to share with sba_iommu.
	 */
	hp->io_pdir_owner = (readq(hp->ioc_regs+HP_ZX1_IBASE) & 0x1) == 0;

	if (hp->io_pdir_owner)
		return hp_zx1_ioc_owner();

	return hp_zx1_ioc_shared();
}

static int
hp_zx1_lba_find_capability (volatile u8 __iomem *hpa, int cap)
{
	u16 status;
	u8 pos, id;
	int ttl = 48;

	status = readw(hpa+PCI_STATUS);
	if (!(status & PCI_STATUS_CAP_LIST))
		return 0;
	pos = readb(hpa+PCI_CAPABILITY_LIST);
	while (ttl-- && pos >= 0x40) {
		pos &= ~3;
		id = readb(hpa+pos+PCI_CAP_LIST_ID);
		if (id == 0xff)
			break;
		if (id == cap)
			return pos;
		pos = readb(hpa+pos+PCI_CAP_LIST_NEXT);
	}
	return 0;
}

static int __init
hp_zx1_lba_init (u64 hpa)
{
	struct _hp_private *hp = &hp_private;
	int cap;

	hp->lba_regs = ioremap(hpa, 256);
	if (!hp->lba_regs)
		return -ENOMEM;

	hp->lba_cap_offset = hp_zx1_lba_find_capability(hp->lba_regs, PCI_CAP_ID_AGP);

	cap = readl(hp->lba_regs+hp->lba_cap_offset) & 0xff;
	if (cap != PCI_CAP_ID_AGP) {
		printk(KERN_ERR PFX "Invalid capability ID 0x%02x at 0x%x\n",
		       cap, hp->lba_cap_offset);
		iounmap(hp->lba_regs);
		return -ENODEV;
	}

	return 0;
}

static int
hp_zx1_fetch_size(void)
{
	int size;

	size = hp_private.gart_size / MB(1);
	hp_zx1_sizes[0].size = size;
	agp_bridge->current_size = (void *) &hp_zx1_sizes[0];
	return size;
}

static int
hp_zx1_configure (void)
{
	struct _hp_private *hp = &hp_private;

	agp_bridge->gart_bus_addr = hp->gart_base;
	agp_bridge->capndx = hp->lba_cap_offset;
	agp_bridge->mode = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);

	if (hp->io_pdir_owner) {
		writel(virt_to_gart(hp->io_pdir), hp->ioc_regs+HP_ZX1_PDIR_BASE);
		readl(hp->ioc_regs+HP_ZX1_PDIR_BASE);
		writel(hp->io_tlb_ps, hp->ioc_regs+HP_ZX1_TCNFG);
		readl(hp->ioc_regs+HP_ZX1_TCNFG);
		writel((unsigned int)(~(HP_ZX1_IOVA_SIZE-1)), hp->ioc_regs+HP_ZX1_IMASK);
		readl(hp->ioc_regs+HP_ZX1_IMASK);
		writel(hp->iova_base|1, hp->ioc_regs+HP_ZX1_IBASE);
		readl(hp->ioc_regs+HP_ZX1_IBASE);
		writel(hp->iova_base|ilog2(HP_ZX1_IOVA_SIZE), hp->ioc_regs+HP_ZX1_PCOM);
		readl(hp->ioc_regs+HP_ZX1_PCOM);
	}

	return 0;
}

static void
hp_zx1_cleanup (void)
{
	struct _hp_private *hp = &hp_private;

	if (hp->ioc_regs) {
		if (hp->io_pdir_owner) {
			writeq(0, hp->ioc_regs+HP_ZX1_IBASE);
			readq(hp->ioc_regs+HP_ZX1_IBASE);
		}
		iounmap(hp->ioc_regs);
	}
	if (hp->lba_regs)
		iounmap(hp->lba_regs);
}

static void
hp_zx1_tlbflush (struct agp_memory *mem)
{
	struct _hp_private *hp = &hp_private;

	writeq(hp->gart_base | ilog2(hp->gart_size), hp->ioc_regs+HP_ZX1_PCOM);
	readq(hp->ioc_regs+HP_ZX1_PCOM);
}

static int
hp_zx1_create_gatt_table (struct agp_bridge_data *bridge)
{
	struct _hp_private *hp = &hp_private;
	int i;

	if (hp->io_pdir_owner) {
		hp->io_pdir = (u64 *) __get_free_pages(GFP_KERNEL,
						get_order(hp->io_pdir_size));
		if (!hp->io_pdir) {
			printk(KERN_ERR PFX "Couldn't allocate contiguous "
				"memory for I/O PDIR\n");
			hp->gatt = NULL;
			hp->gatt_entries = 0;
			return -ENOMEM;
		}
		memset(hp->io_pdir, 0, hp->io_pdir_size);

		hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
	}

	for (i = 0; i < hp->gatt_entries; i++) {
		hp->gatt[i] = (unsigned long) agp_bridge->scratch_page;
	}

	return 0;
}

static int
hp_zx1_free_gatt_table (struct agp_bridge_data *bridge)
{
	struct _hp_private *hp = &hp_private;

	if (hp->io_pdir_owner)
		free_pages((unsigned long) hp->io_pdir,
			    get_order(hp->io_pdir_size));
	else
		hp->gatt[0] = HP_ZX1_SBA_IOMMU_COOKIE;
	return 0;
}

static int
hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type)
{
	struct _hp_private *hp = &hp_private;
	int i, k;
	off_t j, io_pg_start;
	int io_pg_count;

	if (type != 0 || mem->type != 0) {
		return -EINVAL;
	}

	io_pg_start = hp->io_pages_per_kpage * pg_start;
	io_pg_count = hp->io_pages_per_kpage * mem->page_count;
	if ((io_pg_start + io_pg_count) > hp->gatt_entries) {
		return -EINVAL;
	}

	j = io_pg_start;
	while (j < (io_pg_start + io_pg_count)) {
		if (hp->gatt[j]) {
			return -EBUSY;
		}
		j++;
	}

	if (!mem->is_flushed) {
		global_cache_flush();
		mem->is_flushed = true;
	}

	for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
		unsigned long paddr;

		paddr = mem->memory[i];
		for (k = 0;
		     k < hp->io_pages_per_kpage;
		     k++, j++, paddr += hp->io_page_size) {
			hp->gatt[j] =
				agp_bridge->driver->mask_memory(agp_bridge,
					paddr, type);
		}
	}

	agp_bridge->driver->tlb_flush(mem);
	return 0;
}

static int
hp_zx1_remove_memory (struct agp_memory *mem, off_t pg_start, int type)
{
	struct _hp_private *hp = &hp_private;
	int i, io_pg_start, io_pg_count;

	if (type != 0 || mem->type != 0) {
		return -EINVAL;
	}

	io_pg_start = hp->io_pages_per_kpage * pg_start;
	io_pg_count = hp->io_pages_per_kpage * mem->page_count;
	for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
		hp->gatt[i] = agp_bridge->scratch_page;
	}

	agp_bridge->driver->tlb_flush(mem);
	return 0;
}

static unsigned long
hp_zx1_mask_memory (struct agp_bridge_data *bridge,
	unsigned long addr, int type)
{
	return HP_ZX1_PDIR_VALID_BIT | addr;
}

static void
hp_zx1_enable (struct agp_bridge_data *bridge, u32 mode)
{
	struct _hp_private *hp = &hp_private;
	u32 command;

	command = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
	command = agp_collect_device_status(bridge, mode, command);
	command |= 0x00000100;

	writel(command, hp->lba_regs+hp->lba_cap_offset+PCI_AGP_COMMAND);

	agp_device_command(command, (mode & AGP8X_MODE) != 0);
}

const struct agp_bridge_driver hp_zx1_driver = {
	.owner			= THIS_MODULE,
	.size_type		= FIXED_APER_SIZE,
	.configure		= hp_zx1_configure,
	.fetch_size		= hp_zx1_fetch_size,
	.cleanup		= hp_zx1_cleanup,
	.tlb_flush		= hp_zx1_tlbflush,
	.mask_memory		= hp_zx1_mask_memory,
	.masks			= hp_zx1_masks,
	.agp_enable		= hp_zx1_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= hp_zx1_create_gatt_table,
	.free_gatt_table	= hp_zx1_free_gatt_table,
	.insert_memory		= hp_zx1_insert_memory,
	.remove_memory		= hp_zx1_remove_memory,
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_destroy_page	= agp_generic_destroy_page,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
	.cant_use_aperture	= true,
};

static int __init
hp_zx1_setup (u64 ioc_hpa, u64 lba_hpa)
{
	struct agp_bridge_data *bridge;
	int error = 0;

	error = hp_zx1_ioc_init(ioc_hpa);
	if (error)
		goto fail;

	error = hp_zx1_lba_init(lba_hpa);
	if (error)
		goto fail;

	bridge = agp_alloc_bridge();
	if (!bridge) {
		error = -ENOMEM;
		goto fail;
	}
	bridge->driver = &hp_zx1_driver;

	fake_bridge_dev.vendor = PCI_VENDOR_ID_HP;
	fake_bridge_dev.device = PCI_DEVICE_ID_HP_PCIX_LBA;
	bridge->dev = &fake_bridge_dev;

	error = agp_add_bridge(bridge);
  fail:
	if (error)
		hp_zx1_cleanup();
	return error;
}

static acpi_status __init
zx1_gart_probe (acpi_handle obj, u32 depth, void *context, void **ret)
{
	acpi_handle handle, parent;
	acpi_status status;
	struct acpi_buffer buffer;
	struct acpi_device_info *info;
	u64 lba_hpa, sba_hpa, length;
	int match;

	status = hp_acpi_csr_space(obj, &lba_hpa, &length);
	if (ACPI_FAILURE(status))
		return AE_OK; /* keep looking for another bridge */

	/* Look for an enclosing IOC scope and find its CSR space */
	handle = obj;
	do {
		buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
		status = acpi_get_object_info(handle, &buffer);
		if (ACPI_SUCCESS(status)) {
			/* TBD check _CID also */
			info = buffer.pointer;
			info->hardware_id.value[sizeof(info->hardware_id)-1] = '\0';
			match = (strcmp(info->hardware_id.value, "HWP0001") == 0);
			kfree(info);
			if (match) {
				status = hp_acpi_csr_space(handle, &sba_hpa, &length);
				if (ACPI_SUCCESS(status))
					break;
				else {
					printk(KERN_ERR PFX "Detected HP ZX1 "
					       "AGP LBA but no IOC.\n");
					return AE_OK;
				}
			}
		}

		status = acpi_get_parent(handle, &parent);
		handle = parent;
	} while (ACPI_SUCCESS(status));

	if (hp_zx1_setup(sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa))
		return AE_OK;

	printk(KERN_INFO PFX "Detected HP ZX1 %s AGP chipset (ioc=%lx, lba=%lx)\n",
		(char *) context, sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa);

	hp_zx1_gart_found = 1;
	return AE_CTRL_TERMINATE; /* we only support one bridge; quit looking */
}

static int __init
agp_hp_init (void)
{
	if (agp_off)
		return -EINVAL;

	acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003", NULL);
	if (hp_zx1_gart_found)
		return 0;

	acpi_get_devices("HWP0007", zx1_gart_probe, "HWP0007", NULL);
	if (hp_zx1_gart_found)
		return 0;

	return -ENODEV;
}

static void __exit
agp_hp_cleanup (void)
{
}

module_init(agp_hp_init);
module_exit(agp_hp_cleanup);

MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* HP zx1 AGPGART routines.
	3	*
	4	* (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
	5	* Bjorn Helgaas <bjorn.helgaas@hp.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/acpi.h>
	13	#include <linux/module.h>
	14	#include <linux/pci.h>
	15	#include <linux/init.h>
	16	#include <linux/agp_backend.h>
e57aa839	17	#include <linux/log2.h>
1da177e4 LT	18
	19	#include <asm/acpi-ext.h>
	20
	21	#include "agp.h"
	22
1da177e4 LT	23	#define HP_ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */
	24
	25	/* HP ZX1 IOC registers */
	26	#define HP_ZX1_IBASE 0x300
	27	#define HP_ZX1_IMASK 0x308
	28	#define HP_ZX1_PCOM 0x310
	29	#define HP_ZX1_TCNFG 0x318
	30	#define HP_ZX1_PDIR_BASE 0x320
	31
	32	#define HP_ZX1_IOVA_BASE GB(1UL)
	33	#define HP_ZX1_IOVA_SIZE GB(1UL)
	34	#define HP_ZX1_GART_SIZE (HP_ZX1_IOVA_SIZE / 2)
	35	#define HP_ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
	36
	37	#define HP_ZX1_PDIR_VALID_BIT 0x8000000000000000UL
	38	#define HP_ZX1_IOVA_TO_PDIR(va) ((va - hp_private.iova_base) >> hp_private.io_tlb_shift)
	39
	40	#define AGP8X_MODE_BIT 3
	41	#define AGP8X_MODE (1 << AGP8X_MODE_BIT)
	42
	43	/* AGP bridge need not be PCI device, but DRM thinks it is. */
	44	static struct pci_dev fake_bridge_dev;
	45
	46	static int hp_zx1_gart_found;
	47
	48	static struct aper_size_info_fixed hp_zx1_sizes[] =
	49	{
	50	{0, 0, 0}, /* filled in by hp_zx1_fetch_size() */
	51	};
	52
	53	static struct gatt_mask hp_zx1_masks[] =
	54	{
	55	{.mask = HP_ZX1_PDIR_VALID_BIT, .type = 0}
	56	};
	57
	58	static struct _hp_private {
	59	volatile u8 __iomem *ioc_regs;
	60	volatile u8 __iomem *lba_regs;
	61	int lba_cap_offset;
	62	u64 *io_pdir; // PDIR for entire IOVA
	63	u64 *gatt; // PDIR just for GART (subset of above)
	64	u64 gatt_entries;
	65	u64 iova_base;
	66	u64 gart_base;
	67	u64 gart_size;
	68	u64 io_pdir_size;
	69	int io_pdir_owner; // do we own it, or share it with sba_iommu?
	70	int io_page_size;
	71	int io_tlb_shift;
	72	int io_tlb_ps; // IOC ps config
	73	int io_pages_per_kpage;
	74	} hp_private;
	75
	76	static int __init hp_zx1_ioc_shared(void)
	77	{
	78	struct _hp_private *hp = &hp_private;
	79
	80	printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR shared with sba_iommu\n");
	81
	82	/*
	83	* IOC already configured by sba_iommu module; just use
	84	* its setup. We assume:
6a92a4e0 DJ	85	* - IOVA space is 1Gb in size
6a92a4e0 DJ	86	* - first 512Mb is IOMMU, second 512Mb is GART
1da177e4 LT	87	*/
	88	hp->io_tlb_ps = readq(hp->ioc_regs+HP_ZX1_TCNFG);
	89	switch (hp->io_tlb_ps) {
	90	case 0: hp->io_tlb_shift = 12; break;
	91	case 1: hp->io_tlb_shift = 13; break;
	92	case 2: hp->io_tlb_shift = 14; break;
	93	case 3: hp->io_tlb_shift = 16; break;
	94	default:
	95	printk(KERN_ERR PFX "Invalid IOTLB page size "
	96	"configuration 0x%x\n", hp->io_tlb_ps);
	97	hp->gatt = NULL;
	98	hp->gatt_entries = 0;
	99	return -ENODEV;
	100	}
	101	hp->io_page_size = 1 << hp->io_tlb_shift;
	102	hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
	103
	104	hp->iova_base = readq(hp->ioc_regs+HP_ZX1_IBASE) & ~0x1;
	105	hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - HP_ZX1_GART_SIZE;
	106
	107	hp->gart_size = HP_ZX1_GART_SIZE;
	108	hp->gatt_entries = hp->gart_size / hp->io_page_size;
	109
07eee78e	110	hp->io_pdir = gart_to_virt(readq(hp->ioc_regs+HP_ZX1_PDIR_BASE));
1da177e4 LT	111	hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
	112
	113	if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) {
	114	/* Normal case when no AGP device in system */
6a92a4e0	115	hp->gatt = NULL;
1da177e4 LT	116	hp->gatt_entries = 0;
	117	printk(KERN_ERR PFX "No reserved IO PDIR entry found; "
	118	"GART disabled\n");
	119	return -ENODEV;
	120	}
	121
	122	return 0;
	123	}
	124
	125	static int __init
	126	hp_zx1_ioc_owner (void)
	127	{
	128	struct _hp_private *hp = &hp_private;
	129
	130	printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR dedicated to GART\n");
	131
	132	/*
	133	* Select an IOV page size no larger than system page size.
	134	*/
	135	if (PAGE_SIZE >= KB(64)) {
	136	hp->io_tlb_shift = 16;
	137	hp->io_tlb_ps = 3;
	138	} else if (PAGE_SIZE >= KB(16)) {
	139	hp->io_tlb_shift = 14;
	140	hp->io_tlb_ps = 2;
	141	} else if (PAGE_SIZE >= KB(8)) {
	142	hp->io_tlb_shift = 13;
	143	hp->io_tlb_ps = 1;
	144	} else {
	145	hp->io_tlb_shift = 12;
	146	hp->io_tlb_ps = 0;
	147	}
	148	hp->io_page_size = 1 << hp->io_tlb_shift;
	149	hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
	150
	151	hp->iova_base = HP_ZX1_IOVA_BASE;
	152	hp->gart_size = HP_ZX1_GART_SIZE;
	153	hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - hp->gart_size;
	154
	155	hp->gatt_entries = hp->gart_size / hp->io_page_size;
	156	hp->io_pdir_size = (HP_ZX1_IOVA_SIZE / hp->io_page_size) * sizeof(u64);
	157
	158	return 0;
	159	}
	160
	161	static int __init
	162	hp_zx1_ioc_init (u64 hpa)
	163	{
	164	struct _hp_private *hp = &hp_private;
	165
	166	hp->ioc_regs = ioremap(hpa, 1024);
	167	if (!hp->ioc_regs)
	168	return -ENOMEM;
	169
	170	/*
	171	* If the IOTLB is currently disabled, we can take it over.
	172	* Otherwise, we have to share with sba_iommu.
	173	*/
	174	hp->io_pdir_owner = (readq(hp->ioc_regs+HP_ZX1_IBASE) & 0x1) == 0;
	175
	176	if (hp->io_pdir_owner)
	177	return hp_zx1_ioc_owner();
	178
	179	return hp_zx1_ioc_shared();
180	}
181
182	static int
183	hp_zx1_lba_find_capability (volatile u8 __iomem *hpa, int cap)
184	{
185	u16 status;
186	u8 pos, id;
187	int ttl = 48;
188
189	status = readw(hpa+PCI_STATUS);
190	if (!(status & PCI_STATUS_CAP_LIST))
191	return 0;
192	pos = readb(hpa+PCI_CAPABILITY_LIST);
193	while (ttl-- && pos >= 0x40) {
194	pos &= ~3;
195	id = readb(hpa+pos+PCI_CAP_LIST_ID);
196	if (id == 0xff)
197	break;
198	if (id == cap)
199	return pos;
200	pos = readb(hpa+pos+PCI_CAP_LIST_NEXT);
201	}
202	return 0;
203	}
204
205	static int __init
206	hp_zx1_lba_init (u64 hpa)
207	{
208	struct _hp_private *hp = &hp_private;
209	int cap;
210
211	hp->lba_regs = ioremap(hpa, 256);
212	if (!hp->lba_regs)
213	return -ENOMEM;
214
215	hp->lba_cap_offset = hp_zx1_lba_find_capability(hp->lba_regs, PCI_CAP_ID_AGP);
216
217	cap = readl(hp->lba_regs+hp->lba_cap_offset) & 0xff;
218	if (cap != PCI_CAP_ID_AGP) {
219	printk(KERN_ERR PFX "Invalid capability ID 0x%02x at 0x%x\n",
220	cap, hp->lba_cap_offset);
5bdbc7dc	221	iounmap(hp->lba_regs);
1da177e4 LT	222	return -ENODEV;
	223	}
	224
	225	return 0;
	226	}
	227
	228	static int
	229	hp_zx1_fetch_size(void)
	230	{
	231	int size;
	232
	233	size = hp_private.gart_size / MB(1);
	234	hp_zx1_sizes[0].size = size;
	235	agp_bridge->current_size = (void *) &hp_zx1_sizes[0];
	236	return size;
	237	}
	238
	239	static int
	240	hp_zx1_configure (void)
	241	{
	242	struct _hp_private *hp = &hp_private;
	243
	244	agp_bridge->gart_bus_addr = hp->gart_base;
	245	agp_bridge->capndx = hp->lba_cap_offset;
	246	agp_bridge->mode = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
	247
	248	if (hp->io_pdir_owner) {
07eee78e	249	writel(virt_to_gart(hp->io_pdir), hp->ioc_regs+HP_ZX1_PDIR_BASE);
1da177e4 LT	250	readl(hp->ioc_regs+HP_ZX1_PDIR_BASE);
	251	writel(hp->io_tlb_ps, hp->ioc_regs+HP_ZX1_TCNFG);
	252	readl(hp->ioc_regs+HP_ZX1_TCNFG);
24b8e0cc	253	writel((unsigned int)(~(HP_ZX1_IOVA_SIZE-1)), hp->ioc_regs+HP_ZX1_IMASK);
1da177e4 LT	254	readl(hp->ioc_regs+HP_ZX1_IMASK);
	255	writel(hp->iova_base\|1, hp->ioc_regs+HP_ZX1_IBASE);
	256	readl(hp->ioc_regs+HP_ZX1_IBASE);
e57aa839	257	writel(hp->iova_base\|ilog2(HP_ZX1_IOVA_SIZE), hp->ioc_regs+HP_ZX1_PCOM);
1da177e4 LT	258	readl(hp->ioc_regs+HP_ZX1_PCOM);
	259	}
	260
	261	return 0;
	262	}
	263
	264	static void
	265	hp_zx1_cleanup (void)
	266	{
	267	struct _hp_private *hp = &hp_private;
	268
	269	if (hp->ioc_regs) {
	270	if (hp->io_pdir_owner) {
	271	writeq(0, hp->ioc_regs+HP_ZX1_IBASE);
	272	readq(hp->ioc_regs+HP_ZX1_IBASE);
	273	}
	274	iounmap(hp->ioc_regs);
	275	}
	276	if (hp->lba_regs)
	277	iounmap(hp->lba_regs);
	278	}
	279
	280	static void
	281	hp_zx1_tlbflush (struct agp_memory *mem)
	282	{
	283	struct _hp_private *hp = &hp_private;
	284
e57aa839	285	writeq(hp->gart_base \| ilog2(hp->gart_size), hp->ioc_regs+HP_ZX1_PCOM);
1da177e4 LT	286	readq(hp->ioc_regs+HP_ZX1_PCOM);
	287	}
	288
	289	static int
	290	hp_zx1_create_gatt_table (struct agp_bridge_data *bridge)
	291	{
	292	struct _hp_private *hp = &hp_private;
	293	int i;
	294
	295	if (hp->io_pdir_owner) {
	296	hp->io_pdir = (u64 *) __get_free_pages(GFP_KERNEL,
	297	get_order(hp->io_pdir_size));
	298	if (!hp->io_pdir) {
	299	printk(KERN_ERR PFX "Couldn't allocate contiguous "
	300	"memory for I/O PDIR\n");
	301	hp->gatt = NULL;
	302	hp->gatt_entries = 0;
	303	return -ENOMEM;
	304	}
	305	memset(hp->io_pdir, 0, hp->io_pdir_size);
	306
	307	hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
	308	}
	309
	310	for (i = 0; i < hp->gatt_entries; i++) {
	311	hp->gatt[i] = (unsigned long) agp_bridge->scratch_page;
	312	}
	313
	314	return 0;
	315	}
	316
	317	static int
	318	hp_zx1_free_gatt_table (struct agp_bridge_data *bridge)
	319	{
	320	struct _hp_private *hp = &hp_private;
	321
	322	if (hp->io_pdir_owner)
	323	free_pages((unsigned long) hp->io_pdir,
	324	get_order(hp->io_pdir_size));
	325	else
	326	hp->gatt[0] = HP_ZX1_SBA_IOMMU_COOKIE;
	327	return 0;
	328	}
	329
	330	static int
	331	hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type)
	332	{
	333	struct _hp_private *hp = &hp_private;
	334	int i, k;
	335	off_t j, io_pg_start;
	336	int io_pg_count;
	337
	338	if (type != 0 \|\| mem->type != 0) {
	339	return -EINVAL;
	340	}
	341
	342	io_pg_start = hp->io_pages_per_kpage * pg_start;
	343	io_pg_count = hp->io_pages_per_kpage * mem->page_count;
	344	if ((io_pg_start + io_pg_count) > hp->gatt_entries) {
	345	return -EINVAL;
	346	}
	347
	348	j = io_pg_start;
	349	while (j < (io_pg_start + io_pg_count)) {
350	if (hp->gatt[j]) {
351	return -EBUSY;
352	}
353	j++;
354	}
355
c7258012	356	if (!mem->is_flushed) {
1da177e4	357	global_cache_flush();
c7258012	358	mem->is_flushed = true;
1da177e4 LT	359	}
	360
	361	for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
	362	unsigned long paddr;
	363
	364	paddr = mem->memory[i];
	365	for (k = 0;
	366	k < hp->io_pages_per_kpage;
	367	k++, j++, paddr += hp->io_page_size) {
	368	hp->gatt[j] =
	369	agp_bridge->driver->mask_memory(agp_bridge,
	370	paddr, type);
	371	}
	372	}
	373
	374	agp_bridge->driver->tlb_flush(mem);
	375	return 0;
	376	}
	377
	378	static int
	379	hp_zx1_remove_memory (struct agp_memory *mem, off_t pg_start, int type)
	380	{
	381	struct _hp_private *hp = &hp_private;
	382	int i, io_pg_start, io_pg_count;
	383
	384	if (type != 0 \|\| mem->type != 0) {
	385	return -EINVAL;
	386	}
	387
	388	io_pg_start = hp->io_pages_per_kpage * pg_start;
	389	io_pg_count = hp->io_pages_per_kpage * mem->page_count;
	390	for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
	391	hp->gatt[i] = agp_bridge->scratch_page;
	392	}
	393
	394	agp_bridge->driver->tlb_flush(mem);
	395	return 0;
	396	}
	397
	398	static unsigned long
	399	hp_zx1_mask_memory (struct agp_bridge_data *bridge,
	400	unsigned long addr, int type)
	401	{
	402	return HP_ZX1_PDIR_VALID_BIT \| addr;
	403	}
	404
	405	static void
	406	hp_zx1_enable (struct agp_bridge_data *bridge, u32 mode)
	407	{
	408	struct _hp_private *hp = &hp_private;
	409	u32 command;
	410
	411	command = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
	412	command = agp_collect_device_status(bridge, mode, command);
	413	command \|= 0x00000100;
	414
	415	writel(command, hp->lba_regs+hp->lba_cap_offset+PCI_AGP_COMMAND);
	416
	417	agp_device_command(command, (mode & AGP8X_MODE) != 0);
	418	}
	419
e047d1cf	420	const struct agp_bridge_driver hp_zx1_driver = {
1da177e4 LT	421	.owner = THIS_MODULE,
	422	.size_type = FIXED_APER_SIZE,
	423	.configure = hp_zx1_configure,
	424	.fetch_size = hp_zx1_fetch_size,
	425	.cleanup = hp_zx1_cleanup,
	426	.tlb_flush = hp_zx1_tlbflush,
	427	.mask_memory = hp_zx1_mask_memory,
	428	.masks = hp_zx1_masks,
	429	.agp_enable = hp_zx1_enable,
	430	.cache_flush = global_cache_flush,
	431	.create_gatt_table = hp_zx1_create_gatt_table,
	432	.free_gatt_table = hp_zx1_free_gatt_table,
	433	.insert_memory = hp_zx1_insert_memory,
	434	.remove_memory = hp_zx1_remove_memory,
	435	.alloc_by_type = agp_generic_alloc_by_type,
	436	.free_by_type = agp_generic_free_by_type,
	437	.agp_alloc_page = agp_generic_alloc_page,
	438	.agp_destroy_page = agp_generic_destroy_page,
a030ce44	439	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
c7258012	440	.cant_use_aperture = true,
1da177e4 LT	441	};
	442
	443	static int __init
	444	hp_zx1_setup (u64 ioc_hpa, u64 lba_hpa)
	445	{
	446	struct agp_bridge_data *bridge;
	447	int error = 0;
	448
	449	error = hp_zx1_ioc_init(ioc_hpa);
	450	if (error)
	451	goto fail;
	452
	453	error = hp_zx1_lba_init(lba_hpa);
	454	if (error)
	455	goto fail;
	456
	457	bridge = agp_alloc_bridge();
	458	if (!bridge) {
	459	error = -ENOMEM;
	460	goto fail;
	461	}
	462	bridge->driver = &hp_zx1_driver;
	463
	464	fake_bridge_dev.vendor = PCI_VENDOR_ID_HP;
	465	fake_bridge_dev.device = PCI_DEVICE_ID_HP_PCIX_LBA;
	466	bridge->dev = &fake_bridge_dev;
	467
	468	error = agp_add_bridge(bridge);
	469	fail:
	470	if (error)
	471	hp_zx1_cleanup();
	472	return error;
	473	}
	474
	475	static acpi_status __init
	476	zx1_gart_probe (acpi_handle obj, u32 depth, void context, void *ret)
	477	{
	478	acpi_handle handle, parent;
	479	acpi_status status;
	480	struct acpi_buffer buffer;
	481	struct acpi_device_info *info;
	482	u64 lba_hpa, sba_hpa, length;
	483	int match;
	484
	485	status = hp_acpi_csr_space(obj, &lba_hpa, &length);
	486	if (ACPI_FAILURE(status))
	487	return AE_OK; /* keep looking for another bridge */
	488
	489	/* Look for an enclosing IOC scope and find its CSR space */
	490	handle = obj;
	491	do {
	492	buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
	493	status = acpi_get_object_info(handle, &buffer);
	494	if (ACPI_SUCCESS(status)) {
	495	/* TBD check _CID also */
	496	info = buffer.pointer;
	497	info->hardware_id.value[sizeof(info->hardware_id)-1] = '\0';
	498	match = (strcmp(info->hardware_id.value, "HWP0001") == 0);
7f048801	499	kfree(info);
1da177e4 LT	500	if (match) {
	501	status = hp_acpi_csr_space(handle, &sba_hpa, &length);
	502	if (ACPI_SUCCESS(status))
	503	break;
	504	else {
	505	printk(KERN_ERR PFX "Detected HP ZX1 "
	506	"AGP LBA but no IOC.\n");
	507	return AE_OK;
	508	}
	509	}
	510	}
	511
	512	status = acpi_get_parent(handle, &parent);
	513	handle = parent;
	514	} while (ACPI_SUCCESS(status));
	515
	516	if (hp_zx1_setup(sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa))
	517	return AE_OK;
	518
	519	printk(KERN_INFO PFX "Detected HP ZX1 %s AGP chipset (ioc=%lx, lba=%lx)\n",
	520	(char *) context, sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa);
	521
	522	hp_zx1_gart_found = 1;
	523	return AE_CTRL_TERMINATE; /* we only support one bridge; quit looking */
	524	}
	525
	526	static int __init
	527	agp_hp_init (void)
	528	{
	529	if (agp_off)
	530	return -EINVAL;
	531
	532	acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003", NULL);
	533	if (hp_zx1_gart_found)
	534	return 0;
	535
	536	acpi_get_devices("HWP0007", zx1_gart_probe, "HWP0007", NULL);
	537	if (hp_zx1_gart_found)
	538	return 0;
	539
	540	return -ENODEV;
	541	}
	542
	543	static void __exit
	544	agp_hp_cleanup (void)
	545	{
	546	}
	547
	548	module_init(agp_hp_init);
	549	module_exit(agp_hp_cleanup);
	550
	551	MODULE_LICENSE("GPL and additional rights");