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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
21 | #include <linux/blkdev.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/fs.h> | |
24 | #include <linux/genhd.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/moduleparam.h> | |
33 | #include <linux/pci.h> | |
be7b6275 | 34 | #include <linux/poison.h> |
b60503ba MW |
35 | #include <linux/sched.h> |
36 | #include <linux/slab.h> | |
37 | #include <linux/types.h> | |
38 | #include <linux/version.h> | |
39 | ||
40 | #define NVME_Q_DEPTH 1024 | |
41 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
42 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
43 | #define NVME_MINORS 64 | |
e85248e5 MW |
44 | #define IO_TIMEOUT (5 * HZ) |
45 | #define ADMIN_TIMEOUT (60 * HZ) | |
b60503ba MW |
46 | |
47 | static int nvme_major; | |
48 | module_param(nvme_major, int, 0); | |
49 | ||
58ffacb5 MW |
50 | static int use_threaded_interrupts; |
51 | module_param(use_threaded_interrupts, int, 0); | |
52 | ||
b60503ba MW |
53 | /* |
54 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
55 | */ | |
56 | struct nvme_dev { | |
b60503ba MW |
57 | struct nvme_queue **queues; |
58 | u32 __iomem *dbs; | |
59 | struct pci_dev *pci_dev; | |
60 | int instance; | |
61 | int queue_count; | |
62 | u32 ctrl_config; | |
63 | struct msix_entry *entry; | |
64 | struct nvme_bar __iomem *bar; | |
65 | struct list_head namespaces; | |
51814232 MW |
66 | char serial[20]; |
67 | char model[40]; | |
68 | char firmware_rev[8]; | |
b60503ba MW |
69 | }; |
70 | ||
71 | /* | |
72 | * An NVM Express namespace is equivalent to a SCSI LUN | |
73 | */ | |
74 | struct nvme_ns { | |
75 | struct list_head list; | |
76 | ||
77 | struct nvme_dev *dev; | |
78 | struct request_queue *queue; | |
79 | struct gendisk *disk; | |
80 | ||
81 | int ns_id; | |
82 | int lba_shift; | |
83 | }; | |
84 | ||
85 | /* | |
86 | * An NVM Express queue. Each device has at least two (one for admin | |
87 | * commands and one for I/O commands). | |
88 | */ | |
89 | struct nvme_queue { | |
90 | struct device *q_dmadev; | |
91 | spinlock_t q_lock; | |
92 | struct nvme_command *sq_cmds; | |
93 | volatile struct nvme_completion *cqes; | |
94 | dma_addr_t sq_dma_addr; | |
95 | dma_addr_t cq_dma_addr; | |
96 | wait_queue_head_t sq_full; | |
97 | struct bio_list sq_cong; | |
98 | u32 __iomem *q_db; | |
99 | u16 q_depth; | |
100 | u16 cq_vector; | |
101 | u16 sq_head; | |
102 | u16 sq_tail; | |
103 | u16 cq_head; | |
82123460 | 104 | u16 cq_phase; |
b60503ba MW |
105 | unsigned long cmdid_data[]; |
106 | }; | |
107 | ||
108 | /* | |
109 | * Check we didin't inadvertently grow the command struct | |
110 | */ | |
111 | static inline void _nvme_check_size(void) | |
112 | { | |
113 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
114 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
115 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
116 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
117 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
118 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); | |
119 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
120 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
121 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
122 | } | |
123 | ||
e85248e5 MW |
124 | struct nvme_cmd_info { |
125 | unsigned long ctx; | |
126 | unsigned long timeout; | |
127 | }; | |
128 | ||
129 | static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq) | |
130 | { | |
131 | return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)]; | |
132 | } | |
133 | ||
b60503ba MW |
134 | /** |
135 | * alloc_cmdid - Allocate a Command ID | |
136 | * @param nvmeq The queue that will be used for this command | |
137 | * @param ctx A pointer that will be passed to the handler | |
138 | * @param handler The ID of the handler to call | |
139 | * | |
140 | * Allocate a Command ID for a queue. The data passed in will | |
141 | * be passed to the completion handler. This is implemented by using | |
142 | * the bottom two bits of the ctx pointer to store the handler ID. | |
143 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
144 | * We can change this if it becomes a problem. | |
145 | */ | |
e85248e5 MW |
146 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler, |
147 | unsigned timeout) | |
b60503ba MW |
148 | { |
149 | int depth = nvmeq->q_depth; | |
e85248e5 | 150 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba MW |
151 | int cmdid; |
152 | ||
153 | BUG_ON((unsigned long)ctx & 3); | |
154 | ||
155 | do { | |
156 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
157 | if (cmdid >= depth) | |
158 | return -EBUSY; | |
159 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
160 | ||
e85248e5 MW |
161 | info[cmdid].ctx = (unsigned long)ctx | handler; |
162 | info[cmdid].timeout = jiffies + timeout; | |
b60503ba MW |
163 | return cmdid; |
164 | } | |
165 | ||
166 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
e85248e5 | 167 | int handler, unsigned timeout) |
b60503ba MW |
168 | { |
169 | int cmdid; | |
170 | wait_event_killable(nvmeq->sq_full, | |
e85248e5 | 171 | (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0); |
b60503ba MW |
172 | return (cmdid < 0) ? -EINTR : cmdid; |
173 | } | |
174 | ||
175 | /* If you need more than four handlers, you'll need to change how | |
be7b6275 MW |
176 | * alloc_cmdid and nvme_process_cq work. Consider using a special |
177 | * CMD_CTX value instead, if that works for your situation. | |
b60503ba MW |
178 | */ |
179 | enum { | |
180 | sync_completion_id = 0, | |
181 | bio_completion_id, | |
182 | }; | |
183 | ||
be7b6275 MW |
184 | #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id) |
185 | #define CMD_CTX_CANCELLED (0x2008 + CMD_CTX_BASE) | |
b36235df | 186 | #define CMD_CTX_COMPLETED (0x2010 + CMD_CTX_BASE) |
48e3d398 | 187 | #define CMD_CTX_INVALID (0x2014 + CMD_CTX_BASE) |
be7b6275 | 188 | |
b60503ba MW |
189 | static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid) |
190 | { | |
191 | unsigned long data; | |
e85248e5 | 192 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba | 193 | |
e85248e5 | 194 | if (cmdid >= nvmeq->q_depth) |
48e3d398 | 195 | return CMD_CTX_INVALID; |
e85248e5 MW |
196 | data = info[cmdid].ctx; |
197 | info[cmdid].ctx = CMD_CTX_COMPLETED; | |
b60503ba MW |
198 | clear_bit(cmdid, nvmeq->cmdid_data); |
199 | wake_up(&nvmeq->sq_full); | |
200 | return data; | |
201 | } | |
202 | ||
be7b6275 | 203 | static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid) |
3c0cf138 | 204 | { |
e85248e5 MW |
205 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
206 | info[cmdid].ctx = CMD_CTX_CANCELLED; | |
3c0cf138 MW |
207 | } |
208 | ||
b60503ba MW |
209 | static struct nvme_queue *get_nvmeq(struct nvme_ns *ns) |
210 | { | |
1b23484b MW |
211 | int qid, cpu = get_cpu(); |
212 | if (cpu < ns->dev->queue_count) | |
213 | qid = cpu + 1; | |
214 | else | |
215 | qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1; | |
216 | return ns->dev->queues[qid]; | |
b60503ba MW |
217 | } |
218 | ||
219 | static void put_nvmeq(struct nvme_queue *nvmeq) | |
220 | { | |
1b23484b | 221 | put_cpu(); |
b60503ba MW |
222 | } |
223 | ||
224 | /** | |
225 | * nvme_submit_cmd: Copy a command into a queue and ring the doorbell | |
226 | * @nvmeq: The queue to use | |
227 | * @cmd: The command to send | |
228 | * | |
229 | * Safe to use from interrupt context | |
230 | */ | |
231 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
232 | { | |
233 | unsigned long flags; | |
234 | u16 tail; | |
235 | /* XXX: Need to check tail isn't going to overrun head */ | |
236 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
237 | tail = nvmeq->sq_tail; | |
238 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
239 | writel(tail, nvmeq->q_db); | |
240 | if (++tail == nvmeq->q_depth) | |
241 | tail = 0; | |
242 | nvmeq->sq_tail = tail; | |
243 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
248 | struct nvme_req_info { | |
249 | struct bio *bio; | |
250 | int nents; | |
251 | struct scatterlist sg[0]; | |
252 | }; | |
253 | ||
254 | /* XXX: use a mempool */ | |
255 | static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp) | |
256 | { | |
257 | return kmalloc(sizeof(struct nvme_req_info) + | |
258 | sizeof(struct scatterlist) * nseg, gfp); | |
259 | } | |
260 | ||
261 | static void free_info(struct nvme_req_info *info) | |
262 | { | |
263 | kfree(info); | |
264 | } | |
265 | ||
266 | static void bio_completion(struct nvme_queue *nvmeq, void *ctx, | |
267 | struct nvme_completion *cqe) | |
268 | { | |
269 | struct nvme_req_info *info = ctx; | |
270 | struct bio *bio = info->bio; | |
271 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
272 | ||
273 | dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents, | |
274 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
275 | free_info(info); | |
276 | bio_endio(bio, status ? -EIO : 0); | |
277 | } | |
278 | ||
ff22b54f MW |
279 | /* length is in bytes */ |
280 | static void nvme_setup_prps(struct nvme_common_command *cmd, | |
281 | struct scatterlist *sg, int length) | |
282 | { | |
283 | int dma_len = sg_dma_len(sg); | |
284 | u64 dma_addr = sg_dma_address(sg); | |
285 | int offset = offset_in_page(dma_addr); | |
286 | ||
287 | cmd->prp1 = cpu_to_le64(dma_addr); | |
288 | length -= (PAGE_SIZE - offset); | |
289 | if (length <= 0) | |
290 | return; | |
291 | ||
292 | dma_len -= (PAGE_SIZE - offset); | |
293 | if (dma_len) { | |
294 | dma_addr += (PAGE_SIZE - offset); | |
295 | } else { | |
296 | sg = sg_next(sg); | |
297 | dma_addr = sg_dma_address(sg); | |
298 | dma_len = sg_dma_len(sg); | |
299 | } | |
300 | ||
301 | if (length <= PAGE_SIZE) { | |
302 | cmd->prp2 = cpu_to_le64(dma_addr); | |
303 | return; | |
304 | } | |
305 | ||
306 | /* XXX: support PRP lists */ | |
307 | } | |
308 | ||
b60503ba MW |
309 | static int nvme_map_bio(struct device *dev, struct nvme_req_info *info, |
310 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) | |
311 | { | |
312 | struct bio_vec *bvec; | |
313 | struct scatterlist *sg = info->sg; | |
314 | int i, nsegs; | |
315 | ||
316 | sg_init_table(sg, psegs); | |
317 | bio_for_each_segment(bvec, bio, i) { | |
318 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset); | |
319 | /* XXX: handle non-mergable here */ | |
320 | nsegs++; | |
321 | } | |
322 | info->nents = nsegs; | |
323 | ||
324 | return dma_map_sg(dev, info->sg, info->nents, dma_dir); | |
325 | } | |
326 | ||
327 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
328 | struct bio *bio) | |
329 | { | |
ff22b54f | 330 | struct nvme_command *cmnd; |
b60503ba MW |
331 | struct nvme_req_info *info; |
332 | enum dma_data_direction dma_dir; | |
333 | int cmdid; | |
334 | u16 control; | |
335 | u32 dsmgmt; | |
336 | unsigned long flags; | |
337 | int psegs = bio_phys_segments(ns->queue, bio); | |
338 | ||
339 | info = alloc_info(psegs, GFP_NOIO); | |
340 | if (!info) | |
341 | goto congestion; | |
342 | info->bio = bio; | |
343 | ||
e85248e5 | 344 | cmdid = alloc_cmdid(nvmeq, info, bio_completion_id, IO_TIMEOUT); |
b60503ba MW |
345 | if (unlikely(cmdid < 0)) |
346 | goto free_info; | |
347 | ||
348 | control = 0; | |
349 | if (bio->bi_rw & REQ_FUA) | |
350 | control |= NVME_RW_FUA; | |
351 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
352 | control |= NVME_RW_LR; | |
353 | ||
354 | dsmgmt = 0; | |
355 | if (bio->bi_rw & REQ_RAHEAD) | |
356 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
357 | ||
358 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
ff22b54f | 359 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 360 | |
b8deb62c | 361 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 362 | if (bio_data_dir(bio)) { |
ff22b54f | 363 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
364 | dma_dir = DMA_TO_DEVICE; |
365 | } else { | |
ff22b54f | 366 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
367 | dma_dir = DMA_FROM_DEVICE; |
368 | } | |
369 | ||
370 | nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs); | |
371 | ||
ff22b54f MW |
372 | cmnd->rw.flags = 1; |
373 | cmnd->rw.command_id = cmdid; | |
374 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
375 | nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size); | |
376 | cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9)); | |
377 | cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1); | |
378 | cmnd->rw.control = cpu_to_le16(control); | |
379 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba MW |
380 | |
381 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
382 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
383 | nvmeq->sq_tail = 0; | |
384 | ||
385 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
386 | ||
387 | return 0; | |
388 | ||
389 | free_info: | |
390 | free_info(info); | |
391 | congestion: | |
392 | return -EBUSY; | |
393 | } | |
394 | ||
395 | /* | |
396 | * NB: return value of non-zero would mean that we were a stacking driver. | |
397 | * make_request must always succeed. | |
398 | */ | |
399 | static int nvme_make_request(struct request_queue *q, struct bio *bio) | |
400 | { | |
401 | struct nvme_ns *ns = q->queuedata; | |
402 | struct nvme_queue *nvmeq = get_nvmeq(ns); | |
403 | ||
404 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { | |
405 | blk_set_queue_congested(q, rw_is_sync(bio->bi_rw)); | |
406 | bio_list_add(&nvmeq->sq_cong, bio); | |
407 | } | |
408 | put_nvmeq(nvmeq); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | struct sync_cmd_info { | |
414 | struct task_struct *task; | |
415 | u32 result; | |
416 | int status; | |
417 | }; | |
418 | ||
419 | static void sync_completion(struct nvme_queue *nvmeq, void *ctx, | |
420 | struct nvme_completion *cqe) | |
421 | { | |
422 | struct sync_cmd_info *cmdinfo = ctx; | |
be7b6275 MW |
423 | if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED) |
424 | return; | |
b36235df MW |
425 | if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) { |
426 | dev_warn(nvmeq->q_dmadev, | |
427 | "completed id %d twice on queue %d\n", | |
428 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
429 | return; | |
430 | } | |
48e3d398 MW |
431 | if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) { |
432 | dev_warn(nvmeq->q_dmadev, | |
433 | "invalid id %d completed on queue %d\n", | |
434 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
435 | return; | |
436 | } | |
b60503ba MW |
437 | cmdinfo->result = le32_to_cpup(&cqe->result); |
438 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
439 | wake_up_process(cmdinfo->task); | |
440 | } | |
441 | ||
442 | typedef void (*completion_fn)(struct nvme_queue *, void *, | |
443 | struct nvme_completion *); | |
444 | ||
445 | static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq) | |
446 | { | |
82123460 | 447 | u16 head, phase; |
b60503ba MW |
448 | |
449 | static const completion_fn completions[4] = { | |
450 | [sync_completion_id] = sync_completion, | |
451 | [bio_completion_id] = bio_completion, | |
452 | }; | |
453 | ||
454 | head = nvmeq->cq_head; | |
82123460 | 455 | phase = nvmeq->cq_phase; |
b60503ba MW |
456 | |
457 | for (;;) { | |
458 | unsigned long data; | |
459 | void *ptr; | |
460 | unsigned char handler; | |
461 | struct nvme_completion cqe = nvmeq->cqes[head]; | |
82123460 | 462 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
463 | break; |
464 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
465 | if (++head == nvmeq->q_depth) { | |
466 | head = 0; | |
82123460 | 467 | phase = !phase; |
b60503ba MW |
468 | } |
469 | ||
470 | data = free_cmdid(nvmeq, cqe.command_id); | |
471 | handler = data & 3; | |
472 | ptr = (void *)(data & ~3UL); | |
473 | completions[handler](nvmeq, ptr, &cqe); | |
474 | } | |
475 | ||
476 | /* If the controller ignores the cq head doorbell and continuously | |
477 | * writes to the queue, it is theoretically possible to wrap around | |
478 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
479 | * requires that 0.1% of your interrupts are handled, so this isn't | |
480 | * a big problem. | |
481 | */ | |
82123460 | 482 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
b60503ba MW |
483 | return IRQ_NONE; |
484 | ||
485 | writel(head, nvmeq->q_db + 1); | |
486 | nvmeq->cq_head = head; | |
82123460 | 487 | nvmeq->cq_phase = phase; |
b60503ba MW |
488 | |
489 | return IRQ_HANDLED; | |
490 | } | |
491 | ||
492 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
493 | { |
494 | irqreturn_t result; | |
495 | struct nvme_queue *nvmeq = data; | |
496 | spin_lock(&nvmeq->q_lock); | |
497 | result = nvme_process_cq(nvmeq); | |
498 | spin_unlock(&nvmeq->q_lock); | |
499 | return result; | |
500 | } | |
501 | ||
502 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
503 | { | |
504 | struct nvme_queue *nvmeq = data; | |
505 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
506 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
507 | return IRQ_NONE; | |
508 | return IRQ_WAKE_THREAD; | |
509 | } | |
510 | ||
3c0cf138 MW |
511 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
512 | { | |
513 | spin_lock_irq(&nvmeq->q_lock); | |
be7b6275 | 514 | cancel_cmdid_data(nvmeq, cmdid); |
3c0cf138 MW |
515 | spin_unlock_irq(&nvmeq->q_lock); |
516 | } | |
517 | ||
b60503ba MW |
518 | /* |
519 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
520 | * if the result is positive, it's an NVM Express status code | |
521 | */ | |
3c0cf138 | 522 | static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, |
e85248e5 | 523 | struct nvme_command *cmd, u32 *result, unsigned timeout) |
b60503ba MW |
524 | { |
525 | int cmdid; | |
526 | struct sync_cmd_info cmdinfo; | |
527 | ||
528 | cmdinfo.task = current; | |
529 | cmdinfo.status = -EINTR; | |
530 | ||
e85248e5 MW |
531 | cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id, |
532 | timeout); | |
b60503ba MW |
533 | if (cmdid < 0) |
534 | return cmdid; | |
535 | cmd->common.command_id = cmdid; | |
536 | ||
3c0cf138 MW |
537 | set_current_state(TASK_KILLABLE); |
538 | nvme_submit_cmd(nvmeq, cmd); | |
b60503ba MW |
539 | schedule(); |
540 | ||
3c0cf138 MW |
541 | if (cmdinfo.status == -EINTR) { |
542 | nvme_abort_command(nvmeq, cmdid); | |
543 | return -EINTR; | |
544 | } | |
545 | ||
b60503ba MW |
546 | if (result) |
547 | *result = cmdinfo.result; | |
548 | ||
549 | return cmdinfo.status; | |
550 | } | |
551 | ||
552 | static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, | |
553 | u32 *result) | |
554 | { | |
e85248e5 | 555 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
556 | } |
557 | ||
558 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
559 | { | |
560 | int status; | |
561 | struct nvme_command c; | |
562 | ||
563 | memset(&c, 0, sizeof(c)); | |
564 | c.delete_queue.opcode = opcode; | |
565 | c.delete_queue.qid = cpu_to_le16(id); | |
566 | ||
567 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
568 | if (status) | |
569 | return -EIO; | |
570 | return 0; | |
571 | } | |
572 | ||
573 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
574 | struct nvme_queue *nvmeq) | |
575 | { | |
576 | int status; | |
577 | struct nvme_command c; | |
578 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
579 | ||
580 | memset(&c, 0, sizeof(c)); | |
581 | c.create_cq.opcode = nvme_admin_create_cq; | |
582 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
583 | c.create_cq.cqid = cpu_to_le16(qid); | |
584 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
585 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
586 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
587 | ||
588 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
589 | if (status) | |
590 | return -EIO; | |
591 | return 0; | |
592 | } | |
593 | ||
594 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
595 | struct nvme_queue *nvmeq) | |
596 | { | |
597 | int status; | |
598 | struct nvme_command c; | |
599 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
600 | ||
601 | memset(&c, 0, sizeof(c)); | |
602 | c.create_sq.opcode = nvme_admin_create_sq; | |
603 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
604 | c.create_sq.sqid = cpu_to_le16(qid); | |
605 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
606 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
607 | c.create_sq.cqid = cpu_to_le16(qid); | |
608 | ||
609 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
610 | if (status) | |
611 | return -EIO; | |
612 | return 0; | |
613 | } | |
614 | ||
615 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
616 | { | |
617 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
618 | } | |
619 | ||
620 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
621 | { | |
622 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
623 | } | |
624 | ||
625 | static void nvme_free_queue(struct nvme_dev *dev, int qid) | |
626 | { | |
627 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
628 | ||
629 | free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq); | |
630 | ||
631 | /* Don't tell the adapter to delete the admin queue */ | |
632 | if (qid) { | |
633 | adapter_delete_sq(dev, qid); | |
634 | adapter_delete_cq(dev, qid); | |
635 | } | |
636 | ||
637 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
638 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
639 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
640 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
641 | kfree(nvmeq); | |
642 | } | |
643 | ||
644 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
645 | int depth, int vector) | |
646 | { | |
647 | struct device *dmadev = &dev->pci_dev->dev; | |
e85248e5 | 648 | unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info)); |
b60503ba MW |
649 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); |
650 | if (!nvmeq) | |
651 | return NULL; | |
652 | ||
653 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
654 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
655 | if (!nvmeq->cqes) | |
656 | goto free_nvmeq; | |
657 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
658 | ||
659 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
660 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
661 | if (!nvmeq->sq_cmds) | |
662 | goto free_cqdma; | |
663 | ||
664 | nvmeq->q_dmadev = dmadev; | |
665 | spin_lock_init(&nvmeq->q_lock); | |
666 | nvmeq->cq_head = 0; | |
82123460 | 667 | nvmeq->cq_phase = 1; |
b60503ba MW |
668 | init_waitqueue_head(&nvmeq->sq_full); |
669 | bio_list_init(&nvmeq->sq_cong); | |
670 | nvmeq->q_db = &dev->dbs[qid * 2]; | |
671 | nvmeq->q_depth = depth; | |
672 | nvmeq->cq_vector = vector; | |
673 | ||
674 | return nvmeq; | |
675 | ||
676 | free_cqdma: | |
677 | dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes, | |
678 | nvmeq->cq_dma_addr); | |
679 | free_nvmeq: | |
680 | kfree(nvmeq); | |
681 | return NULL; | |
682 | } | |
683 | ||
3001082c MW |
684 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
685 | const char *name) | |
686 | { | |
58ffacb5 MW |
687 | if (use_threaded_interrupts) |
688 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
ec6ce618 | 689 | nvme_irq_check, nvme_irq, |
58ffacb5 MW |
690 | IRQF_DISABLED | IRQF_SHARED, |
691 | name, nvmeq); | |
3001082c MW |
692 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
693 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
694 | } | |
695 | ||
b60503ba MW |
696 | static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, |
697 | int qid, int cq_size, int vector) | |
698 | { | |
699 | int result; | |
700 | struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector); | |
701 | ||
3f85d50b MW |
702 | if (!nvmeq) |
703 | return NULL; | |
704 | ||
b60503ba MW |
705 | result = adapter_alloc_cq(dev, qid, nvmeq); |
706 | if (result < 0) | |
707 | goto free_nvmeq; | |
708 | ||
709 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
710 | if (result < 0) | |
711 | goto release_cq; | |
712 | ||
3001082c | 713 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
714 | if (result < 0) |
715 | goto release_sq; | |
716 | ||
717 | return nvmeq; | |
718 | ||
719 | release_sq: | |
720 | adapter_delete_sq(dev, qid); | |
721 | release_cq: | |
722 | adapter_delete_cq(dev, qid); | |
723 | free_nvmeq: | |
724 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
725 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
726 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
727 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
728 | kfree(nvmeq); | |
729 | return NULL; | |
730 | } | |
731 | ||
732 | static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev) | |
733 | { | |
734 | int result; | |
735 | u32 aqa; | |
736 | struct nvme_queue *nvmeq; | |
737 | ||
738 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
739 | ||
740 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
3f85d50b MW |
741 | if (!nvmeq) |
742 | return -ENOMEM; | |
b60503ba MW |
743 | |
744 | aqa = nvmeq->q_depth - 1; | |
745 | aqa |= aqa << 16; | |
746 | ||
747 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
748 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
749 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
750 | ||
5911f200 | 751 | writel(0, &dev->bar->cc); |
b60503ba MW |
752 | writel(aqa, &dev->bar->aqa); |
753 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
754 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
755 | writel(dev->ctrl_config, &dev->bar->cc); | |
756 | ||
757 | while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) { | |
758 | msleep(100); | |
759 | if (fatal_signal_pending(current)) | |
760 | return -EINTR; | |
761 | } | |
762 | ||
3001082c | 763 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
b60503ba MW |
764 | dev->queues[0] = nvmeq; |
765 | return result; | |
766 | } | |
767 | ||
7fc3cdab MW |
768 | static int nvme_map_user_pages(struct nvme_dev *dev, int write, |
769 | unsigned long addr, unsigned length, | |
770 | struct scatterlist **sgp) | |
b60503ba | 771 | { |
36c14ed9 | 772 | int i, err, count, nents, offset; |
7fc3cdab MW |
773 | struct scatterlist *sg; |
774 | struct page **pages; | |
36c14ed9 MW |
775 | |
776 | if (addr & 3) | |
777 | return -EINVAL; | |
7fc3cdab MW |
778 | if (!length) |
779 | return -EINVAL; | |
780 | ||
36c14ed9 | 781 | offset = offset_in_page(addr); |
7fc3cdab MW |
782 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
783 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
36c14ed9 MW |
784 | |
785 | err = get_user_pages_fast(addr, count, 1, pages); | |
786 | if (err < count) { | |
787 | count = err; | |
788 | err = -EFAULT; | |
789 | goto put_pages; | |
790 | } | |
7fc3cdab MW |
791 | |
792 | sg = kcalloc(count, sizeof(*sg), GFP_KERNEL); | |
36c14ed9 | 793 | sg_init_table(sg, count); |
ff22b54f | 794 | sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset); |
7fc3cdab MW |
795 | length -= (PAGE_SIZE - offset); |
796 | for (i = 1; i < count; i++) { | |
797 | sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0); | |
798 | length -= PAGE_SIZE; | |
799 | } | |
800 | ||
801 | err = -ENOMEM; | |
802 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
803 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 MW |
804 | if (!nents) |
805 | goto put_pages; | |
b60503ba | 806 | |
7fc3cdab MW |
807 | kfree(pages); |
808 | *sgp = sg; | |
809 | return nents; | |
b60503ba | 810 | |
7fc3cdab MW |
811 | put_pages: |
812 | for (i = 0; i < count; i++) | |
813 | put_page(pages[i]); | |
814 | kfree(pages); | |
815 | return err; | |
816 | } | |
b60503ba | 817 | |
7fc3cdab MW |
818 | static void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
819 | unsigned long addr, int length, | |
820 | struct scatterlist *sg, int nents) | |
821 | { | |
822 | int i, count; | |
b60503ba | 823 | |
7fc3cdab | 824 | count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE); |
36c14ed9 | 825 | dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE); |
7fc3cdab | 826 | |
36c14ed9 | 827 | for (i = 0; i < count; i++) |
7fc3cdab MW |
828 | put_page(sg_page(&sg[i])); |
829 | } | |
b60503ba | 830 | |
7fc3cdab MW |
831 | static int nvme_submit_user_admin_command(struct nvme_dev *dev, |
832 | unsigned long addr, unsigned length, | |
833 | struct nvme_command *cmd) | |
834 | { | |
835 | int err, nents; | |
836 | struct scatterlist *sg; | |
837 | ||
838 | nents = nvme_map_user_pages(dev, 0, addr, length, &sg); | |
839 | if (nents < 0) | |
840 | return nents; | |
841 | nvme_setup_prps(&cmd->common, sg, length); | |
842 | err = nvme_submit_admin_cmd(dev, cmd, NULL); | |
843 | nvme_unmap_user_pages(dev, 0, addr, length, sg, nents); | |
844 | return err ? -EIO : 0; | |
b60503ba MW |
845 | } |
846 | ||
bd38c555 | 847 | static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns) |
b60503ba | 848 | { |
b60503ba | 849 | struct nvme_command c; |
b60503ba | 850 | |
bd38c555 MW |
851 | memset(&c, 0, sizeof(c)); |
852 | c.identify.opcode = nvme_admin_identify; | |
853 | c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id); | |
854 | c.identify.cns = cpu_to_le32(cns); | |
855 | ||
856 | return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c); | |
857 | } | |
858 | ||
859 | static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr) | |
860 | { | |
861 | struct nvme_command c; | |
b60503ba MW |
862 | |
863 | memset(&c, 0, sizeof(c)); | |
864 | c.features.opcode = nvme_admin_get_features; | |
865 | c.features.nsid = cpu_to_le32(ns->ns_id); | |
b60503ba MW |
866 | c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE); |
867 | ||
bd38c555 | 868 | return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c); |
b60503ba MW |
869 | } |
870 | ||
a53295b6 MW |
871 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
872 | { | |
873 | struct nvme_dev *dev = ns->dev; | |
874 | struct nvme_queue *nvmeq; | |
875 | struct nvme_user_io io; | |
876 | struct nvme_command c; | |
877 | unsigned length; | |
878 | u32 result; | |
879 | int nents, status; | |
880 | struct scatterlist *sg; | |
881 | ||
882 | if (copy_from_user(&io, uio, sizeof(io))) | |
883 | return -EFAULT; | |
884 | length = io.nblocks << io.block_shift; | |
885 | nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg); | |
886 | if (nents < 0) | |
887 | return nents; | |
888 | ||
889 | memset(&c, 0, sizeof(c)); | |
890 | c.rw.opcode = io.opcode; | |
891 | c.rw.flags = io.flags; | |
892 | c.rw.nsid = cpu_to_le32(io.nsid); | |
893 | c.rw.slba = cpu_to_le64(io.slba); | |
894 | c.rw.length = cpu_to_le16(io.nblocks - 1); | |
895 | c.rw.control = cpu_to_le16(io.control); | |
896 | c.rw.dsmgmt = cpu_to_le16(io.dsmgmt); | |
897 | c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */ | |
898 | c.rw.apptag = cpu_to_le16(io.apptag); | |
899 | c.rw.appmask = cpu_to_le16(io.appmask); | |
900 | /* XXX: metadata */ | |
901 | nvme_setup_prps(&c.common, sg, length); | |
902 | ||
903 | nvmeq = get_nvmeq(ns); | |
b1ad37ef MW |
904 | /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption |
905 | * disabled. We may be preempted at any point, and be rescheduled | |
906 | * to a different CPU. That will cause cacheline bouncing, but no | |
907 | * additional races since q_lock already protects against other CPUs. | |
908 | */ | |
a53295b6 | 909 | put_nvmeq(nvmeq); |
e85248e5 | 910 | status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT); |
a53295b6 MW |
911 | |
912 | nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents); | |
913 | put_user(result, &uio->result); | |
914 | return status; | |
915 | } | |
916 | ||
6ee44cdc MW |
917 | static int nvme_download_firmware(struct nvme_ns *ns, |
918 | struct nvme_dlfw __user *udlfw) | |
919 | { | |
920 | struct nvme_dev *dev = ns->dev; | |
921 | struct nvme_dlfw dlfw; | |
922 | struct nvme_command c; | |
923 | int nents, status; | |
924 | struct scatterlist *sg; | |
925 | ||
926 | if (copy_from_user(&dlfw, udlfw, sizeof(dlfw))) | |
927 | return -EFAULT; | |
928 | if (dlfw.length >= (1 << 30)) | |
929 | return -EINVAL; | |
930 | ||
931 | nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg); | |
932 | if (nents < 0) | |
933 | return nents; | |
934 | ||
935 | memset(&c, 0, sizeof(c)); | |
936 | c.dlfw.opcode = nvme_admin_download_fw; | |
937 | c.dlfw.numd = cpu_to_le32(dlfw.length); | |
938 | c.dlfw.offset = cpu_to_le32(dlfw.offset); | |
939 | nvme_setup_prps(&c.common, sg, dlfw.length * 4); | |
940 | ||
941 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
942 | nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents); | |
943 | return status; | |
944 | } | |
945 | ||
946 | static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg) | |
947 | { | |
948 | struct nvme_dev *dev = ns->dev; | |
949 | struct nvme_command c; | |
950 | ||
951 | memset(&c, 0, sizeof(c)); | |
952 | c.common.opcode = nvme_admin_activate_fw; | |
953 | c.common.rsvd10[0] = cpu_to_le32(arg); | |
954 | ||
955 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
956 | } | |
957 | ||
b60503ba MW |
958 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
959 | unsigned long arg) | |
960 | { | |
961 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
962 | ||
963 | switch (cmd) { | |
964 | case NVME_IOCTL_IDENTIFY_NS: | |
36c14ed9 | 965 | return nvme_identify(ns, arg, 0); |
b60503ba | 966 | case NVME_IOCTL_IDENTIFY_CTRL: |
36c14ed9 | 967 | return nvme_identify(ns, arg, 1); |
b60503ba | 968 | case NVME_IOCTL_GET_RANGE_TYPE: |
bd38c555 | 969 | return nvme_get_range_type(ns, arg); |
a53295b6 MW |
970 | case NVME_IOCTL_SUBMIT_IO: |
971 | return nvme_submit_io(ns, (void __user *)arg); | |
6ee44cdc MW |
972 | case NVME_IOCTL_DOWNLOAD_FW: |
973 | return nvme_download_firmware(ns, (void __user *)arg); | |
974 | case NVME_IOCTL_ACTIVATE_FW: | |
975 | return nvme_activate_firmware(ns, arg); | |
b60503ba MW |
976 | default: |
977 | return -ENOTTY; | |
978 | } | |
979 | } | |
980 | ||
981 | static const struct block_device_operations nvme_fops = { | |
982 | .owner = THIS_MODULE, | |
983 | .ioctl = nvme_ioctl, | |
984 | }; | |
985 | ||
986 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index, | |
987 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) | |
988 | { | |
989 | struct nvme_ns *ns; | |
990 | struct gendisk *disk; | |
991 | int lbaf; | |
992 | ||
993 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
994 | return NULL; | |
995 | ||
996 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
997 | if (!ns) | |
998 | return NULL; | |
999 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
1000 | if (!ns->queue) | |
1001 | goto out_free_ns; | |
1002 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES | | |
1003 | QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD; | |
1004 | blk_queue_make_request(ns->queue, nvme_make_request); | |
1005 | ns->dev = dev; | |
1006 | ns->queue->queuedata = ns; | |
1007 | ||
1008 | disk = alloc_disk(NVME_MINORS); | |
1009 | if (!disk) | |
1010 | goto out_free_queue; | |
1011 | ns->ns_id = index; | |
1012 | ns->disk = disk; | |
1013 | lbaf = id->flbas & 0xf; | |
1014 | ns->lba_shift = id->lbaf[lbaf].ds; | |
1015 | ||
1016 | disk->major = nvme_major; | |
1017 | disk->minors = NVME_MINORS; | |
1018 | disk->first_minor = NVME_MINORS * index; | |
1019 | disk->fops = &nvme_fops; | |
1020 | disk->private_data = ns; | |
1021 | disk->queue = ns->queue; | |
388f037f | 1022 | disk->driverfs_dev = &dev->pci_dev->dev; |
b60503ba MW |
1023 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index); |
1024 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); | |
1025 | ||
1026 | return ns; | |
1027 | ||
1028 | out_free_queue: | |
1029 | blk_cleanup_queue(ns->queue); | |
1030 | out_free_ns: | |
1031 | kfree(ns); | |
1032 | return NULL; | |
1033 | } | |
1034 | ||
1035 | static void nvme_ns_free(struct nvme_ns *ns) | |
1036 | { | |
1037 | put_disk(ns->disk); | |
1038 | blk_cleanup_queue(ns->queue); | |
1039 | kfree(ns); | |
1040 | } | |
1041 | ||
b3b06812 | 1042 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1043 | { |
1044 | int status; | |
1045 | u32 result; | |
1046 | struct nvme_command c; | |
b3b06812 | 1047 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba MW |
1048 | |
1049 | memset(&c, 0, sizeof(c)); | |
1050 | c.features.opcode = nvme_admin_get_features; | |
1051 | c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES); | |
1052 | c.features.dword11 = cpu_to_le32(q_count); | |
1053 | ||
1054 | status = nvme_submit_admin_cmd(dev, &c, &result); | |
1055 | if (status) | |
1056 | return -EIO; | |
1057 | return min(result & 0xffff, result >> 16) + 1; | |
1058 | } | |
1059 | ||
b60503ba MW |
1060 | static int __devinit nvme_setup_io_queues(struct nvme_dev *dev) |
1061 | { | |
1b23484b | 1062 | int result, cpu, i, nr_queues; |
b60503ba | 1063 | |
1b23484b MW |
1064 | nr_queues = num_online_cpus(); |
1065 | result = set_queue_count(dev, nr_queues); | |
1066 | if (result < 0) | |
1067 | return result; | |
1068 | if (result < nr_queues) | |
1069 | nr_queues = result; | |
b60503ba | 1070 | |
1b23484b MW |
1071 | /* Deregister the admin queue's interrupt */ |
1072 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
1073 | ||
1074 | for (i = 0; i < nr_queues; i++) | |
1075 | dev->entry[i].entry = i; | |
1076 | for (;;) { | |
1077 | result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues); | |
1078 | if (result == 0) { | |
1079 | break; | |
1080 | } else if (result > 0) { | |
1081 | nr_queues = result; | |
1082 | continue; | |
1083 | } else { | |
1084 | nr_queues = 1; | |
1085 | break; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); | |
1090 | /* XXX: handle failure here */ | |
1091 | ||
1092 | cpu = cpumask_first(cpu_online_mask); | |
1093 | for (i = 0; i < nr_queues; i++) { | |
1094 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); | |
1095 | cpu = cpumask_next(cpu, cpu_online_mask); | |
1096 | } | |
1097 | ||
1098 | for (i = 0; i < nr_queues; i++) { | |
1099 | dev->queues[i + 1] = nvme_create_queue(dev, i + 1, | |
1100 | NVME_Q_DEPTH, i); | |
1101 | if (!dev->queues[i + 1]) | |
1102 | return -ENOMEM; | |
1103 | dev->queue_count++; | |
1104 | } | |
b60503ba MW |
1105 | |
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | static void nvme_free_queues(struct nvme_dev *dev) | |
1110 | { | |
1111 | int i; | |
1112 | ||
1113 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1114 | nvme_free_queue(dev, i); | |
1115 | } | |
1116 | ||
1117 | static int __devinit nvme_dev_add(struct nvme_dev *dev) | |
1118 | { | |
1119 | int res, nn, i; | |
1120 | struct nvme_ns *ns, *next; | |
51814232 | 1121 | struct nvme_id_ctrl *ctrl; |
b60503ba MW |
1122 | void *id; |
1123 | dma_addr_t dma_addr; | |
1124 | struct nvme_command cid, crt; | |
1125 | ||
1126 | res = nvme_setup_io_queues(dev); | |
1127 | if (res) | |
1128 | return res; | |
1129 | ||
1130 | /* XXX: Switch to a SG list once prp2 works */ | |
1131 | id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, | |
1132 | GFP_KERNEL); | |
1133 | ||
1134 | memset(&cid, 0, sizeof(cid)); | |
1135 | cid.identify.opcode = nvme_admin_identify; | |
1136 | cid.identify.nsid = 0; | |
1137 | cid.identify.prp1 = cpu_to_le64(dma_addr); | |
1138 | cid.identify.cns = cpu_to_le32(1); | |
1139 | ||
1140 | res = nvme_submit_admin_cmd(dev, &cid, NULL); | |
1141 | if (res) { | |
1142 | res = -EIO; | |
1143 | goto out_free; | |
1144 | } | |
1145 | ||
51814232 MW |
1146 | ctrl = id; |
1147 | nn = le32_to_cpup(&ctrl->nn); | |
1148 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); | |
1149 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1150 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
b60503ba MW |
1151 | |
1152 | cid.identify.cns = 0; | |
1153 | memset(&crt, 0, sizeof(crt)); | |
1154 | crt.features.opcode = nvme_admin_get_features; | |
1155 | crt.features.prp1 = cpu_to_le64(dma_addr + 4096); | |
1156 | crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE); | |
1157 | ||
1158 | for (i = 0; i < nn; i++) { | |
1159 | cid.identify.nsid = cpu_to_le32(i); | |
1160 | res = nvme_submit_admin_cmd(dev, &cid, NULL); | |
1161 | if (res) | |
1162 | continue; | |
1163 | ||
1164 | if (((struct nvme_id_ns *)id)->ncap == 0) | |
1165 | continue; | |
1166 | ||
1167 | crt.features.nsid = cpu_to_le32(i); | |
1168 | res = nvme_submit_admin_cmd(dev, &crt, NULL); | |
1169 | if (res) | |
1170 | continue; | |
1171 | ||
1172 | ns = nvme_alloc_ns(dev, i, id, id + 4096); | |
1173 | if (ns) | |
1174 | list_add_tail(&ns->list, &dev->namespaces); | |
1175 | } | |
1176 | list_for_each_entry(ns, &dev->namespaces, list) | |
1177 | add_disk(ns->disk); | |
1178 | ||
1179 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); | |
1180 | return 0; | |
1181 | ||
1182 | out_free: | |
1183 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1184 | list_del(&ns->list); | |
1185 | nvme_ns_free(ns); | |
1186 | } | |
1187 | ||
1188 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); | |
1189 | return res; | |
1190 | } | |
1191 | ||
1192 | static int nvme_dev_remove(struct nvme_dev *dev) | |
1193 | { | |
1194 | struct nvme_ns *ns, *next; | |
1195 | ||
1196 | /* TODO: wait all I/O finished or cancel them */ | |
1197 | ||
1198 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1199 | list_del(&ns->list); | |
1200 | del_gendisk(ns->disk); | |
1201 | nvme_ns_free(ns); | |
1202 | } | |
1203 | ||
1204 | nvme_free_queues(dev); | |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
1209 | /* XXX: Use an ida or something to let remove / add work correctly */ | |
1210 | static void nvme_set_instance(struct nvme_dev *dev) | |
1211 | { | |
1212 | static int instance; | |
1213 | dev->instance = instance++; | |
1214 | } | |
1215 | ||
1216 | static void nvme_release_instance(struct nvme_dev *dev) | |
1217 | { | |
1218 | } | |
1219 | ||
1220 | static int __devinit nvme_probe(struct pci_dev *pdev, | |
1221 | const struct pci_device_id *id) | |
1222 | { | |
574e8b95 | 1223 | int bars, result = -ENOMEM; |
b60503ba MW |
1224 | struct nvme_dev *dev; |
1225 | ||
1226 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1227 | if (!dev) | |
1228 | return -ENOMEM; | |
1229 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
1230 | GFP_KERNEL); | |
1231 | if (!dev->entry) | |
1232 | goto free; | |
1b23484b MW |
1233 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
1234 | GFP_KERNEL); | |
b60503ba MW |
1235 | if (!dev->queues) |
1236 | goto free; | |
1237 | ||
0ee5a7d7 SMM |
1238 | if (pci_enable_device_mem(pdev)) |
1239 | goto free; | |
f64d3365 | 1240 | pci_set_master(pdev); |
574e8b95 MW |
1241 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1242 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1243 | goto disable; | |
0ee5a7d7 | 1244 | |
b60503ba MW |
1245 | INIT_LIST_HEAD(&dev->namespaces); |
1246 | dev->pci_dev = pdev; | |
1247 | pci_set_drvdata(pdev, dev); | |
2930353f MW |
1248 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
1249 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
b60503ba | 1250 | nvme_set_instance(dev); |
53c9577e | 1251 | dev->entry[0].vector = pdev->irq; |
b60503ba MW |
1252 | |
1253 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1254 | if (!dev->bar) { | |
1255 | result = -ENOMEM; | |
574e8b95 | 1256 | goto disable_msix; |
b60503ba MW |
1257 | } |
1258 | ||
1259 | result = nvme_configure_admin_queue(dev); | |
1260 | if (result) | |
1261 | goto unmap; | |
1262 | dev->queue_count++; | |
1263 | ||
1264 | result = nvme_dev_add(dev); | |
1265 | if (result) | |
1266 | goto delete; | |
1267 | return 0; | |
1268 | ||
1269 | delete: | |
1270 | nvme_free_queues(dev); | |
1271 | unmap: | |
1272 | iounmap(dev->bar); | |
574e8b95 | 1273 | disable_msix: |
b60503ba MW |
1274 | pci_disable_msix(pdev); |
1275 | nvme_release_instance(dev); | |
574e8b95 | 1276 | disable: |
0ee5a7d7 | 1277 | pci_disable_device(pdev); |
574e8b95 | 1278 | pci_release_regions(pdev); |
b60503ba MW |
1279 | free: |
1280 | kfree(dev->queues); | |
1281 | kfree(dev->entry); | |
1282 | kfree(dev); | |
1283 | return result; | |
1284 | } | |
1285 | ||
1286 | static void __devexit nvme_remove(struct pci_dev *pdev) | |
1287 | { | |
1288 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
1289 | nvme_dev_remove(dev); | |
1290 | pci_disable_msix(pdev); | |
1291 | iounmap(dev->bar); | |
1292 | nvme_release_instance(dev); | |
0ee5a7d7 | 1293 | pci_disable_device(pdev); |
574e8b95 | 1294 | pci_release_regions(pdev); |
b60503ba MW |
1295 | kfree(dev->queues); |
1296 | kfree(dev->entry); | |
1297 | kfree(dev); | |
1298 | } | |
1299 | ||
1300 | /* These functions are yet to be implemented */ | |
1301 | #define nvme_error_detected NULL | |
1302 | #define nvme_dump_registers NULL | |
1303 | #define nvme_link_reset NULL | |
1304 | #define nvme_slot_reset NULL | |
1305 | #define nvme_error_resume NULL | |
1306 | #define nvme_suspend NULL | |
1307 | #define nvme_resume NULL | |
1308 | ||
1309 | static struct pci_error_handlers nvme_err_handler = { | |
1310 | .error_detected = nvme_error_detected, | |
1311 | .mmio_enabled = nvme_dump_registers, | |
1312 | .link_reset = nvme_link_reset, | |
1313 | .slot_reset = nvme_slot_reset, | |
1314 | .resume = nvme_error_resume, | |
1315 | }; | |
1316 | ||
1317 | /* Move to pci_ids.h later */ | |
1318 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
1319 | ||
1320 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
1321 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
1322 | { 0, } | |
1323 | }; | |
1324 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
1325 | ||
1326 | static struct pci_driver nvme_driver = { | |
1327 | .name = "nvme", | |
1328 | .id_table = nvme_id_table, | |
1329 | .probe = nvme_probe, | |
1330 | .remove = __devexit_p(nvme_remove), | |
1331 | .suspend = nvme_suspend, | |
1332 | .resume = nvme_resume, | |
1333 | .err_handler = &nvme_err_handler, | |
1334 | }; | |
1335 | ||
1336 | static int __init nvme_init(void) | |
1337 | { | |
1338 | int result; | |
1339 | ||
1340 | nvme_major = register_blkdev(nvme_major, "nvme"); | |
1341 | if (nvme_major <= 0) | |
1342 | return -EBUSY; | |
1343 | ||
1344 | result = pci_register_driver(&nvme_driver); | |
1345 | if (!result) | |
1346 | return 0; | |
1347 | ||
1348 | unregister_blkdev(nvme_major, "nvme"); | |
1349 | return result; | |
1350 | } | |
1351 | ||
1352 | static void __exit nvme_exit(void) | |
1353 | { | |
1354 | pci_unregister_driver(&nvme_driver); | |
1355 | unregister_blkdev(nvme_major, "nvme"); | |
1356 | } | |
1357 | ||
1358 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
1359 | MODULE_LICENSE("GPL"); | |
db5d0c19 | 1360 | MODULE_VERSION("0.2"); |
b60503ba MW |
1361 | module_init(nvme_init); |
1362 | module_exit(nvme_exit); |