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NVMe: Release 0.2
[linux-2.6-block.git] / drivers / block / nvme.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
21#include <linux/blkdev.h>
22#include <linux/errno.h>
23#include <linux/fs.h>
24#include <linux/genhd.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kdev_t.h>
29#include <linux/kernel.h>
30#include <linux/mm.h>
31#include <linux/module.h>
32#include <linux/moduleparam.h>
33#include <linux/pci.h>
34#include <linux/sched.h>
35#include <linux/slab.h>
36#include <linux/types.h>
37#include <linux/version.h>
38
39#define NVME_Q_DEPTH 1024
40#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
41#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
42#define NVME_MINORS 64
43
44static int nvme_major;
45module_param(nvme_major, int, 0);
46
47/*
48 * Represents an NVM Express device. Each nvme_dev is a PCI function.
49 */
50struct nvme_dev {
b60503ba
MW		 51 struct nvme_queue **queues;
52 u32 __iomem *dbs;
53 struct pci_dev *pci_dev;
54 int instance;
55 int queue_count;
56 u32 ctrl_config;
57 struct msix_entry *entry;
58 struct nvme_bar __iomem *bar;
59 struct list_head namespaces;
51814232
MW		 60 char serial[20];
61 char model[40];
62 char firmware_rev[8];
b60503ba
MW		 63};
64
65/*
66 * An NVM Express namespace is equivalent to a SCSI LUN
67 */
68struct nvme_ns {
69 struct list_head list;
70
71 struct nvme_dev *dev;
72 struct request_queue *queue;
73 struct gendisk *disk;
74
75 int ns_id;
76 int lba_shift;
77};
78
79/*
80 * An NVM Express queue. Each device has at least two (one for admin
81 * commands and one for I/O commands).
82 */
83struct nvme_queue {
84 struct device *q_dmadev;
85 spinlock_t q_lock;
86 struct nvme_command *sq_cmds;
87 volatile struct nvme_completion *cqes;
88 dma_addr_t sq_dma_addr;
89 dma_addr_t cq_dma_addr;
90 wait_queue_head_t sq_full;
91 struct bio_list sq_cong;
92 u32 __iomem *q_db;
93 u16 q_depth;
94 u16 cq_vector;
95 u16 sq_head;
96 u16 sq_tail;
97 u16 cq_head;
82123460 98 u16 cq_phase;
b60503ba
MW		 99 unsigned long cmdid_data[];
100};
101
102/*
103 * Check we didin't inadvertently grow the command struct
104 */
105static inline void _nvme_check_size(void)
106{
107 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
108 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
109 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
110 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
111 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
112 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
113 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
114 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
115 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
116}
117
118/**
119 * alloc_cmdid - Allocate a Command ID
120 * @param nvmeq The queue that will be used for this command
121 * @param ctx A pointer that will be passed to the handler
122 * @param handler The ID of the handler to call
123 *
124 * Allocate a Command ID for a queue. The data passed in will
125 * be passed to the completion handler. This is implemented by using
126 * the bottom two bits of the ctx pointer to store the handler ID.
127 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
128 * We can change this if it becomes a problem.
129 */
130static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler)
131{
132 int depth = nvmeq->q_depth;
133 unsigned long data = (unsigned long)ctx | handler;
134 int cmdid;
135
136 BUG_ON((unsigned long)ctx & 3);
137
138 do {
139 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
140 if (cmdid >= depth)
141 return -EBUSY;
142 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
143
144 nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(depth)] = data;
145 return cmdid;
146}
147
148static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
149 int handler)
150{
151 int cmdid;
152 wait_event_killable(nvmeq->sq_full,
153 (cmdid = alloc_cmdid(nvmeq, ctx, handler)) >= 0);
154 return (cmdid < 0) ? -EINTR : cmdid;
155}
156
157/* If you need more than four handlers, you'll need to change how
158 * alloc_cmdid and nvme_process_cq work
159 */
160enum {
161 sync_completion_id = 0,
162 bio_completion_id,
163};
164
165static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
166{
167 unsigned long data;
168
169 data = nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)];
170 clear_bit(cmdid, nvmeq->cmdid_data);
171 wake_up(&nvmeq->sq_full);
172 return data;
173}
174
175static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
176{
1b23484b
MW		 177 int qid, cpu = get_cpu();
178 if (cpu < ns->dev->queue_count)
179 qid = cpu + 1;
180 else
181 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
182 return ns->dev->queues[qid];
b60503ba
MW		 183}
184
185static void put_nvmeq(struct nvme_queue *nvmeq)
186{
1b23484b 187 put_cpu();
b60503ba
MW		 188}
189
190/**
191 * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
192 * @nvmeq: The queue to use
193 * @cmd: The command to send
194 *
195 * Safe to use from interrupt context
196 */
197static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
198{
199 unsigned long flags;
200 u16 tail;
201 /* XXX: Need to check tail isn't going to overrun head */
202 spin_lock_irqsave(&nvmeq->q_lock, flags);
203 tail = nvmeq->sq_tail;
204 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
205 writel(tail, nvmeq->q_db);
206 if (++tail == nvmeq->q_depth)
207 tail = 0;
208 nvmeq->sq_tail = tail;
209 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
210
211 return 0;
212}
213
214struct nvme_req_info {
215 struct bio *bio;
216 int nents;
217 struct scatterlist sg[0];
218};
219
220/* XXX: use a mempool */
221static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
222{
223 return kmalloc(sizeof(struct nvme_req_info) +
224 sizeof(struct scatterlist) * nseg, gfp);
225}
226
227static void free_info(struct nvme_req_info *info)
228{
229 kfree(info);
230}
231
232static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
233 struct nvme_completion *cqe)
234{
235 struct nvme_req_info *info = ctx;
236 struct bio *bio = info->bio;
237 u16 status = le16_to_cpup(&cqe->status) >> 1;
238
239 dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
240 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
241 free_info(info);
242 bio_endio(bio, status ? -EIO : 0);
243}
244
ff22b54f
MW		 245/* length is in bytes */
246static void nvme_setup_prps(struct nvme_common_command *cmd,
247 struct scatterlist *sg, int length)
248{
249 int dma_len = sg_dma_len(sg);
250 u64 dma_addr = sg_dma_address(sg);
251 int offset = offset_in_page(dma_addr);
252
253 cmd->prp1 = cpu_to_le64(dma_addr);
254 length -= (PAGE_SIZE - offset);
255 if (length <= 0)
256 return;
257
258 dma_len -= (PAGE_SIZE - offset);
259 if (dma_len) {
260 dma_addr += (PAGE_SIZE - offset);
261 } else {
262 sg = sg_next(sg);
263 dma_addr = sg_dma_address(sg);
264 dma_len = sg_dma_len(sg);
265 }
266
267 if (length <= PAGE_SIZE) {
268 cmd->prp2 = cpu_to_le64(dma_addr);
269 return;
270 }
271
272 /* XXX: support PRP lists */
273}
274
b60503ba
MW		 275static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
276 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
277{
278 struct bio_vec *bvec;
279 struct scatterlist *sg = info->sg;
280 int i, nsegs;
281
282 sg_init_table(sg, psegs);
283 bio_for_each_segment(bvec, bio, i) {
284 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
285 /* XXX: handle non-mergable here */
286 nsegs++;
287 }
288 info->nents = nsegs;
289
290 return dma_map_sg(dev, info->sg, info->nents, dma_dir);
291}
292
293static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
294 struct bio *bio)
295{
ff22b54f 296 struct nvme_command *cmnd;
b60503ba
MW		 297 struct nvme_req_info *info;
298 enum dma_data_direction dma_dir;
299 int cmdid;
300 u16 control;
301 u32 dsmgmt;
302 unsigned long flags;
303 int psegs = bio_phys_segments(ns->queue, bio);
304
305 info = alloc_info(psegs, GFP_NOIO);
306 if (!info)
307 goto congestion;
308 info->bio = bio;
309
310 cmdid = alloc_cmdid(nvmeq, info, bio_completion_id);
311 if (unlikely(cmdid < 0))
312 goto free_info;
313
314 control = 0;
315 if (bio->bi_rw & REQ_FUA)
316 control |= NVME_RW_FUA;
317 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
318 control |= NVME_RW_LR;
319
320 dsmgmt = 0;
321 if (bio->bi_rw & REQ_RAHEAD)
322 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
323
324 spin_lock_irqsave(&nvmeq->q_lock, flags);
ff22b54f 325 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 326
b8deb62c 327 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 328 if (bio_data_dir(bio)) {
ff22b54f 329 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW		 330 dma_dir = DMA_TO_DEVICE;
331 } else {
ff22b54f 332 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW		 333 dma_dir = DMA_FROM_DEVICE;
334 }
335
336 nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
337
ff22b54f
MW		 338 cmnd->rw.flags = 1;
339 cmnd->rw.command_id = cmdid;
340 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
341 nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
342 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
343 cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
344 cmnd->rw.control = cpu_to_le16(control);
345 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba
MW		 346
347 writel(nvmeq->sq_tail, nvmeq->q_db);
348 if (++nvmeq->sq_tail == nvmeq->q_depth)
349 nvmeq->sq_tail = 0;
350
351 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
352
353 return 0;
354
355 free_info:
356 free_info(info);
357 congestion:
358 return -EBUSY;
359}
360
361/*
362 * NB: return value of non-zero would mean that we were a stacking driver.
363 * make_request must always succeed.
364 */
365static int nvme_make_request(struct request_queue *q, struct bio *bio)
366{
367 struct nvme_ns *ns = q->queuedata;
368 struct nvme_queue *nvmeq = get_nvmeq(ns);
369
370 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
371 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
372 bio_list_add(&nvmeq->sq_cong, bio);
373 }
374 put_nvmeq(nvmeq);
375
376 return 0;
377}
378
379struct sync_cmd_info {
380 struct task_struct *task;
381 u32 result;
382 int status;
383};
384
385static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
386 struct nvme_completion *cqe)
387{
388 struct sync_cmd_info *cmdinfo = ctx;
389 cmdinfo->result = le32_to_cpup(&cqe->result);
390 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
391 wake_up_process(cmdinfo->task);
392}
393
394typedef void (*completion_fn)(struct nvme_queue *, void *,
395 struct nvme_completion *);
396
397static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
398{
82123460 399 u16 head, phase;
b60503ba
MW		 400
401 static const completion_fn completions[4] = {
402 [sync_completion_id] = sync_completion,
403 [bio_completion_id] = bio_completion,
404 };
405
406 head = nvmeq->cq_head;
82123460 407 phase = nvmeq->cq_phase;
b60503ba
MW		 408
409 for (;;) {
410 unsigned long data;
411 void *ptr;
412 unsigned char handler;
413 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 414 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 415 break;
416 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
417 if (++head == nvmeq->q_depth) {
418 head = 0;
82123460 419 phase = !phase;
b60503ba
MW		 420 }
421
422 data = free_cmdid(nvmeq, cqe.command_id);
423 handler = data & 3;
424 ptr = (void *)(data & ~3UL);
425 completions[handler](nvmeq, ptr, &cqe);
426 }
427
428 /* If the controller ignores the cq head doorbell and continuously
429 * writes to the queue, it is theoretically possible to wrap around
430 * the queue twice and mistakenly return IRQ_NONE. Linux only
431 * requires that 0.1% of your interrupts are handled, so this isn't
432 * a big problem.
433 */
82123460 434 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
b60503ba
MW		 435 return IRQ_NONE;
436
437 writel(head, nvmeq->q_db + 1);
438 nvmeq->cq_head = head;
82123460 439 nvmeq->cq_phase = phase;
b60503ba
MW		 440
441 return IRQ_HANDLED;
442}
443
444static irqreturn_t nvme_irq(int irq, void *data)
445{
446 return nvme_process_cq(data);
447}
448
449/*
450 * Returns 0 on success. If the result is negative, it's a Linux error code;
451 * if the result is positive, it's an NVM Express status code
452 */
453static int nvme_submit_sync_cmd(struct nvme_queue *q, struct nvme_command *cmd,
454 u32 *result)
455{
456 int cmdid;
457 struct sync_cmd_info cmdinfo;
458
459 cmdinfo.task = current;
460 cmdinfo.status = -EINTR;
461
462 cmdid = alloc_cmdid_killable(q, &cmdinfo, sync_completion_id);
463 if (cmdid < 0)
464 return cmdid;
465 cmd->common.command_id = cmdid;
466
467 set_current_state(TASK_UNINTERRUPTIBLE);
468 nvme_submit_cmd(q, cmd);
469 schedule();
470
471 if (result)
472 *result = cmdinfo.result;
473
474 return cmdinfo.status;
475}
476
477static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
478 u32 *result)
479{
480 return nvme_submit_sync_cmd(dev->queues[0], cmd, result);
481}
482
483static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
484{
485 int status;
486 struct nvme_command c;
487
488 memset(&c, 0, sizeof(c));
489 c.delete_queue.opcode = opcode;
490 c.delete_queue.qid = cpu_to_le16(id);
491
492 status = nvme_submit_admin_cmd(dev, &c, NULL);
493 if (status)
494 return -EIO;
495 return 0;
496}
497
498static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
499 struct nvme_queue *nvmeq)
500{
501 int status;
502 struct nvme_command c;
503 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
504
505 memset(&c, 0, sizeof(c));
506 c.create_cq.opcode = nvme_admin_create_cq;
507 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
508 c.create_cq.cqid = cpu_to_le16(qid);
509 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
510 c.create_cq.cq_flags = cpu_to_le16(flags);
511 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
512
513 status = nvme_submit_admin_cmd(dev, &c, NULL);
514 if (status)
515 return -EIO;
516 return 0;
517}
518
519static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
520 struct nvme_queue *nvmeq)
521{
522 int status;
523 struct nvme_command c;
524 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
525
526 memset(&c, 0, sizeof(c));
527 c.create_sq.opcode = nvme_admin_create_sq;
528 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
529 c.create_sq.sqid = cpu_to_le16(qid);
530 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
531 c.create_sq.sq_flags = cpu_to_le16(flags);
532 c.create_sq.cqid = cpu_to_le16(qid);
533
534 status = nvme_submit_admin_cmd(dev, &c, NULL);
535 if (status)
536 return -EIO;
537 return 0;
538}
539
540static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
541{
542 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
543}
544
545static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
546{
547 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
548}
549
550static void nvme_free_queue(struct nvme_dev *dev, int qid)
551{
552 struct nvme_queue *nvmeq = dev->queues[qid];
553
554 free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
555
556 /* Don't tell the adapter to delete the admin queue */
557 if (qid) {
558 adapter_delete_sq(dev, qid);
559 adapter_delete_cq(dev, qid);
560 }
561
562 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
563 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
564 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
565 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
566 kfree(nvmeq);
567}
568
569static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
570 int depth, int vector)
571{
572 struct device *dmadev = &dev->pci_dev->dev;
573 unsigned extra = (depth + BITS_TO_LONGS(depth)) * sizeof(long);
574 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
575 if (!nvmeq)
576 return NULL;
577
578 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
579 &nvmeq->cq_dma_addr, GFP_KERNEL);
580 if (!nvmeq->cqes)
581 goto free_nvmeq;
582 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
583
584 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
585 &nvmeq->sq_dma_addr, GFP_KERNEL);
586 if (!nvmeq->sq_cmds)
587 goto free_cqdma;
588
589 nvmeq->q_dmadev = dmadev;
590 spin_lock_init(&nvmeq->q_lock);
591 nvmeq->cq_head = 0;
82123460 592 nvmeq->cq_phase = 1;
b60503ba
MW		 593 init_waitqueue_head(&nvmeq->sq_full);
594 bio_list_init(&nvmeq->sq_cong);
595 nvmeq->q_db = &dev->dbs[qid * 2];
596 nvmeq->q_depth = depth;
597 nvmeq->cq_vector = vector;
598
599 return nvmeq;
600
601 free_cqdma:
602 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
603 nvmeq->cq_dma_addr);
604 free_nvmeq:
605 kfree(nvmeq);
606 return NULL;
607}
608
3001082c
MW		 609static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
610 const char *name)
611{
612 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
613 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
614}
615
b60503ba
MW		 616static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
617 int qid, int cq_size, int vector)
618{
619 int result;
620 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
621
3f85d50b
MW		 622 if (!nvmeq)
623 return NULL;
624
b60503ba
MW		 625 result = adapter_alloc_cq(dev, qid, nvmeq);
626 if (result < 0)
627 goto free_nvmeq;
628
629 result = adapter_alloc_sq(dev, qid, nvmeq);
630 if (result < 0)
631 goto release_cq;
632
3001082c 633 result = queue_request_irq(dev, nvmeq, "nvme");
b60503ba
MW		 634 if (result < 0)
635 goto release_sq;
636
637 return nvmeq;
638
639 release_sq:
640 adapter_delete_sq(dev, qid);
641 release_cq:
642 adapter_delete_cq(dev, qid);
643 free_nvmeq:
644 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
645 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
646 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
647 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
648 kfree(nvmeq);
649 return NULL;
650}
651
652static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
653{
654 int result;
655 u32 aqa;
656 struct nvme_queue *nvmeq;
657
658 dev->dbs = ((void __iomem *)dev->bar) + 4096;
659
660 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
3f85d50b
MW		 661 if (!nvmeq)
662 return -ENOMEM;
b60503ba
MW		 663
664 aqa = nvmeq->q_depth - 1;
665 aqa |= aqa << 16;
666
667 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
668 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
669 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
670
5911f200 671 writel(0, &dev->bar->cc);
b60503ba
MW		 672 writel(aqa, &dev->bar->aqa);
673 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
674 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
675 writel(dev->ctrl_config, &dev->bar->cc);
676
677 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
678 msleep(100);
679 if (fatal_signal_pending(current))
680 return -EINTR;
681 }
682
3001082c 683 result = queue_request_irq(dev, nvmeq, "nvme admin");
b60503ba
MW		 684 dev->queues[0] = nvmeq;
685 return result;
686}
687
7fc3cdab
MW		 688static int nvme_map_user_pages(struct nvme_dev *dev, int write,
689 unsigned long addr, unsigned length,
690 struct scatterlist **sgp)
b60503ba 691{
36c14ed9 692 int i, err, count, nents, offset;
7fc3cdab
MW		 693 struct scatterlist *sg;
694 struct page **pages;
36c14ed9
MW		 695
696 if (addr & 3)
697 return -EINVAL;
7fc3cdab
MW		 698 if (!length)
699 return -EINVAL;
700
36c14ed9 701 offset = offset_in_page(addr);
7fc3cdab
MW		 702 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
703 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
36c14ed9
MW		 704
705 err = get_user_pages_fast(addr, count, 1, pages);
706 if (err < count) {
707 count = err;
708 err = -EFAULT;
709 goto put_pages;
710 }
7fc3cdab
MW		 711
712 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
36c14ed9 713 sg_init_table(sg, count);
ff22b54f 714 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
7fc3cdab
MW		 715 length -= (PAGE_SIZE - offset);
716 for (i = 1; i < count; i++) {
717 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
718 length -= PAGE_SIZE;
719 }
720
721 err = -ENOMEM;
722 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
723 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9
MW		 724 if (!nents)
725 goto put_pages;
b60503ba 726
7fc3cdab
MW		 727 kfree(pages);
728 *sgp = sg;
729 return nents;
b60503ba 730
7fc3cdab
MW		 731 put_pages:
732 for (i = 0; i < count; i++)
733 put_page(pages[i]);
734 kfree(pages);
735 return err;
736}
b60503ba 737
7fc3cdab
MW		 738static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
739 unsigned long addr, int length,
740 struct scatterlist *sg, int nents)
741{
742 int i, count;
b60503ba 743
7fc3cdab 744 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
36c14ed9 745 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
7fc3cdab 746
36c14ed9 747 for (i = 0; i < count; i++)
7fc3cdab
MW		 748 put_page(sg_page(&sg[i]));
749}
b60503ba 750
7fc3cdab
MW		 751static int nvme_submit_user_admin_command(struct nvme_dev *dev,
752 unsigned long addr, unsigned length,
753 struct nvme_command *cmd)
754{
755 int err, nents;
756 struct scatterlist *sg;
757
758 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
759 if (nents < 0)
760 return nents;
761 nvme_setup_prps(&cmd->common, sg, length);
762 err = nvme_submit_admin_cmd(dev, cmd, NULL);
763 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
764 return err ? -EIO : 0;
b60503ba
MW		 765}
766
bd38c555 767static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
b60503ba 768{
b60503ba 769 struct nvme_command c;
b60503ba 770
bd38c555
MW		 771 memset(&c, 0, sizeof(c));
772 c.identify.opcode = nvme_admin_identify;
773 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
774 c.identify.cns = cpu_to_le32(cns);
775
776 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
777}
778
779static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
780{
781 struct nvme_command c;
b60503ba
MW		 782
783 memset(&c, 0, sizeof(c));
784 c.features.opcode = nvme_admin_get_features;
785 c.features.nsid = cpu_to_le32(ns->ns_id);
b60503ba
MW		 786 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
787
bd38c555 788 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
b60503ba
MW		 789}
790
a53295b6
MW		 791static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
792{
793 struct nvme_dev *dev = ns->dev;
794 struct nvme_queue *nvmeq;
795 struct nvme_user_io io;
796 struct nvme_command c;
797 unsigned length;
798 u32 result;
799 int nents, status;
800 struct scatterlist *sg;
801
802 if (copy_from_user(&io, uio, sizeof(io)))
803 return -EFAULT;
804 length = io.nblocks << io.block_shift;
805 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
806 if (nents < 0)
807 return nents;
808
809 memset(&c, 0, sizeof(c));
810 c.rw.opcode = io.opcode;
811 c.rw.flags = io.flags;
812 c.rw.nsid = cpu_to_le32(io.nsid);
813 c.rw.slba = cpu_to_le64(io.slba);
814 c.rw.length = cpu_to_le16(io.nblocks - 1);
815 c.rw.control = cpu_to_le16(io.control);
816 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
817 c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */
818 c.rw.apptag = cpu_to_le16(io.apptag);
819 c.rw.appmask = cpu_to_le16(io.appmask);
820 /* XXX: metadata */
821 nvme_setup_prps(&c.common, sg, length);
822
823 nvmeq = get_nvmeq(ns);
824 status = nvme_submit_sync_cmd(nvmeq, &c, &result);
825 put_nvmeq(nvmeq);
826
827 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
828 put_user(result, &uio->result);
829 return status;
830}
831
6ee44cdc
MW		 832static int nvme_download_firmware(struct nvme_ns *ns,
833 struct nvme_dlfw __user *udlfw)
834{
835 struct nvme_dev *dev = ns->dev;
836 struct nvme_dlfw dlfw;
837 struct nvme_command c;
838 int nents, status;
839 struct scatterlist *sg;
840
841 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
842 return -EFAULT;
843 if (dlfw.length >= (1 << 30))
844 return -EINVAL;
845
846 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
847 if (nents < 0)
848 return nents;
849
850 memset(&c, 0, sizeof(c));
851 c.dlfw.opcode = nvme_admin_download_fw;
852 c.dlfw.numd = cpu_to_le32(dlfw.length);
853 c.dlfw.offset = cpu_to_le32(dlfw.offset);
854 nvme_setup_prps(&c.common, sg, dlfw.length * 4);
855
856 status = nvme_submit_admin_cmd(dev, &c, NULL);
857 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
858 return status;
859}
860
861static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
862{
863 struct nvme_dev *dev = ns->dev;
864 struct nvme_command c;
865
866 memset(&c, 0, sizeof(c));
867 c.common.opcode = nvme_admin_activate_fw;
868 c.common.rsvd10[0] = cpu_to_le32(arg);
869
870 return nvme_submit_admin_cmd(dev, &c, NULL);
871}
872
b60503ba
MW		 873static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
874 unsigned long arg)
875{
876 struct nvme_ns *ns = bdev->bd_disk->private_data;
877
878 switch (cmd) {
879 case NVME_IOCTL_IDENTIFY_NS:
36c14ed9 880 return nvme_identify(ns, arg, 0);
b60503ba 881 case NVME_IOCTL_IDENTIFY_CTRL:
36c14ed9 882 return nvme_identify(ns, arg, 1);
b60503ba 883 case NVME_IOCTL_GET_RANGE_TYPE:
bd38c555 884 return nvme_get_range_type(ns, arg);
a53295b6
MW		 885 case NVME_IOCTL_SUBMIT_IO:
886 return nvme_submit_io(ns, (void __user *)arg);
6ee44cdc
MW		 887 case NVME_IOCTL_DOWNLOAD_FW:
888 return nvme_download_firmware(ns, (void __user *)arg);
889 case NVME_IOCTL_ACTIVATE_FW:
890 return nvme_activate_firmware(ns, arg);
b60503ba
MW		 891 default:
892 return -ENOTTY;
893 }
894}
895
896static const struct block_device_operations nvme_fops = {
897 .owner = THIS_MODULE,
898 .ioctl = nvme_ioctl,
899};
900
901static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
902 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
903{
904 struct nvme_ns *ns;
905 struct gendisk *disk;
906 int lbaf;
907
908 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
909 return NULL;
910
911 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
912 if (!ns)
913 return NULL;
914 ns->queue = blk_alloc_queue(GFP_KERNEL);
915 if (!ns->queue)
916 goto out_free_ns;
917 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
918 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
919 blk_queue_make_request(ns->queue, nvme_make_request);
920 ns->dev = dev;
921 ns->queue->queuedata = ns;
922
923 disk = alloc_disk(NVME_MINORS);
924 if (!disk)
925 goto out_free_queue;
926 ns->ns_id = index;
927 ns->disk = disk;
928 lbaf = id->flbas & 0xf;
929 ns->lba_shift = id->lbaf[lbaf].ds;
930
931 disk->major = nvme_major;
932 disk->minors = NVME_MINORS;
933 disk->first_minor = NVME_MINORS * index;
934 disk->fops = &nvme_fops;
935 disk->private_data = ns;
936 disk->queue = ns->queue;
388f037f 937 disk->driverfs_dev = &dev->pci_dev->dev;
b60503ba
MW		 938 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
939 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
940
941 return ns;
942
943 out_free_queue:
944 blk_cleanup_queue(ns->queue);
945 out_free_ns:
946 kfree(ns);
947 return NULL;
948}
949
950static void nvme_ns_free(struct nvme_ns *ns)
951{
952 put_disk(ns->disk);
953 blk_cleanup_queue(ns->queue);
954 kfree(ns);
955}
956
b3b06812 957static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 958{
959 int status;
960 u32 result;
961 struct nvme_command c;
b3b06812 962 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba
MW		 963
964 memset(&c, 0, sizeof(c));
965 c.features.opcode = nvme_admin_get_features;
966 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
967 c.features.dword11 = cpu_to_le32(q_count);
968
969 status = nvme_submit_admin_cmd(dev, &c, &result);
970 if (status)
971 return -EIO;
972 return min(result & 0xffff, result >> 16) + 1;
973}
974
b60503ba
MW		 975static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
976{
1b23484b 977 int result, cpu, i, nr_queues;
b60503ba 978
1b23484b
MW		 979 nr_queues = num_online_cpus();
980 result = set_queue_count(dev, nr_queues);
981 if (result < 0)
982 return result;
983 if (result < nr_queues)
984 nr_queues = result;
b60503ba 985
1b23484b
MW		 986 /* Deregister the admin queue's interrupt */
987 free_irq(dev->entry[0].vector, dev->queues[0]);
988
989 for (i = 0; i < nr_queues; i++)
990 dev->entry[i].entry = i;
991 for (;;) {
992 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
993 if (result == 0) {
994 break;
995 } else if (result > 0) {
996 nr_queues = result;
997 continue;
998 } else {
999 nr_queues = 1;
1000 break;
1001 }
1002 }
1003
1004 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1005 /* XXX: handle failure here */
1006
1007 cpu = cpumask_first(cpu_online_mask);
1008 for (i = 0; i < nr_queues; i++) {
1009 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1010 cpu = cpumask_next(cpu, cpu_online_mask);
1011 }
1012
1013 for (i = 0; i < nr_queues; i++) {
1014 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1015 NVME_Q_DEPTH, i);
1016 if (!dev->queues[i + 1])
1017 return -ENOMEM;
1018 dev->queue_count++;
1019 }
b60503ba
MW		 1020
1021 return 0;
1022}
1023
1024static void nvme_free_queues(struct nvme_dev *dev)
1025{
1026 int i;
1027
1028 for (i = dev->queue_count - 1; i >= 0; i--)
1029 nvme_free_queue(dev, i);
1030}
1031
1032static int __devinit nvme_dev_add(struct nvme_dev *dev)
1033{
1034 int res, nn, i;
1035 struct nvme_ns *ns, *next;
51814232 1036 struct nvme_id_ctrl *ctrl;
b60503ba
MW		 1037 void *id;
1038 dma_addr_t dma_addr;
1039 struct nvme_command cid, crt;
1040
1041 res = nvme_setup_io_queues(dev);
1042 if (res)
1043 return res;
1044
1045 /* XXX: Switch to a SG list once prp2 works */
1046 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1047 GFP_KERNEL);
1048
1049 memset(&cid, 0, sizeof(cid));
1050 cid.identify.opcode = nvme_admin_identify;
1051 cid.identify.nsid = 0;
1052 cid.identify.prp1 = cpu_to_le64(dma_addr);
1053 cid.identify.cns = cpu_to_le32(1);
1054
1055 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1056 if (res) {
1057 res = -EIO;
1058 goto out_free;
1059 }
1060
51814232
MW		 1061 ctrl = id;
1062 nn = le32_to_cpup(&ctrl->nn);
1063 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1064 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1065 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
b60503ba
MW		 1066
1067 cid.identify.cns = 0;
1068 memset(&crt, 0, sizeof(crt));
1069 crt.features.opcode = nvme_admin_get_features;
1070 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1071 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1072
1073 for (i = 0; i < nn; i++) {
1074 cid.identify.nsid = cpu_to_le32(i);
1075 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1076 if (res)
1077 continue;
1078
1079 if (((struct nvme_id_ns *)id)->ncap == 0)
1080 continue;
1081
1082 crt.features.nsid = cpu_to_le32(i);
1083 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1084 if (res)
1085 continue;
1086
1087 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1088 if (ns)
1089 list_add_tail(&ns->list, &dev->namespaces);
1090 }
1091 list_for_each_entry(ns, &dev->namespaces, list)
1092 add_disk(ns->disk);
1093
1094 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1095 return 0;
1096
1097 out_free:
1098 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1099 list_del(&ns->list);
1100 nvme_ns_free(ns);
1101 }
1102
1103 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1104 return res;
1105}
1106
1107static int nvme_dev_remove(struct nvme_dev *dev)
1108{
1109 struct nvme_ns *ns, *next;
1110
1111 /* TODO: wait all I/O finished or cancel them */
1112
1113 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1114 list_del(&ns->list);
1115 del_gendisk(ns->disk);
1116 nvme_ns_free(ns);
1117 }
1118
1119 nvme_free_queues(dev);
1120
1121 return 0;
1122}
1123
1124/* XXX: Use an ida or something to let remove / add work correctly */
1125static void nvme_set_instance(struct nvme_dev *dev)
1126{
1127 static int instance;
1128 dev->instance = instance++;
1129}
1130
1131static void nvme_release_instance(struct nvme_dev *dev)
1132{
1133}
1134
1135static int __devinit nvme_probe(struct pci_dev *pdev,
1136 const struct pci_device_id *id)
1137{
574e8b95 1138 int bars, result = -ENOMEM;
b60503ba
MW		 1139 struct nvme_dev *dev;
1140
1141 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1142 if (!dev)
1143 return -ENOMEM;
1144 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1145 GFP_KERNEL);
1146 if (!dev->entry)
1147 goto free;
1b23484b
MW		 1148 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1149 GFP_KERNEL);
b60503ba
MW		 1150 if (!dev->queues)
1151 goto free;
1152
0ee5a7d7
SMM		 1153 if (pci_enable_device_mem(pdev))
1154 goto free;
f64d3365 1155 pci_set_master(pdev);
574e8b95
MW		 1156 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1157 if (pci_request_selected_regions(pdev, bars, "nvme"))
1158 goto disable;
0ee5a7d7 1159
b60503ba
MW		 1160 INIT_LIST_HEAD(&dev->namespaces);
1161 dev->pci_dev = pdev;
1162 pci_set_drvdata(pdev, dev);
2930353f
MW		 1163 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1164 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
b60503ba 1165 nvme_set_instance(dev);
53c9577e 1166 dev->entry[0].vector = pdev->irq;
b60503ba
MW		 1167
1168 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1169 if (!dev->bar) {
1170 result = -ENOMEM;
574e8b95 1171 goto disable_msix;
b60503ba
MW		 1172 }
1173
1174 result = nvme_configure_admin_queue(dev);
1175 if (result)
1176 goto unmap;
1177 dev->queue_count++;
1178
1179 result = nvme_dev_add(dev);
1180 if (result)
1181 goto delete;
1182 return 0;
1183
1184 delete:
1185 nvme_free_queues(dev);
1186 unmap:
1187 iounmap(dev->bar);
574e8b95 1188 disable_msix:
b60503ba
MW		 1189 pci_disable_msix(pdev);
1190 nvme_release_instance(dev);
574e8b95 1191 disable:
0ee5a7d7 1192 pci_disable_device(pdev);
574e8b95 1193 pci_release_regions(pdev);
b60503ba
MW		 1194 free:
1195 kfree(dev->queues);
1196 kfree(dev->entry);
1197 kfree(dev);
1198 return result;
1199}
1200
1201static void __devexit nvme_remove(struct pci_dev *pdev)
1202{
1203 struct nvme_dev *dev = pci_get_drvdata(pdev);
1204 nvme_dev_remove(dev);
1205 pci_disable_msix(pdev);
1206 iounmap(dev->bar);
1207 nvme_release_instance(dev);
0ee5a7d7 1208 pci_disable_device(pdev);
574e8b95 1209 pci_release_regions(pdev);
b60503ba
MW		 1210 kfree(dev->queues);
1211 kfree(dev->entry);
1212 kfree(dev);
1213}
1214
1215/* These functions are yet to be implemented */
1216#define nvme_error_detected NULL
1217#define nvme_dump_registers NULL
1218#define nvme_link_reset NULL
1219#define nvme_slot_reset NULL
1220#define nvme_error_resume NULL
1221#define nvme_suspend NULL
1222#define nvme_resume NULL
1223
1224static struct pci_error_handlers nvme_err_handler = {
1225 .error_detected = nvme_error_detected,
1226 .mmio_enabled = nvme_dump_registers,
1227 .link_reset = nvme_link_reset,
1228 .slot_reset = nvme_slot_reset,
1229 .resume = nvme_error_resume,
1230};
1231
1232/* Move to pci_ids.h later */
1233#define PCI_CLASS_STORAGE_EXPRESS 0x010802
1234
1235static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1236 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1237 { 0, }
1238};
1239MODULE_DEVICE_TABLE(pci, nvme_id_table);
1240
1241static struct pci_driver nvme_driver = {
1242 .name = "nvme",
1243 .id_table = nvme_id_table,
1244 .probe = nvme_probe,
1245 .remove = __devexit_p(nvme_remove),
1246 .suspend = nvme_suspend,
1247 .resume = nvme_resume,
1248 .err_handler = &nvme_err_handler,
1249};
1250
1251static int __init nvme_init(void)
1252{
1253 int result;
1254
1255 nvme_major = register_blkdev(nvme_major, "nvme");
1256 if (nvme_major <= 0)
1257 return -EBUSY;
1258
1259 result = pci_register_driver(&nvme_driver);
1260 if (!result)
1261 return 0;
1262
1263 unregister_blkdev(nvme_major, "nvme");
1264 return result;
1265}
1266
1267static void __exit nvme_exit(void)
1268{
1269 pci_unregister_driver(&nvme_driver);
1270 unregister_blkdev(nvme_major, "nvme");
1271}
1272
1273MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1274MODULE_LICENSE("GPL");
db5d0c19 1275MODULE_VERSION("0.2");
b60503ba
MW		 1276module_init(nvme_init);
1277module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)