projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
NVMe: Add NVME_IOCTL_SUBMIT_IO
[linux-2.6-block.git] / drivers / block / nvme.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
21#include <linux/blkdev.h>
22#include <linux/errno.h>
23#include <linux/fs.h>
24#include <linux/genhd.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kdev_t.h>
29#include <linux/kernel.h>
30#include <linux/mm.h>
31#include <linux/module.h>
32#include <linux/moduleparam.h>
33#include <linux/pci.h>
34#include <linux/sched.h>
35#include <linux/slab.h>
36#include <linux/types.h>
37#include <linux/version.h>
38
39#define NVME_Q_DEPTH 1024
40#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
41#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
42#define NVME_MINORS 64
43
44static int nvme_major;
45module_param(nvme_major, int, 0);
46
47/*
48 * Represents an NVM Express device. Each nvme_dev is a PCI function.
49 */
50struct nvme_dev {
51 struct list_head node;
52 struct nvme_queue **queues;
53 u32 __iomem *dbs;
54 struct pci_dev *pci_dev;
55 int instance;
56 int queue_count;
57 u32 ctrl_config;
58 struct msix_entry *entry;
59 struct nvme_bar __iomem *bar;
60 struct list_head namespaces;
61};
62
63/*
64 * An NVM Express namespace is equivalent to a SCSI LUN
65 */
66struct nvme_ns {
67 struct list_head list;
68
69 struct nvme_dev *dev;
70 struct request_queue *queue;
71 struct gendisk *disk;
72
73 int ns_id;
74 int lba_shift;
75};
76
77/*
78 * An NVM Express queue. Each device has at least two (one for admin
79 * commands and one for I/O commands).
80 */
81struct nvme_queue {
82 struct device *q_dmadev;
83 spinlock_t q_lock;
84 struct nvme_command *sq_cmds;
85 volatile struct nvme_completion *cqes;
86 dma_addr_t sq_dma_addr;
87 dma_addr_t cq_dma_addr;
88 wait_queue_head_t sq_full;
89 struct bio_list sq_cong;
90 u32 __iomem *q_db;
91 u16 q_depth;
92 u16 cq_vector;
93 u16 sq_head;
94 u16 sq_tail;
95 u16 cq_head;
82123460 96 u16 cq_phase;
b60503ba
MW		 97 unsigned long cmdid_data[];
98};
99
100/*
101 * Check we didin't inadvertently grow the command struct
102 */
103static inline void _nvme_check_size(void)
104{
105 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
106 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
107 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
108 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
109 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
110 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
111 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
112 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
113 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
114}
115
116/**
117 * alloc_cmdid - Allocate a Command ID
118 * @param nvmeq The queue that will be used for this command
119 * @param ctx A pointer that will be passed to the handler
120 * @param handler The ID of the handler to call
121 *
122 * Allocate a Command ID for a queue. The data passed in will
123 * be passed to the completion handler. This is implemented by using
124 * the bottom two bits of the ctx pointer to store the handler ID.
125 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
126 * We can change this if it becomes a problem.
127 */
128static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler)
129{
130 int depth = nvmeq->q_depth;
131 unsigned long data = (unsigned long)ctx | handler;
132 int cmdid;
133
134 BUG_ON((unsigned long)ctx & 3);
135
136 do {
137 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
138 if (cmdid >= depth)
139 return -EBUSY;
140 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
141
142 nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(depth)] = data;
143 return cmdid;
144}
145
146static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
147 int handler)
148{
149 int cmdid;
150 wait_event_killable(nvmeq->sq_full,
151 (cmdid = alloc_cmdid(nvmeq, ctx, handler)) >= 0);
152 return (cmdid < 0) ? -EINTR : cmdid;
153}
154
155/* If you need more than four handlers, you'll need to change how
156 * alloc_cmdid and nvme_process_cq work
157 */
158enum {
159 sync_completion_id = 0,
160 bio_completion_id,
161};
162
163static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
164{
165 unsigned long data;
166
167 data = nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)];
168 clear_bit(cmdid, nvmeq->cmdid_data);
169 wake_up(&nvmeq->sq_full);
170 return data;
171}
172
173static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
174{
1b23484b
MW		 175 int qid, cpu = get_cpu();
176 if (cpu < ns->dev->queue_count)
177 qid = cpu + 1;
178 else
179 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
180 return ns->dev->queues[qid];
b60503ba
MW		 181}
182
183static void put_nvmeq(struct nvme_queue *nvmeq)
184{
1b23484b 185 put_cpu();
b60503ba
MW		 186}
187
188/**
189 * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
190 * @nvmeq: The queue to use
191 * @cmd: The command to send
192 *
193 * Safe to use from interrupt context
194 */
195static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
196{
197 unsigned long flags;
198 u16 tail;
199 /* XXX: Need to check tail isn't going to overrun head */
200 spin_lock_irqsave(&nvmeq->q_lock, flags);
201 tail = nvmeq->sq_tail;
202 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
203 writel(tail, nvmeq->q_db);
204 if (++tail == nvmeq->q_depth)
205 tail = 0;
206 nvmeq->sq_tail = tail;
207 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
208
209 return 0;
210}
211
212struct nvme_req_info {
213 struct bio *bio;
214 int nents;
215 struct scatterlist sg[0];
216};
217
218/* XXX: use a mempool */
219static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
220{
221 return kmalloc(sizeof(struct nvme_req_info) +
222 sizeof(struct scatterlist) * nseg, gfp);
223}
224
225static void free_info(struct nvme_req_info *info)
226{
227 kfree(info);
228}
229
230static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
231 struct nvme_completion *cqe)
232{
233 struct nvme_req_info *info = ctx;
234 struct bio *bio = info->bio;
235 u16 status = le16_to_cpup(&cqe->status) >> 1;
236
237 dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
238 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
239 free_info(info);
240 bio_endio(bio, status ? -EIO : 0);
241}
242
ff22b54f
MW		 243/* length is in bytes */
244static void nvme_setup_prps(struct nvme_common_command *cmd,
245 struct scatterlist *sg, int length)
246{
247 int dma_len = sg_dma_len(sg);
248 u64 dma_addr = sg_dma_address(sg);
249 int offset = offset_in_page(dma_addr);
250
251 cmd->prp1 = cpu_to_le64(dma_addr);
252 length -= (PAGE_SIZE - offset);
253 if (length <= 0)
254 return;
255
256 dma_len -= (PAGE_SIZE - offset);
257 if (dma_len) {
258 dma_addr += (PAGE_SIZE - offset);
259 } else {
260 sg = sg_next(sg);
261 dma_addr = sg_dma_address(sg);
262 dma_len = sg_dma_len(sg);
263 }
264
265 if (length <= PAGE_SIZE) {
266 cmd->prp2 = cpu_to_le64(dma_addr);
267 return;
268 }
269
270 /* XXX: support PRP lists */
271}
272
b60503ba
MW		 273static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
274 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
275{
276 struct bio_vec *bvec;
277 struct scatterlist *sg = info->sg;
278 int i, nsegs;
279
280 sg_init_table(sg, psegs);
281 bio_for_each_segment(bvec, bio, i) {
282 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
283 /* XXX: handle non-mergable here */
284 nsegs++;
285 }
286 info->nents = nsegs;
287
288 return dma_map_sg(dev, info->sg, info->nents, dma_dir);
289}
290
291static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
292 struct bio *bio)
293{
ff22b54f 294 struct nvme_command *cmnd;
b60503ba
MW		 295 struct nvme_req_info *info;
296 enum dma_data_direction dma_dir;
297 int cmdid;
298 u16 control;
299 u32 dsmgmt;
300 unsigned long flags;
301 int psegs = bio_phys_segments(ns->queue, bio);
302
303 info = alloc_info(psegs, GFP_NOIO);
304 if (!info)
305 goto congestion;
306 info->bio = bio;
307
308 cmdid = alloc_cmdid(nvmeq, info, bio_completion_id);
309 if (unlikely(cmdid < 0))
310 goto free_info;
311
312 control = 0;
313 if (bio->bi_rw & REQ_FUA)
314 control |= NVME_RW_FUA;
315 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
316 control |= NVME_RW_LR;
317
318 dsmgmt = 0;
319 if (bio->bi_rw & REQ_RAHEAD)
320 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
321
322 spin_lock_irqsave(&nvmeq->q_lock, flags);
ff22b54f 323 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 324
b8deb62c 325 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 326 if (bio_data_dir(bio)) {
ff22b54f 327 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW		 328 dma_dir = DMA_TO_DEVICE;
329 } else {
ff22b54f 330 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW		 331 dma_dir = DMA_FROM_DEVICE;
332 }
333
334 nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
335
ff22b54f
MW		 336 cmnd->rw.flags = 1;
337 cmnd->rw.command_id = cmdid;
338 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
339 nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
340 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
341 cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
342 cmnd->rw.control = cpu_to_le16(control);
343 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba
MW		 344
345 writel(nvmeq->sq_tail, nvmeq->q_db);
346 if (++nvmeq->sq_tail == nvmeq->q_depth)
347 nvmeq->sq_tail = 0;
348
349 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
350
351 return 0;
352
353 free_info:
354 free_info(info);
355 congestion:
356 return -EBUSY;
357}
358
359/*
360 * NB: return value of non-zero would mean that we were a stacking driver.
361 * make_request must always succeed.
362 */
363static int nvme_make_request(struct request_queue *q, struct bio *bio)
364{
365 struct nvme_ns *ns = q->queuedata;
366 struct nvme_queue *nvmeq = get_nvmeq(ns);
367
368 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
369 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
370 bio_list_add(&nvmeq->sq_cong, bio);
371 }
372 put_nvmeq(nvmeq);
373
374 return 0;
375}
376
377struct sync_cmd_info {
378 struct task_struct *task;
379 u32 result;
380 int status;
381};
382
383static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
384 struct nvme_completion *cqe)
385{
386 struct sync_cmd_info *cmdinfo = ctx;
387 cmdinfo->result = le32_to_cpup(&cqe->result);
388 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
389 wake_up_process(cmdinfo->task);
390}
391
392typedef void (*completion_fn)(struct nvme_queue *, void *,
393 struct nvme_completion *);
394
395static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
396{
82123460 397 u16 head, phase;
b60503ba
MW		 398
399 static const completion_fn completions[4] = {
400 [sync_completion_id] = sync_completion,
401 [bio_completion_id] = bio_completion,
402 };
403
404 head = nvmeq->cq_head;
82123460 405 phase = nvmeq->cq_phase;
b60503ba
MW		 406
407 for (;;) {
408 unsigned long data;
409 void *ptr;
410 unsigned char handler;
411 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 412 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 413 break;
414 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
415 if (++head == nvmeq->q_depth) {
416 head = 0;
82123460 417 phase = !phase;
b60503ba
MW		 418 }
419
420 data = free_cmdid(nvmeq, cqe.command_id);
421 handler = data & 3;
422 ptr = (void *)(data & ~3UL);
423 completions[handler](nvmeq, ptr, &cqe);
424 }
425
426 /* If the controller ignores the cq head doorbell and continuously
427 * writes to the queue, it is theoretically possible to wrap around
428 * the queue twice and mistakenly return IRQ_NONE. Linux only
429 * requires that 0.1% of your interrupts are handled, so this isn't
430 * a big problem.
431 */
82123460 432 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
b60503ba
MW		 433 return IRQ_NONE;
434
435 writel(head, nvmeq->q_db + 1);
436 nvmeq->cq_head = head;
82123460 437 nvmeq->cq_phase = phase;
b60503ba
MW		 438
439 return IRQ_HANDLED;
440}
441
442static irqreturn_t nvme_irq(int irq, void *data)
443{
444 return nvme_process_cq(data);
445}
446
447/*
448 * Returns 0 on success. If the result is negative, it's a Linux error code;
449 * if the result is positive, it's an NVM Express status code
450 */
451static int nvme_submit_sync_cmd(struct nvme_queue *q, struct nvme_command *cmd,
452 u32 *result)
453{
454 int cmdid;
455 struct sync_cmd_info cmdinfo;
456
457 cmdinfo.task = current;
458 cmdinfo.status = -EINTR;
459
460 cmdid = alloc_cmdid_killable(q, &cmdinfo, sync_completion_id);
461 if (cmdid < 0)
462 return cmdid;
463 cmd->common.command_id = cmdid;
464
465 set_current_state(TASK_UNINTERRUPTIBLE);
466 nvme_submit_cmd(q, cmd);
467 schedule();
468
469 if (result)
470 *result = cmdinfo.result;
471
472 return cmdinfo.status;
473}
474
475static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
476 u32 *result)
477{
478 return nvme_submit_sync_cmd(dev->queues[0], cmd, result);
479}
480
481static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
482{
483 int status;
484 struct nvme_command c;
485
486 memset(&c, 0, sizeof(c));
487 c.delete_queue.opcode = opcode;
488 c.delete_queue.qid = cpu_to_le16(id);
489
490 status = nvme_submit_admin_cmd(dev, &c, NULL);
491 if (status)
492 return -EIO;
493 return 0;
494}
495
496static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
497 struct nvme_queue *nvmeq)
498{
499 int status;
500 struct nvme_command c;
501 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
502
503 memset(&c, 0, sizeof(c));
504 c.create_cq.opcode = nvme_admin_create_cq;
505 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
506 c.create_cq.cqid = cpu_to_le16(qid);
507 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
508 c.create_cq.cq_flags = cpu_to_le16(flags);
509 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
510
511 status = nvme_submit_admin_cmd(dev, &c, NULL);
512 if (status)
513 return -EIO;
514 return 0;
515}
516
517static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
518 struct nvme_queue *nvmeq)
519{
520 int status;
521 struct nvme_command c;
522 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
523
524 memset(&c, 0, sizeof(c));
525 c.create_sq.opcode = nvme_admin_create_sq;
526 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
527 c.create_sq.sqid = cpu_to_le16(qid);
528 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
529 c.create_sq.sq_flags = cpu_to_le16(flags);
530 c.create_sq.cqid = cpu_to_le16(qid);
531
532 status = nvme_submit_admin_cmd(dev, &c, NULL);
533 if (status)
534 return -EIO;
535 return 0;
536}
537
538static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
539{
540 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
541}
542
543static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
544{
545 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
546}
547
548static void nvme_free_queue(struct nvme_dev *dev, int qid)
549{
550 struct nvme_queue *nvmeq = dev->queues[qid];
551
552 free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
553
554 /* Don't tell the adapter to delete the admin queue */
555 if (qid) {
556 adapter_delete_sq(dev, qid);
557 adapter_delete_cq(dev, qid);
558 }
559
560 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
561 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
562 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
563 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
564 kfree(nvmeq);
565}
566
567static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
568 int depth, int vector)
569{
570 struct device *dmadev = &dev->pci_dev->dev;
571 unsigned extra = (depth + BITS_TO_LONGS(depth)) * sizeof(long);
572 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
573 if (!nvmeq)
574 return NULL;
575
576 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
577 &nvmeq->cq_dma_addr, GFP_KERNEL);
578 if (!nvmeq->cqes)
579 goto free_nvmeq;
580 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
581
582 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
583 &nvmeq->sq_dma_addr, GFP_KERNEL);
584 if (!nvmeq->sq_cmds)
585 goto free_cqdma;
586
587 nvmeq->q_dmadev = dmadev;
588 spin_lock_init(&nvmeq->q_lock);
589 nvmeq->cq_head = 0;
82123460 590 nvmeq->cq_phase = 1;
b60503ba
MW		 591 init_waitqueue_head(&nvmeq->sq_full);
592 bio_list_init(&nvmeq->sq_cong);
593 nvmeq->q_db = &dev->dbs[qid * 2];
594 nvmeq->q_depth = depth;
595 nvmeq->cq_vector = vector;
596
597 return nvmeq;
598
599 free_cqdma:
600 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
601 nvmeq->cq_dma_addr);
602 free_nvmeq:
603 kfree(nvmeq);
604 return NULL;
605}
606
3001082c
MW		 607static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
608 const char *name)
609{
610 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
611 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
612}
613
b60503ba
MW		 614static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
615 int qid, int cq_size, int vector)
616{
617 int result;
618 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
619
620 result = adapter_alloc_cq(dev, qid, nvmeq);
621 if (result < 0)
622 goto free_nvmeq;
623
624 result = adapter_alloc_sq(dev, qid, nvmeq);
625 if (result < 0)
626 goto release_cq;
627
3001082c 628 result = queue_request_irq(dev, nvmeq, "nvme");
b60503ba
MW		 629 if (result < 0)
630 goto release_sq;
631
632 return nvmeq;
633
634 release_sq:
635 adapter_delete_sq(dev, qid);
636 release_cq:
637 adapter_delete_cq(dev, qid);
638 free_nvmeq:
639 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
640 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
641 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
642 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
643 kfree(nvmeq);
644 return NULL;
645}
646
647static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
648{
649 int result;
650 u32 aqa;
651 struct nvme_queue *nvmeq;
652
653 dev->dbs = ((void __iomem *)dev->bar) + 4096;
654
655 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
656
657 aqa = nvmeq->q_depth - 1;
658 aqa |= aqa << 16;
659
660 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
661 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
662 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
663
664 writel(aqa, &dev->bar->aqa);
665 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
666 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
667 writel(dev->ctrl_config, &dev->bar->cc);
668
669 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
670 msleep(100);
671 if (fatal_signal_pending(current))
672 return -EINTR;
673 }
674
3001082c 675 result = queue_request_irq(dev, nvmeq, "nvme admin");
b60503ba
MW		 676 dev->queues[0] = nvmeq;
677 return result;
678}
679
7fc3cdab
MW		 680static int nvme_map_user_pages(struct nvme_dev *dev, int write,
681 unsigned long addr, unsigned length,
682 struct scatterlist **sgp)
b60503ba 683{
36c14ed9 684 int i, err, count, nents, offset;
7fc3cdab
MW		 685 struct scatterlist *sg;
686 struct page **pages;
36c14ed9
MW		 687
688 if (addr & 3)
689 return -EINVAL;
7fc3cdab
MW		 690 if (!length)
691 return -EINVAL;
692
36c14ed9 693 offset = offset_in_page(addr);
7fc3cdab
MW		 694 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
695 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
36c14ed9
MW		 696
697 err = get_user_pages_fast(addr, count, 1, pages);
698 if (err < count) {
699 count = err;
700 err = -EFAULT;
701 goto put_pages;
702 }
7fc3cdab
MW		 703
704 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
36c14ed9 705 sg_init_table(sg, count);
ff22b54f 706 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
7fc3cdab
MW		 707 length -= (PAGE_SIZE - offset);
708 for (i = 1; i < count; i++) {
709 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
710 length -= PAGE_SIZE;
711 }
712
713 err = -ENOMEM;
714 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
715 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9
MW		 716 if (!nents)
717 goto put_pages;
b60503ba 718
7fc3cdab
MW		 719 kfree(pages);
720 *sgp = sg;
721 return nents;
b60503ba 722
7fc3cdab
MW		 723 put_pages:
724 for (i = 0; i < count; i++)
725 put_page(pages[i]);
726 kfree(pages);
727 return err;
728}
b60503ba 729
7fc3cdab
MW		 730static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
731 unsigned long addr, int length,
732 struct scatterlist *sg, int nents)
733{
734 int i, count;
b60503ba 735
7fc3cdab 736 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
36c14ed9 737 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
7fc3cdab 738
36c14ed9 739 for (i = 0; i < count; i++)
7fc3cdab
MW		 740 put_page(sg_page(&sg[i]));
741}
b60503ba 742
7fc3cdab
MW		 743static int nvme_submit_user_admin_command(struct nvme_dev *dev,
744 unsigned long addr, unsigned length,
745 struct nvme_command *cmd)
746{
747 int err, nents;
748 struct scatterlist *sg;
749
750 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
751 if (nents < 0)
752 return nents;
753 nvme_setup_prps(&cmd->common, sg, length);
754 err = nvme_submit_admin_cmd(dev, cmd, NULL);
755 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
756 return err ? -EIO : 0;
b60503ba
MW		 757}
758
bd38c555 759static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
b60503ba 760{
b60503ba 761 struct nvme_command c;
b60503ba 762
bd38c555
MW		 763 memset(&c, 0, sizeof(c));
764 c.identify.opcode = nvme_admin_identify;
765 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
766 c.identify.cns = cpu_to_le32(cns);
767
768 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
769}
770
771static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
772{
773 struct nvme_command c;
b60503ba
MW		 774
775 memset(&c, 0, sizeof(c));
776 c.features.opcode = nvme_admin_get_features;
777 c.features.nsid = cpu_to_le32(ns->ns_id);
b60503ba
MW		 778 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
779
bd38c555 780 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
b60503ba
MW		 781}
782
a53295b6
MW		 783static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
784{
785 struct nvme_dev *dev = ns->dev;
786 struct nvme_queue *nvmeq;
787 struct nvme_user_io io;
788 struct nvme_command c;
789 unsigned length;
790 u32 result;
791 int nents, status;
792 struct scatterlist *sg;
793
794 if (copy_from_user(&io, uio, sizeof(io)))
795 return -EFAULT;
796 length = io.nblocks << io.block_shift;
797 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
798 if (nents < 0)
799 return nents;
800
801 memset(&c, 0, sizeof(c));
802 c.rw.opcode = io.opcode;
803 c.rw.flags = io.flags;
804 c.rw.nsid = cpu_to_le32(io.nsid);
805 c.rw.slba = cpu_to_le64(io.slba);
806 c.rw.length = cpu_to_le16(io.nblocks - 1);
807 c.rw.control = cpu_to_le16(io.control);
808 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
809 c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */
810 c.rw.apptag = cpu_to_le16(io.apptag);
811 c.rw.appmask = cpu_to_le16(io.appmask);
812 /* XXX: metadata */
813 nvme_setup_prps(&c.common, sg, length);
814
815 nvmeq = get_nvmeq(ns);
816 status = nvme_submit_sync_cmd(nvmeq, &c, &result);
817 put_nvmeq(nvmeq);
818
819 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
820 put_user(result, &uio->result);
821 return status;
822}
823
b60503ba
MW		 824static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
825 unsigned long arg)
826{
827 struct nvme_ns *ns = bdev->bd_disk->private_data;
828
829 switch (cmd) {
830 case NVME_IOCTL_IDENTIFY_NS:
36c14ed9 831 return nvme_identify(ns, arg, 0);
b60503ba 832 case NVME_IOCTL_IDENTIFY_CTRL:
36c14ed9 833 return nvme_identify(ns, arg, 1);
b60503ba 834 case NVME_IOCTL_GET_RANGE_TYPE:
bd38c555 835 return nvme_get_range_type(ns, arg);
a53295b6
MW		 836 case NVME_IOCTL_SUBMIT_IO:
837 return nvme_submit_io(ns, (void __user *)arg);
b60503ba
MW		 838 default:
839 return -ENOTTY;
840 }
841}
842
843static const struct block_device_operations nvme_fops = {
844 .owner = THIS_MODULE,
845 .ioctl = nvme_ioctl,
846};
847
848static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
849 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
850{
851 struct nvme_ns *ns;
852 struct gendisk *disk;
853 int lbaf;
854
855 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
856 return NULL;
857
858 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
859 if (!ns)
860 return NULL;
861 ns->queue = blk_alloc_queue(GFP_KERNEL);
862 if (!ns->queue)
863 goto out_free_ns;
864 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
865 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
866 blk_queue_make_request(ns->queue, nvme_make_request);
867 ns->dev = dev;
868 ns->queue->queuedata = ns;
869
870 disk = alloc_disk(NVME_MINORS);
871 if (!disk)
872 goto out_free_queue;
873 ns->ns_id = index;
874 ns->disk = disk;
875 lbaf = id->flbas & 0xf;
876 ns->lba_shift = id->lbaf[lbaf].ds;
877
878 disk->major = nvme_major;
879 disk->minors = NVME_MINORS;
880 disk->first_minor = NVME_MINORS * index;
881 disk->fops = &nvme_fops;
882 disk->private_data = ns;
883 disk->queue = ns->queue;
884 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
885 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
886
887 return ns;
888
889 out_free_queue:
890 blk_cleanup_queue(ns->queue);
891 out_free_ns:
892 kfree(ns);
893 return NULL;
894}
895
896static void nvme_ns_free(struct nvme_ns *ns)
897{
898 put_disk(ns->disk);
899 blk_cleanup_queue(ns->queue);
900 kfree(ns);
901}
902
b3b06812 903static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 904{
905 int status;
906 u32 result;
907 struct nvme_command c;
b3b06812 908 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba
MW		 909
910 memset(&c, 0, sizeof(c));
911 c.features.opcode = nvme_admin_get_features;
912 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
913 c.features.dword11 = cpu_to_le32(q_count);
914
915 status = nvme_submit_admin_cmd(dev, &c, &result);
916 if (status)
917 return -EIO;
918 return min(result & 0xffff, result >> 16) + 1;
919}
920
b60503ba
MW		 921static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
922{
1b23484b 923 int result, cpu, i, nr_queues;
b60503ba 924
1b23484b
MW		 925 nr_queues = num_online_cpus();
926 result = set_queue_count(dev, nr_queues);
927 if (result < 0)
928 return result;
929 if (result < nr_queues)
930 nr_queues = result;
b60503ba 931
1b23484b
MW		 932 /* Deregister the admin queue's interrupt */
933 free_irq(dev->entry[0].vector, dev->queues[0]);
934
935 for (i = 0; i < nr_queues; i++)
936 dev->entry[i].entry = i;
937 for (;;) {
938 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
939 if (result == 0) {
940 break;
941 } else if (result > 0) {
942 nr_queues = result;
943 continue;
944 } else {
945 nr_queues = 1;
946 break;
947 }
948 }
949
950 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
951 /* XXX: handle failure here */
952
953 cpu = cpumask_first(cpu_online_mask);
954 for (i = 0; i < nr_queues; i++) {
955 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
956 cpu = cpumask_next(cpu, cpu_online_mask);
957 }
958
959 for (i = 0; i < nr_queues; i++) {
960 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
961 NVME_Q_DEPTH, i);
962 if (!dev->queues[i + 1])
963 return -ENOMEM;
964 dev->queue_count++;
965 }
b60503ba
MW		 966
967 return 0;
968}
969
970static void nvme_free_queues(struct nvme_dev *dev)
971{
972 int i;
973
974 for (i = dev->queue_count - 1; i >= 0; i--)
975 nvme_free_queue(dev, i);
976}
977
978static int __devinit nvme_dev_add(struct nvme_dev *dev)
979{
980 int res, nn, i;
981 struct nvme_ns *ns, *next;
982 void *id;
983 dma_addr_t dma_addr;
984 struct nvme_command cid, crt;
985
986 res = nvme_setup_io_queues(dev);
987 if (res)
988 return res;
989
990 /* XXX: Switch to a SG list once prp2 works */
991 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
992 GFP_KERNEL);
993
994 memset(&cid, 0, sizeof(cid));
995 cid.identify.opcode = nvme_admin_identify;
996 cid.identify.nsid = 0;
997 cid.identify.prp1 = cpu_to_le64(dma_addr);
998 cid.identify.cns = cpu_to_le32(1);
999
1000 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1001 if (res) {
1002 res = -EIO;
1003 goto out_free;
1004 }
1005
1006 nn = le32_to_cpup(&((struct nvme_id_ctrl *)id)->nn);
1007
1008 cid.identify.cns = 0;
1009 memset(&crt, 0, sizeof(crt));
1010 crt.features.opcode = nvme_admin_get_features;
1011 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1012 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1013
1014 for (i = 0; i < nn; i++) {
1015 cid.identify.nsid = cpu_to_le32(i);
1016 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1017 if (res)
1018 continue;
1019
1020 if (((struct nvme_id_ns *)id)->ncap == 0)
1021 continue;
1022
1023 crt.features.nsid = cpu_to_le32(i);
1024 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1025 if (res)
1026 continue;
1027
1028 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1029 if (ns)
1030 list_add_tail(&ns->list, &dev->namespaces);
1031 }
1032 list_for_each_entry(ns, &dev->namespaces, list)
1033 add_disk(ns->disk);
1034
1035 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1036 return 0;
1037
1038 out_free:
1039 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1040 list_del(&ns->list);
1041 nvme_ns_free(ns);
1042 }
1043
1044 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1045 return res;
1046}
1047
1048static int nvme_dev_remove(struct nvme_dev *dev)
1049{
1050 struct nvme_ns *ns, *next;
1051
1052 /* TODO: wait all I/O finished or cancel them */
1053
1054 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1055 list_del(&ns->list);
1056 del_gendisk(ns->disk);
1057 nvme_ns_free(ns);
1058 }
1059
1060 nvme_free_queues(dev);
1061
1062 return 0;
1063}
1064
1065/* XXX: Use an ida or something to let remove / add work correctly */
1066static void nvme_set_instance(struct nvme_dev *dev)
1067{
1068 static int instance;
1069 dev->instance = instance++;
1070}
1071
1072static void nvme_release_instance(struct nvme_dev *dev)
1073{
1074}
1075
1076static int __devinit nvme_probe(struct pci_dev *pdev,
1077 const struct pci_device_id *id)
1078{
1079 int result = -ENOMEM;
1080 struct nvme_dev *dev;
1081
1082 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1083 if (!dev)
1084 return -ENOMEM;
1085 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1086 GFP_KERNEL);
1087 if (!dev->entry)
1088 goto free;
1b23484b
MW		 1089 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1090 GFP_KERNEL);
b60503ba
MW		 1091 if (!dev->queues)
1092 goto free;
1093
1094 INIT_LIST_HEAD(&dev->namespaces);
1095 dev->pci_dev = pdev;
1096 pci_set_drvdata(pdev, dev);
1097 dma_set_mask(&dev->pci_dev->dev, DMA_BIT_MASK(64));
1098 nvme_set_instance(dev);
53c9577e 1099 dev->entry[0].vector = pdev->irq;
b60503ba
MW		 1100
1101 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1102 if (!dev->bar) {
1103 result = -ENOMEM;
1104 goto disable;
1105 }
1106
1107 result = nvme_configure_admin_queue(dev);
1108 if (result)
1109 goto unmap;
1110 dev->queue_count++;
1111
1112 result = nvme_dev_add(dev);
1113 if (result)
1114 goto delete;
1115 return 0;
1116
1117 delete:
1118 nvme_free_queues(dev);
1119 unmap:
1120 iounmap(dev->bar);
1121 disable:
1122 pci_disable_msix(pdev);
1123 nvme_release_instance(dev);
1124 free:
1125 kfree(dev->queues);
1126 kfree(dev->entry);
1127 kfree(dev);
1128 return result;
1129}
1130
1131static void __devexit nvme_remove(struct pci_dev *pdev)
1132{
1133 struct nvme_dev *dev = pci_get_drvdata(pdev);
1134 nvme_dev_remove(dev);
1135 pci_disable_msix(pdev);
1136 iounmap(dev->bar);
1137 nvme_release_instance(dev);
1138 kfree(dev->queues);
1139 kfree(dev->entry);
1140 kfree(dev);
1141}
1142
1143/* These functions are yet to be implemented */
1144#define nvme_error_detected NULL
1145#define nvme_dump_registers NULL
1146#define nvme_link_reset NULL
1147#define nvme_slot_reset NULL
1148#define nvme_error_resume NULL
1149#define nvme_suspend NULL
1150#define nvme_resume NULL
1151
1152static struct pci_error_handlers nvme_err_handler = {
1153 .error_detected = nvme_error_detected,
1154 .mmio_enabled = nvme_dump_registers,
1155 .link_reset = nvme_link_reset,
1156 .slot_reset = nvme_slot_reset,
1157 .resume = nvme_error_resume,
1158};
1159
1160/* Move to pci_ids.h later */
1161#define PCI_CLASS_STORAGE_EXPRESS 0x010802
1162
1163static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1164 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1165 { 0, }
1166};
1167MODULE_DEVICE_TABLE(pci, nvme_id_table);
1168
1169static struct pci_driver nvme_driver = {
1170 .name = "nvme",
1171 .id_table = nvme_id_table,
1172 .probe = nvme_probe,
1173 .remove = __devexit_p(nvme_remove),
1174 .suspend = nvme_suspend,
1175 .resume = nvme_resume,
1176 .err_handler = &nvme_err_handler,
1177};
1178
1179static int __init nvme_init(void)
1180{
1181 int result;
1182
1183 nvme_major = register_blkdev(nvme_major, "nvme");
1184 if (nvme_major <= 0)
1185 return -EBUSY;
1186
1187 result = pci_register_driver(&nvme_driver);
1188 if (!result)
1189 return 0;
1190
1191 unregister_blkdev(nvme_major, "nvme");
1192 return result;
1193}
1194
1195static void __exit nvme_exit(void)
1196{
1197 pci_unregister_driver(&nvme_driver);
1198 unregister_blkdev(nvme_major, "nvme");
1199}
1200
1201MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1202MODULE_LICENSE("GPL");
1203MODULE_VERSION("0.1");
1204module_init(nvme_init);
1205module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)