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NVMe: Switch to use DMA Pool API
[linux-2.6-block.git] / drivers / block / nvme.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
21#include <linux/blkdev.h>
22#include <linux/errno.h>
23#include <linux/fs.h>
24#include <linux/genhd.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kdev_t.h>
29#include <linux/kernel.h>
30#include <linux/mm.h>
31#include <linux/module.h>
32#include <linux/moduleparam.h>
33#include <linux/pci.h>
be7b6275 34#include <linux/poison.h>
b60503ba
MW		 35#include <linux/sched.h>
36#include <linux/slab.h>
37#include <linux/types.h>
38#include <linux/version.h>
39
40#define NVME_Q_DEPTH 1024
41#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
42#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
43#define NVME_MINORS 64
e85248e5
MW		 44#define IO_TIMEOUT (5 * HZ)
45#define ADMIN_TIMEOUT (60 * HZ)
b60503ba
MW		 46
47static int nvme_major;
48module_param(nvme_major, int, 0);
49
58ffacb5
MW		 50static int use_threaded_interrupts;
51module_param(use_threaded_interrupts, int, 0);
52
b60503ba
MW		 53/*
54 * Represents an NVM Express device. Each nvme_dev is a PCI function.
55 */
56struct nvme_dev {
b60503ba
MW		 57 struct nvme_queue **queues;
58 u32 __iomem *dbs;
59 struct pci_dev *pci_dev;
091b6092 60 struct dma_pool *prp_page_pool;
b60503ba
MW		 61 int instance;
62 int queue_count;
63 u32 ctrl_config;
64 struct msix_entry *entry;
65 struct nvme_bar __iomem *bar;
66 struct list_head namespaces;
51814232
MW		 67 char serial[20];
68 char model[40];
69 char firmware_rev[8];
b60503ba
MW		 70};
71
72/*
73 * An NVM Express namespace is equivalent to a SCSI LUN
74 */
75struct nvme_ns {
76 struct list_head list;
77
78 struct nvme_dev *dev;
79 struct request_queue *queue;
80 struct gendisk *disk;
81
82 int ns_id;
83 int lba_shift;
84};
85
86/*
87 * An NVM Express queue. Each device has at least two (one for admin
88 * commands and one for I/O commands).
89 */
90struct nvme_queue {
91 struct device *q_dmadev;
091b6092 92 struct nvme_dev *dev;
b60503ba
MW		 93 spinlock_t q_lock;
94 struct nvme_command *sq_cmds;
95 volatile struct nvme_completion *cqes;
96 dma_addr_t sq_dma_addr;
97 dma_addr_t cq_dma_addr;
98 wait_queue_head_t sq_full;
99 struct bio_list sq_cong;
100 u32 __iomem *q_db;
101 u16 q_depth;
102 u16 cq_vector;
103 u16 sq_head;
104 u16 sq_tail;
105 u16 cq_head;
82123460 106 u16 cq_phase;
b60503ba
MW		 107 unsigned long cmdid_data[];
108};
109
9294bbed
MW		 110static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio);
111
b60503ba
MW		 112/*
113 * Check we didin't inadvertently grow the command struct
114 */
115static inline void _nvme_check_size(void)
116{
117 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
118 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
119 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
120 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
121 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
122 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
123 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
124 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
125 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
126}
127
e85248e5
MW		 128struct nvme_cmd_info {
129 unsigned long ctx;
130 unsigned long timeout;
131};
132
133static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
134{
135 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
136}
137
b60503ba
MW		 138/**
139 * alloc_cmdid - Allocate a Command ID
140 * @param nvmeq The queue that will be used for this command
141 * @param ctx A pointer that will be passed to the handler
142 * @param handler The ID of the handler to call
143 *
144 * Allocate a Command ID for a queue. The data passed in will
145 * be passed to the completion handler. This is implemented by using
146 * the bottom two bits of the ctx pointer to store the handler ID.
147 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
148 * We can change this if it becomes a problem.
149 */
e85248e5
MW		 150static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
151 unsigned timeout)
b60503ba
MW		 152{
153 int depth = nvmeq->q_depth;
e85248e5 154 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 155 int cmdid;
156
157 BUG_ON((unsigned long)ctx & 3);
158
159 do {
160 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
161 if (cmdid >= depth)
162 return -EBUSY;
163 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
164
e85248e5
MW		 165 info[cmdid].ctx = (unsigned long)ctx | handler;
166 info[cmdid].timeout = jiffies + timeout;
b60503ba
MW		 167 return cmdid;
168}
169
170static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
e85248e5 171 int handler, unsigned timeout)
b60503ba
MW		 172{
173 int cmdid;
174 wait_event_killable(nvmeq->sq_full,
e85248e5 175 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 176 return (cmdid < 0) ? -EINTR : cmdid;
177}
178
179/* If you need more than four handlers, you'll need to change how
be7b6275
MW		 180 * alloc_cmdid and nvme_process_cq work. Consider using a special
181 * CMD_CTX value instead, if that works for your situation.
b60503ba
MW		 182 */
183enum {
184 sync_completion_id = 0,
185 bio_completion_id,
186};
187
be7b6275 188#define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
d2d87034
MW		 189#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
190#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
191#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 192
b60503ba
MW		 193static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
194{
195 unsigned long data;
e85248e5 196 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 197
e85248e5 198 if (cmdid >= nvmeq->q_depth)
48e3d398 199 return CMD_CTX_INVALID;
e85248e5
MW		 200 data = info[cmdid].ctx;
201 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 202 clear_bit(cmdid, nvmeq->cmdid_data);
203 wake_up(&nvmeq->sq_full);
204 return data;
205}
206
be7b6275 207static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
3c0cf138 208{
e85248e5
MW		 209 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
210 info[cmdid].ctx = CMD_CTX_CANCELLED;
3c0cf138
MW		 211}
212
b60503ba
MW		 213static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
214{
1b23484b
MW		 215 int qid, cpu = get_cpu();
216 if (cpu < ns->dev->queue_count)
217 qid = cpu + 1;
218 else
219 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
220 return ns->dev->queues[qid];
b60503ba
MW		 221}
222
223static void put_nvmeq(struct nvme_queue *nvmeq)
224{
1b23484b 225 put_cpu();
b60503ba
MW		 226}
227
228/**
229 * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
230 * @nvmeq: The queue to use
231 * @cmd: The command to send
232 *
233 * Safe to use from interrupt context
234 */
235static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
236{
237 unsigned long flags;
238 u16 tail;
239 /* XXX: Need to check tail isn't going to overrun head */
240 spin_lock_irqsave(&nvmeq->q_lock, flags);
241 tail = nvmeq->sq_tail;
242 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
243 writel(tail, nvmeq->q_db);
244 if (++tail == nvmeq->q_depth)
245 tail = 0;
246 nvmeq->sq_tail = tail;
247 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
248
249 return 0;
250}
251
091b6092 252static __le64 *alloc_prp_list(struct nvme_dev *dev, dma_addr_t *addr)
e025344c 253{
091b6092 254 return dma_pool_alloc(dev->prp_page_pool, GFP_ATOMIC, addr);
e025344c
SMM		 255}
256
257struct nvme_prps {
258 int npages;
259 dma_addr_t first_dma;
260 __le64 *list[0];
261};
262
263static void nvme_free_prps(struct nvme_queue *nvmeq, struct nvme_prps *prps)
264{
265 const int last_prp = PAGE_SIZE / 8 - 1;
091b6092 266 struct nvme_dev *dev = nvmeq->dev;
e025344c
SMM		 267 int i;
268 dma_addr_t prp_dma;
269
270 if (!prps)
271 return;
272
273 prp_dma = prps->first_dma;
274 for (i = 0; i < prps->npages; i++) {
275 __le64 *prp_list = prps->list[i];
276 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
091b6092 277 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
e025344c
SMM		 278 prp_dma = next_prp_dma;
279 }
280 kfree(prps);
281}
282
d534df3c 283struct nvme_bio {
b60503ba
MW		 284 struct bio *bio;
285 int nents;
e025344c 286 struct nvme_prps *prps;
b60503ba
MW		 287 struct scatterlist sg[0];
288};
289
290/* XXX: use a mempool */
d534df3c 291static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
b60503ba 292{
d534df3c 293 return kzalloc(sizeof(struct nvme_bio) +
b60503ba
MW		 294 sizeof(struct scatterlist) * nseg, gfp);
295}
296
d534df3c 297static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
b60503ba 298{
d534df3c
MW		 299 nvme_free_prps(nvmeq, nbio->prps);
300 kfree(nbio);
b60503ba
MW		 301}
302
303static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
304 struct nvme_completion *cqe)
305{
d534df3c
MW		 306 struct nvme_bio *nbio = ctx;
307 struct bio *bio = nbio->bio;
b60503ba
MW		 308 u16 status = le16_to_cpup(&cqe->status) >> 1;
309
d534df3c 310 dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
b60503ba 311 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
d534df3c 312 free_nbio(nvmeq, nbio);
b60503ba 313 bio_endio(bio, status ? -EIO : 0);
9294bbed
MW		 314 bio = bio_list_pop(&nvmeq->sq_cong);
315 if (bio)
316 nvme_resubmit_bio(nvmeq, bio);
b60503ba
MW		 317}
318
ff22b54f 319/* length is in bytes */
e025344c
SMM		 320static struct nvme_prps *nvme_setup_prps(struct nvme_queue *nvmeq,
321 struct nvme_common_command *cmd,
ff22b54f
MW		 322 struct scatterlist *sg, int length)
323{
091b6092 324 struct nvme_dev *dev = nvmeq->dev;
ff22b54f
MW		 325 int dma_len = sg_dma_len(sg);
326 u64 dma_addr = sg_dma_address(sg);
327 int offset = offset_in_page(dma_addr);
e025344c
SMM		 328 __le64 *prp_list;
329 dma_addr_t prp_dma;
330 int nprps, npages, i, prp_page;
331 struct nvme_prps *prps = NULL;
ff22b54f
MW		 332
333 cmd->prp1 = cpu_to_le64(dma_addr);
334 length -= (PAGE_SIZE - offset);
335 if (length <= 0)
e025344c 336 return prps;
ff22b54f
MW		 337
338 dma_len -= (PAGE_SIZE - offset);
339 if (dma_len) {
340 dma_addr += (PAGE_SIZE - offset);
341 } else {
342 sg = sg_next(sg);
343 dma_addr = sg_dma_address(sg);
344 dma_len = sg_dma_len(sg);
345 }
346
347 if (length <= PAGE_SIZE) {
348 cmd->prp2 = cpu_to_le64(dma_addr);
e025344c
SMM		 349 return prps;
350 }
351
352 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
353 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
354 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
355 prps->npages = npages;
356 prp_page = 0;
091b6092 357 prp_list = alloc_prp_list(dev, &prp_dma);
e025344c
SMM		 358 prps->list[prp_page++] = prp_list;
359 prps->first_dma = prp_dma;
360 cmd->prp2 = cpu_to_le64(prp_dma);
361 i = 0;
362 for (;;) {
363 if (i == PAGE_SIZE / 8 - 1) {
364 __le64 *old_prp_list = prp_list;
091b6092 365 prp_list = alloc_prp_list(dev, &prp_dma);
e025344c
SMM		 366 prps->list[prp_page++] = prp_list;
367 old_prp_list[i] = cpu_to_le64(prp_dma);
368 i = 0;
369 }
370 prp_list[i++] = cpu_to_le64(dma_addr);
371 dma_len -= PAGE_SIZE;
372 dma_addr += PAGE_SIZE;
373 length -= PAGE_SIZE;
374 if (length <= 0)
375 break;
376 if (dma_len > 0)
377 continue;
378 BUG_ON(dma_len < 0);
379 sg = sg_next(sg);
380 dma_addr = sg_dma_address(sg);
381 dma_len = sg_dma_len(sg);
ff22b54f
MW		 382 }
383
e025344c 384 return prps;
ff22b54f
MW		 385}
386
d534df3c 387static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
b60503ba
MW		 388 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
389{
390 struct bio_vec *bvec;
d534df3c 391 struct scatterlist *sg = nbio->sg;
b60503ba
MW		 392 int i, nsegs;
393
394 sg_init_table(sg, psegs);
395 bio_for_each_segment(bvec, bio, i) {
396 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
51882d00 397 sg++;
b60503ba
MW		 398 /* XXX: handle non-mergable here */
399 nsegs++;
400 }
d534df3c 401 nbio->nents = nsegs;
b60503ba 402
d534df3c 403 return dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir);
b60503ba
MW		 404}
405
406static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
407 struct bio *bio)
408{
ff22b54f 409 struct nvme_command *cmnd;
d534df3c 410 struct nvme_bio *nbio;
b60503ba
MW		 411 enum dma_data_direction dma_dir;
412 int cmdid;
413 u16 control;
414 u32 dsmgmt;
415 unsigned long flags;
416 int psegs = bio_phys_segments(ns->queue, bio);
417
d534df3c
MW		 418 nbio = alloc_nbio(psegs, GFP_NOIO);
419 if (!nbio)
b60503ba 420 goto congestion;
d534df3c 421 nbio->bio = bio;
b60503ba 422
d534df3c 423 cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
b60503ba 424 if (unlikely(cmdid < 0))
d534df3c 425 goto free_nbio;
b60503ba
MW		 426
427 control = 0;
428 if (bio->bi_rw & REQ_FUA)
429 control |= NVME_RW_FUA;
430 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
431 control |= NVME_RW_LR;
432
433 dsmgmt = 0;
434 if (bio->bi_rw & REQ_RAHEAD)
435 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
436
437 spin_lock_irqsave(&nvmeq->q_lock, flags);
ff22b54f 438 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 439
b8deb62c 440 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 441 if (bio_data_dir(bio)) {
ff22b54f 442 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW		 443 dma_dir = DMA_TO_DEVICE;
444 } else {
ff22b54f 445 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW		 446 dma_dir = DMA_FROM_DEVICE;
447 }
448
d534df3c 449 nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
b60503ba 450
ff22b54f
MW		 451 cmnd->rw.flags = 1;
452 cmnd->rw.command_id = cmdid;
453 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
d534df3c 454 nbio->prps = nvme_setup_prps(nvmeq, &cmnd->common, nbio->sg,
e025344c 455 bio->bi_size);
ff22b54f
MW		 456 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
457 cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
458 cmnd->rw.control = cpu_to_le16(control);
459 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba
MW		 460
461 writel(nvmeq->sq_tail, nvmeq->q_db);
462 if (++nvmeq->sq_tail == nvmeq->q_depth)
463 nvmeq->sq_tail = 0;
464
465 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
466
467 return 0;
468
d534df3c
MW		 469 free_nbio:
470 free_nbio(nvmeq, nbio);
b60503ba
MW		 471 congestion:
472 return -EBUSY;
473}
474
9294bbed
MW		 475static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio)
476{
477 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
478 if (nvme_submit_bio_queue(nvmeq, ns, bio))
479 bio_list_add_head(&nvmeq->sq_cong, bio);
480 else if (bio_list_empty(&nvmeq->sq_cong))
481 blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw));
482 /* XXX: Need to duplicate the logic from __freed_request here */
483}
484
b60503ba
MW		 485/*
486 * NB: return value of non-zero would mean that we were a stacking driver.
487 * make_request must always succeed.
488 */
489static int nvme_make_request(struct request_queue *q, struct bio *bio)
490{
491 struct nvme_ns *ns = q->queuedata;
492 struct nvme_queue *nvmeq = get_nvmeq(ns);
493
494 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
495 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
9294bbed 496 spin_lock_irq(&nvmeq->q_lock);
b60503ba 497 bio_list_add(&nvmeq->sq_cong, bio);
9294bbed 498 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 499 }
500 put_nvmeq(nvmeq);
501
502 return 0;
503}
504
505struct sync_cmd_info {
506 struct task_struct *task;
507 u32 result;
508 int status;
509};
510
511static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
512 struct nvme_completion *cqe)
513{
514 struct sync_cmd_info *cmdinfo = ctx;
be7b6275
MW		 515 if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
516 return;
b36235df
MW		 517 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
518 dev_warn(nvmeq->q_dmadev,
519 "completed id %d twice on queue %d\n",
520 cqe->command_id, le16_to_cpup(&cqe->sq_id));
521 return;
522 }
48e3d398
MW		 523 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
524 dev_warn(nvmeq->q_dmadev,
525 "invalid id %d completed on queue %d\n",
526 cqe->command_id, le16_to_cpup(&cqe->sq_id));
527 return;
528 }
b60503ba
MW		 529 cmdinfo->result = le32_to_cpup(&cqe->result);
530 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
531 wake_up_process(cmdinfo->task);
532}
533
534typedef void (*completion_fn)(struct nvme_queue *, void *,
535 struct nvme_completion *);
536
537static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
538{
82123460 539 u16 head, phase;
b60503ba
MW		 540
541 static const completion_fn completions[4] = {
542 [sync_completion_id] = sync_completion,
543 [bio_completion_id] = bio_completion,
544 };
545
546 head = nvmeq->cq_head;
82123460 547 phase = nvmeq->cq_phase;
b60503ba
MW		 548
549 for (;;) {
550 unsigned long data;
551 void *ptr;
552 unsigned char handler;
553 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 554 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 555 break;
556 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
557 if (++head == nvmeq->q_depth) {
558 head = 0;
82123460 559 phase = !phase;
b60503ba
MW		 560 }
561
562 data = free_cmdid(nvmeq, cqe.command_id);
563 handler = data & 3;
564 ptr = (void *)(data & ~3UL);
565 completions[handler](nvmeq, ptr, &cqe);
566 }
567
568 /* If the controller ignores the cq head doorbell and continuously
569 * writes to the queue, it is theoretically possible to wrap around
570 * the queue twice and mistakenly return IRQ_NONE. Linux only
571 * requires that 0.1% of your interrupts are handled, so this isn't
572 * a big problem.
573 */
82123460 574 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
b60503ba
MW		 575 return IRQ_NONE;
576
577 writel(head, nvmeq->q_db + 1);
578 nvmeq->cq_head = head;
82123460 579 nvmeq->cq_phase = phase;
b60503ba
MW		 580
581 return IRQ_HANDLED;
582}
583
584static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 585{
586 irqreturn_t result;
587 struct nvme_queue *nvmeq = data;
588 spin_lock(&nvmeq->q_lock);
589 result = nvme_process_cq(nvmeq);
590 spin_unlock(&nvmeq->q_lock);
591 return result;
592}
593
594static irqreturn_t nvme_irq_check(int irq, void *data)
595{
596 struct nvme_queue *nvmeq = data;
597 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
598 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
599 return IRQ_NONE;
600 return IRQ_WAKE_THREAD;
601}
602
3c0cf138
MW		 603static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
604{
605 spin_lock_irq(&nvmeq->q_lock);
be7b6275 606 cancel_cmdid_data(nvmeq, cmdid);
3c0cf138
MW		 607 spin_unlock_irq(&nvmeq->q_lock);
608}
609
b60503ba
MW		 610/*
611 * Returns 0 on success. If the result is negative, it's a Linux error code;
612 * if the result is positive, it's an NVM Express status code
613 */
3c0cf138 614static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
e85248e5 615 struct nvme_command *cmd, u32 *result, unsigned timeout)
b60503ba
MW		 616{
617 int cmdid;
618 struct sync_cmd_info cmdinfo;
619
620 cmdinfo.task = current;
621 cmdinfo.status = -EINTR;
622
e85248e5
MW		 623 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
624 timeout);
b60503ba
MW		 625 if (cmdid < 0)
626 return cmdid;
627 cmd->common.command_id = cmdid;
628
3c0cf138
MW		 629 set_current_state(TASK_KILLABLE);
630 nvme_submit_cmd(nvmeq, cmd);
b60503ba
MW		 631 schedule();
632
3c0cf138
MW		 633 if (cmdinfo.status == -EINTR) {
634 nvme_abort_command(nvmeq, cmdid);
635 return -EINTR;
636 }
637
b60503ba
MW		 638 if (result)
639 *result = cmdinfo.result;
640
641 return cmdinfo.status;
642}
643
644static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
645 u32 *result)
646{
e85248e5 647 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 648}
649
650static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
651{
652 int status;
653 struct nvme_command c;
654
655 memset(&c, 0, sizeof(c));
656 c.delete_queue.opcode = opcode;
657 c.delete_queue.qid = cpu_to_le16(id);
658
659 status = nvme_submit_admin_cmd(dev, &c, NULL);
660 if (status)
661 return -EIO;
662 return 0;
663}
664
665static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
666 struct nvme_queue *nvmeq)
667{
668 int status;
669 struct nvme_command c;
670 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
671
672 memset(&c, 0, sizeof(c));
673 c.create_cq.opcode = nvme_admin_create_cq;
674 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
675 c.create_cq.cqid = cpu_to_le16(qid);
676 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
677 c.create_cq.cq_flags = cpu_to_le16(flags);
678 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
679
680 status = nvme_submit_admin_cmd(dev, &c, NULL);
681 if (status)
682 return -EIO;
683 return 0;
684}
685
686static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
687 struct nvme_queue *nvmeq)
688{
689 int status;
690 struct nvme_command c;
691 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
692
693 memset(&c, 0, sizeof(c));
694 c.create_sq.opcode = nvme_admin_create_sq;
695 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
696 c.create_sq.sqid = cpu_to_le16(qid);
697 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
698 c.create_sq.sq_flags = cpu_to_le16(flags);
699 c.create_sq.cqid = cpu_to_le16(qid);
700
701 status = nvme_submit_admin_cmd(dev, &c, NULL);
702 if (status)
703 return -EIO;
704 return 0;
705}
706
707static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
708{
709 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
710}
711
712static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
713{
714 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
715}
716
717static void nvme_free_queue(struct nvme_dev *dev, int qid)
718{
719 struct nvme_queue *nvmeq = dev->queues[qid];
720
721 free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
722
723 /* Don't tell the adapter to delete the admin queue */
724 if (qid) {
725 adapter_delete_sq(dev, qid);
726 adapter_delete_cq(dev, qid);
727 }
728
729 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
730 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
731 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
732 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
733 kfree(nvmeq);
734}
735
736static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
737 int depth, int vector)
738{
739 struct device *dmadev = &dev->pci_dev->dev;
e85248e5 740 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
b60503ba
MW		 741 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
742 if (!nvmeq)
743 return NULL;
744
745 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
746 &nvmeq->cq_dma_addr, GFP_KERNEL);
747 if (!nvmeq->cqes)
748 goto free_nvmeq;
749 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
750
751 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
752 &nvmeq->sq_dma_addr, GFP_KERNEL);
753 if (!nvmeq->sq_cmds)
754 goto free_cqdma;
755
756 nvmeq->q_dmadev = dmadev;
091b6092 757 nvmeq->dev = dev;
b60503ba
MW		 758 spin_lock_init(&nvmeq->q_lock);
759 nvmeq->cq_head = 0;
82123460 760 nvmeq->cq_phase = 1;
b60503ba
MW		 761 init_waitqueue_head(&nvmeq->sq_full);
762 bio_list_init(&nvmeq->sq_cong);
763 nvmeq->q_db = &dev->dbs[qid * 2];
764 nvmeq->q_depth = depth;
765 nvmeq->cq_vector = vector;
766
767 return nvmeq;
768
769 free_cqdma:
770 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
771 nvmeq->cq_dma_addr);
772 free_nvmeq:
773 kfree(nvmeq);
774 return NULL;
775}
776
3001082c
MW		 777static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
778 const char *name)
779{
58ffacb5
MW		 780 if (use_threaded_interrupts)
781 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
ec6ce618 782 nvme_irq_check, nvme_irq,
58ffacb5
MW		 783 IRQF_DISABLED | IRQF_SHARED,
784 name, nvmeq);
3001082c
MW		 785 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
786 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
787}
788
b60503ba
MW		 789static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
790 int qid, int cq_size, int vector)
791{
792 int result;
793 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
794
3f85d50b
MW		 795 if (!nvmeq)
796 return NULL;
797
b60503ba
MW		 798 result = adapter_alloc_cq(dev, qid, nvmeq);
799 if (result < 0)
800 goto free_nvmeq;
801
802 result = adapter_alloc_sq(dev, qid, nvmeq);
803 if (result < 0)
804 goto release_cq;
805
3001082c 806 result = queue_request_irq(dev, nvmeq, "nvme");
b60503ba
MW		 807 if (result < 0)
808 goto release_sq;
809
810 return nvmeq;
811
812 release_sq:
813 adapter_delete_sq(dev, qid);
814 release_cq:
815 adapter_delete_cq(dev, qid);
816 free_nvmeq:
817 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
818 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
819 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
820 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
821 kfree(nvmeq);
822 return NULL;
823}
824
825static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
826{
827 int result;
828 u32 aqa;
829 struct nvme_queue *nvmeq;
830
831 dev->dbs = ((void __iomem *)dev->bar) + 4096;
832
833 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
3f85d50b
MW		 834 if (!nvmeq)
835 return -ENOMEM;
b60503ba
MW		 836
837 aqa = nvmeq->q_depth - 1;
838 aqa |= aqa << 16;
839
840 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
841 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
842 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
843
5911f200 844 writel(0, &dev->bar->cc);
b60503ba
MW		 845 writel(aqa, &dev->bar->aqa);
846 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
847 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
848 writel(dev->ctrl_config, &dev->bar->cc);
849
850 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
851 msleep(100);
852 if (fatal_signal_pending(current))
853 return -EINTR;
854 }
855
3001082c 856 result = queue_request_irq(dev, nvmeq, "nvme admin");
b60503ba
MW		 857 dev->queues[0] = nvmeq;
858 return result;
859}
860
7fc3cdab
MW		 861static int nvme_map_user_pages(struct nvme_dev *dev, int write,
862 unsigned long addr, unsigned length,
863 struct scatterlist **sgp)
b60503ba 864{
36c14ed9 865 int i, err, count, nents, offset;
7fc3cdab
MW		 866 struct scatterlist *sg;
867 struct page **pages;
36c14ed9
MW		 868
869 if (addr & 3)
870 return -EINVAL;
7fc3cdab
MW		 871 if (!length)
872 return -EINVAL;
873
36c14ed9 874 offset = offset_in_page(addr);
7fc3cdab
MW		 875 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
876 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
36c14ed9
MW		 877
878 err = get_user_pages_fast(addr, count, 1, pages);
879 if (err < count) {
880 count = err;
881 err = -EFAULT;
882 goto put_pages;
883 }
7fc3cdab
MW		 884
885 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
36c14ed9 886 sg_init_table(sg, count);
ff22b54f 887 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
7fc3cdab
MW		 888 length -= (PAGE_SIZE - offset);
889 for (i = 1; i < count; i++) {
890 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
891 length -= PAGE_SIZE;
892 }
893
894 err = -ENOMEM;
895 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
896 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9
MW		 897 if (!nents)
898 goto put_pages;
b60503ba 899
7fc3cdab
MW		 900 kfree(pages);
901 *sgp = sg;
902 return nents;
b60503ba 903
7fc3cdab
MW		 904 put_pages:
905 for (i = 0; i < count; i++)
906 put_page(pages[i]);
907 kfree(pages);
908 return err;
909}
b60503ba 910
7fc3cdab
MW		 911static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
912 unsigned long addr, int length,
913 struct scatterlist *sg, int nents)
914{
915 int i, count;
b60503ba 916
7fc3cdab 917 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
36c14ed9 918 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
7fc3cdab 919
36c14ed9 920 for (i = 0; i < count; i++)
7fc3cdab
MW		 921 put_page(sg_page(&sg[i]));
922}
b60503ba 923
7fc3cdab
MW		 924static int nvme_submit_user_admin_command(struct nvme_dev *dev,
925 unsigned long addr, unsigned length,
926 struct nvme_command *cmd)
927{
928 int err, nents;
929 struct scatterlist *sg;
e025344c 930 struct nvme_prps *prps;
7fc3cdab
MW		 931
932 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
933 if (nents < 0)
934 return nents;
e025344c 935 prps = nvme_setup_prps(dev->queues[0], &cmd->common, sg, length);
7fc3cdab
MW		 936 err = nvme_submit_admin_cmd(dev, cmd, NULL);
937 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
e025344c 938 nvme_free_prps(dev->queues[0], prps);
7fc3cdab 939 return err ? -EIO : 0;
b60503ba
MW		 940}
941
bd38c555 942static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
b60503ba 943{
b60503ba 944 struct nvme_command c;
b60503ba 945
bd38c555
MW		 946 memset(&c, 0, sizeof(c));
947 c.identify.opcode = nvme_admin_identify;
948 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
949 c.identify.cns = cpu_to_le32(cns);
950
951 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
952}
953
954static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
955{
956 struct nvme_command c;
b60503ba
MW		 957
958 memset(&c, 0, sizeof(c));
959 c.features.opcode = nvme_admin_get_features;
960 c.features.nsid = cpu_to_le32(ns->ns_id);
b60503ba
MW		 961 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
962
bd38c555 963 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
b60503ba
MW		 964}
965
a53295b6
MW		 966static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
967{
968 struct nvme_dev *dev = ns->dev;
969 struct nvme_queue *nvmeq;
970 struct nvme_user_io io;
971 struct nvme_command c;
972 unsigned length;
973 u32 result;
974 int nents, status;
975 struct scatterlist *sg;
e025344c 976 struct nvme_prps *prps;
a53295b6
MW		 977
978 if (copy_from_user(&io, uio, sizeof(io)))
979 return -EFAULT;
980 length = io.nblocks << io.block_shift;
981 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
982 if (nents < 0)
983 return nents;
984
985 memset(&c, 0, sizeof(c));
986 c.rw.opcode = io.opcode;
987 c.rw.flags = io.flags;
988 c.rw.nsid = cpu_to_le32(io.nsid);
989 c.rw.slba = cpu_to_le64(io.slba);
990 c.rw.length = cpu_to_le16(io.nblocks - 1);
991 c.rw.control = cpu_to_le16(io.control);
992 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
993 c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */
994 c.rw.apptag = cpu_to_le16(io.apptag);
995 c.rw.appmask = cpu_to_le16(io.appmask);
e025344c 996 nvmeq = get_nvmeq(ns);
a53295b6 997 /* XXX: metadata */
e025344c 998 prps = nvme_setup_prps(nvmeq, &c.common, sg, length);
a53295b6 999
b1ad37ef
MW		 1000 /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1001 * disabled. We may be preempted at any point, and be rescheduled
1002 * to a different CPU. That will cause cacheline bouncing, but no
1003 * additional races since q_lock already protects against other CPUs.
1004 */
a53295b6 1005 put_nvmeq(nvmeq);
e85248e5 1006 status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
a53295b6
MW		 1007
1008 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
e025344c 1009 nvme_free_prps(nvmeq, prps);
a53295b6
MW		 1010 put_user(result, &uio->result);
1011 return status;
1012}
1013
6ee44cdc
MW		 1014static int nvme_download_firmware(struct nvme_ns *ns,
1015 struct nvme_dlfw __user *udlfw)
1016{
1017 struct nvme_dev *dev = ns->dev;
1018 struct nvme_dlfw dlfw;
1019 struct nvme_command c;
1020 int nents, status;
1021 struct scatterlist *sg;
e025344c 1022 struct nvme_prps *prps;
6ee44cdc
MW		 1023
1024 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1025 return -EFAULT;
1026 if (dlfw.length >= (1 << 30))
1027 return -EINVAL;
1028
1029 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1030 if (nents < 0)
1031 return nents;
1032
1033 memset(&c, 0, sizeof(c));
1034 c.dlfw.opcode = nvme_admin_download_fw;
1035 c.dlfw.numd = cpu_to_le32(dlfw.length);
1036 c.dlfw.offset = cpu_to_le32(dlfw.offset);
e025344c 1037 prps = nvme_setup_prps(dev->queues[0], &c.common, sg, dlfw.length * 4);
6ee44cdc
MW		 1038
1039 status = nvme_submit_admin_cmd(dev, &c, NULL);
1040 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
e025344c 1041 nvme_free_prps(dev->queues[0], prps);
6ee44cdc
MW		 1042 return status;
1043}
1044
1045static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1046{
1047 struct nvme_dev *dev = ns->dev;
1048 struct nvme_command c;
1049
1050 memset(&c, 0, sizeof(c));
1051 c.common.opcode = nvme_admin_activate_fw;
1052 c.common.rsvd10[0] = cpu_to_le32(arg);
1053
1054 return nvme_submit_admin_cmd(dev, &c, NULL);
1055}
1056
b60503ba
MW		 1057static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1058 unsigned long arg)
1059{
1060 struct nvme_ns *ns = bdev->bd_disk->private_data;
1061
1062 switch (cmd) {
1063 case NVME_IOCTL_IDENTIFY_NS:
36c14ed9 1064 return nvme_identify(ns, arg, 0);
b60503ba 1065 case NVME_IOCTL_IDENTIFY_CTRL:
36c14ed9 1066 return nvme_identify(ns, arg, 1);
b60503ba 1067 case NVME_IOCTL_GET_RANGE_TYPE:
bd38c555 1068 return nvme_get_range_type(ns, arg);
a53295b6
MW		 1069 case NVME_IOCTL_SUBMIT_IO:
1070 return nvme_submit_io(ns, (void __user *)arg);
6ee44cdc
MW		 1071 case NVME_IOCTL_DOWNLOAD_FW:
1072 return nvme_download_firmware(ns, (void __user *)arg);
1073 case NVME_IOCTL_ACTIVATE_FW:
1074 return nvme_activate_firmware(ns, arg);
b60503ba
MW		 1075 default:
1076 return -ENOTTY;
1077 }
1078}
1079
1080static const struct block_device_operations nvme_fops = {
1081 .owner = THIS_MODULE,
1082 .ioctl = nvme_ioctl,
1083};
1084
1085static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1086 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1087{
1088 struct nvme_ns *ns;
1089 struct gendisk *disk;
1090 int lbaf;
1091
1092 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1093 return NULL;
1094
1095 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1096 if (!ns)
1097 return NULL;
1098 ns->queue = blk_alloc_queue(GFP_KERNEL);
1099 if (!ns->queue)
1100 goto out_free_ns;
1101 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1102 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1103 blk_queue_make_request(ns->queue, nvme_make_request);
1104 ns->dev = dev;
1105 ns->queue->queuedata = ns;
1106
1107 disk = alloc_disk(NVME_MINORS);
1108 if (!disk)
1109 goto out_free_queue;
1110 ns->ns_id = index;
1111 ns->disk = disk;
1112 lbaf = id->flbas & 0xf;
1113 ns->lba_shift = id->lbaf[lbaf].ds;
1114
1115 disk->major = nvme_major;
1116 disk->minors = NVME_MINORS;
1117 disk->first_minor = NVME_MINORS * index;
1118 disk->fops = &nvme_fops;
1119 disk->private_data = ns;
1120 disk->queue = ns->queue;
388f037f 1121 disk->driverfs_dev = &dev->pci_dev->dev;
b60503ba
MW		 1122 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1123 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1124
1125 return ns;
1126
1127 out_free_queue:
1128 blk_cleanup_queue(ns->queue);
1129 out_free_ns:
1130 kfree(ns);
1131 return NULL;
1132}
1133
1134static void nvme_ns_free(struct nvme_ns *ns)
1135{
1136 put_disk(ns->disk);
1137 blk_cleanup_queue(ns->queue);
1138 kfree(ns);
1139}
1140
b3b06812 1141static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1142{
1143 int status;
1144 u32 result;
1145 struct nvme_command c;
b3b06812 1146 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba
MW		 1147
1148 memset(&c, 0, sizeof(c));
1149 c.features.opcode = nvme_admin_get_features;
1150 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1151 c.features.dword11 = cpu_to_le32(q_count);
1152
1153 status = nvme_submit_admin_cmd(dev, &c, &result);
1154 if (status)
1155 return -EIO;
1156 return min(result & 0xffff, result >> 16) + 1;
1157}
1158
b60503ba
MW		 1159static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1160{
1b23484b 1161 int result, cpu, i, nr_queues;
b60503ba 1162
1b23484b
MW		 1163 nr_queues = num_online_cpus();
1164 result = set_queue_count(dev, nr_queues);
1165 if (result < 0)
1166 return result;
1167 if (result < nr_queues)
1168 nr_queues = result;
b60503ba 1169
1b23484b
MW		 1170 /* Deregister the admin queue's interrupt */
1171 free_irq(dev->entry[0].vector, dev->queues[0]);
1172
1173 for (i = 0; i < nr_queues; i++)
1174 dev->entry[i].entry = i;
1175 for (;;) {
1176 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1177 if (result == 0) {
1178 break;
1179 } else if (result > 0) {
1180 nr_queues = result;
1181 continue;
1182 } else {
1183 nr_queues = 1;
1184 break;
1185 }
1186 }
1187
1188 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1189 /* XXX: handle failure here */
1190
1191 cpu = cpumask_first(cpu_online_mask);
1192 for (i = 0; i < nr_queues; i++) {
1193 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1194 cpu = cpumask_next(cpu, cpu_online_mask);
1195 }
1196
1197 for (i = 0; i < nr_queues; i++) {
1198 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1199 NVME_Q_DEPTH, i);
1200 if (!dev->queues[i + 1])
1201 return -ENOMEM;
1202 dev->queue_count++;
1203 }
b60503ba
MW		 1204
1205 return 0;
1206}
1207
1208static void nvme_free_queues(struct nvme_dev *dev)
1209{
1210 int i;
1211
1212 for (i = dev->queue_count - 1; i >= 0; i--)
1213 nvme_free_queue(dev, i);
1214}
1215
1216static int __devinit nvme_dev_add(struct nvme_dev *dev)
1217{
1218 int res, nn, i;
1219 struct nvme_ns *ns, *next;
51814232 1220 struct nvme_id_ctrl *ctrl;
b60503ba
MW		 1221 void *id;
1222 dma_addr_t dma_addr;
1223 struct nvme_command cid, crt;
1224
1225 res = nvme_setup_io_queues(dev);
1226 if (res)
1227 return res;
1228
1229 /* XXX: Switch to a SG list once prp2 works */
1230 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1231 GFP_KERNEL);
1232
1233 memset(&cid, 0, sizeof(cid));
1234 cid.identify.opcode = nvme_admin_identify;
1235 cid.identify.nsid = 0;
1236 cid.identify.prp1 = cpu_to_le64(dma_addr);
1237 cid.identify.cns = cpu_to_le32(1);
1238
1239 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1240 if (res) {
1241 res = -EIO;
1242 goto out_free;
1243 }
1244
51814232
MW		 1245 ctrl = id;
1246 nn = le32_to_cpup(&ctrl->nn);
1247 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1248 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1249 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
b60503ba
MW		 1250
1251 cid.identify.cns = 0;
1252 memset(&crt, 0, sizeof(crt));
1253 crt.features.opcode = nvme_admin_get_features;
1254 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1255 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1256
1257 for (i = 0; i < nn; i++) {
1258 cid.identify.nsid = cpu_to_le32(i);
1259 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1260 if (res)
1261 continue;
1262
1263 if (((struct nvme_id_ns *)id)->ncap == 0)
1264 continue;
1265
1266 crt.features.nsid = cpu_to_le32(i);
1267 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1268 if (res)
1269 continue;
1270
1271 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1272 if (ns)
1273 list_add_tail(&ns->list, &dev->namespaces);
1274 }
1275 list_for_each_entry(ns, &dev->namespaces, list)
1276 add_disk(ns->disk);
1277
1278 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1279 return 0;
1280
1281 out_free:
1282 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1283 list_del(&ns->list);
1284 nvme_ns_free(ns);
1285 }
1286
1287 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1288 return res;
1289}
1290
1291static int nvme_dev_remove(struct nvme_dev *dev)
1292{
1293 struct nvme_ns *ns, *next;
1294
1295 /* TODO: wait all I/O finished or cancel them */
1296
1297 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1298 list_del(&ns->list);
1299 del_gendisk(ns->disk);
1300 nvme_ns_free(ns);
1301 }
1302
1303 nvme_free_queues(dev);
1304
1305 return 0;
1306}
1307
091b6092
MW		 1308static int nvme_setup_prp_pools(struct nvme_dev *dev)
1309{
1310 struct device *dmadev = &dev->pci_dev->dev;
1311 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1312 PAGE_SIZE, PAGE_SIZE, 0);
1313 if (!dev->prp_page_pool)
1314 return -ENOMEM;
1315
1316 return 0;
1317}
1318
1319static void nvme_release_prp_pools(struct nvme_dev *dev)
1320{
1321 dma_pool_destroy(dev->prp_page_pool);
1322}
1323
b60503ba
MW		 1324/* XXX: Use an ida or something to let remove / add work correctly */
1325static void nvme_set_instance(struct nvme_dev *dev)
1326{
1327 static int instance;
1328 dev->instance = instance++;
1329}
1330
1331static void nvme_release_instance(struct nvme_dev *dev)
1332{
1333}
1334
1335static int __devinit nvme_probe(struct pci_dev *pdev,
1336 const struct pci_device_id *id)
1337{
574e8b95 1338 int bars, result = -ENOMEM;
b60503ba
MW		 1339 struct nvme_dev *dev;
1340
1341 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1342 if (!dev)
1343 return -ENOMEM;
1344 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1345 GFP_KERNEL);
1346 if (!dev->entry)
1347 goto free;
1b23484b
MW		 1348 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1349 GFP_KERNEL);
b60503ba
MW		 1350 if (!dev->queues)
1351 goto free;
1352
0ee5a7d7
SMM		 1353 if (pci_enable_device_mem(pdev))
1354 goto free;
f64d3365 1355 pci_set_master(pdev);
574e8b95
MW		 1356 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1357 if (pci_request_selected_regions(pdev, bars, "nvme"))
1358 goto disable;
0ee5a7d7 1359
b60503ba
MW		 1360 INIT_LIST_HEAD(&dev->namespaces);
1361 dev->pci_dev = pdev;
1362 pci_set_drvdata(pdev, dev);
2930353f
MW		 1363 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1364 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
b60503ba 1365 nvme_set_instance(dev);
53c9577e 1366 dev->entry[0].vector = pdev->irq;
b60503ba 1367
091b6092
MW		 1368 result = nvme_setup_prp_pools(dev);
1369 if (result)
1370 goto disable_msix;
1371
b60503ba
MW		 1372 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1373 if (!dev->bar) {
1374 result = -ENOMEM;
574e8b95 1375 goto disable_msix;
b60503ba
MW		 1376 }
1377
1378 result = nvme_configure_admin_queue(dev);
1379 if (result)
1380 goto unmap;
1381 dev->queue_count++;
1382
1383 result = nvme_dev_add(dev);
1384 if (result)
1385 goto delete;
1386 return 0;
1387
1388 delete:
1389 nvme_free_queues(dev);
1390 unmap:
1391 iounmap(dev->bar);
574e8b95 1392 disable_msix:
b60503ba
MW		 1393 pci_disable_msix(pdev);
1394 nvme_release_instance(dev);
091b6092 1395 nvme_release_prp_pools(dev);
574e8b95 1396 disable:
0ee5a7d7 1397 pci_disable_device(pdev);
574e8b95 1398 pci_release_regions(pdev);
b60503ba
MW		 1399 free:
1400 kfree(dev->queues);
1401 kfree(dev->entry);
1402 kfree(dev);
1403 return result;
1404}
1405
1406static void __devexit nvme_remove(struct pci_dev *pdev)
1407{
1408 struct nvme_dev *dev = pci_get_drvdata(pdev);
1409 nvme_dev_remove(dev);
1410 pci_disable_msix(pdev);
1411 iounmap(dev->bar);
1412 nvme_release_instance(dev);
091b6092 1413 nvme_release_prp_pools(dev);
0ee5a7d7 1414 pci_disable_device(pdev);
574e8b95 1415 pci_release_regions(pdev);
b60503ba
MW		 1416 kfree(dev->queues);
1417 kfree(dev->entry);
1418 kfree(dev);
1419}
1420
1421/* These functions are yet to be implemented */
1422#define nvme_error_detected NULL
1423#define nvme_dump_registers NULL
1424#define nvme_link_reset NULL
1425#define nvme_slot_reset NULL
1426#define nvme_error_resume NULL
1427#define nvme_suspend NULL
1428#define nvme_resume NULL
1429
1430static struct pci_error_handlers nvme_err_handler = {
1431 .error_detected = nvme_error_detected,
1432 .mmio_enabled = nvme_dump_registers,
1433 .link_reset = nvme_link_reset,
1434 .slot_reset = nvme_slot_reset,
1435 .resume = nvme_error_resume,
1436};
1437
1438/* Move to pci_ids.h later */
1439#define PCI_CLASS_STORAGE_EXPRESS 0x010802
1440
1441static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1442 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1443 { 0, }
1444};
1445MODULE_DEVICE_TABLE(pci, nvme_id_table);
1446
1447static struct pci_driver nvme_driver = {
1448 .name = "nvme",
1449 .id_table = nvme_id_table,
1450 .probe = nvme_probe,
1451 .remove = __devexit_p(nvme_remove),
1452 .suspend = nvme_suspend,
1453 .resume = nvme_resume,
1454 .err_handler = &nvme_err_handler,
1455};
1456
1457static int __init nvme_init(void)
1458{
1459 int result;
1460
1461 nvme_major = register_blkdev(nvme_major, "nvme");
1462 if (nvme_major <= 0)
1463 return -EBUSY;
1464
1465 result = pci_register_driver(&nvme_driver);
1466 if (!result)
1467 return 0;
1468
1469 unregister_blkdev(nvme_major, "nvme");
1470 return result;
1471}
1472
1473static void __exit nvme_exit(void)
1474{
1475 pci_unregister_driver(&nvme_driver);
1476 unregister_blkdev(nvme_major, "nvme");
1477}
1478
1479MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1480MODULE_LICENSE("GPL");
db5d0c19 1481MODULE_VERSION("0.2");
b60503ba
MW		 1482module_init(nvme_init);
1483module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)