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NVMe: add sysfs and ioctl controller reset
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
e1e5e564 40#include <linux/t10-pi.h>
b60503ba 41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
b3fffdef 45#define NVME_MINORS (1U << MINORBITS)
9d43cf64 46#define NVME_Q_DEPTH 1024
d31af0a3 47#define NVME_AQ_DEPTH 256
b60503ba
MW		 48#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 50#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 51#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 52
53static unsigned char admin_timeout = 60;
54module_param(admin_timeout, byte, 0644);
55MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 56
bd67608a
MW		 57unsigned char nvme_io_timeout = 30;
58module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 59MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 60
2484f407
DM		 61static unsigned char shutdown_timeout = 5;
62module_param(shutdown_timeout, byte, 0644);
63MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
64
b60503ba
MW		 65static int nvme_major;
66module_param(nvme_major, int, 0);
67
b3fffdef
KB		 68static int nvme_char_major;
69module_param(nvme_char_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
1fa6aead 79
b3fffdef
KB		 80static struct class *nvme_class;
81
d4b4ff8e 82static void nvme_reset_failed_dev(struct work_struct *ws);
4cc06521 83static int nvme_reset(struct nvme_dev *dev);
a4aea562 84static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 85
4d115420
KB		 86struct async_cmd_info {
87 struct kthread_work work;
88 struct kthread_worker *worker;
a4aea562 89 struct request *req;
4d115420
KB		 90 u32 result;
91 int status;
92 void *ctx;
93};
1fa6aead 94
b60503ba
MW		 95/*
96 * An NVM Express queue. Each device has at least two (one for admin
97 * commands and one for I/O commands).
98 */
99struct nvme_queue {
100 struct device *q_dmadev;
091b6092 101 struct nvme_dev *dev;
3193f07b 102 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 103 spinlock_t q_lock;
104 struct nvme_command *sq_cmds;
105 volatile struct nvme_completion *cqes;
42483228 106 struct blk_mq_tags **tags;
b60503ba
MW		 107 dma_addr_t sq_dma_addr;
108 dma_addr_t cq_dma_addr;
b60503ba
MW		 109 u32 __iomem *q_db;
110 u16 q_depth;
6222d172 111 s16 cq_vector;
b60503ba
MW		 112 u16 sq_head;
113 u16 sq_tail;
114 u16 cq_head;
c30341dc 115 u16 qid;
e9539f47
MW		 116 u8 cq_phase;
117 u8 cqe_seen;
4d115420 118 struct async_cmd_info cmdinfo;
b60503ba
MW		 119};
120
121/*
122 * Check we didin't inadvertently grow the command struct
123 */
124static inline void _nvme_check_size(void)
125{
126 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 131 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 132 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 133 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 137 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 138}
139
edd10d33 140typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 141 struct nvme_completion *);
142
e85248e5 143struct nvme_cmd_info {
c2f5b650
MW		 144 nvme_completion_fn fn;
145 void *ctx;
c30341dc 146 int aborted;
a4aea562 147 struct nvme_queue *nvmeq;
ac3dd5bd 148 struct nvme_iod iod[0];
e85248e5
MW		 149};
150
ac3dd5bd
JA		 151/*
152 * Max size of iod being embedded in the request payload
153 */
154#define NVME_INT_PAGES 2
155#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 156#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 157
158/*
159 * Will slightly overestimate the number of pages needed. This is OK
160 * as it only leads to a small amount of wasted memory for the lifetime of
161 * the I/O.
162 */
163static int nvme_npages(unsigned size, struct nvme_dev *dev)
164{
165 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
166 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
167}
168
169static unsigned int nvme_cmd_size(struct nvme_dev *dev)
170{
171 unsigned int ret = sizeof(struct nvme_cmd_info);
172
173 ret += sizeof(struct nvme_iod);
174 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
175 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
176
177 return ret;
178}
179
a4aea562
MB		 180static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
181 unsigned int hctx_idx)
e85248e5 182{
a4aea562
MB		 183 struct nvme_dev *dev = data;
184 struct nvme_queue *nvmeq = dev->queues[0];
185
42483228
KB		 186 WARN_ON(hctx_idx != 0);
187 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
188 WARN_ON(nvmeq->tags);
189
a4aea562 190 hctx->driver_data = nvmeq;
42483228 191 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 192 return 0;
e85248e5
MW		 193}
194
a4aea562
MB		 195static int nvme_admin_init_request(void *data, struct request *req,
196 unsigned int hctx_idx, unsigned int rq_idx,
197 unsigned int numa_node)
22404274 198{
a4aea562
MB		 199 struct nvme_dev *dev = data;
200 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
201 struct nvme_queue *nvmeq = dev->queues[0];
202
203 BUG_ON(!nvmeq);
204 cmd->nvmeq = nvmeq;
205 return 0;
22404274
KB		 206}
207
a4aea562
MB		 208static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
209 unsigned int hctx_idx)
b60503ba 210{
a4aea562 211 struct nvme_dev *dev = data;
42483228 212 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 213
42483228
KB		 214 if (!nvmeq->tags)
215 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 216
42483228 217 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 218 hctx->driver_data = nvmeq;
219 return 0;
b60503ba
MW		 220}
221
a4aea562
MB		 222static int nvme_init_request(void *data, struct request *req,
223 unsigned int hctx_idx, unsigned int rq_idx,
224 unsigned int numa_node)
b60503ba 225{
a4aea562
MB		 226 struct nvme_dev *dev = data;
227 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
228 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
229
230 BUG_ON(!nvmeq);
231 cmd->nvmeq = nvmeq;
232 return 0;
233}
234
235static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
236 nvme_completion_fn handler)
237{
238 cmd->fn = handler;
239 cmd->ctx = ctx;
240 cmd->aborted = 0;
c917dfe5 241 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 242}
243
ac3dd5bd
JA		 244static void *iod_get_private(struct nvme_iod *iod)
245{
246 return (void *) (iod->private & ~0x1UL);
247}
248
249/*
250 * If bit 0 is set, the iod is embedded in the request payload.
251 */
252static bool iod_should_kfree(struct nvme_iod *iod)
253{
fda631ff 254 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 255}
256
c2f5b650
MW		 257/* Special values must be less than 0x1000 */
258#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 259#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
260#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
261#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 262
edd10d33 263static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 264 struct nvme_completion *cqe)
265{
266 if (ctx == CMD_CTX_CANCELLED)
267 return;
c2f5b650 268 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 269 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 270 "completed id %d twice on queue %d\n",
271 cqe->command_id, le16_to_cpup(&cqe->sq_id));
272 return;
273 }
274 if (ctx == CMD_CTX_INVALID) {
edd10d33 275 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 276 "invalid id %d completed on queue %d\n",
277 cqe->command_id, le16_to_cpup(&cqe->sq_id));
278 return;
279 }
edd10d33 280 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 281}
282
a4aea562 283static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 284{
c2f5b650 285 void *ctx;
b60503ba 286
859361a2 287 if (fn)
a4aea562
MB		 288 *fn = cmd->fn;
289 ctx = cmd->ctx;
290 cmd->fn = special_completion;
291 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 292 return ctx;
b60503ba
MW		 293}
294
a4aea562
MB		 295static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
296 struct nvme_completion *cqe)
3c0cf138 297{
a4aea562
MB		 298 u32 result = le32_to_cpup(&cqe->result);
299 u16 status = le16_to_cpup(&cqe->status) >> 1;
300
301 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
302 ++nvmeq->dev->event_limit;
303 if (status == NVME_SC_SUCCESS)
304 dev_warn(nvmeq->q_dmadev,
305 "async event result %08x\n", result);
b60503ba
MW		 306}
307
a4aea562
MB		 308static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
309 struct nvme_completion *cqe)
5a92e700 310{
a4aea562
MB		 311 struct request *req = ctx;
312
313 u16 status = le16_to_cpup(&cqe->status) >> 1;
314 u32 result = le32_to_cpup(&cqe->result);
a51afb54 315
42483228 316 blk_mq_free_request(req);
a51afb54 317
a4aea562
MB		 318 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
319 ++nvmeq->dev->abort_limit;
5a92e700
KB		 320}
321
a4aea562
MB		 322static void async_completion(struct nvme_queue *nvmeq, void *ctx,
323 struct nvme_completion *cqe)
b60503ba 324{
a4aea562
MB		 325 struct async_cmd_info *cmdinfo = ctx;
326 cmdinfo->result = le32_to_cpup(&cqe->result);
327 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
328 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
42483228 329 blk_mq_free_request(cmdinfo->req);
b60503ba
MW		 330}
331
a4aea562
MB		 332static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
333 unsigned int tag)
b60503ba 334{
42483228 335 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
a51afb54 336
a4aea562 337 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 338}
339
a4aea562
MB		 340/*
341 * Called with local interrupts disabled and the q_lock held. May not sleep.
342 */
343static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
344 nvme_completion_fn *fn)
4f5099af 345{
a4aea562
MB		 346 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
347 void *ctx;
348 if (tag >= nvmeq->q_depth) {
349 *fn = special_completion;
350 return CMD_CTX_INVALID;
351 }
352 if (fn)
353 *fn = cmd->fn;
354 ctx = cmd->ctx;
355 cmd->fn = special_completion;
356 cmd->ctx = CMD_CTX_COMPLETED;
357 return ctx;
b60503ba
MW		 358}
359
360/**
714a7a22 361 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 362 * @nvmeq: The queue to use
363 * @cmd: The command to send
364 *
365 * Safe to use from interrupt context
366 */
a4aea562 367static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 368{
a4aea562
MB		 369 u16 tail = nvmeq->sq_tail;
370
b60503ba 371 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 372 if (++tail == nvmeq->q_depth)
373 tail = 0;
7547881d 374 writel(tail, nvmeq->q_db);
b60503ba 375 nvmeq->sq_tail = tail;
b60503ba
MW		 376
377 return 0;
378}
379
a4aea562
MB		 380static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
381{
382 unsigned long flags;
383 int ret;
384 spin_lock_irqsave(&nvmeq->q_lock, flags);
385 ret = __nvme_submit_cmd(nvmeq, cmd);
386 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
387 return ret;
388}
389
eca18b23 390static __le64 **iod_list(struct nvme_iod *iod)
e025344c 391{
eca18b23 392 return ((void *)iod) + iod->offset;
e025344c
SMM		 393}
394
ac3dd5bd
JA		 395static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
396 unsigned nseg, unsigned long private)
eca18b23 397{
ac3dd5bd
JA		 398 iod->private = private;
399 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
400 iod->npages = -1;
401 iod->length = nbytes;
402 iod->nents = 0;
eca18b23 403}
b60503ba 404
eca18b23 405static struct nvme_iod *
ac3dd5bd
JA		 406__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
407 unsigned long priv, gfp_t gfp)
b60503ba 408{
eca18b23 409 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 410 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 411 sizeof(struct scatterlist) * nseg, gfp);
412
ac3dd5bd
JA		 413 if (iod)
414 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 415
416 return iod;
b60503ba
MW		 417}
418
ac3dd5bd
JA		 419static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
420 gfp_t gfp)
421{
422 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
423 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 424 struct nvme_iod *iod;
425
426 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
427 size <= NVME_INT_BYTES(dev)) {
428 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
429
430 iod = cmd->iod;
ac3dd5bd 431 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 432 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 433 return iod;
434 }
435
436 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
437 (unsigned long) rq, gfp);
438}
439
d29ec824 440static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 441{
1d090624 442 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 443 int i;
444 __le64 **list = iod_list(iod);
445 dma_addr_t prp_dma = iod->first_dma;
446
447 if (iod->npages == 0)
448 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
449 for (i = 0; i < iod->npages; i++) {
450 __le64 *prp_list = list[i];
451 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
452 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
453 prp_dma = next_prp_dma;
454 }
ac3dd5bd
JA		 455
456 if (iod_should_kfree(iod))
457 kfree(iod);
b60503ba
MW		 458}
459
b4ff9c8d
KB		 460static int nvme_error_status(u16 status)
461{
462 switch (status & 0x7ff) {
463 case NVME_SC_SUCCESS:
464 return 0;
465 case NVME_SC_CAP_EXCEEDED:
466 return -ENOSPC;
467 default:
468 return -EIO;
469 }
470}
471
52b68d7e 472#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 473static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
474{
475 if (be32_to_cpu(pi->ref_tag) == v)
476 pi->ref_tag = cpu_to_be32(p);
477}
478
479static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
480{
481 if (be32_to_cpu(pi->ref_tag) == p)
482 pi->ref_tag = cpu_to_be32(v);
483}
484
485/**
486 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
487 *
488 * The virtual start sector is the one that was originally submitted by the
489 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
490 * start sector may be different. Remap protection information to match the
491 * physical LBA on writes, and back to the original seed on reads.
492 *
493 * Type 0 and 3 do not have a ref tag, so no remapping required.
494 */
495static void nvme_dif_remap(struct request *req,
496 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
497{
498 struct nvme_ns *ns = req->rq_disk->private_data;
499 struct bio_integrity_payload *bip;
500 struct t10_pi_tuple *pi;
501 void *p, *pmap;
502 u32 i, nlb, ts, phys, virt;
503
504 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
505 return;
506
507 bip = bio_integrity(req->bio);
508 if (!bip)
509 return;
510
511 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 512
513 p = pmap;
514 virt = bip_get_seed(bip);
515 phys = nvme_block_nr(ns, blk_rq_pos(req));
516 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
517 ts = ns->disk->integrity->tuple_size;
518
519 for (i = 0; i < nlb; i++, virt++, phys++) {
520 pi = (struct t10_pi_tuple *)p;
521 dif_swap(phys, virt, pi);
522 p += ts;
523 }
524 kunmap_atomic(pmap);
525}
526
52b68d7e
KB		 527static int nvme_noop_verify(struct blk_integrity_iter *iter)
528{
529 return 0;
530}
531
532static int nvme_noop_generate(struct blk_integrity_iter *iter)
533{
534 return 0;
535}
536
537struct blk_integrity nvme_meta_noop = {
538 .name = "NVME_META_NOOP",
539 .generate_fn = nvme_noop_generate,
540 .verify_fn = nvme_noop_verify,
541};
542
543static void nvme_init_integrity(struct nvme_ns *ns)
544{
545 struct blk_integrity integrity;
546
547 switch (ns->pi_type) {
548 case NVME_NS_DPS_PI_TYPE3:
549 integrity = t10_pi_type3_crc;
550 break;
551 case NVME_NS_DPS_PI_TYPE1:
552 case NVME_NS_DPS_PI_TYPE2:
553 integrity = t10_pi_type1_crc;
554 break;
555 default:
556 integrity = nvme_meta_noop;
557 break;
558 }
559 integrity.tuple_size = ns->ms;
560 blk_integrity_register(ns->disk, &integrity);
561 blk_queue_max_integrity_segments(ns->queue, 1);
562}
563#else /* CONFIG_BLK_DEV_INTEGRITY */
564static void nvme_dif_remap(struct request *req,
565 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
566{
567}
568static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
569{
570}
571static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
572{
573}
574static void nvme_init_integrity(struct nvme_ns *ns)
575{
576}
577#endif
578
a4aea562 579static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 580 struct nvme_completion *cqe)
581{
eca18b23 582 struct nvme_iod *iod = ctx;
ac3dd5bd 583 struct request *req = iod_get_private(iod);
a4aea562
MB		 584 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
585
b60503ba
MW		 586 u16 status = le16_to_cpup(&cqe->status) >> 1;
587
edd10d33 588 if (unlikely(status)) {
a4aea562
MB		 589 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
590 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 591 unsigned long flags;
592
a4aea562 593 blk_mq_requeue_request(req);
c9d3bf88
KB		 594 spin_lock_irqsave(req->q->queue_lock, flags);
595 if (!blk_queue_stopped(req->q))
596 blk_mq_kick_requeue_list(req->q);
597 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 598 return;
599 }
d29ec824 600 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
d29ec824
CH		 601 req->errors = status;
602 } else {
603 req->errors = nvme_error_status(status);
604 }
a4aea562
MB		 605 } else
606 req->errors = 0;
a0a931d6
KB		 607 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
608 u32 result = le32_to_cpup(&cqe->result);
609 req->special = (void *)(uintptr_t)result;
610 }
a4aea562
MB		 611
612 if (cmd_rq->aborted)
e75ec752 613 dev_warn(nvmeq->dev->dev,
a4aea562
MB		 614 "completing aborted command with status:%04x\n",
615 status);
616
e1e5e564 617 if (iod->nents) {
e75ec752 618 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
a4aea562 619 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 620 if (blk_integrity_rq(req)) {
621 if (!rq_data_dir(req))
622 nvme_dif_remap(req, nvme_dif_complete);
e75ec752 623 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
e1e5e564
KB		 624 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
625 }
626 }
edd10d33 627 nvme_free_iod(nvmeq->dev, iod);
3291fa57 628
a4aea562 629 blk_mq_complete_request(req);
b60503ba
MW		 630}
631
184d2944 632/* length is in bytes. gfp flags indicates whether we may sleep. */
d29ec824
CH		 633static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
634 int total_len, gfp_t gfp)
ff22b54f 635{
99802a7a 636 struct dma_pool *pool;
eca18b23
MW		 637 int length = total_len;
638 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 639 int dma_len = sg_dma_len(sg);
640 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 641 u32 page_size = dev->page_size;
642 int offset = dma_addr & (page_size - 1);
e025344c 643 __le64 *prp_list;
eca18b23 644 __le64 **list = iod_list(iod);
e025344c 645 dma_addr_t prp_dma;
eca18b23 646 int nprps, i;
ff22b54f 647
1d090624 648 length -= (page_size - offset);
ff22b54f 649 if (length <= 0)
eca18b23 650 return total_len;
ff22b54f 651
1d090624 652 dma_len -= (page_size - offset);
ff22b54f 653 if (dma_len) {
1d090624 654 dma_addr += (page_size - offset);
ff22b54f
MW		 655 } else {
656 sg = sg_next(sg);
657 dma_addr = sg_dma_address(sg);
658 dma_len = sg_dma_len(sg);
659 }
660
1d090624 661 if (length <= page_size) {
edd10d33 662 iod->first_dma = dma_addr;
eca18b23 663 return total_len;
e025344c
SMM		 664 }
665
1d090624 666 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 667 if (nprps <= (256 / 8)) {
668 pool = dev->prp_small_pool;
eca18b23 669 iod->npages = 0;
99802a7a
MW		 670 } else {
671 pool = dev->prp_page_pool;
eca18b23 672 iod->npages = 1;
99802a7a
MW		 673 }
674
b77954cb
MW		 675 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
676 if (!prp_list) {
edd10d33 677 iod->first_dma = dma_addr;
eca18b23 678 iod->npages = -1;
1d090624 679 return (total_len - length) + page_size;
b77954cb 680 }
eca18b23
MW		 681 list[0] = prp_list;
682 iod->first_dma = prp_dma;
e025344c
SMM		 683 i = 0;
684 for (;;) {
1d090624 685 if (i == page_size >> 3) {
e025344c 686 __le64 *old_prp_list = prp_list;
b77954cb 687 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 688 if (!prp_list)
689 return total_len - length;
690 list[iod->npages++] = prp_list;
7523d834
MW		 691 prp_list[0] = old_prp_list[i - 1];
692 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
693 i = 1;
e025344c
SMM		 694 }
695 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 696 dma_len -= page_size;
697 dma_addr += page_size;
698 length -= page_size;
e025344c
SMM		 699 if (length <= 0)
700 break;
701 if (dma_len > 0)
702 continue;
703 BUG_ON(dma_len < 0);
704 sg = sg_next(sg);
705 dma_addr = sg_dma_address(sg);
706 dma_len = sg_dma_len(sg);
ff22b54f
MW		 707 }
708
eca18b23 709 return total_len;
ff22b54f
MW		 710}
711
d29ec824
CH		 712static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
713 struct nvme_iod *iod)
714{
715 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
716
717 memcpy(cmnd, req->cmd, sizeof(struct nvme_command));
718 cmnd->rw.command_id = req->tag;
719 if (req->nr_phys_segments) {
720 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
721 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
722 }
723
724 if (++nvmeq->sq_tail == nvmeq->q_depth)
725 nvmeq->sq_tail = 0;
726 writel(nvmeq->sq_tail, nvmeq->q_db);
727}
728
a4aea562
MB		 729/*
730 * We reuse the small pool to allocate the 16-byte range here as it is not
731 * worth having a special pool for these or additional cases to handle freeing
732 * the iod.
733 */
734static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
735 struct request *req, struct nvme_iod *iod)
0e5e4f0e 736{
edd10d33
KB		 737 struct nvme_dsm_range *range =
738 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 739 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
740
0e5e4f0e 741 range->cattr = cpu_to_le32(0);
a4aea562
MB		 742 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
743 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 744
745 memset(cmnd, 0, sizeof(*cmnd));
746 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 747 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 748 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
749 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
750 cmnd->dsm.nr = 0;
751 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
752
753 if (++nvmeq->sq_tail == nvmeq->q_depth)
754 nvmeq->sq_tail = 0;
755 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 756}
757
a4aea562 758static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 759 int cmdid)
760{
761 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
762
763 memset(cmnd, 0, sizeof(*cmnd));
764 cmnd->common.opcode = nvme_cmd_flush;
765 cmnd->common.command_id = cmdid;
766 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
767
768 if (++nvmeq->sq_tail == nvmeq->q_depth)
769 nvmeq->sq_tail = 0;
770 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 771}
772
a4aea562
MB		 773static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
774 struct nvme_ns *ns)
b60503ba 775{
ac3dd5bd 776 struct request *req = iod_get_private(iod);
ff22b54f 777 struct nvme_command *cmnd;
a4aea562
MB		 778 u16 control = 0;
779 u32 dsmgmt = 0;
00df5cb4 780
a4aea562 781 if (req->cmd_flags & REQ_FUA)
b60503ba 782 control |= NVME_RW_FUA;
a4aea562 783 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 784 control |= NVME_RW_LR;
785
a4aea562 786 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 787 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
788
ff22b54f 789 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 790 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 791
a4aea562
MB		 792 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
793 cmnd->rw.command_id = req->tag;
ff22b54f 794 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 795 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
796 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 797 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
798 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
e1e5e564
KB		 799
800 if (blk_integrity_rq(req)) {
801 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
802 switch (ns->pi_type) {
803 case NVME_NS_DPS_PI_TYPE3:
804 control |= NVME_RW_PRINFO_PRCHK_GUARD;
805 break;
806 case NVME_NS_DPS_PI_TYPE1:
807 case NVME_NS_DPS_PI_TYPE2:
808 control |= NVME_RW_PRINFO_PRCHK_GUARD |
809 NVME_RW_PRINFO_PRCHK_REF;
810 cmnd->rw.reftag = cpu_to_le32(
811 nvme_block_nr(ns, blk_rq_pos(req)));
812 break;
813 }
814 } else if (ns->ms)
815 control |= NVME_RW_PRINFO_PRACT;
816
ff22b54f
MW		 817 cmnd->rw.control = cpu_to_le16(control);
818 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 819
b60503ba
MW		 820 if (++nvmeq->sq_tail == nvmeq->q_depth)
821 nvmeq->sq_tail = 0;
7547881d 822 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 823
1974b1ae 824 return 0;
edd10d33
KB		 825}
826
d29ec824
CH		 827/*
828 * NOTE: ns is NULL when called on the admin queue.
829 */
a4aea562
MB		 830static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
831 const struct blk_mq_queue_data *bd)
edd10d33 832{
a4aea562
MB		 833 struct nvme_ns *ns = hctx->queue->queuedata;
834 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 835 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 836 struct request *req = bd->rq;
837 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 838 struct nvme_iod *iod;
a4aea562 839 enum dma_data_direction dma_dir;
edd10d33 840
e1e5e564
KB		 841 /*
842 * If formated with metadata, require the block layer provide a buffer
843 * unless this namespace is formated such that the metadata can be
844 * stripped/generated by the controller with PRACT=1.
845 */
d29ec824 846 if (ns && ns->ms && !blk_integrity_rq(req)) {
e1e5e564
KB		 847 if (!(ns->pi_type && ns->ms == 8)) {
848 req->errors = -EFAULT;
849 blk_mq_complete_request(req);
850 return BLK_MQ_RQ_QUEUE_OK;
851 }
852 }
853
d29ec824 854 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
edd10d33 855 if (!iod)
fe54303e 856 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 857
a4aea562 858 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 859 void *range;
860 /*
861 * We reuse the small pool to allocate the 16-byte range here
862 * as it is not worth having a special pool for these or
863 * additional cases to handle freeing the iod.
864 */
d29ec824 865 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
edd10d33 866 &iod->first_dma);
a4aea562 867 if (!range)
fe54303e 868 goto retry_cmd;
edd10d33
KB		 869 iod_list(iod)[0] = (__le64 *)range;
870 iod->npages = 0;
ac3dd5bd 871 } else if (req->nr_phys_segments) {
a4aea562
MB		 872 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
873
ac3dd5bd 874 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 875 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 876 if (!iod->nents)
877 goto error_cmd;
a4aea562
MB		 878
879 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 880 goto retry_cmd;
a4aea562 881
fe54303e 882 if (blk_rq_bytes(req) !=
d29ec824
CH		 883 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
884 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
fe54303e
JA		 885 goto retry_cmd;
886 }
e1e5e564
KB		 887 if (blk_integrity_rq(req)) {
888 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
889 goto error_cmd;
890
891 sg_init_table(iod->meta_sg, 1);
892 if (blk_rq_map_integrity_sg(
893 req->q, req->bio, iod->meta_sg) != 1)
894 goto error_cmd;
895
896 if (rq_data_dir(req))
897 nvme_dif_remap(req, nvme_dif_prep);
898
899 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
900 goto error_cmd;
901 }
edd10d33 902 }
1974b1ae 903
9af8785a 904 nvme_set_info(cmd, iod, req_completion);
a4aea562 905 spin_lock_irq(&nvmeq->q_lock);
d29ec824
CH		 906 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
907 nvme_submit_priv(nvmeq, req, iod);
908 else if (req->cmd_flags & REQ_DISCARD)
a4aea562
MB		 909 nvme_submit_discard(nvmeq, ns, req, iod);
910 else if (req->cmd_flags & REQ_FLUSH)
911 nvme_submit_flush(nvmeq, ns, req->tag);
912 else
913 nvme_submit_iod(nvmeq, iod, ns);
914
915 nvme_process_cq(nvmeq);
916 spin_unlock_irq(&nvmeq->q_lock);
917 return BLK_MQ_RQ_QUEUE_OK;
918
fe54303e 919 error_cmd:
d29ec824 920 nvme_free_iod(dev, iod);
fe54303e
JA		 921 return BLK_MQ_RQ_QUEUE_ERROR;
922 retry_cmd:
d29ec824 923 nvme_free_iod(dev, iod);
fe54303e 924 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 925}
926
e9539f47 927static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 928{
82123460 929 u16 head, phase;
b60503ba 930
b60503ba 931 head = nvmeq->cq_head;
82123460 932 phase = nvmeq->cq_phase;
b60503ba
MW		 933
934 for (;;) {
c2f5b650
MW		 935 void *ctx;
936 nvme_completion_fn fn;
b60503ba 937 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 938 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 939 break;
940 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
941 if (++head == nvmeq->q_depth) {
942 head = 0;
82123460 943 phase = !phase;
b60503ba 944 }
a4aea562 945 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 946 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 947 }
948
949 /* If the controller ignores the cq head doorbell and continuously
950 * writes to the queue, it is theoretically possible to wrap around
951 * the queue twice and mistakenly return IRQ_NONE. Linux only
952 * requires that 0.1% of your interrupts are handled, so this isn't
953 * a big problem.
954 */
82123460 955 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 956 return 0;
b60503ba 957
b80d5ccc 958 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 959 nvmeq->cq_head = head;
82123460 960 nvmeq->cq_phase = phase;
b60503ba 961
e9539f47
MW		 962 nvmeq->cqe_seen = 1;
963 return 1;
b60503ba
MW		 964}
965
966static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 967{
968 irqreturn_t result;
969 struct nvme_queue *nvmeq = data;
970 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 971 nvme_process_cq(nvmeq);
972 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
973 nvmeq->cqe_seen = 0;
58ffacb5
MW		 974 spin_unlock(&nvmeq->q_lock);
975 return result;
976}
977
978static irqreturn_t nvme_irq_check(int irq, void *data)
979{
980 struct nvme_queue *nvmeq = data;
981 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
982 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
983 return IRQ_NONE;
984 return IRQ_WAKE_THREAD;
985}
986
b60503ba
MW		 987/*
988 * Returns 0 on success. If the result is negative, it's a Linux error code;
989 * if the result is positive, it's an NVM Express status code
990 */
d29ec824
CH		 991int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
992 void *buffer, void __user *ubuffer, unsigned bufflen,
993 u32 *result, unsigned timeout)
b60503ba 994{
d29ec824
CH		 995 bool write = cmd->common.opcode & 1;
996 struct bio *bio = NULL;
f705f837 997 struct request *req;
d29ec824 998 int ret;
f705f837 999
d29ec824 1000 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
f705f837
CH		 1001 if (IS_ERR(req))
1002 return PTR_ERR(req);
b60503ba 1003
d29ec824 1004 req->cmd_type = REQ_TYPE_DRV_PRIV;
75619bfa 1005 req->cmd_flags = REQ_FAILFAST_DRIVER;
d29ec824
CH		 1006 req->__data_len = 0;
1007 req->__sector = (sector_t) -1;
1008 req->bio = req->biotail = NULL;
b60503ba 1009
f4ff414a 1010 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
a4aea562 1011
d29ec824
CH		 1012 req->cmd = (unsigned char *)cmd;
1013 req->cmd_len = sizeof(struct nvme_command);
a0a931d6 1014 req->special = (void *)0;
b60503ba 1015
d29ec824
CH		 1016 if (buffer && bufflen) {
1017 ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
1018 if (ret)
1019 goto out;
1020 } else if (ubuffer && bufflen) {
1021 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
1022 if (ret)
1023 goto out;
1024 bio = req->bio;
1025 }
3c0cf138 1026
d29ec824
CH		 1027 blk_execute_rq(req->q, NULL, req, 0);
1028 if (bio)
1029 blk_rq_unmap_user(bio);
b60503ba 1030 if (result)
a0a931d6 1031 *result = (u32)(uintptr_t)req->special;
d29ec824
CH		 1032 ret = req->errors;
1033 out:
f705f837 1034 blk_mq_free_request(req);
d29ec824 1035 return ret;
f705f837
CH		 1036}
1037
d29ec824
CH		 1038int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1039 void *buffer, unsigned bufflen)
f705f837 1040{
d29ec824 1041 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
b60503ba
MW		 1042}
1043
a4aea562
MB		 1044static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1045{
1046 struct nvme_queue *nvmeq = dev->queues[0];
1047 struct nvme_command c;
1048 struct nvme_cmd_info *cmd_info;
1049 struct request *req;
1050
1efccc9d 1051 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1052 if (IS_ERR(req))
1053 return PTR_ERR(req);
a4aea562 1054
c917dfe5 1055 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1056 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1057 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1058
1059 memset(&c, 0, sizeof(c));
1060 c.common.opcode = nvme_admin_async_event;
1061 c.common.command_id = req->tag;
1062
42483228 1063 blk_mq_free_request(req);
a4aea562
MB		 1064 return __nvme_submit_cmd(nvmeq, &c);
1065}
1066
1067static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1068 struct nvme_command *cmd,
1069 struct async_cmd_info *cmdinfo, unsigned timeout)
1070{
a4aea562
MB		 1071 struct nvme_queue *nvmeq = dev->queues[0];
1072 struct request *req;
1073 struct nvme_cmd_info *cmd_rq;
4d115420 1074
a4aea562 1075 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1076 if (IS_ERR(req))
1077 return PTR_ERR(req);
a4aea562
MB		 1078
1079 req->timeout = timeout;
1080 cmd_rq = blk_mq_rq_to_pdu(req);
1081 cmdinfo->req = req;
1082 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1083 cmdinfo->status = -EINTR;
a4aea562
MB		 1084
1085 cmd->common.command_id = req->tag;
1086
4f5099af 1087 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 1088}
1089
b60503ba
MW		 1090static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1091{
b60503ba
MW		 1092 struct nvme_command c;
1093
1094 memset(&c, 0, sizeof(c));
1095 c.delete_queue.opcode = opcode;
1096 c.delete_queue.qid = cpu_to_le16(id);
1097
d29ec824 1098 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1099}
1100
1101static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1102 struct nvme_queue *nvmeq)
1103{
b60503ba
MW		 1104 struct nvme_command c;
1105 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1106
d29ec824
CH		 1107 /*
1108 * Note: we (ab)use the fact the the prp fields survive if no data
1109 * is attached to the request.
1110 */
b60503ba
MW		 1111 memset(&c, 0, sizeof(c));
1112 c.create_cq.opcode = nvme_admin_create_cq;
1113 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1114 c.create_cq.cqid = cpu_to_le16(qid);
1115 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1116 c.create_cq.cq_flags = cpu_to_le16(flags);
1117 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1118
d29ec824 1119 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1120}
1121
1122static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1123 struct nvme_queue *nvmeq)
1124{
b60503ba
MW		 1125 struct nvme_command c;
1126 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1127
d29ec824
CH		 1128 /*
1129 * Note: we (ab)use the fact the the prp fields survive if no data
1130 * is attached to the request.
1131 */
b60503ba
MW		 1132 memset(&c, 0, sizeof(c));
1133 c.create_sq.opcode = nvme_admin_create_sq;
1134 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1135 c.create_sq.sqid = cpu_to_le16(qid);
1136 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1137 c.create_sq.sq_flags = cpu_to_le16(flags);
1138 c.create_sq.cqid = cpu_to_le16(qid);
1139
d29ec824 1140 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1141}
1142
1143static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1144{
1145 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1146}
1147
1148static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1149{
1150 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1151}
1152
d29ec824 1153int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
bc5fc7e4 1154{
d29ec824
CH		 1155 struct nvme_command c = {
1156 .identify.opcode = nvme_admin_identify,
1157 .identify.cns = cpu_to_le32(1),
1158 };
1159 int error;
bc5fc7e4 1160
d29ec824
CH		 1161 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1162 if (!*id)
1163 return -ENOMEM;
1164
1165 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1166 sizeof(struct nvme_id_ctrl));
1167 if (error)
1168 kfree(*id);
1169 return error;
1170}
1171
1172int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1173 struct nvme_id_ns **id)
1174{
1175 struct nvme_command c = {
1176 .identify.opcode = nvme_admin_identify,
1177 .identify.nsid = cpu_to_le32(nsid),
1178 };
1179 int error;
bc5fc7e4 1180
d29ec824
CH		 1181 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1182 if (!*id)
1183 return -ENOMEM;
1184
1185 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1186 sizeof(struct nvme_id_ns));
1187 if (error)
1188 kfree(*id);
1189 return error;
bc5fc7e4
MW		 1190}
1191
5d0f6131 1192int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1193 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1194{
1195 struct nvme_command c;
1196
1197 memset(&c, 0, sizeof(c));
1198 c.features.opcode = nvme_admin_get_features;
a42cecce 1199 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1200 c.features.prp1 = cpu_to_le64(dma_addr);
1201 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1202
d29ec824
CH		 1203 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1204 result, 0);
df348139
MW		 1205}
1206
5d0f6131
VV		 1207int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1208 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1209{
1210 struct nvme_command c;
1211
1212 memset(&c, 0, sizeof(c));
1213 c.features.opcode = nvme_admin_set_features;
1214 c.features.prp1 = cpu_to_le64(dma_addr);
1215 c.features.fid = cpu_to_le32(fid);
1216 c.features.dword11 = cpu_to_le32(dword11);
1217
d29ec824
CH		 1218 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1219 result, 0);
1220}
1221
1222int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1223{
1224 struct nvme_command c = {
1225 .common.opcode = nvme_admin_get_log_page,
1226 .common.nsid = cpu_to_le32(0xFFFFFFFF),
1227 .common.cdw10[0] = cpu_to_le32(
1228 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1229 NVME_LOG_SMART),
1230 };
1231 int error;
1232
1233 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1234 if (!*log)
1235 return -ENOMEM;
1236
1237 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1238 sizeof(struct nvme_smart_log));
1239 if (error)
1240 kfree(*log);
1241 return error;
bc5fc7e4
MW		 1242}
1243
c30341dc 1244/**
a4aea562 1245 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1246 *
1247 * Schedule controller reset if the command was already aborted once before and
1248 * still hasn't been returned to the driver, or if this is the admin queue.
1249 */
a4aea562 1250static void nvme_abort_req(struct request *req)
c30341dc 1251{
a4aea562
MB		 1252 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1253 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1254 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1255 struct request *abort_req;
1256 struct nvme_cmd_info *abort_cmd;
1257 struct nvme_command cmd;
c30341dc 1258
a4aea562 1259 if (!nvmeq->qid || cmd_rq->aborted) {
7a509a6b
KB		 1260 unsigned long flags;
1261
1262 spin_lock_irqsave(&dev_list_lock, flags);
c30341dc 1263 if (work_busy(&dev->reset_work))
7a509a6b 1264 goto out;
c30341dc 1265 list_del_init(&dev->node);
e75ec752 1266 dev_warn(dev->dev, "I/O %d QID %d timeout, reset controller\n",
a4aea562 1267 req->tag, nvmeq->qid);
9ca97374 1268 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc 1269 queue_work(nvme_workq, &dev->reset_work);
7a509a6b
KB		 1270 out:
1271 spin_unlock_irqrestore(&dev_list_lock, flags);
c30341dc
KB		 1272 return;
1273 }
1274
1275 if (!dev->abort_limit)
1276 return;
1277
a4aea562
MB		 1278 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1279 false);
9f173b33 1280 if (IS_ERR(abort_req))
c30341dc
KB		 1281 return;
1282
a4aea562
MB		 1283 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1284 nvme_set_info(abort_cmd, abort_req, abort_completion);
1285
c30341dc
KB		 1286 memset(&cmd, 0, sizeof(cmd));
1287 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1288 cmd.abort.cid = req->tag;
c30341dc 1289 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1290 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1291
1292 --dev->abort_limit;
a4aea562 1293 cmd_rq->aborted = 1;
c30341dc 1294
a4aea562 1295 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1296 nvmeq->qid);
a4aea562
MB		 1297 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1298 dev_warn(nvmeq->q_dmadev,
1299 "Could not abort I/O %d QID %d",
1300 req->tag, nvmeq->qid);
c87fd540 1301 blk_mq_free_request(abort_req);
a4aea562 1302 }
c30341dc
KB		 1303}
1304
42483228 1305static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
a09115b2 1306{
a4aea562
MB		 1307 struct nvme_queue *nvmeq = data;
1308 void *ctx;
1309 nvme_completion_fn fn;
1310 struct nvme_cmd_info *cmd;
cef6a948
KB		 1311 struct nvme_completion cqe;
1312
1313 if (!blk_mq_request_started(req))
1314 return;
a09115b2 1315
a4aea562 1316 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1317
a4aea562
MB		 1318 if (cmd->ctx == CMD_CTX_CANCELLED)
1319 return;
1320
cef6a948
KB		 1321 if (blk_queue_dying(req->q))
1322 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1323 else
1324 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1325
1326
a4aea562
MB		 1327 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1328 req->tag, nvmeq->qid);
1329 ctx = cancel_cmd_info(cmd, &fn);
1330 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1331}
1332
a4aea562 1333static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1334{
a4aea562
MB		 1335 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1336 struct nvme_queue *nvmeq = cmd->nvmeq;
1337
1338 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1339 nvmeq->qid);
7a509a6b 1340 spin_lock_irq(&nvmeq->q_lock);
07836e65 1341 nvme_abort_req(req);
7a509a6b 1342 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1343
07836e65
KB		 1344 /*
1345 * The aborted req will be completed on receiving the abort req.
1346 * We enable the timer again. If hit twice, it'll cause a device reset,
1347 * as the device then is in a faulty state.
1348 */
1349 return BLK_EH_RESET_TIMER;
a4aea562 1350}
22404274 1351
a4aea562
MB		 1352static void nvme_free_queue(struct nvme_queue *nvmeq)
1353{
9e866774
MW		 1354 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1355 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1356 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1357 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1358 kfree(nvmeq);
1359}
1360
a1a5ef99 1361static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1362{
1363 int i;
1364
a1a5ef99 1365 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1366 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1367 dev->queue_count--;
a4aea562 1368 dev->queues[i] = NULL;
f435c282 1369 nvme_free_queue(nvmeq);
121c7ad4 1370 }
22404274
KB		 1371}
1372
4d115420
KB		 1373/**
1374 * nvme_suspend_queue - put queue into suspended state
1375 * @nvmeq - queue to suspend
4d115420
KB		 1376 */
1377static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1378{
2b25d981 1379 int vector;
b60503ba 1380
a09115b2 1381 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1382 if (nvmeq->cq_vector == -1) {
1383 spin_unlock_irq(&nvmeq->q_lock);
1384 return 1;
1385 }
1386 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1387 nvmeq->dev->online_queues--;
2b25d981 1388 nvmeq->cq_vector = -1;
a09115b2
MW		 1389 spin_unlock_irq(&nvmeq->q_lock);
1390
6df3dbc8
KB		 1391 if (!nvmeq->qid && nvmeq->dev->admin_q)
1392 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1393
aba2080f
MW		 1394 irq_set_affinity_hint(vector, NULL);
1395 free_irq(vector, nvmeq);
b60503ba 1396
4d115420
KB		 1397 return 0;
1398}
b60503ba 1399
4d115420
KB		 1400static void nvme_clear_queue(struct nvme_queue *nvmeq)
1401{
22404274 1402 spin_lock_irq(&nvmeq->q_lock);
42483228
KB		 1403 if (nvmeq->tags && *nvmeq->tags)
1404 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
22404274 1405 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1406}
1407
4d115420
KB		 1408static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1409{
a4aea562 1410 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1411
1412 if (!nvmeq)
1413 return;
1414 if (nvme_suspend_queue(nvmeq))
1415 return;
1416
0e53d180
KB		 1417 /* Don't tell the adapter to delete the admin queue.
1418 * Don't tell a removed adapter to delete IO queues. */
1419 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1420 adapter_delete_sq(dev, qid);
1421 adapter_delete_cq(dev, qid);
1422 }
07836e65
KB		 1423
1424 spin_lock_irq(&nvmeq->q_lock);
1425 nvme_process_cq(nvmeq);
1426 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1427}
1428
1429static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1430 int depth)
b60503ba 1431{
a4aea562 1432 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1433 if (!nvmeq)
1434 return NULL;
1435
e75ec752 1436 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1437 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1438 if (!nvmeq->cqes)
1439 goto free_nvmeq;
b60503ba 1440
e75ec752 1441 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
b60503ba
MW		 1442 &nvmeq->sq_dma_addr, GFP_KERNEL);
1443 if (!nvmeq->sq_cmds)
1444 goto free_cqdma;
1445
e75ec752 1446 nvmeq->q_dmadev = dev->dev;
091b6092 1447 nvmeq->dev = dev;
3193f07b
MW		 1448 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1449 dev->instance, qid);
b60503ba
MW		 1450 spin_lock_init(&nvmeq->q_lock);
1451 nvmeq->cq_head = 0;
82123460 1452 nvmeq->cq_phase = 1;
b80d5ccc 1453 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1454 nvmeq->q_depth = depth;
c30341dc 1455 nvmeq->qid = qid;
22404274 1456 dev->queue_count++;
a4aea562 1457 dev->queues[qid] = nvmeq;
b60503ba
MW		 1458
1459 return nvmeq;
1460
1461 free_cqdma:
e75ec752 1462 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1463 nvmeq->cq_dma_addr);
1464 free_nvmeq:
1465 kfree(nvmeq);
1466 return NULL;
1467}
1468
3001082c
MW		 1469static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1470 const char *name)
1471{
58ffacb5
MW		 1472 if (use_threaded_interrupts)
1473 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1474 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1475 name, nvmeq);
3001082c 1476 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1477 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1478}
1479
22404274 1480static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1481{
22404274 1482 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1483
7be50e93 1484 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1485 nvmeq->sq_tail = 0;
1486 nvmeq->cq_head = 0;
1487 nvmeq->cq_phase = 1;
b80d5ccc 1488 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1489 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1490 dev->online_queues++;
7be50e93 1491 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1492}
1493
1494static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1495{
1496 struct nvme_dev *dev = nvmeq->dev;
1497 int result;
3f85d50b 1498
2b25d981 1499 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1500 result = adapter_alloc_cq(dev, qid, nvmeq);
1501 if (result < 0)
22404274 1502 return result;
b60503ba
MW		 1503
1504 result = adapter_alloc_sq(dev, qid, nvmeq);
1505 if (result < 0)
1506 goto release_cq;
1507
3193f07b 1508 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1509 if (result < 0)
1510 goto release_sq;
1511
22404274 1512 nvme_init_queue(nvmeq, qid);
22404274 1513 return result;
b60503ba
MW		 1514
1515 release_sq:
1516 adapter_delete_sq(dev, qid);
1517 release_cq:
1518 adapter_delete_cq(dev, qid);
22404274 1519 return result;
b60503ba
MW		 1520}
1521
ba47e386
MW		 1522static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1523{
1524 unsigned long timeout;
1525 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1526
1527 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1528
1529 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1530 msleep(100);
1531 if (fatal_signal_pending(current))
1532 return -EINTR;
1533 if (time_after(jiffies, timeout)) {
e75ec752 1534 dev_err(dev->dev,
27e8166c
MW		 1535 "Device not ready; aborting %s\n", enabled ?
1536 "initialisation" : "reset");
ba47e386
MW		 1537 return -ENODEV;
1538 }
1539 }
1540
1541 return 0;
1542}
1543
1544/*
1545 * If the device has been passed off to us in an enabled state, just clear
1546 * the enabled bit. The spec says we should set the 'shutdown notification
1547 * bits', but doing so may cause the device to complete commands to the
1548 * admin queue ... and we don't know what memory that might be pointing at!
1549 */
1550static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1551{
01079522
DM		 1552 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1553 dev->ctrl_config &= ~NVME_CC_ENABLE;
1554 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1555
ba47e386
MW		 1556 return nvme_wait_ready(dev, cap, false);
1557}
1558
1559static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1560{
01079522
DM		 1561 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1562 dev->ctrl_config |= NVME_CC_ENABLE;
1563 writel(dev->ctrl_config, &dev->bar->cc);
1564
ba47e386
MW		 1565 return nvme_wait_ready(dev, cap, true);
1566}
1567
1894d8f1
KB		 1568static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1569{
1570 unsigned long timeout;
1894d8f1 1571
01079522
DM		 1572 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1573 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1574
1575 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1576
2484f407 1577 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1578 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1579 NVME_CSTS_SHST_CMPLT) {
1580 msleep(100);
1581 if (fatal_signal_pending(current))
1582 return -EINTR;
1583 if (time_after(jiffies, timeout)) {
e75ec752 1584 dev_err(dev->dev,
1894d8f1
KB		 1585 "Device shutdown incomplete; abort shutdown\n");
1586 return -ENODEV;
1587 }
1588 }
1589
1590 return 0;
1591}
1592
a4aea562 1593static struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1594 .queue_rq = nvme_queue_rq,
a4aea562
MB		 1595 .map_queue = blk_mq_map_queue,
1596 .init_hctx = nvme_admin_init_hctx,
1597 .init_request = nvme_admin_init_request,
1598 .timeout = nvme_timeout,
1599};
1600
1601static struct blk_mq_ops nvme_mq_ops = {
1602 .queue_rq = nvme_queue_rq,
1603 .map_queue = blk_mq_map_queue,
1604 .init_hctx = nvme_init_hctx,
1605 .init_request = nvme_init_request,
1606 .timeout = nvme_timeout,
1607};
1608
ea191d2f
KB		 1609static void nvme_dev_remove_admin(struct nvme_dev *dev)
1610{
1611 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1612 blk_cleanup_queue(dev->admin_q);
1613 blk_mq_free_tag_set(&dev->admin_tagset);
1614 }
1615}
1616
a4aea562
MB		 1617static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1618{
1619 if (!dev->admin_q) {
1620 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1621 dev->admin_tagset.nr_hw_queues = 1;
1622 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1623 dev->admin_tagset.reserved_tags = 1;
a4aea562 1624 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1625 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1626 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1627 dev->admin_tagset.driver_data = dev;
1628
1629 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1630 return -ENOMEM;
1631
1632 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1633 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1634 blk_mq_free_tag_set(&dev->admin_tagset);
1635 return -ENOMEM;
1636 }
ea191d2f
KB		 1637 if (!blk_get_queue(dev->admin_q)) {
1638 nvme_dev_remove_admin(dev);
1639 return -ENODEV;
1640 }
0fb59cbc
KB		 1641 } else
1642 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1643
1644 return 0;
1645}
1646
8d85fce7 1647static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1648{
ba47e386 1649 int result;
b60503ba 1650 u32 aqa;
ba47e386 1651 u64 cap = readq(&dev->bar->cap);
b60503ba 1652 struct nvme_queue *nvmeq;
1d090624
KB		 1653 unsigned page_shift = PAGE_SHIFT;
1654 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1655 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1656
1657 if (page_shift < dev_page_min) {
e75ec752 1658 dev_err(dev->dev,
1d090624
KB		 1659 "Minimum device page size (%u) too large for "
1660 "host (%u)\n", 1 << dev_page_min,
1661 1 << page_shift);
1662 return -ENODEV;
1663 }
1664 if (page_shift > dev_page_max) {
e75ec752 1665 dev_info(dev->dev,
1d090624
KB		 1666 "Device maximum page size (%u) smaller than "
1667 "host (%u); enabling work-around\n",
1668 1 << dev_page_max, 1 << page_shift);
1669 page_shift = dev_page_max;
1670 }
b60503ba 1671
ba47e386
MW		 1672 result = nvme_disable_ctrl(dev, cap);
1673 if (result < 0)
1674 return result;
b60503ba 1675
a4aea562 1676 nvmeq = dev->queues[0];
cd638946 1677 if (!nvmeq) {
2b25d981 1678 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1679 if (!nvmeq)
1680 return -ENOMEM;
cd638946 1681 }
b60503ba
MW		 1682
1683 aqa = nvmeq->q_depth - 1;
1684 aqa |= aqa << 16;
1685
1d090624
KB		 1686 dev->page_size = 1 << page_shift;
1687
01079522 1688 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1689 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1690 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1691 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1692
1693 writel(aqa, &dev->bar->aqa);
1694 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1695 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1696
ba47e386 1697 result = nvme_enable_ctrl(dev, cap);
025c557a 1698 if (result)
a4aea562
MB		 1699 goto free_nvmeq;
1700
2b25d981 1701 nvmeq->cq_vector = 0;
3193f07b 1702 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1703 if (result)
0fb59cbc 1704 goto free_nvmeq;
025c557a 1705
b60503ba 1706 return result;
a4aea562 1707
a4aea562
MB		 1708 free_nvmeq:
1709 nvme_free_queues(dev, 0);
1710 return result;
b60503ba
MW		 1711}
1712
a53295b6
MW		 1713static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1714{
1715 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1716 struct nvme_user_io io;
1717 struct nvme_command c;
d29ec824 1718 unsigned length, meta_len;
a67a9513 1719 int status, write;
a67a9513
KB		 1720 dma_addr_t meta_dma = 0;
1721 void *meta = NULL;
a53295b6
MW		 1722
1723 if (copy_from_user(&io, uio, sizeof(io)))
1724 return -EFAULT;
6c7d4945
MW		 1725
1726 switch (io.opcode) {
1727 case nvme_cmd_write:
1728 case nvme_cmd_read:
6bbf1acd 1729 case nvme_cmd_compare:
6413214c 1730 break;
6c7d4945 1731 default:
6bbf1acd 1732 return -EINVAL;
6c7d4945
MW		 1733 }
1734
d29ec824
CH		 1735 length = (io.nblocks + 1) << ns->lba_shift;
1736 meta_len = (io.nblocks + 1) * ns->ms;
1737 write = io.opcode & 1;
a53295b6 1738
a67a9513 1739 if (meta_len) {
d29ec824
CH		 1740 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1741 return -EINVAL;
1742
1743 if (ns->ext) {
1744 length += meta_len;
1745 meta_len = 0;
1746 }
1747
e75ec752 1748 meta = dma_alloc_coherent(dev->dev, meta_len,
a67a9513
KB		 1749 &meta_dma, GFP_KERNEL);
1750 if (!meta) {
1751 status = -ENOMEM;
1752 goto unmap;
1753 }
1754 if (write) {
1755 if (copy_from_user(meta, (void __user *)io.metadata,
1756 meta_len)) {
1757 status = -EFAULT;
1758 goto unmap;
1759 }
1760 }
1761 }
1762
a53295b6
MW		 1763 memset(&c, 0, sizeof(c));
1764 c.rw.opcode = io.opcode;
1765 c.rw.flags = io.flags;
6c7d4945 1766 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1767 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1768 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1769 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1770 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1771 c.rw.reftag = cpu_to_le32(io.reftag);
1772 c.rw.apptag = cpu_to_le16(io.apptag);
1773 c.rw.appmask = cpu_to_le16(io.appmask);
a67a9513 1774 c.rw.metadata = cpu_to_le64(meta_dma);
d29ec824
CH		 1775
1776 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1777 (void __user *)io.addr, length, NULL, 0);
f410c680 1778 unmap:
a67a9513
KB		 1779 if (meta) {
1780 if (status == NVME_SC_SUCCESS && !write) {
1781 if (copy_to_user((void __user *)io.metadata, meta,
1782 meta_len))
1783 status = -EFAULT;
1784 }
e75ec752 1785 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
f410c680 1786 }
a53295b6
MW		 1787 return status;
1788}
1789
a4aea562
MB		 1790static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1791 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1792{
7963e521 1793 struct nvme_passthru_cmd cmd;
6ee44cdc 1794 struct nvme_command c;
d29ec824
CH		 1795 unsigned timeout = 0;
1796 int status;
6ee44cdc 1797
6bbf1acd
MW		 1798 if (!capable(CAP_SYS_ADMIN))
1799 return -EACCES;
1800 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1801 return -EFAULT;
6ee44cdc
MW		 1802
1803 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1804 c.common.opcode = cmd.opcode;
1805 c.common.flags = cmd.flags;
1806 c.common.nsid = cpu_to_le32(cmd.nsid);
1807 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1808 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1809 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1810 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1811 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1812 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1813 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1814 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1815
d29ec824
CH		 1816 if (cmd.timeout_ms)
1817 timeout = msecs_to_jiffies(cmd.timeout_ms);
f705f837
CH		 1818
1819 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
d29ec824
CH		 1820 NULL, (void __user *)cmd.addr, cmd.data_len,
1821 &cmd.result, timeout);
1822 if (status >= 0) {
1823 if (put_user(cmd.result, &ucmd->result))
1824 return -EFAULT;
6bbf1acd 1825 }
f4f117f6 1826
6ee44cdc
MW		 1827 return status;
1828}
1829
b60503ba
MW		 1830static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1831 unsigned long arg)
1832{
1833 struct nvme_ns *ns = bdev->bd_disk->private_data;
1834
1835 switch (cmd) {
6bbf1acd 1836 case NVME_IOCTL_ID:
c3bfe717 1837 force_successful_syscall_return();
6bbf1acd
MW		 1838 return ns->ns_id;
1839 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1840 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1841 case NVME_IOCTL_IO_CMD:
a4aea562 1842 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1843 case NVME_IOCTL_SUBMIT_IO:
1844 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1845 case SG_GET_VERSION_NUM:
1846 return nvme_sg_get_version_num((void __user *)arg);
1847 case SG_IO:
1848 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1849 default:
1850 return -ENOTTY;
1851 }
1852}
1853
320a3827
KB		 1854#ifdef CONFIG_COMPAT
1855static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1856 unsigned int cmd, unsigned long arg)
1857{
320a3827
KB		 1858 switch (cmd) {
1859 case SG_IO:
e179729a 1860 return -ENOIOCTLCMD;
320a3827
KB		 1861 }
1862 return nvme_ioctl(bdev, mode, cmd, arg);
1863}
1864#else
1865#define nvme_compat_ioctl NULL
1866#endif
1867
9ac27090
KB		 1868static int nvme_open(struct block_device *bdev, fmode_t mode)
1869{
9e60352c
KB		 1870 int ret = 0;
1871 struct nvme_ns *ns;
9ac27090 1872
9e60352c
KB		 1873 spin_lock(&dev_list_lock);
1874 ns = bdev->bd_disk->private_data;
1875 if (!ns)
1876 ret = -ENXIO;
1877 else if (!kref_get_unless_zero(&ns->dev->kref))
1878 ret = -ENXIO;
1879 spin_unlock(&dev_list_lock);
1880
1881 return ret;
9ac27090
KB		 1882}
1883
1884static void nvme_free_dev(struct kref *kref);
1885
1886static void nvme_release(struct gendisk *disk, fmode_t mode)
1887{
1888 struct nvme_ns *ns = disk->private_data;
1889 struct nvme_dev *dev = ns->dev;
1890
1891 kref_put(&dev->kref, nvme_free_dev);
1892}
1893
4cc09e2d
KB		 1894static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1895{
1896 /* some standard values */
1897 geo->heads = 1 << 6;
1898 geo->sectors = 1 << 5;
1899 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1900 return 0;
1901}
1902
e1e5e564
KB		 1903static void nvme_config_discard(struct nvme_ns *ns)
1904{
1905 u32 logical_block_size = queue_logical_block_size(ns->queue);
1906 ns->queue->limits.discard_zeroes_data = 0;
1907 ns->queue->limits.discard_alignment = logical_block_size;
1908 ns->queue->limits.discard_granularity = logical_block_size;
1909 ns->queue->limits.max_discard_sectors = 0xffffffff;
1910 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1911}
1912
1b9dbf7f
KB		 1913static int nvme_revalidate_disk(struct gendisk *disk)
1914{
1915 struct nvme_ns *ns = disk->private_data;
1916 struct nvme_dev *dev = ns->dev;
1917 struct nvme_id_ns *id;
a67a9513
KB		 1918 u8 lbaf, pi_type;
1919 u16 old_ms;
e1e5e564 1920 unsigned short bs;
1b9dbf7f 1921
d29ec824
CH		 1922 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
1923 dev_warn(dev->dev, "%s: Identify failure\n", __func__);
1b9dbf7f
KB		 1924 return 0;
1925 }
1926
e1e5e564
KB		 1927 old_ms = ns->ms;
1928 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 1929 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 1930 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 1931 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 1932
1933 /*
1934 * If identify namespace failed, use default 512 byte block size so
1935 * block layer can use before failing read/write for 0 capacity.
1936 */
1937 if (ns->lba_shift == 0)
1938 ns->lba_shift = 9;
1939 bs = 1 << ns->lba_shift;
1940
1941 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
1942 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
1943 id->dps & NVME_NS_DPS_PI_MASK : 0;
1944
52b68d7e
KB		 1945 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
1946 ns->ms != old_ms ||
e1e5e564 1947 bs != queue_logical_block_size(disk->queue) ||
a67a9513 1948 (ns->ms && ns->ext)))
e1e5e564
KB		 1949 blk_integrity_unregister(disk);
1950
1951 ns->pi_type = pi_type;
1952 blk_queue_logical_block_size(ns->queue, bs);
1953
52b68d7e 1954 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
a67a9513 1955 !ns->ext)
e1e5e564
KB		 1956 nvme_init_integrity(ns);
1957
52b68d7e 1958 if (id->ncap == 0 || (ns->ms && !blk_get_integrity(disk)))
e1e5e564
KB		 1959 set_capacity(disk, 0);
1960 else
1961 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1962
1963 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1964 nvme_config_discard(ns);
1b9dbf7f 1965
d29ec824 1966 kfree(id);
1b9dbf7f
KB		 1967 return 0;
1968}
1969
b60503ba
MW		 1970static const struct block_device_operations nvme_fops = {
1971 .owner = THIS_MODULE,
1972 .ioctl = nvme_ioctl,
320a3827 1973 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1974 .open = nvme_open,
1975 .release = nvme_release,
4cc09e2d 1976 .getgeo = nvme_getgeo,
1b9dbf7f 1977 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 1978};
1979
1fa6aead
MW		 1980static int nvme_kthread(void *data)
1981{
d4b4ff8e 1982 struct nvme_dev *dev, *next;
1fa6aead
MW		 1983
1984 while (!kthread_should_stop()) {
564a232c 1985 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1986 spin_lock(&dev_list_lock);
d4b4ff8e 1987 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1988 int i;
07836e65 1989 if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
d4b4ff8e
KB		 1990 if (work_busy(&dev->reset_work))
1991 continue;
1992 list_del_init(&dev->node);
e75ec752 1993 dev_warn(dev->dev,
a4aea562
MB		 1994 "Failed status: %x, reset controller\n",
1995 readl(&dev->bar->csts));
9ca97374 1996 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1997 queue_work(nvme_workq, &dev->reset_work);
1998 continue;
1999 }
1fa6aead 2000 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2001 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2002 if (!nvmeq)
2003 continue;
1fa6aead 2004 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2005 nvme_process_cq(nvmeq);
6fccf938
KB		 2006
2007 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2008 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2009 break;
2010 dev->event_limit--;
2011 }
1fa6aead
MW		 2012 spin_unlock_irq(&nvmeq->q_lock);
2013 }
2014 }
2015 spin_unlock(&dev_list_lock);
acb7aa0d 2016 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2017 }
2018 return 0;
2019}
2020
e1e5e564 2021static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2022{
2023 struct nvme_ns *ns;
2024 struct gendisk *disk;
e75ec752 2025 int node = dev_to_node(dev->dev);
b60503ba 2026
a4aea562 2027 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2028 if (!ns)
e1e5e564
KB		 2029 return;
2030
a4aea562 2031 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2032 if (IS_ERR(ns->queue))
b60503ba 2033 goto out_free_ns;
4eeb9215
MW		 2034 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2035 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 2036 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 2037 ns->dev = dev;
2038 ns->queue->queuedata = ns;
2039
a4aea562 2040 disk = alloc_disk_node(0, node);
b60503ba
MW		 2041 if (!disk)
2042 goto out_free_queue;
a4aea562 2043
5aff9382 2044 ns->ns_id = nsid;
b60503ba 2045 ns->disk = disk;
e1e5e564
KB		 2046 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2047 list_add_tail(&ns->list, &dev->namespaces);
2048
e9ef4636 2049 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 2050 if (dev->max_hw_sectors)
2051 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 2052 if (dev->stripe_size)
2053 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2054 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2055 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 2056
2057 disk->major = nvme_major;
469071a3 2058 disk->first_minor = 0;
b60503ba
MW		 2059 disk->fops = &nvme_fops;
2060 disk->private_data = ns;
2061 disk->queue = ns->queue;
b3fffdef 2062 disk->driverfs_dev = dev->device;
469071a3 2063 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2064 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2065
e1e5e564
KB		 2066 /*
2067 * Initialize capacity to 0 until we establish the namespace format and
2068 * setup integrity extentions if necessary. The revalidate_disk after
2069 * add_disk allows the driver to register with integrity if the format
2070 * requires it.
2071 */
2072 set_capacity(disk, 0);
2073 nvme_revalidate_disk(ns->disk);
2074 add_disk(ns->disk);
2075 if (ns->ms)
2076 revalidate_disk(ns->disk);
2077 return;
b60503ba
MW		 2078 out_free_queue:
2079 blk_cleanup_queue(ns->queue);
2080 out_free_ns:
2081 kfree(ns);
b60503ba
MW		 2082}
2083
42f61420
KB		 2084static void nvme_create_io_queues(struct nvme_dev *dev)
2085{
a4aea562 2086 unsigned i;
42f61420 2087
a4aea562 2088 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2089 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2090 break;
2091
a4aea562
MB		 2092 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2093 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 2094 break;
2095}
2096
b3b06812 2097static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2098{
2099 int status;
2100 u32 result;
b3b06812 2101 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2102
df348139 2103 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2104 &result);
27e8166c
MW		 2105 if (status < 0)
2106 return status;
2107 if (status > 0) {
e75ec752 2108 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
badc34d4 2109 return 0;
27e8166c 2110 }
b60503ba
MW		 2111 return min(result & 0xffff, result >> 16) + 1;
2112}
2113
9d713c2b
KB		 2114static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2115{
b80d5ccc 2116 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2117}
2118
8d85fce7 2119static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2120{
a4aea562 2121 struct nvme_queue *adminq = dev->queues[0];
e75ec752 2122 struct pci_dev *pdev = to_pci_dev(dev->dev);
42f61420 2123 int result, i, vecs, nr_io_queues, size;
b60503ba 2124
42f61420 2125 nr_io_queues = num_possible_cpus();
b348b7d5 2126 result = set_queue_count(dev, nr_io_queues);
badc34d4 2127 if (result <= 0)
1b23484b 2128 return result;
b348b7d5
MW		 2129 if (result < nr_io_queues)
2130 nr_io_queues = result;
b60503ba 2131
9d713c2b
KB		 2132 size = db_bar_size(dev, nr_io_queues);
2133 if (size > 8192) {
f1938f6e 2134 iounmap(dev->bar);
9d713c2b
KB		 2135 do {
2136 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2137 if (dev->bar)
2138 break;
2139 if (!--nr_io_queues)
2140 return -ENOMEM;
2141 size = db_bar_size(dev, nr_io_queues);
2142 } while (1);
f1938f6e 2143 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2144 adminq->q_db = dev->dbs;
f1938f6e
MW		 2145 }
2146
9d713c2b 2147 /* Deregister the admin queue's interrupt */
3193f07b 2148 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2149
e32efbfc
JA		 2150 /*
2151 * If we enable msix early due to not intx, disable it again before
2152 * setting up the full range we need.
2153 */
2154 if (!pdev->irq)
2155 pci_disable_msix(pdev);
2156
be577fab 2157 for (i = 0; i < nr_io_queues; i++)
1b23484b 2158 dev->entry[i].entry = i;
be577fab
AG		 2159 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2160 if (vecs < 0) {
2161 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2162 if (vecs < 0) {
2163 vecs = 1;
2164 } else {
2165 for (i = 0; i < vecs; i++)
2166 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2167 }
2168 }
2169
063a8096
MW		 2170 /*
2171 * Should investigate if there's a performance win from allocating
2172 * more queues than interrupt vectors; it might allow the submission
2173 * path to scale better, even if the receive path is limited by the
2174 * number of interrupts.
2175 */
2176 nr_io_queues = vecs;
42f61420 2177 dev->max_qid = nr_io_queues;
063a8096 2178
3193f07b 2179 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2180 if (result)
22404274 2181 goto free_queues;
1b23484b 2182
cd638946 2183 /* Free previously allocated queues that are no longer usable */
42f61420 2184 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2185 nvme_create_io_queues(dev);
9ecdc946 2186
22404274 2187 return 0;
b60503ba 2188
22404274 2189 free_queues:
a1a5ef99 2190 nvme_free_queues(dev, 1);
22404274 2191 return result;
b60503ba
MW		 2192}
2193
422ef0c7
MW		 2194/*
2195 * Return: error value if an error occurred setting up the queues or calling
2196 * Identify Device. 0 if these succeeded, even if adding some of the
2197 * namespaces failed. At the moment, these failures are silent. TBD which
2198 * failures should be reported.
2199 */
8d85fce7 2200static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2201{
e75ec752 2202 struct pci_dev *pdev = to_pci_dev(dev->dev);
c3bfe717
MW		 2203 int res;
2204 unsigned nn, i;
51814232 2205 struct nvme_id_ctrl *ctrl;
159b67d7 2206 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2207
d29ec824 2208 res = nvme_identify_ctrl(dev, &ctrl);
b60503ba 2209 if (res) {
e75ec752 2210 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564 2211 return -EIO;
b60503ba
MW		 2212 }
2213
51814232 2214 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2215 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2216 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2217 dev->vwc = ctrl->vwc;
51814232
MW		 2218 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2219 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2220 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2221 if (ctrl->mdts)
8fc23e03 2222 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2223 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2224 (pdev->device == 0x0953) && ctrl->vs[3]) {
2225 unsigned int max_hw_sectors;
2226
159b67d7 2227 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2228 max_hw_sectors = dev->stripe_size >> (shift - 9);
2229 if (dev->max_hw_sectors) {
2230 dev->max_hw_sectors = min(max_hw_sectors,
2231 dev->max_hw_sectors);
2232 } else
2233 dev->max_hw_sectors = max_hw_sectors;
2234 }
d29ec824 2235 kfree(ctrl);
a4aea562
MB		 2236
2237 dev->tagset.ops = &nvme_mq_ops;
2238 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2239 dev->tagset.timeout = NVME_IO_TIMEOUT;
e75ec752 2240 dev->tagset.numa_node = dev_to_node(dev->dev);
a4aea562
MB		 2241 dev->tagset.queue_depth =
2242 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ac3dd5bd 2243 dev->tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 2244 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2245 dev->tagset.driver_data = dev;
2246
2247 if (blk_mq_alloc_tag_set(&dev->tagset))
e1e5e564 2248 return 0;
b60503ba 2249
e1e5e564
KB		 2250 for (i = 1; i <= nn; i++)
2251 nvme_alloc_ns(dev, i);
b60503ba 2252
e1e5e564 2253 return 0;
b60503ba
MW		 2254}
2255
0877cb0d
KB		 2256static int nvme_dev_map(struct nvme_dev *dev)
2257{
42f61420 2258 u64 cap;
0877cb0d 2259 int bars, result = -ENOMEM;
e75ec752 2260 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2261
2262 if (pci_enable_device_mem(pdev))
2263 return result;
2264
2265 dev->entry[0].vector = pdev->irq;
2266 pci_set_master(pdev);
2267 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2268 if (!bars)
2269 goto disable_pci;
2270
0877cb0d
KB		 2271 if (pci_request_selected_regions(pdev, bars, "nvme"))
2272 goto disable_pci;
2273
e75ec752
CH		 2274 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2275 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2276 goto disable;
0877cb0d 2277
0877cb0d
KB		 2278 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2279 if (!dev->bar)
2280 goto disable;
e32efbfc 2281
0e53d180
KB		 2282 if (readl(&dev->bar->csts) == -1) {
2283 result = -ENODEV;
2284 goto unmap;
2285 }
e32efbfc
JA		 2286
2287 /*
2288 * Some devices don't advertse INTx interrupts, pre-enable a single
2289 * MSIX vec for setup. We'll adjust this later.
2290 */
2291 if (!pdev->irq) {
2292 result = pci_enable_msix(pdev, dev->entry, 1);
2293 if (result < 0)
2294 goto unmap;
2295 }
2296
42f61420
KB		 2297 cap = readq(&dev->bar->cap);
2298 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2299 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2300 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2301
2302 return 0;
2303
0e53d180
KB		 2304 unmap:
2305 iounmap(dev->bar);
2306 dev->bar = NULL;
0877cb0d
KB		 2307 disable:
2308 pci_release_regions(pdev);
2309 disable_pci:
2310 pci_disable_device(pdev);
2311 return result;
2312}
2313
2314static void nvme_dev_unmap(struct nvme_dev *dev)
2315{
e75ec752
CH		 2316 struct pci_dev *pdev = to_pci_dev(dev->dev);
2317
2318 if (pdev->msi_enabled)
2319 pci_disable_msi(pdev);
2320 else if (pdev->msix_enabled)
2321 pci_disable_msix(pdev);
0877cb0d
KB		 2322
2323 if (dev->bar) {
2324 iounmap(dev->bar);
2325 dev->bar = NULL;
e75ec752 2326 pci_release_regions(pdev);
0877cb0d
KB		 2327 }
2328
e75ec752
CH		 2329 if (pci_is_enabled(pdev))
2330 pci_disable_device(pdev);
0877cb0d
KB		 2331}
2332
4d115420
KB		 2333struct nvme_delq_ctx {
2334 struct task_struct *waiter;
2335 struct kthread_worker *worker;
2336 atomic_t refcount;
2337};
2338
2339static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2340{
2341 dq->waiter = current;
2342 mb();
2343
2344 for (;;) {
2345 set_current_state(TASK_KILLABLE);
2346 if (!atomic_read(&dq->refcount))
2347 break;
2348 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2349 fatal_signal_pending(current)) {
0fb59cbc
KB		 2350 /*
2351 * Disable the controller first since we can't trust it
2352 * at this point, but leave the admin queue enabled
2353 * until all queue deletion requests are flushed.
2354 * FIXME: This may take a while if there are more h/w
2355 * queues than admin tags.
2356 */
4d115420 2357 set_current_state(TASK_RUNNING);
4d115420 2358 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2359 nvme_clear_queue(dev->queues[0]);
4d115420 2360 flush_kthread_worker(dq->worker);
0fb59cbc 2361 nvme_disable_queue(dev, 0);
4d115420
KB		 2362 return;
2363 }
2364 }
2365 set_current_state(TASK_RUNNING);
2366}
2367
2368static void nvme_put_dq(struct nvme_delq_ctx *dq)
2369{
2370 atomic_dec(&dq->refcount);
2371 if (dq->waiter)
2372 wake_up_process(dq->waiter);
2373}
2374
2375static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2376{
2377 atomic_inc(&dq->refcount);
2378 return dq;
2379}
2380
2381static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2382{
2383 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2384 nvme_put_dq(dq);
2385}
2386
2387static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2388 kthread_work_func_t fn)
2389{
2390 struct nvme_command c;
2391
2392 memset(&c, 0, sizeof(c));
2393 c.delete_queue.opcode = opcode;
2394 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2395
2396 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2397 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2398 ADMIN_TIMEOUT);
4d115420
KB		 2399}
2400
2401static void nvme_del_cq_work_handler(struct kthread_work *work)
2402{
2403 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2404 cmdinfo.work);
2405 nvme_del_queue_end(nvmeq);
2406}
2407
2408static int nvme_delete_cq(struct nvme_queue *nvmeq)
2409{
2410 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2411 nvme_del_cq_work_handler);
2412}
2413
2414static void nvme_del_sq_work_handler(struct kthread_work *work)
2415{
2416 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2417 cmdinfo.work);
2418 int status = nvmeq->cmdinfo.status;
2419
2420 if (!status)
2421 status = nvme_delete_cq(nvmeq);
2422 if (status)
2423 nvme_del_queue_end(nvmeq);
2424}
2425
2426static int nvme_delete_sq(struct nvme_queue *nvmeq)
2427{
2428 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2429 nvme_del_sq_work_handler);
2430}
2431
2432static void nvme_del_queue_start(struct kthread_work *work)
2433{
2434 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2435 cmdinfo.work);
4d115420
KB		 2436 if (nvme_delete_sq(nvmeq))
2437 nvme_del_queue_end(nvmeq);
2438}
2439
2440static void nvme_disable_io_queues(struct nvme_dev *dev)
2441{
2442 int i;
2443 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2444 struct nvme_delq_ctx dq;
2445 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2446 &worker, "nvme%d", dev->instance);
2447
2448 if (IS_ERR(kworker_task)) {
e75ec752 2449 dev_err(dev->dev,
4d115420
KB		 2450 "Failed to create queue del task\n");
2451 for (i = dev->queue_count - 1; i > 0; i--)
2452 nvme_disable_queue(dev, i);
2453 return;
2454 }
2455
2456 dq.waiter = NULL;
2457 atomic_set(&dq.refcount, 0);
2458 dq.worker = &worker;
2459 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2460 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2461
2462 if (nvme_suspend_queue(nvmeq))
2463 continue;
2464 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2465 nvmeq->cmdinfo.worker = dq.worker;
2466 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2467 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2468 }
2469 nvme_wait_dq(&dq, dev);
2470 kthread_stop(kworker_task);
2471}
2472
b9afca3e
DM		 2473/*
2474* Remove the node from the device list and check
2475* for whether or not we need to stop the nvme_thread.
2476*/
2477static void nvme_dev_list_remove(struct nvme_dev *dev)
2478{
2479 struct task_struct *tmp = NULL;
2480
2481 spin_lock(&dev_list_lock);
2482 list_del_init(&dev->node);
2483 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2484 tmp = nvme_thread;
2485 nvme_thread = NULL;
2486 }
2487 spin_unlock(&dev_list_lock);
2488
2489 if (tmp)
2490 kthread_stop(tmp);
2491}
2492
c9d3bf88
KB		 2493static void nvme_freeze_queues(struct nvme_dev *dev)
2494{
2495 struct nvme_ns *ns;
2496
2497 list_for_each_entry(ns, &dev->namespaces, list) {
2498 blk_mq_freeze_queue_start(ns->queue);
2499
cddcd72b 2500 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2501 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2502 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2503
2504 blk_mq_cancel_requeue_work(ns->queue);
2505 blk_mq_stop_hw_queues(ns->queue);
2506 }
2507}
2508
2509static void nvme_unfreeze_queues(struct nvme_dev *dev)
2510{
2511 struct nvme_ns *ns;
2512
2513 list_for_each_entry(ns, &dev->namespaces, list) {
2514 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2515 blk_mq_unfreeze_queue(ns->queue);
2516 blk_mq_start_stopped_hw_queues(ns->queue, true);
2517 blk_mq_kick_requeue_list(ns->queue);
2518 }
2519}
2520
f0b50732 2521static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2522{
22404274 2523 int i;
7c1b2450 2524 u32 csts = -1;
22404274 2525
b9afca3e 2526 nvme_dev_list_remove(dev);
1fa6aead 2527
c9d3bf88
KB		 2528 if (dev->bar) {
2529 nvme_freeze_queues(dev);
7c1b2450 2530 csts = readl(&dev->bar->csts);
c9d3bf88 2531 }
7c1b2450 2532 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2533 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2534 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2535 nvme_suspend_queue(nvmeq);
4d115420
KB		 2536 }
2537 } else {
2538 nvme_disable_io_queues(dev);
1894d8f1 2539 nvme_shutdown_ctrl(dev);
4d115420
KB		 2540 nvme_disable_queue(dev, 0);
2541 }
f0b50732 2542 nvme_dev_unmap(dev);
07836e65
KB		 2543
2544 for (i = dev->queue_count - 1; i >= 0; i--)
2545 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2546}
2547
2548static void nvme_dev_remove(struct nvme_dev *dev)
2549{
9ac27090 2550 struct nvme_ns *ns;
f0b50732 2551
9ac27090 2552 list_for_each_entry(ns, &dev->namespaces, list) {
e1e5e564 2553 if (ns->disk->flags & GENHD_FL_UP) {
52b68d7e 2554 if (blk_get_integrity(ns->disk))
e1e5e564 2555 blk_integrity_unregister(ns->disk);
9ac27090 2556 del_gendisk(ns->disk);
e1e5e564 2557 }
cef6a948
KB		 2558 if (!blk_queue_dying(ns->queue)) {
2559 blk_mq_abort_requeue_list(ns->queue);
9ac27090 2560 blk_cleanup_queue(ns->queue);
cef6a948 2561 }
b60503ba 2562 }
b60503ba
MW		 2563}
2564
091b6092
MW		 2565static int nvme_setup_prp_pools(struct nvme_dev *dev)
2566{
e75ec752 2567 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2568 PAGE_SIZE, PAGE_SIZE, 0);
2569 if (!dev->prp_page_pool)
2570 return -ENOMEM;
2571
99802a7a 2572 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2573 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2574 256, 256, 0);
2575 if (!dev->prp_small_pool) {
2576 dma_pool_destroy(dev->prp_page_pool);
2577 return -ENOMEM;
2578 }
091b6092
MW		 2579 return 0;
2580}
2581
2582static void nvme_release_prp_pools(struct nvme_dev *dev)
2583{
2584 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2585 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2586}
2587
cd58ad7d
QSA		 2588static DEFINE_IDA(nvme_instance_ida);
2589
2590static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2591{
cd58ad7d
QSA		 2592 int instance, error;
2593
2594 do {
2595 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2596 return -ENODEV;
2597
2598 spin_lock(&dev_list_lock);
2599 error = ida_get_new(&nvme_instance_ida, &instance);
2600 spin_unlock(&dev_list_lock);
2601 } while (error == -EAGAIN);
2602
2603 if (error)
2604 return -ENODEV;
2605
2606 dev->instance = instance;
2607 return 0;
b60503ba
MW		 2608}
2609
2610static void nvme_release_instance(struct nvme_dev *dev)
2611{
cd58ad7d
QSA		 2612 spin_lock(&dev_list_lock);
2613 ida_remove(&nvme_instance_ida, dev->instance);
2614 spin_unlock(&dev_list_lock);
b60503ba
MW		 2615}
2616
9ac27090
KB		 2617static void nvme_free_namespaces(struct nvme_dev *dev)
2618{
2619 struct nvme_ns *ns, *next;
2620
2621 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2622 list_del(&ns->list);
9e60352c
KB		 2623
2624 spin_lock(&dev_list_lock);
2625 ns->disk->private_data = NULL;
2626 spin_unlock(&dev_list_lock);
2627
9ac27090
KB		 2628 put_disk(ns->disk);
2629 kfree(ns);
2630 }
2631}
2632
5e82e952
KB		 2633static void nvme_free_dev(struct kref *kref)
2634{
2635 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2636
e75ec752 2637 put_device(dev->dev);
b3fffdef 2638 put_device(dev->device);
9ac27090 2639 nvme_free_namespaces(dev);
285dffc9 2640 nvme_release_instance(dev);
a4aea562 2641 blk_mq_free_tag_set(&dev->tagset);
ea191d2f 2642 blk_put_queue(dev->admin_q);
5e82e952
KB		 2643 kfree(dev->queues);
2644 kfree(dev->entry);
2645 kfree(dev);
2646}
2647
2648static int nvme_dev_open(struct inode *inode, struct file *f)
2649{
b3fffdef
KB		 2650 struct nvme_dev *dev;
2651 int instance = iminor(inode);
2652 int ret = -ENODEV;
2653
2654 spin_lock(&dev_list_lock);
2655 list_for_each_entry(dev, &dev_list, node) {
2656 if (dev->instance == instance) {
2e1d8448
KB		 2657 if (!dev->admin_q) {
2658 ret = -EWOULDBLOCK;
2659 break;
2660 }
b3fffdef
KB		 2661 if (!kref_get_unless_zero(&dev->kref))
2662 break;
2663 f->private_data = dev;
2664 ret = 0;
2665 break;
2666 }
2667 }
2668 spin_unlock(&dev_list_lock);
2669
2670 return ret;
5e82e952
KB		 2671}
2672
2673static int nvme_dev_release(struct inode *inode, struct file *f)
2674{
2675 struct nvme_dev *dev = f->private_data;
2676 kref_put(&dev->kref, nvme_free_dev);
2677 return 0;
2678}
2679
2680static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2681{
2682 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2683 struct nvme_ns *ns;
2684
5e82e952
KB		 2685 switch (cmd) {
2686 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2687 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2688 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2689 if (list_empty(&dev->namespaces))
2690 return -ENOTTY;
2691 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2692 return nvme_user_cmd(dev, ns, (void __user *)arg);
4cc06521
KB		 2693 case NVME_IOCTL_RESET:
2694 dev_warn(dev->dev, "resetting controller\n");
2695 return nvme_reset(dev);
5e82e952
KB		 2696 default:
2697 return -ENOTTY;
2698 }
2699}
2700
2701static const struct file_operations nvme_dev_fops = {
2702 .owner = THIS_MODULE,
2703 .open = nvme_dev_open,
2704 .release = nvme_dev_release,
2705 .unlocked_ioctl = nvme_dev_ioctl,
2706 .compat_ioctl = nvme_dev_ioctl,
2707};
2708
a4aea562
MB		 2709static void nvme_set_irq_hints(struct nvme_dev *dev)
2710{
2711 struct nvme_queue *nvmeq;
2712 int i;
2713
2714 for (i = 0; i < dev->online_queues; i++) {
2715 nvmeq = dev->queues[i];
2716
42483228 2717 if (!nvmeq->tags || !(*nvmeq->tags))
a4aea562
MB		 2718 continue;
2719
2720 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
42483228 2721 blk_mq_tags_cpumask(*nvmeq->tags));
a4aea562
MB		 2722 }
2723}
2724
f0b50732
KB		 2725static int nvme_dev_start(struct nvme_dev *dev)
2726{
2727 int result;
b9afca3e 2728 bool start_thread = false;
f0b50732
KB		 2729
2730 result = nvme_dev_map(dev);
2731 if (result)
2732 return result;
2733
2734 result = nvme_configure_admin_queue(dev);
2735 if (result)
2736 goto unmap;
2737
2738 spin_lock(&dev_list_lock);
b9afca3e
DM		 2739 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2740 start_thread = true;
2741 nvme_thread = NULL;
2742 }
f0b50732
KB		 2743 list_add(&dev->node, &dev_list);
2744 spin_unlock(&dev_list_lock);
2745
b9afca3e
DM		 2746 if (start_thread) {
2747 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2748 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2749 } else
2750 wait_event_killable(nvme_kthread_wait, nvme_thread);
2751
2752 if (IS_ERR_OR_NULL(nvme_thread)) {
2753 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2754 goto disable;
2755 }
a4aea562
MB		 2756
2757 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 2758 result = nvme_alloc_admin_tags(dev);
2759 if (result)
2760 goto disable;
b9afca3e 2761
f0b50732 2762 result = nvme_setup_io_queues(dev);
badc34d4 2763 if (result)
0fb59cbc 2764 goto free_tags;
f0b50732 2765
a4aea562
MB		 2766 nvme_set_irq_hints(dev);
2767
1efccc9d 2768 dev->event_limit = 1;
d82e8bfd 2769 return result;
f0b50732 2770
0fb59cbc
KB		 2771 free_tags:
2772 nvme_dev_remove_admin(dev);
f0b50732 2773 disable:
a1a5ef99 2774 nvme_disable_queue(dev, 0);
b9afca3e 2775 nvme_dev_list_remove(dev);
f0b50732
KB		 2776 unmap:
2777 nvme_dev_unmap(dev);
2778 return result;
2779}
2780
9a6b9458
KB		 2781static int nvme_remove_dead_ctrl(void *arg)
2782{
2783 struct nvme_dev *dev = (struct nvme_dev *)arg;
e75ec752 2784 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2785
2786 if (pci_get_drvdata(pdev))
c81f4975 2787 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2788 kref_put(&dev->kref, nvme_free_dev);
2789 return 0;
2790}
2791
2792static void nvme_remove_disks(struct work_struct *ws)
2793{
9a6b9458
KB		 2794 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2795
5a92e700 2796 nvme_free_queues(dev, 1);
302c6727 2797 nvme_dev_remove(dev);
9a6b9458
KB		 2798}
2799
2800static int nvme_dev_resume(struct nvme_dev *dev)
2801{
2802 int ret;
2803
2804 ret = nvme_dev_start(dev);
badc34d4 2805 if (ret)
9a6b9458 2806 return ret;
badc34d4 2807 if (dev->online_queues < 2) {
9a6b9458 2808 spin_lock(&dev_list_lock);
9ca97374 2809 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2810 queue_work(nvme_workq, &dev->reset_work);
2811 spin_unlock(&dev_list_lock);
c9d3bf88
KB		 2812 } else {
2813 nvme_unfreeze_queues(dev);
2814 nvme_set_irq_hints(dev);
9a6b9458
KB		 2815 }
2816 return 0;
2817}
2818
2819static void nvme_dev_reset(struct nvme_dev *dev)
2820{
2821 nvme_dev_shutdown(dev);
2822 if (nvme_dev_resume(dev)) {
e75ec752 2823 dev_warn(dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2824 kref_get(&dev->kref);
2825 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2826 dev->instance))) {
e75ec752 2827 dev_err(dev->dev,
9a6b9458
KB		 2828 "Failed to start controller remove task\n");
2829 kref_put(&dev->kref, nvme_free_dev);
2830 }
2831 }
2832}
2833
2834static void nvme_reset_failed_dev(struct work_struct *ws)
2835{
2836 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2837 nvme_dev_reset(dev);
2838}
2839
9ca97374
TH		 2840static void nvme_reset_workfn(struct work_struct *work)
2841{
2842 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2843 dev->reset_workfn(work);
2844}
2845
4cc06521
KB		 2846static int nvme_reset(struct nvme_dev *dev)
2847{
2848 int ret = -EBUSY;
2849
2850 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
2851 return -ENODEV;
2852
2853 spin_lock(&dev_list_lock);
2854 if (!work_pending(&dev->reset_work)) {
2855 dev->reset_workfn = nvme_reset_failed_dev;
2856 queue_work(nvme_workq, &dev->reset_work);
2857 ret = 0;
2858 }
2859 spin_unlock(&dev_list_lock);
2860
2861 if (!ret) {
2862 flush_work(&dev->reset_work);
2863 return 0;
2864 }
2865
2866 return ret;
2867}
2868
2869static ssize_t nvme_sysfs_reset(struct device *dev,
2870 struct device_attribute *attr, const char *buf,
2871 size_t count)
2872{
2873 struct nvme_dev *ndev = dev_get_drvdata(dev);
2874 int ret;
2875
2876 ret = nvme_reset(ndev);
2877 if (ret < 0)
2878 return ret;
2879
2880 return count;
2881}
2882static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
2883
2e1d8448 2884static void nvme_async_probe(struct work_struct *work);
8d85fce7 2885static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2886{
a4aea562 2887 int node, result = -ENOMEM;
b60503ba
MW		 2888 struct nvme_dev *dev;
2889
a4aea562
MB		 2890 node = dev_to_node(&pdev->dev);
2891 if (node == NUMA_NO_NODE)
2892 set_dev_node(&pdev->dev, 0);
2893
2894 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2895 if (!dev)
2896 return -ENOMEM;
a4aea562
MB		 2897 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2898 GFP_KERNEL, node);
b60503ba
MW		 2899 if (!dev->entry)
2900 goto free;
a4aea562
MB		 2901 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2902 GFP_KERNEL, node);
b60503ba
MW		 2903 if (!dev->queues)
2904 goto free;
2905
2906 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2907 dev->reset_workfn = nvme_reset_failed_dev;
2908 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
e75ec752 2909 dev->dev = get_device(&pdev->dev);
9a6b9458 2910 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2911 result = nvme_set_instance(dev);
2912 if (result)
a96d4f5c 2913 goto put_pci;
b60503ba 2914
091b6092
MW		 2915 result = nvme_setup_prp_pools(dev);
2916 if (result)
0877cb0d 2917 goto release;
091b6092 2918
fb35e914 2919 kref_init(&dev->kref);
b3fffdef
KB		 2920 dev->device = device_create(nvme_class, &pdev->dev,
2921 MKDEV(nvme_char_major, dev->instance),
2922 dev, "nvme%d", dev->instance);
2923 if (IS_ERR(dev->device)) {
2924 result = PTR_ERR(dev->device);
2e1d8448 2925 goto release_pools;
b3fffdef
KB		 2926 }
2927 get_device(dev->device);
4cc06521
KB		 2928 dev_set_drvdata(dev->device, dev);
2929
2930 result = device_create_file(dev->device, &dev_attr_reset_controller);
2931 if (result)
2932 goto put_dev;
740216fc 2933
e6e96d73 2934 INIT_LIST_HEAD(&dev->node);
2e1d8448
KB		 2935 INIT_WORK(&dev->probe_work, nvme_async_probe);
2936 schedule_work(&dev->probe_work);
b60503ba
MW		 2937 return 0;
2938
4cc06521
KB		 2939 put_dev:
2940 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
2941 put_device(dev->device);
0877cb0d 2942 release_pools:
091b6092 2943 nvme_release_prp_pools(dev);
0877cb0d
KB		 2944 release:
2945 nvme_release_instance(dev);
a96d4f5c 2946 put_pci:
e75ec752 2947 put_device(dev->dev);
b60503ba
MW		 2948 free:
2949 kfree(dev->queues);
2950 kfree(dev->entry);
2951 kfree(dev);
2952 return result;
2953}
2954
2e1d8448
KB		 2955static void nvme_async_probe(struct work_struct *work)
2956{
2957 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
2958 int result;
2959
2960 result = nvme_dev_start(dev);
2961 if (result)
2962 goto reset;
2963
2964 if (dev->online_queues > 1)
2965 result = nvme_dev_add(dev);
2966 if (result)
2967 goto reset;
2968
2969 nvme_set_irq_hints(dev);
2e1d8448
KB		 2970 return;
2971 reset:
4cc06521 2972 spin_lock(&dev_list_lock);
07836e65
KB		 2973 if (!work_busy(&dev->reset_work)) {
2974 dev->reset_workfn = nvme_reset_failed_dev;
2975 queue_work(nvme_workq, &dev->reset_work);
2976 }
4cc06521 2977 spin_unlock(&dev_list_lock);
2e1d8448
KB		 2978}
2979
f0d54a54
KB		 2980static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2981{
a6739479 2982 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2983
a6739479
KB		 2984 if (prepare)
2985 nvme_dev_shutdown(dev);
2986 else
2987 nvme_dev_resume(dev);
f0d54a54
KB		 2988}
2989
09ece142
KB		 2990static void nvme_shutdown(struct pci_dev *pdev)
2991{
2992 struct nvme_dev *dev = pci_get_drvdata(pdev);
2993 nvme_dev_shutdown(dev);
2994}
2995
8d85fce7 2996static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2997{
2998 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2999
3000 spin_lock(&dev_list_lock);
3001 list_del_init(&dev->node);
3002 spin_unlock(&dev_list_lock);
3003
3004 pci_set_drvdata(pdev, NULL);
2e1d8448 3005 flush_work(&dev->probe_work);
9a6b9458 3006 flush_work(&dev->reset_work);
4cc06521 3007 device_remove_file(dev->device, &dev_attr_reset_controller);
9a6b9458 3008 nvme_dev_shutdown(dev);
c9d3bf88 3009 nvme_dev_remove(dev);
a4aea562 3010 nvme_dev_remove_admin(dev);
b3fffdef 3011 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3012 nvme_free_queues(dev, 0);
9a6b9458 3013 nvme_release_prp_pools(dev);
5e82e952 3014 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3015}
3016
3017/* These functions are yet to be implemented */
3018#define nvme_error_detected NULL
3019#define nvme_dump_registers NULL
3020#define nvme_link_reset NULL
3021#define nvme_slot_reset NULL
3022#define nvme_error_resume NULL
cd638946 3023
671a6018 3024#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3025static int nvme_suspend(struct device *dev)
3026{
3027 struct pci_dev *pdev = to_pci_dev(dev);
3028 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3029
3030 nvme_dev_shutdown(ndev);
3031 return 0;
3032}
3033
3034static int nvme_resume(struct device *dev)
3035{
3036 struct pci_dev *pdev = to_pci_dev(dev);
3037 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3038
9a6b9458 3039 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 3040 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 3041 queue_work(nvme_workq, &ndev->reset_work);
3042 }
3043 return 0;
cd638946 3044}
671a6018 3045#endif
cd638946
KB		 3046
3047static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3048
1d352035 3049static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3050 .error_detected = nvme_error_detected,
3051 .mmio_enabled = nvme_dump_registers,
3052 .link_reset = nvme_link_reset,
3053 .slot_reset = nvme_slot_reset,
3054 .resume = nvme_error_resume,
f0d54a54 3055 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3056};
3057
3058/* Move to pci_ids.h later */
3059#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3060
6eb0d698 3061static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3062 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3063 { 0, }
3064};
3065MODULE_DEVICE_TABLE(pci, nvme_id_table);
3066
3067static struct pci_driver nvme_driver = {
3068 .name = "nvme",
3069 .id_table = nvme_id_table,
3070 .probe = nvme_probe,
8d85fce7 3071 .remove = nvme_remove,
09ece142 3072 .shutdown = nvme_shutdown,
cd638946
KB		 3073 .driver = {
3074 .pm = &nvme_dev_pm_ops,
3075 },
b60503ba
MW		 3076 .err_handler = &nvme_err_handler,
3077};
3078
3079static int __init nvme_init(void)
3080{
0ac13140 3081 int result;
1fa6aead 3082
b9afca3e 3083 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3084
9a6b9458
KB		 3085 nvme_workq = create_singlethread_workqueue("nvme");
3086 if (!nvme_workq)
b9afca3e 3087 return -ENOMEM;
9a6b9458 3088
5c42ea16
KB		 3089 result = register_blkdev(nvme_major, "nvme");
3090 if (result < 0)
9a6b9458 3091 goto kill_workq;
5c42ea16 3092 else if (result > 0)
0ac13140 3093 nvme_major = result;
b60503ba 3094
b3fffdef
KB		 3095 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3096 &nvme_dev_fops);
3097 if (result < 0)
3098 goto unregister_blkdev;
3099 else if (result > 0)
3100 nvme_char_major = result;
3101
3102 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3103 if (IS_ERR(nvme_class)) {
3104 result = PTR_ERR(nvme_class);
b3fffdef 3105 goto unregister_chrdev;
c727040b 3106 }
b3fffdef 3107
f3db22fe
KB		 3108 result = pci_register_driver(&nvme_driver);
3109 if (result)
b3fffdef 3110 goto destroy_class;
1fa6aead 3111 return 0;
b60503ba 3112
b3fffdef
KB		 3113 destroy_class:
3114 class_destroy(nvme_class);
3115 unregister_chrdev:
3116 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3117 unregister_blkdev:
b60503ba 3118 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3119 kill_workq:
3120 destroy_workqueue(nvme_workq);
b60503ba
MW		 3121 return result;
3122}
3123
3124static void __exit nvme_exit(void)
3125{
3126 pci_unregister_driver(&nvme_driver);
3127 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3128 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3129 class_destroy(nvme_class);
3130 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3131 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3132 _nvme_check_size();
b60503ba
MW		 3133}
3134
3135MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3136MODULE_LICENSE("GPL");
c78b4713 3137MODULE_VERSION("1.0");
b60503ba
MW		 3138module_init(nvme_init);
3139module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)