[linux-2.6-block.git] / drivers / ata / sata_vsc.c

/*
 *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
 *
 *  Maintained by:  Jeremy Higdon @ SGI
 * 		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 SGI
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Vitesse hardware documentation presumably available under NDA.
 *  Intel 31244 (same hardware interface) documentation presumably
 *  available from http://developer.intel.com/
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_vsc"
#define DRV_VERSION	"2.3"

enum {
	VSC_MMIO_BAR			= 0,

	/* Interrupt register offsets (from chip base address) */
	VSC_SATA_INT_STAT_OFFSET	= 0x00,
	VSC_SATA_INT_MASK_OFFSET	= 0x04,

	/* Taskfile registers offsets */
	VSC_SATA_TF_CMD_OFFSET		= 0x00,
	VSC_SATA_TF_DATA_OFFSET		= 0x00,
	VSC_SATA_TF_ERROR_OFFSET	= 0x04,
	VSC_SATA_TF_FEATURE_OFFSET	= 0x06,
	VSC_SATA_TF_NSECT_OFFSET	= 0x08,
	VSC_SATA_TF_LBAL_OFFSET		= 0x0c,
	VSC_SATA_TF_LBAM_OFFSET		= 0x10,
	VSC_SATA_TF_LBAH_OFFSET		= 0x14,
	VSC_SATA_TF_DEVICE_OFFSET	= 0x18,
	VSC_SATA_TF_STATUS_OFFSET	= 0x1c,
	VSC_SATA_TF_COMMAND_OFFSET	= 0x1d,
	VSC_SATA_TF_ALTSTATUS_OFFSET	= 0x28,
	VSC_SATA_TF_CTL_OFFSET		= 0x29,

	/* DMA base */
	VSC_SATA_UP_DESCRIPTOR_OFFSET	= 0x64,
	VSC_SATA_UP_DATA_BUFFER_OFFSET	= 0x6C,
	VSC_SATA_DMA_CMD_OFFSET		= 0x70,

	/* SCRs base */
	VSC_SATA_SCR_STATUS_OFFSET	= 0x100,
	VSC_SATA_SCR_ERROR_OFFSET	= 0x104,
	VSC_SATA_SCR_CONTROL_OFFSET	= 0x108,

	/* Port stride */
	VSC_SATA_PORT_OFFSET		= 0x200,

	/* Error interrupt status bit offsets */
	VSC_SATA_INT_ERROR_CRC		= 0x40,
	VSC_SATA_INT_ERROR_T		= 0x20,
	VSC_SATA_INT_ERROR_P		= 0x10,
	VSC_SATA_INT_ERROR_R		= 0x8,
	VSC_SATA_INT_ERROR_E		= 0x4,
	VSC_SATA_INT_ERROR_M		= 0x2,
	VSC_SATA_INT_PHY_CHANGE		= 0x1,
	VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
			      VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
			      VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
			      VSC_SATA_INT_PHY_CHANGE),
};

static int vsc_sata_scr_read(struct ata_link *link,
			     unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static int vsc_sata_scr_write(struct ata_link *link,
			      unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static void vsc_freeze(struct ata_port *ap)
{
	void __iomem *mask_addr;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;

	writeb(0, mask_addr);
}


static void vsc_thaw(struct ata_port *ap)
{
	void __iomem *mask_addr;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;

	writeb(0xff, mask_addr);
}


static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
{
	void __iomem *mask_addr;
	u8 mask;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	mask = readb(mask_addr);
	if (ctl & ATA_NIEN)
		mask |= 0x80;
	else
		mask &= 0x7F;
	writeb(mask, mask_addr);
}


static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	/*
	 * The only thing the ctl register is used for is SRST.
	 * That is not enabled or disabled via tf_load.
	 * However, if ATA_NIEN is changed, then we need to change
	 * the interrupt register.
	 */
	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
		ap->last_ctl = tf->ctl;
		vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = ata_sff_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
	}
}

static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
{
	if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
		ata_port_freeze(ap);
	else
		ata_port_abort(ap);
}

static void vsc_port_intr(u8 port_status, struct ata_port *ap)
{
	struct ata_queued_cmd *qc;
	int handled = 0;

	if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
		vsc_error_intr(port_status, ap);
		return;
	}

	qc = ata_qc_from_tag(ap, ap->link.active_tag);
	if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
		handled = ata_bmdma_port_intr(ap, qc);

	/* We received an interrupt during a polled command,
	 * or some other spurious condition.  Interrupt reporting
	 * with this hardware is fairly reliable so it is safe to
	 * simply clear the interrupt
	 */
	if (unlikely(!handled))
		ap->ops->sff_check_status(ap);
}

/*
 * vsc_sata_interrupt
 *
 * Read the interrupt register and process for the devices that have
 * them pending.
 */
static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	unsigned int i;
	unsigned int handled = 0;
	u32 status;

	status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);

	if (unlikely(status == 0xffffffff || status == 0)) {
		if (status)
			dev_err(host->dev,
				": IRQ status == 0xffffffff, PCI fault or device removal?\n");
		goto out;
	}

	spin_lock(&host->lock);

	for (i = 0; i < host->n_ports; i++) {
		u8 port_status = (status >> (8 * i)) & 0xff;
		if (port_status) {
			vsc_port_intr(port_status, host->ports[i]);
			handled++;
		}
	}

	spin_unlock(&host->lock);
out:
	return IRQ_RETVAL(handled);
}


static struct scsi_host_template vsc_sata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};


static struct ata_port_operations vsc_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	/* The IRQ handling is not quite standard SFF behaviour so we
	   cannot use the default lost interrupt handler */
	.lost_interrupt		= ATA_OP_NULL,
	.sff_tf_load		= vsc_sata_tf_load,
	.sff_tf_read		= vsc_sata_tf_read,
	.freeze			= vsc_freeze,
	.thaw			= vsc_thaw,
	.scr_read		= vsc_sata_scr_read,
	.scr_write		= vsc_sata_scr_write,
};

static void vsc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		= base + VSC_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + VSC_SATA_TF_DATA_OFFSET;
	port->error_addr	= base + VSC_SATA_TF_ERROR_OFFSET;
	port->feature_addr	= base + VSC_SATA_TF_FEATURE_OFFSET;
	port->nsect_addr	= base + VSC_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + VSC_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + VSC_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + VSC_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + VSC_SATA_TF_DEVICE_OFFSET;
	port->status_addr	= base + VSC_SATA_TF_STATUS_OFFSET;
	port->command_addr	= base + VSC_SATA_TF_COMMAND_OFFSET;
	port->altstatus_addr	= base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	port->ctl_addr		= base + VSC_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + VSC_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + VSC_SATA_SCR_STATUS_OFFSET;
	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
}


static int vsc_sata_init_one(struct pci_dev *pdev,
			     const struct pci_device_id *ent)
{
	static const struct ata_port_info pi = {
		.flags		= ATA_FLAG_SATA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &vsc_sata_ops,
	};
	const struct ata_port_info *ppi[] = { &pi, NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int i, rc;
	u8 cls;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	/* allocate host */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
	if (!host)
		return -ENOMEM;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* check if we have needed resource mapped */
	if (pci_resource_len(pdev, 0) == 0)
		return -ENODEV;

	/* map IO regions and initialize host accordingly */
	rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);

	mmio_base = host->iomap[VSC_MMIO_BAR];

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;

		vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);

		ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
		ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
	}

	/*
	 * Use 32 bit DMA mask, because 64 bit address support is poor.
	 */
	rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
	if (rc)
		return rc;
	rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
	if (rc)
		return rc;

	/*
	 * Due to a bug in the chip, the default cache line size can't be
	 * used (unless the default is non-zero).
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
	if (cls == 0x00)
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);

	if (pci_enable_msi(pdev) == 0)
		pci_intx(pdev, 0);

	/*
	 * Config offset 0x98 is "Extended Control and Status Register 0"
	 * Default value is (1 << 28).  All bits except bit 28 are reserved in
	 * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
	 * If bit 28 is clear, each port has its own LED.
	 */
	pci_write_config_dword(pdev, 0x98, 0);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
				 IRQF_SHARED, &vsc_sata_sht);
}

static const struct pci_device_id vsc_sata_pci_tbl[] = {
	{ PCI_VENDOR_ID_VITESSE, 0x7174,
	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
	{ PCI_VENDOR_ID_INTEL, 0x3200,
	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },

	{ }	/* terminate list */
};

static struct pci_driver vsc_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= vsc_sata_pci_tbl,
	.probe			= vsc_sata_init_one,
	.remove			= ata_pci_remove_one,
};

module_pci_driver(vsc_sata_pci_driver);

MODULE_AUTHOR("Jeremy Higdon");
MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
	3	*
	4	* Maintained by: Jeremy Higdon @ SGI
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 SGI
	9	*
	10	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	11	*
af36d7f0 JG	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2, or (at your option)
	16	* any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; see the file COPYING. If not, write to
	25	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	26	*
	27	*
	28	* libata documentation is available via 'make {ps\|pdf}docs',
	29	* as Documentation/DocBook/libata.*
	30	*
	31	* Vitesse hardware documentation presumably available under NDA.
	32	* Intel 31244 (same hardware interface) documentation presumably
	33	* available from http://developer.intel.com/
	34	*
1da177e4 LT	35	*/
	36
	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/pci.h>
1da177e4 LT	40	#include <linux/blkdev.h>
	41	#include <linux/delay.h>
	42	#include <linux/interrupt.h>
7003c05d	43	#include <linux/dma-mapping.h>
a9524a76	44	#include <linux/device.h>
1da177e4 LT	45	#include <scsi/scsi_host.h>
	46	#include <linux/libata.h>
	47
	48	#define DRV_NAME "sata_vsc"
2a3103ce	49	#define DRV_VERSION "2.3"
1da177e4	50
55cca65e	51	enum {
0d5ff566 TH	52	VSC_MMIO_BAR = 0,
0d5ff566 TH	53
55cca65e JG	54	/* Interrupt register offsets (from chip base address) */
	55	VSC_SATA_INT_STAT_OFFSET = 0x00,
	56	VSC_SATA_INT_MASK_OFFSET = 0x04,
1da177e4	57
55cca65e JG	58	/* Taskfile registers offsets */
	59	VSC_SATA_TF_CMD_OFFSET = 0x00,
	60	VSC_SATA_TF_DATA_OFFSET = 0x00,
	61	VSC_SATA_TF_ERROR_OFFSET = 0x04,
	62	VSC_SATA_TF_FEATURE_OFFSET = 0x06,
	63	VSC_SATA_TF_NSECT_OFFSET = 0x08,
	64	VSC_SATA_TF_LBAL_OFFSET = 0x0c,
	65	VSC_SATA_TF_LBAM_OFFSET = 0x10,
	66	VSC_SATA_TF_LBAH_OFFSET = 0x14,
	67	VSC_SATA_TF_DEVICE_OFFSET = 0x18,
	68	VSC_SATA_TF_STATUS_OFFSET = 0x1c,
	69	VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
	70	VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
	71	VSC_SATA_TF_CTL_OFFSET = 0x29,
1da177e4	72
55cca65e JG	73	/* DMA base */
	74	VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
	75	VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
	76	VSC_SATA_DMA_CMD_OFFSET = 0x70,
1da177e4	77
55cca65e JG	78	/* SCRs base */
	79	VSC_SATA_SCR_STATUS_OFFSET = 0x100,
	80	VSC_SATA_SCR_ERROR_OFFSET = 0x104,
	81	VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
1da177e4	82
55cca65e JG	83	/* Port stride */
	84	VSC_SATA_PORT_OFFSET = 0x200,
	85
	86	/* Error interrupt status bit offsets */
	87	VSC_SATA_INT_ERROR_CRC = 0x40,
	88	VSC_SATA_INT_ERROR_T = 0x20,
	89	VSC_SATA_INT_ERROR_P = 0x10,
	90	VSC_SATA_INT_ERROR_R = 0x8,
	91	VSC_SATA_INT_ERROR_E = 0x4,
	92	VSC_SATA_INT_ERROR_M = 0x2,
	93	VSC_SATA_INT_PHY_CHANGE = 0x1,
	94	VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC \| VSC_SATA_INT_ERROR_T \| \
	95	VSC_SATA_INT_ERROR_P \| VSC_SATA_INT_ERROR_R \| \
	96	VSC_SATA_INT_ERROR_E \| VSC_SATA_INT_ERROR_M \| \
	97	VSC_SATA_INT_PHY_CHANGE),
7cbaa86b	98	};
c962990a	99
82ef04fb TH	100	static int vsc_sata_scr_read(struct ata_link *link,
82ef04fb TH	101	unsigned int sc_reg, u32 *val)
1da177e4 LT	102	{
1da177e4 LT	103	if (sc_reg > SCR_CONTROL)
da3dbb17	104	return -EINVAL;
82ef04fb	105	val = readl(link->ap->ioaddr.scr_addr + (sc_reg 4));
da3dbb17	106	return 0;
1da177e4 LT	107	}
	108
	109
82ef04fb TH	110	static int vsc_sata_scr_write(struct ata_link *link,
82ef04fb TH	111	unsigned int sc_reg, u32 val)
1da177e4 LT	112	{
1da177e4 LT	113	if (sc_reg > SCR_CONTROL)
da3dbb17	114	return -EINVAL;
82ef04fb	115	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17	116	return 0;
1da177e4 LT	117	}
	118
	119
ea34e45a DW	120	static void vsc_freeze(struct ata_port *ap)
	121	{
	122	void __iomem *mask_addr;
	123
	124	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
	125	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	126
	127	writeb(0, mask_addr);
	128	}
	129
	130
	131	static void vsc_thaw(struct ata_port *ap)
	132	{
	133	void __iomem *mask_addr;
	134
	135	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
	136	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	137
	138	writeb(0xff, mask_addr);
	139	}
	140
	141
1da177e4 LT	142	static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
1da177e4 LT	143	{
307e4dc2	144	void __iomem *mask_addr;
1da177e4 LT	145	u8 mask;
1da177e4 LT	146
0d5ff566	147	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
1da177e4 LT	148	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	149	mask = readb(mask_addr);
	150	if (ctl & ATA_NIEN)
	151	mask \|= 0x80;
	152	else
	153	mask &= 0x7F;
	154	writeb(mask, mask_addr);
	155	}
	156
	157
057ace5e	158	static void vsc_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	159	{
	160	struct ata_ioports *ioaddr = &ap->ioaddr;
	161	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	162
	163	/*
	164	* The only thing the ctl register is used for is SRST.
	165	* That is not enabled or disabled via tf_load.
5796d1c4 JG	166	* However, if ATA_NIEN is changed, then we need to change
5796d1c4 JG	167	* the interrupt register.
1da177e4 LT	168	*/
	169	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
	170	ap->last_ctl = tf->ctl;
	171	vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	172	}
	173	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a	174	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
0d5ff566	175	ioaddr->feature_addr);
850a9d8a	176	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
0d5ff566	177	ioaddr->nsect_addr);
850a9d8a	178	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
0d5ff566	179	ioaddr->lbal_addr);
850a9d8a	180	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
0d5ff566	181	ioaddr->lbam_addr);
850a9d8a	182	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
0d5ff566	183	ioaddr->lbah_addr);
1da177e4	184	} else if (is_addr) {
0d5ff566 TH	185	writew(tf->feature, ioaddr->feature_addr);
	186	writew(tf->nsect, ioaddr->nsect_addr);
	187	writew(tf->lbal, ioaddr->lbal_addr);
	188	writew(tf->lbam, ioaddr->lbam_addr);
	189	writew(tf->lbah, ioaddr->lbah_addr);
1da177e4 LT	190	}
	191
	192	if (tf->flags & ATA_TFLAG_DEVICE)
0d5ff566	193	writeb(tf->device, ioaddr->device_addr);
1da177e4 LT	194
	195	ata_wait_idle(ap);
	196	}
	197
	198
	199	static void vsc_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	200	{
	201	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	202	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	203
9363c382	204	tf->command = ata_sff_check_status(ap);
0d5ff566 TH	205	tf->device = readw(ioaddr->device_addr);
	206	feature = readw(ioaddr->error_addr);
	207	nsect = readw(ioaddr->nsect_addr);
	208	lbal = readw(ioaddr->lbal_addr);
	209	lbam = readw(ioaddr->lbam_addr);
	210	lbah = readw(ioaddr->lbah_addr);
ac19bff2 JG	211
	212	tf->feature = feature;
	213	tf->nsect = nsect;
	214	tf->lbal = lbal;
	215	tf->lbam = lbam;
	216	tf->lbah = lbah;
1da177e4 LT	217
1da177e4 LT	218	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	219	tf->hob_feature = feature >> 8;
1da177e4 LT	220	tf->hob_nsect = nsect >> 8;
	221	tf->hob_lbal = lbal >> 8;
	222	tf->hob_lbam = lbam >> 8;
	223	tf->hob_lbah = lbah >> 8;
5796d1c4	224	}
1da177e4 LT	225	}
1da177e4 LT	226
ea34e45a DW	227	static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
	228	{
	229	if (port_status & (VSC_SATA_INT_PHY_CHANGE \| VSC_SATA_INT_ERROR_M))
	230	ata_port_freeze(ap);
	231	else
	232	ata_port_abort(ap);
	233	}
	234
	235	static void vsc_port_intr(u8 port_status, struct ata_port *ap)
	236	{
	237	struct ata_queued_cmd *qc;
	238	int handled = 0;
	239
	240	if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
	241	vsc_error_intr(port_status, ap);
	242	return;
	243	}
	244
9af5c9c9	245	qc = ata_qc_from_tag(ap, ap->link.active_tag);
ea34e45a	246	if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
c3b28894	247	handled = ata_bmdma_port_intr(ap, qc);
ea34e45a DW	248
	249	/* We received an interrupt during a polled command,
	250	* or some other spurious condition. Interrupt reporting
	251	* with this hardware is fairly reliable so it is safe to
	252	* simply clear the interrupt
	253	*/
	254	if (unlikely(!handled))
5682ed33	255	ap->ops->sff_check_status(ap);
ea34e45a	256	}
1da177e4 LT	257
	258	/*
	259	* vsc_sata_interrupt
	260	*
5796d1c4 JG	261	* Read the interrupt register and process for the devices that have
5796d1c4 JG	262	* them pending.
1da177e4	263	*/
5796d1c4	264	static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
1da177e4	265	{
cca3974e	266	struct ata_host *host = dev_instance;
1da177e4 LT	267	unsigned int i;
1da177e4 LT	268	unsigned int handled = 0;
ea34e45a	269	u32 status;
1da177e4	270
ea34e45a	271	status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
1da177e4	272
ea34e45a DW	273	if (unlikely(status == 0xffffffff \|\| status == 0)) {
ea34e45a DW	274	if (status)
a44fec1f JP	275	dev_err(host->dev,
a44fec1f JP	276	": IRQ status == 0xffffffff, PCI fault or device removal?\n");
ea34e45a DW	277	goto out;
ea34e45a DW	278	}
1da177e4	279
ea34e45a	280	spin_lock(&host->lock);
2ae5b30f	281
ea34e45a DW	282	for (i = 0; i < host->n_ports; i++) {
	283	u8 port_status = (status >> (8 * i)) & 0xff;
	284	if (port_status) {
3e4ec344 TH	285	vsc_port_intr(port_status, host->ports[i]);
3e4ec344 TH	286	handled++;
1da177e4 LT	287	}
	288	}
	289
cca3974e	290	spin_unlock(&host->lock);
ea34e45a	291	out:
1da177e4 LT	292	return IRQ_RETVAL(handled);
	293	}
	294
	295
193515d5	296	static struct scsi_host_template vsc_sata_sht = {
68d1d07b	297	ATA_BMDMA_SHT(DRV_NAME),
1da177e4 LT	298	};
	299
	300
029cfd6b TH	301	static struct ata_port_operations vsc_sata_ops = {
029cfd6b TH	302	.inherits = &ata_bmdma_port_ops,
c96f1732 AC	303	/* The IRQ handling is not quite standard SFF behaviour so we
	304	cannot use the default lost interrupt handler */
	305	.lost_interrupt = ATA_OP_NULL,
5682ed33 TH	306	.sff_tf_load = vsc_sata_tf_load,
5682ed33 TH	307	.sff_tf_read = vsc_sata_tf_read,
ea34e45a DW	308	.freeze = vsc_freeze,
ea34e45a DW	309	.thaw = vsc_thaw,
1da177e4 LT	310	.scr_read = vsc_sata_scr_read,
1da177e4 LT	311	.scr_write = vsc_sata_scr_write,
1da177e4 LT	312	};
1da177e4 LT	313
0ec24914	314	static void vsc_sata_setup_port(struct ata_ioports port, void __iomem base)
1da177e4 LT	315	{
	316	port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
	317	port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
	318	port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
	319	port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
	320	port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
	321	port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
	322	port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
	323	port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
	324	port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
	325	port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
	326	port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
	327	port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	328	port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
	329	port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
	330	port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
0d5ff566 TH	331	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
0d5ff566 TH	332	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
1da177e4 LT	333	}
	334
	335
0ec24914 GKH	336	static int vsc_sata_init_one(struct pci_dev *pdev,
0ec24914 GKH	337	const struct pci_device_id *ent)
1da177e4	338	{
4447d351	339	static const struct ata_port_info pi = {
9cbe056f	340	.flags = ATA_FLAG_SATA,
14bdef98 EIB	341	.pio_mask = ATA_PIO4,
14bdef98 EIB	342	.mwdma_mask = ATA_MWDMA2,
bf6263a8	343	.udma_mask = ATA_UDMA6,
4447d351 TH	344	.port_ops = &vsc_sata_ops,
	345	};
	346	const struct ata_port_info *ppi[] = { &pi, NULL };
4447d351	347	struct ata_host *host;
307e4dc2	348	void __iomem *mmio_base;
4447d351	349	int i, rc;
7de970e1	350	u8 cls;
1da177e4	351
06296a1e	352	ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4	353
4447d351 TH	354	/* allocate host */
	355	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
	356	if (!host)
	357	return -ENOMEM;
	358
24dc5f33	359	rc = pcim_enable_device(pdev);
1da177e4 LT	360	if (rc)
	361	return rc;
	362
4447d351	363	/* check if we have needed resource mapped */
24dc5f33 TH	364	if (pci_resource_len(pdev, 0) == 0)
24dc5f33 TH	365	return -ENODEV;
1da177e4	366
b595076a	367	/* map IO regions and initialize host accordingly */
0d5ff566 TH	368	rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
0d5ff566 TH	369	if (rc == -EBUSY)
24dc5f33	370	pcim_pin_device(pdev);
0d5ff566	371	if (rc)
24dc5f33	372	return rc;
4447d351 TH	373	host->iomap = pcim_iomap_table(pdev);
	374
	375	mmio_base = host->iomap[VSC_MMIO_BAR];
	376
cbcdd875 TH	377	for (i = 0; i < host->n_ports; i++) {
	378	struct ata_port *ap = host->ports[i];
	379	unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;
	380
	381	vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);
	382
	383	ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
	384	ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
	385	}
1da177e4 LT	386
	387	/*
	388	* Use 32 bit DMA mask, because 64 bit address support is poor.
	389	*/
c54c719b	390	rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4	391	if (rc)
24dc5f33	392	return rc;
c54c719b	393	rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4	394	if (rc)
24dc5f33	395	return rc;
7cbaa86b	396
1da177e4	397	/*
7de970e1 ND	398	* Due to a bug in the chip, the default cache line size can't be
7de970e1 ND	399	* used (unless the default is non-zero).
1da177e4	400	*/
7de970e1 ND	401	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
	402	if (cls == 0x00)
	403	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
1da177e4	404
24dc5f33	405	if (pci_enable_msi(pdev) == 0)
7cbaa86b	406	pci_intx(pdev, 0);
1da177e4	407
8a60a071	408	/*
1da177e4 LT	409	* Config offset 0x98 is "Extended Control and Status Register 0"
	410	* Default value is (1 << 28). All bits except bit 28 are reserved in
	411	* DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
	412	* If bit 28 is clear, each port has its own LED.
	413	*/
	414	pci_write_config_dword(pdev, 0x98, 0);
	415
4447d351 TH	416	pci_set_master(pdev);
	417	return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
	418	IRQF_SHARED, &vsc_sata_sht);
1da177e4 LT	419	}
1da177e4 LT	420
3b7d697d	421	static const struct pci_device_id vsc_sata_pci_tbl[] = {
438bc9c3	422	{ PCI_VENDOR_ID_VITESSE, 0x7174,
74d0a988	423	PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
438bc9c3	424	{ PCI_VENDOR_ID_INTEL, 0x3200,
74d0a988	425	PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
2d2744fc	426
438bc9c3	427	{ } /* terminate list */
1da177e4 LT	428	};
1da177e4 LT	429
1da177e4 LT	430	static struct pci_driver vsc_sata_pci_driver = {
	431	.name = DRV_NAME,
	432	.id_table = vsc_sata_pci_tbl,
	433	.probe = vsc_sata_init_one,
	434	.remove = ata_pci_remove_one,
	435	};
	436
2fc75da0	437	module_pci_driver(vsc_sata_pci_driver);
1da177e4	438
1da177e4 LT	439	MODULE_AUTHOR("Jeremy Higdon");
	440	MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
	441	MODULE_LICENSE("GPL");
	442	MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
	443	MODULE_VERSION(DRV_VERSION);