[linux-2.6-block.git] / drivers / ata / pdc_adma.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  pdc_adma.c - Pacific Digital Corporation ADMA
 *
 *  Maintained by:  Tejun Heo <tj@kernel.org>
 *
 *  Copyright 2005 Mark Lord
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/driver-api/libata.rst
 *
 *  Supports ATA disks in single-packet ADMA mode.
 *  Uses PIO for everything else.
 *
 *  TODO:  Use ADMA transfers for ATAPI devices, when possible.
 *  This requires careful attention to a number of quirks of the chip.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pdc_adma"
#define DRV_VERSION	"1.0"

/* macro to calculate base address for ATA regs */
#define ADMA_ATA_REGS(base, port_no)	((base) + ((port_no) * 0x40))

/* macro to calculate base address for ADMA regs */
#define ADMA_REGS(base, port_no)	((base) + 0x80 + ((port_no) * 0x20))

/* macro to obtain addresses from ata_port */
#define ADMA_PORT_REGS(ap) \
	ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)

enum {
	ADMA_MMIO_BAR		= 4,

	ADMA_PORTS		= 2,
	ADMA_CPB_BYTES		= 40,
	ADMA_PRD_BYTES		= LIBATA_MAX_PRD * 16,
	ADMA_PKT_BYTES		= ADMA_CPB_BYTES + ADMA_PRD_BYTES,

	ADMA_DMA_BOUNDARY	= 0xffffffff,

	/* global register offsets */
	ADMA_MODE_LOCK		= 0x00c7,

	/* per-channel register offsets */
	ADMA_CONTROL		= 0x0000, /* ADMA control */
	ADMA_STATUS		= 0x0002, /* ADMA status */
	ADMA_CPB_COUNT		= 0x0004, /* CPB count */
	ADMA_CPB_CURRENT	= 0x000c, /* current CPB address */
	ADMA_CPB_NEXT		= 0x000c, /* next CPB address */
	ADMA_CPB_LOOKUP		= 0x0010, /* CPB lookup table */
	ADMA_FIFO_IN		= 0x0014, /* input FIFO threshold */
	ADMA_FIFO_OUT		= 0x0016, /* output FIFO threshold */

	/* ADMA_CONTROL register bits */
	aNIEN			= (1 << 8), /* irq mask: 1==masked */
	aGO			= (1 << 7), /* packet trigger ("Go!") */
	aRSTADM			= (1 << 5), /* ADMA logic reset */
	aPIOMD4			= 0x0003,   /* PIO mode 4 */

	/* ADMA_STATUS register bits */
	aPSD			= (1 << 6),
	aUIRQ			= (1 << 4),
	aPERR			= (1 << 0),

	/* CPB bits */
	cDONE			= (1 << 0),
	cATERR			= (1 << 3),

	cVLD			= (1 << 0),
	cDAT			= (1 << 2),
	cIEN			= (1 << 3),

	/* PRD bits */
	pORD			= (1 << 4),
	pDIRO			= (1 << 5),
	pEND			= (1 << 7),

	/* ATA register flags */
	rIGN			= (1 << 5),
	rEND			= (1 << 7),

	/* ATA register addresses */
	ADMA_REGS_CONTROL	= 0x0e,
	ADMA_REGS_SECTOR_COUNT	= 0x12,
	ADMA_REGS_LBA_LOW	= 0x13,
	ADMA_REGS_LBA_MID	= 0x14,
	ADMA_REGS_LBA_HIGH	= 0x15,
	ADMA_REGS_DEVICE	= 0x16,
	ADMA_REGS_COMMAND	= 0x17,

	/* PCI device IDs */
	board_1841_idx		= 0,	/* ADMA 2-port controller */
};

typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;

struct adma_port_priv {
	u8			*pkt;
	dma_addr_t		pkt_dma;
	adma_state_t		state;
};

static int adma_ata_init_one(struct pci_dev *pdev,
				const struct pci_device_id *ent);
static int adma_port_start(struct ata_port *ap);
static void adma_port_stop(struct ata_port *ap);
static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc);
static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
static void adma_freeze(struct ata_port *ap);
static void adma_thaw(struct ata_port *ap);
static int adma_prereset(struct ata_link *link, unsigned long deadline);

static struct scsi_host_template adma_ata_sht = {
	ATA_BASE_SHT(DRV_NAME),
	.sg_tablesize		= LIBATA_MAX_PRD,
	.dma_boundary		= ADMA_DMA_BOUNDARY,
};

static struct ata_port_operations adma_ata_ops = {
	.inherits		= &ata_sff_port_ops,

	.lost_interrupt		= ATA_OP_NULL,

	.check_atapi_dma	= adma_check_atapi_dma,
	.qc_prep		= adma_qc_prep,
	.qc_issue		= adma_qc_issue,

	.freeze			= adma_freeze,
	.thaw			= adma_thaw,
	.prereset		= adma_prereset,

	.port_start		= adma_port_start,
	.port_stop		= adma_port_stop,
};

static struct ata_port_info adma_port_info[] = {
	/* board_1841_idx */
	{
		.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING,
		.pio_mask	= ATA_PIO4_ONLY,
		.udma_mask	= ATA_UDMA4,
		.port_ops	= &adma_ata_ops,
	},
};

static const struct pci_device_id adma_ata_pci_tbl[] = {
	{ PCI_VDEVICE(PDC, 0x1841), board_1841_idx },

	{ }	/* terminate list */
};

static struct pci_driver adma_ata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= adma_ata_pci_tbl,
	.probe			= adma_ata_init_one,
	.remove			= ata_pci_remove_one,
};

static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
{
	return 1;	/* ATAPI DMA not yet supported */
}

static void adma_reset_engine(struct ata_port *ap)
{
	void __iomem *chan = ADMA_PORT_REGS(ap);

	/* reset ADMA to idle state */
	writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
	udelay(2);
	writew(aPIOMD4, chan + ADMA_CONTROL);
	udelay(2);
}

static void adma_reinit_engine(struct ata_port *ap)
{
	struct adma_port_priv *pp = ap->private_data;
	void __iomem *chan = ADMA_PORT_REGS(ap);

	/* mask/clear ATA interrupts */
	writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
	ata_sff_check_status(ap);

	/* reset the ADMA engine */
	adma_reset_engine(ap);

	/* set in-FIFO threshold to 0x100 */
	writew(0x100, chan + ADMA_FIFO_IN);

	/* set CPB pointer */
	writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);

	/* set out-FIFO threshold to 0x100 */
	writew(0x100, chan + ADMA_FIFO_OUT);

	/* set CPB count */
	writew(1, chan + ADMA_CPB_COUNT);

	/* read/discard ADMA status */
	readb(chan + ADMA_STATUS);
}

static inline void adma_enter_reg_mode(struct ata_port *ap)
{
	void __iomem *chan = ADMA_PORT_REGS(ap);

	writew(aPIOMD4, chan + ADMA_CONTROL);
	readb(chan + ADMA_STATUS);	/* flush */
}

static void adma_freeze(struct ata_port *ap)
{
	void __iomem *chan = ADMA_PORT_REGS(ap);

	/* mask/clear ATA interrupts */
	writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
	ata_sff_check_status(ap);

	/* reset ADMA to idle state */
	writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
	udelay(2);
	writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
	udelay(2);
}

static void adma_thaw(struct ata_port *ap)
{
	adma_reinit_engine(ap);
}

static int adma_prereset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct adma_port_priv *pp = ap->private_data;

	if (pp->state != adma_state_idle) /* healthy paranoia */
		pp->state = adma_state_mmio;
	adma_reinit_engine(ap);

	return ata_sff_prereset(link, deadline);
}

static int adma_fill_sg(struct ata_queued_cmd *qc)
{
	struct scatterlist *sg;
	struct ata_port *ap = qc->ap;
	struct adma_port_priv *pp = ap->private_data;
	u8  *buf = pp->pkt, *last_buf = NULL;
	int i = (2 + buf[3]) * 8;
	u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
	unsigned int si;

	for_each_sg(qc->sg, sg, qc->n_elem, si) {
		u32 addr;
		u32 len;

		addr = (u32)sg_dma_address(sg);
		*(__le32 *)(buf + i) = cpu_to_le32(addr);
		i += 4;

		len = sg_dma_len(sg) >> 3;
		*(__le32 *)(buf + i) = cpu_to_le32(len);
		i += 4;

		last_buf = &buf[i];
		buf[i++] = pFLAGS;
		buf[i++] = qc->dev->dma_mode & 0xf;
		buf[i++] = 0;	/* pPKLW */
		buf[i++] = 0;	/* reserved */

		*(__le32 *)(buf + i) =
			(pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
		i += 4;

		VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
					(unsigned long)addr, len);
	}

	if (likely(last_buf))
		*last_buf |= pEND;

	return i;
}

static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc)
{
	struct adma_port_priv *pp = qc->ap->private_data;
	u8  *buf = pp->pkt;
	u32 pkt_dma = (u32)pp->pkt_dma;
	int i = 0;

	VPRINTK("ENTER\n");

	adma_enter_reg_mode(qc->ap);
	if (qc->tf.protocol != ATA_PROT_DMA)
		return AC_ERR_OK;

	buf[i++] = 0;	/* Response flags */
	buf[i++] = 0;	/* reserved */
	buf[i++] = cVLD | cDAT | cIEN;
	i++;		/* cLEN, gets filled in below */

	*(__le32 *)(buf+i) = cpu_to_le32(pkt_dma);	/* cNCPB */
	i += 4;		/* cNCPB */
	i += 4;		/* cPRD, gets filled in below */

	buf[i++] = 0;	/* reserved */
	buf[i++] = 0;	/* reserved */
	buf[i++] = 0;	/* reserved */
	buf[i++] = 0;	/* reserved */

	/* ATA registers; must be a multiple of 4 */
	buf[i++] = qc->tf.device;
	buf[i++] = ADMA_REGS_DEVICE;
	if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
		buf[i++] = qc->tf.hob_nsect;
		buf[i++] = ADMA_REGS_SECTOR_COUNT;
		buf[i++] = qc->tf.hob_lbal;
		buf[i++] = ADMA_REGS_LBA_LOW;
		buf[i++] = qc->tf.hob_lbam;
		buf[i++] = ADMA_REGS_LBA_MID;
		buf[i++] = qc->tf.hob_lbah;
		buf[i++] = ADMA_REGS_LBA_HIGH;
	}
	buf[i++] = qc->tf.nsect;
	buf[i++] = ADMA_REGS_SECTOR_COUNT;
	buf[i++] = qc->tf.lbal;
	buf[i++] = ADMA_REGS_LBA_LOW;
	buf[i++] = qc->tf.lbam;
	buf[i++] = ADMA_REGS_LBA_MID;
	buf[i++] = qc->tf.lbah;
	buf[i++] = ADMA_REGS_LBA_HIGH;
	buf[i++] = 0;
	buf[i++] = ADMA_REGS_CONTROL;
	buf[i++] = rIGN;
	buf[i++] = 0;
	buf[i++] = qc->tf.command;
	buf[i++] = ADMA_REGS_COMMAND | rEND;

	buf[3] = (i >> 3) - 2;				/* cLEN */
	*(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i);	/* cPRD */

	i = adma_fill_sg(qc);
	wmb();	/* flush PRDs and pkt to memory */
#if 0
	/* dump out CPB + PRDs for debug */
	{
		int j, len = 0;
		static char obuf[2048];
		for (j = 0; j < i; ++j) {
			len += sprintf(obuf+len, "%02x ", buf[j]);
			if ((j & 7) == 7) {
				printk("%s\n", obuf);
				len = 0;
			}
		}
		if (len)
			printk("%s\n", obuf);
	}
#endif
	return AC_ERR_OK;
}

static inline void adma_packet_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void __iomem *chan = ADMA_PORT_REGS(ap);

	VPRINTK("ENTER, ap %p\n", ap);

	/* fire up the ADMA engine */
	writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
}

static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
{
	struct adma_port_priv *pp = qc->ap->private_data;

	switch (qc->tf.protocol) {
	case ATA_PROT_DMA:
		pp->state = adma_state_pkt;
		adma_packet_start(qc);
		return 0;

	case ATAPI_PROT_DMA:
		BUG();
		break;

	default:
		break;
	}

	pp->state = adma_state_mmio;
	return ata_sff_qc_issue(qc);
}

static inline unsigned int adma_intr_pkt(struct ata_host *host)
{
	unsigned int handled = 0, port_no;

	for (port_no = 0; port_no < host->n_ports; ++port_no) {
		struct ata_port *ap = host->ports[port_no];
		struct adma_port_priv *pp;
		struct ata_queued_cmd *qc;
		void __iomem *chan = ADMA_PORT_REGS(ap);
		u8 status = readb(chan + ADMA_STATUS);

		if (status == 0)
			continue;
		handled = 1;
		adma_enter_reg_mode(ap);
		pp = ap->private_data;
		if (!pp || pp->state != adma_state_pkt)
			continue;
		qc = ata_qc_from_tag(ap, ap->link.active_tag);
		if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
			if (status & aPERR)
				qc->err_mask |= AC_ERR_HOST_BUS;
			else if ((status & (aPSD | aUIRQ)))
				qc->err_mask |= AC_ERR_OTHER;

			if (pp->pkt[0] & cATERR)
				qc->err_mask |= AC_ERR_DEV;
			else if (pp->pkt[0] != cDONE)
				qc->err_mask |= AC_ERR_OTHER;

			if (!qc->err_mask)
				ata_qc_complete(qc);
			else {
				struct ata_eh_info *ehi = &ap->link.eh_info;
				ata_ehi_clear_desc(ehi);
				ata_ehi_push_desc(ehi,
					"ADMA-status 0x%02X", status);
				ata_ehi_push_desc(ehi,
					"pkt[0] 0x%02X", pp->pkt[0]);

				if (qc->err_mask == AC_ERR_DEV)
					ata_port_abort(ap);
				else
					ata_port_freeze(ap);
			}
		}
	}
	return handled;
}

static inline unsigned int adma_intr_mmio(struct ata_host *host)
{
	unsigned int handled = 0, port_no;

	for (port_no = 0; port_no < host->n_ports; ++port_no) {
		struct ata_port *ap = host->ports[port_no];
		struct adma_port_priv *pp = ap->private_data;
		struct ata_queued_cmd *qc;

		if (!pp || pp->state != adma_state_mmio)
			continue;
		qc = ata_qc_from_tag(ap, ap->link.active_tag);
		if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {

			/* check main status, clearing INTRQ */
			u8 status = ata_sff_check_status(ap);
			if ((status & ATA_BUSY))
				continue;
			DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
				ap->print_id, qc->tf.protocol, status);

			/* complete taskfile transaction */
			pp->state = adma_state_idle;
			qc->err_mask |= ac_err_mask(status);
			if (!qc->err_mask)
				ata_qc_complete(qc);
			else {
				struct ata_eh_info *ehi = &ap->link.eh_info;
				ata_ehi_clear_desc(ehi);
				ata_ehi_push_desc(ehi, "status 0x%02X", status);

				if (qc->err_mask == AC_ERR_DEV)
					ata_port_abort(ap);
				else
					ata_port_freeze(ap);
			}
			handled = 1;
		}
	}
	return handled;
}

static irqreturn_t adma_intr(int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	unsigned int handled = 0;

	VPRINTK("ENTER\n");

	spin_lock(&host->lock);
	handled  = adma_intr_pkt(host) | adma_intr_mmio(host);
	spin_unlock(&host->lock);

	VPRINTK("EXIT\n");

	return IRQ_RETVAL(handled);
}

static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		=
	port->data_addr		= base + 0x000;
	port->error_addr	=
	port->feature_addr	= base + 0x004;
	port->nsect_addr	= base + 0x008;
	port->lbal_addr		= base + 0x00c;
	port->lbam_addr		= base + 0x010;
	port->lbah_addr		= base + 0x014;
	port->device_addr	= base + 0x018;
	port->status_addr	=
	port->command_addr	= base + 0x01c;
	port->altstatus_addr	=
	port->ctl_addr		= base + 0x038;
}

static int adma_port_start(struct ata_port *ap)
{
	struct device *dev = ap->host->dev;
	struct adma_port_priv *pp;

	adma_enter_reg_mode(ap);
	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
	if (!pp)
		return -ENOMEM;
	pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
				      GFP_KERNEL);
	if (!pp->pkt)
		return -ENOMEM;
	/* paranoia? */
	if ((pp->pkt_dma & 7) != 0) {
		printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
						(u32)pp->pkt_dma);
		return -ENOMEM;
	}
	ap->private_data = pp;
	adma_reinit_engine(ap);
	return 0;
}

static void adma_port_stop(struct ata_port *ap)
{
	adma_reset_engine(ap);
}

static void adma_host_init(struct ata_host *host, unsigned int chip_id)
{
	unsigned int port_no;

	/* enable/lock aGO operation */
	writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);

	/* reset the ADMA logic */
	for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
		adma_reset_engine(host->ports[port_no]);
}

static int adma_ata_init_one(struct pci_dev *pdev,
			     const struct pci_device_id *ent)
{
	unsigned int board_idx = (unsigned int) ent->driver_data;
	const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int rc, port_no;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	/* alloc host */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
	if (!host)
		return -ENOMEM;

	/* acquire resources and fill host */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
		return -ENODEV;

	rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	mmio_base = host->iomap[ADMA_MMIO_BAR];

	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
	if (rc) {
		dev_err(&pdev->dev, "32-bit DMA enable failed\n");
		return rc;
	}

	for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
		struct ata_port *ap = host->ports[port_no];
		void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
		unsigned int offset = port_base - mmio_base;

		adma_ata_setup_port(&ap->ioaddr, port_base);

		ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
		ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
	}

	/* initialize adapter */
	adma_host_init(host, board_idx);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
				 &adma_ata_sht);
}

module_pci_driver(adma_ata_pci_driver);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
c82ee6d3	1	// SPDX-License-Identifier: GPL-2.0-or-later
edea3ab5 ML	2	/*
	3	* pdc_adma.c - Pacific Digital Corporation ADMA
	4	*
8c3d3d4b	5	* Maintained by: Tejun Heo <tj@kernel.org>
edea3ab5 ML	6	*
	7	* Copyright 2005 Mark Lord
	8	*
68399bb5	9	* libata documentation is available via 'make {ps\|pdf}docs',
19285f3c	10	* as Documentation/driver-api/libata.rst
edea3ab5	11	*
edea3ab5 ML	12	* Supports ATA disks in single-packet ADMA mode.
	13	* Uses PIO for everything else.
	14	*
	15	* TODO: Use ADMA transfers for ATAPI devices, when possible.
	16	* This requires careful attention to a number of quirks of the chip.
edea3ab5 ML	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
5a0e3ad6	21	#include <linux/gfp.h>
edea3ab5	22	#include <linux/pci.h>
edea3ab5 ML	23	#include <linux/blkdev.h>
	24	#include <linux/delay.h>
	25	#include <linux/interrupt.h>
a9524a76	26	#include <linux/device.h>
edea3ab5	27	#include <scsi/scsi_host.h>
edea3ab5 ML	28	#include <linux/libata.h>
	29
	30	#define DRV_NAME "pdc_adma"
2a3103ce	31	#define DRV_VERSION "1.0"
edea3ab5 ML	32
edea3ab5 ML	33	/* macro to calculate base address for ATA regs */
5796d1c4	34	#define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
edea3ab5 ML	35
edea3ab5 ML	36	/* macro to calculate base address for ADMA regs */
5796d1c4	37	#define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
0d5ff566	38
5d728824 TH	39	/* macro to obtain addresses from ata_port */
	40	#define ADMA_PORT_REGS(ap) \
	41	ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
edea3ab5 ML	42
edea3ab5 ML	43	enum {
0d5ff566 TH	44	ADMA_MMIO_BAR = 4,
0d5ff566 TH	45
edea3ab5 ML	46	ADMA_PORTS = 2,
	47	ADMA_CPB_BYTES = 40,
	48	ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
	49	ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
	50
	51	ADMA_DMA_BOUNDARY = 0xffffffff,
	52
	53	/* global register offsets */
	54	ADMA_MODE_LOCK = 0x00c7,
	55
	56	/* per-channel register offsets */
	57	ADMA_CONTROL = 0x0000, /* ADMA control */
	58	ADMA_STATUS = 0x0002, /* ADMA status */
	59	ADMA_CPB_COUNT = 0x0004, /* CPB count */
	60	ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
	61	ADMA_CPB_NEXT = 0x000c, /* next CPB address */
	62	ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
	63	ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
	64	ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
	65
	66	/* ADMA_CONTROL register bits */
	67	aNIEN = (1 << 8), /* irq mask: 1==masked */
	68	aGO = (1 << 7), /* packet trigger ("Go!") */
	69	aRSTADM = (1 << 5), /* ADMA logic reset */
edea3ab5 ML	70	aPIOMD4 = 0x0003, /* PIO mode 4 */
	71
	72	/* ADMA_STATUS register bits */
	73	aPSD = (1 << 6),
	74	aUIRQ = (1 << 4),
	75	aPERR = (1 << 0),
	76
	77	/* CPB bits */
	78	cDONE = (1 << 0),
640fdb50 JG	79	cATERR = (1 << 3),
640fdb50 JG	80
edea3ab5 ML	81	cVLD = (1 << 0),
	82	cDAT = (1 << 2),
	83	cIEN = (1 << 3),
	84
	85	/* PRD bits */
	86	pORD = (1 << 4),
	87	pDIRO = (1 << 5),
	88	pEND = (1 << 7),
	89
	90	/* ATA register flags */
	91	rIGN = (1 << 5),
	92	rEND = (1 << 7),
	93
	94	/* ATA register addresses */
	95	ADMA_REGS_CONTROL = 0x0e,
	96	ADMA_REGS_SECTOR_COUNT = 0x12,
	97	ADMA_REGS_LBA_LOW = 0x13,
	98	ADMA_REGS_LBA_MID = 0x14,
	99	ADMA_REGS_LBA_HIGH = 0x15,
	100	ADMA_REGS_DEVICE = 0x16,
	101	ADMA_REGS_COMMAND = 0x17,
	102
	103	/* PCI device IDs */
	104	board_1841_idx = 0, /* ADMA 2-port controller */
	105	};
	106
	107	typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
	108
	109	struct adma_port_priv {
	110	u8 *pkt;
	111	dma_addr_t pkt_dma;
	112	adma_state_t state;
	113	};
	114
5796d1c4	115	static int adma_ata_init_one(struct pci_dev *pdev,
edea3ab5	116	const struct pci_device_id *ent);
edea3ab5	117	static int adma_port_start(struct ata_port *ap);
edea3ab5	118	static void adma_port_stop(struct ata_port *ap);
95364f36	119	static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0	120	static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
edea3ab5	121	static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
640fdb50 JG	122	static void adma_freeze(struct ata_port *ap);
640fdb50 JG	123	static void adma_thaw(struct ata_port *ap);
a1efdaba	124	static int adma_prereset(struct ata_link *link, unsigned long deadline);
edea3ab5	125
193515d5	126	static struct scsi_host_template adma_ata_sht = {
68d1d07b	127	ATA_BASE_SHT(DRV_NAME),
edea3ab5	128	.sg_tablesize = LIBATA_MAX_PRD,
49de0ac8	129	.dma_boundary = ADMA_DMA_BOUNDARY,
edea3ab5 ML	130	};
edea3ab5 ML	131
029cfd6b	132	static struct ata_port_operations adma_ata_ops = {
b0316b15 TH	133	.inherits = &ata_sff_port_ops,
b0316b15 TH	134
c96f1732 AC	135	.lost_interrupt = ATA_OP_NULL,
c96f1732 AC	136
029cfd6b	137	.check_atapi_dma = adma_check_atapi_dma,
edea3ab5 ML	138	.qc_prep = adma_qc_prep,
edea3ab5 ML	139	.qc_issue = adma_qc_issue,
029cfd6b	140
640fdb50 JG	141	.freeze = adma_freeze,
640fdb50 JG	142	.thaw = adma_thaw,
a1efdaba	143	.prereset = adma_prereset,
029cfd6b	144
edea3ab5 ML	145	.port_start = adma_port_start,
edea3ab5 ML	146	.port_stop = adma_port_stop,
edea3ab5 ML	147	};
	148
	149	static struct ata_port_info adma_port_info[] = {
	150	/* board_1841_idx */
	151	{
9cbe056f	152	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_PIO_POLLING,
14bdef98	153	.pio_mask = ATA_PIO4_ONLY,
bf6263a8	154	.udma_mask = ATA_UDMA4,
edea3ab5 ML	155	.port_ops = &adma_ata_ops,
	156	},
	157	};
	158
3b7d697d	159	static const struct pci_device_id adma_ata_pci_tbl[] = {
54bb3a94	160	{ PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
edea3ab5 ML	161
	162	{ } /* terminate list */
	163	};
	164
	165	static struct pci_driver adma_ata_pci_driver = {
	166	.name = DRV_NAME,
	167	.id_table = adma_ata_pci_tbl,
	168	.probe = adma_ata_init_one,
	169	.remove = ata_pci_remove_one,
	170	};
	171
	172	static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
	173	{
	174	return 1; /* ATAPI DMA not yet supported */
	175	}
	176
5d728824	177	static void adma_reset_engine(struct ata_port *ap)
edea3ab5	178	{
5d728824 TH	179	void __iomem *chan = ADMA_PORT_REGS(ap);
5d728824 TH	180
edea3ab5 ML	181	/* reset ADMA to idle state */
	182	writew(aPIOMD4 \| aNIEN \| aRSTADM, chan + ADMA_CONTROL);
	183	udelay(2);
	184	writew(aPIOMD4, chan + ADMA_CONTROL);
	185	udelay(2);
	186	}
	187
	188	static void adma_reinit_engine(struct ata_port *ap)
	189	{
	190	struct adma_port_priv *pp = ap->private_data;
5d728824	191	void __iomem *chan = ADMA_PORT_REGS(ap);
edea3ab5 ML	192
edea3ab5 ML	193	/* mask/clear ATA interrupts */
0d5ff566	194	writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
9363c382	195	ata_sff_check_status(ap);
edea3ab5 ML	196
edea3ab5 ML	197	/* reset the ADMA engine */
5d728824	198	adma_reset_engine(ap);
edea3ab5 ML	199
	200	/* set in-FIFO threshold to 0x100 */
	201	writew(0x100, chan + ADMA_FIFO_IN);
	202
	203	/* set CPB pointer */
	204	writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
	205
	206	/* set out-FIFO threshold to 0x100 */
	207	writew(0x100, chan + ADMA_FIFO_OUT);
	208
	209	/* set CPB count */
	210	writew(1, chan + ADMA_CPB_COUNT);
	211
	212	/* read/discard ADMA status */
	213	readb(chan + ADMA_STATUS);
	214	}
	215
	216	static inline void adma_enter_reg_mode(struct ata_port *ap)
	217	{
5d728824	218	void __iomem *chan = ADMA_PORT_REGS(ap);
edea3ab5 ML	219
	220	writew(aPIOMD4, chan + ADMA_CONTROL);
	221	readb(chan + ADMA_STATUS); /* flush */
	222	}
	223
640fdb50	224	static void adma_freeze(struct ata_port *ap)
edea3ab5	225	{
640fdb50 JG	226	void __iomem *chan = ADMA_PORT_REGS(ap);
	227
	228	/* mask/clear ATA interrupts */
	229	writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
9363c382	230	ata_sff_check_status(ap);
640fdb50 JG	231
	232	/* reset ADMA to idle state */
	233	writew(aPIOMD4 \| aNIEN \| aRSTADM, chan + ADMA_CONTROL);
	234	udelay(2);
	235	writew(aPIOMD4 \| aNIEN, chan + ADMA_CONTROL);
	236	udelay(2);
	237	}
edea3ab5	238
640fdb50 JG	239	static void adma_thaw(struct ata_port *ap)
640fdb50 JG	240	{
edea3ab5	241	adma_reinit_engine(ap);
edea3ab5 ML	242	}
edea3ab5 ML	243
0260731f	244	static int adma_prereset(struct ata_link *link, unsigned long deadline)
edea3ab5	245	{
0260731f	246	struct ata_port *ap = link->ap;
edea3ab5 ML	247	struct adma_port_priv *pp = ap->private_data;
	248
	249	if (pp->state != adma_state_idle) /* healthy paranoia */
	250	pp->state = adma_state_mmio;
	251	adma_reinit_engine(ap);
640fdb50	252
9363c382	253	return ata_sff_prereset(link, deadline);
640fdb50 JG	254	}
640fdb50 JG	255
edea3ab5 ML	256	static int adma_fill_sg(struct ata_queued_cmd *qc)
edea3ab5 ML	257	{
972c26bd	258	struct scatterlist *sg;
edea3ab5 ML	259	struct ata_port *ap = qc->ap;
edea3ab5 ML	260	struct adma_port_priv *pp = ap->private_data;
3be6cbd7	261	u8 buf = pp->pkt, last_buf = NULL;
972c26bd	262	int i = (2 + buf[3]) * 8;
edea3ab5	263	u8 pFLAGS = pORD \| ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
ff2aeb1e	264	unsigned int si;
edea3ab5	265
ff2aeb1e	266	for_each_sg(qc->sg, sg, qc->n_elem, si) {
edea3ab5 ML	267	u32 addr;
	268	u32 len;
	269
	270	addr = (u32)sg_dma_address(sg);
	271	(__le32 )(buf + i) = cpu_to_le32(addr);
	272	i += 4;
	273
	274	len = sg_dma_len(sg) >> 3;
	275	(__le32 )(buf + i) = cpu_to_le32(len);
	276	i += 4;
	277
3be6cbd7	278	last_buf = &buf[i];
edea3ab5 ML	279	buf[i++] = pFLAGS;
	280	buf[i++] = qc->dev->dma_mode & 0xf;
	281	buf[i++] = 0; /* pPKLW */
	282	buf[i++] = 0; /* reserved */
	283
5796d1c4 JG	284	(__le32 )(buf + i) =
5796d1c4 JG	285	(pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
edea3ab5 ML	286	i += 4;
edea3ab5 ML	287
db7f44d9	288	VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
edea3ab5 ML	289	(unsigned long)addr, len);
edea3ab5 ML	290	}
3be6cbd7 JG	291
	292	if (likely(last_buf))
	293	*last_buf \|= pEND;
	294
edea3ab5 ML	295	return i;
	296	}
	297
95364f36	298	static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc)
edea3ab5 ML	299	{
	300	struct adma_port_priv *pp = qc->ap->private_data;
	301	u8 *buf = pp->pkt;
	302	u32 pkt_dma = (u32)pp->pkt_dma;
	303	int i = 0;
	304
	305	VPRINTK("ENTER\n");
	306
	307	adma_enter_reg_mode(qc->ap);
f47451c4	308	if (qc->tf.protocol != ATA_PROT_DMA)
95364f36	309	return AC_ERR_OK;
edea3ab5 ML	310
	311	buf[i++] = 0; /* Response flags */
	312	buf[i++] = 0; /* reserved */
	313	buf[i++] = cVLD \| cDAT \| cIEN;
	314	i++; /* cLEN, gets filled in below */
	315
	316	(__le32 )(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
	317	i += 4; /* cNCPB */
	318	i += 4; /* cPRD, gets filled in below */
	319
	320	buf[i++] = 0; /* reserved */
	321	buf[i++] = 0; /* reserved */
	322	buf[i++] = 0; /* reserved */
	323	buf[i++] = 0; /* reserved */
	324
	325	/* ATA registers; must be a multiple of 4 */
	326	buf[i++] = qc->tf.device;
	327	buf[i++] = ADMA_REGS_DEVICE;
	328	if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
	329	buf[i++] = qc->tf.hob_nsect;
	330	buf[i++] = ADMA_REGS_SECTOR_COUNT;
	331	buf[i++] = qc->tf.hob_lbal;
	332	buf[i++] = ADMA_REGS_LBA_LOW;
	333	buf[i++] = qc->tf.hob_lbam;
	334	buf[i++] = ADMA_REGS_LBA_MID;
	335	buf[i++] = qc->tf.hob_lbah;
	336	buf[i++] = ADMA_REGS_LBA_HIGH;
	337	}
	338	buf[i++] = qc->tf.nsect;
	339	buf[i++] = ADMA_REGS_SECTOR_COUNT;
	340	buf[i++] = qc->tf.lbal;
	341	buf[i++] = ADMA_REGS_LBA_LOW;
	342	buf[i++] = qc->tf.lbam;
	343	buf[i++] = ADMA_REGS_LBA_MID;
	344	buf[i++] = qc->tf.lbah;
	345	buf[i++] = ADMA_REGS_LBA_HIGH;
	346	buf[i++] = 0;
	347	buf[i++] = ADMA_REGS_CONTROL;
	348	buf[i++] = rIGN;
	349	buf[i++] = 0;
	350	buf[i++] = qc->tf.command;
	351	buf[i++] = ADMA_REGS_COMMAND \| rEND;
	352
	353	buf[3] = (i >> 3) - 2; /* cLEN */
	354	(__le32 )(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
	355
	356	i = adma_fill_sg(qc);
	357	wmb(); /* flush PRDs and pkt to memory */
	358	#if 0
	359	/* dump out CPB + PRDs for debug */
	360	{
	361	int j, len = 0;
	362	static char obuf[2048];
	363	for (j = 0; j < i; ++j) {
	364	len += sprintf(obuf+len, "%02x ", buf[j]);
	365	if ((j & 7) == 7) {
	366	printk("%s\n", obuf);
	367	len = 0;
	368	}
	369	}
	370	if (len)
	371	printk("%s\n", obuf);
	372	}
	373	#endif
95364f36	374	return AC_ERR_OK;
edea3ab5 ML	375	}
	376
	377	static inline void adma_packet_start(struct ata_queued_cmd *qc)
	378	{
	379	struct ata_port *ap = qc->ap;
5d728824	380	void __iomem *chan = ADMA_PORT_REGS(ap);
edea3ab5 ML	381
	382	VPRINTK("ENTER, ap %p\n", ap);
	383
	384	/* fire up the ADMA engine */
68399bb5	385	writew(aPIOMD4 \| aGO, chan + ADMA_CONTROL);
edea3ab5 ML	386	}
edea3ab5 ML	387
9a3d9eb0	388	static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
edea3ab5 ML	389	{
	390	struct adma_port_priv *pp = qc->ap->private_data;
	391
	392	switch (qc->tf.protocol) {
	393	case ATA_PROT_DMA:
	394	pp->state = adma_state_pkt;
	395	adma_packet_start(qc);
	396	return 0;
	397
0dc36888	398	case ATAPI_PROT_DMA:
edea3ab5 ML	399	BUG();
	400	break;
	401
	402	default:
	403	break;
	404	}
	405
	406	pp->state = adma_state_mmio;
9363c382	407	return ata_sff_qc_issue(qc);
edea3ab5 ML	408	}
edea3ab5 ML	409
cca3974e	410	static inline unsigned int adma_intr_pkt(struct ata_host *host)
edea3ab5 ML	411	{
edea3ab5 ML	412	unsigned int handled = 0, port_no;
edea3ab5	413
cca3974e JG	414	for (port_no = 0; port_no < host->n_ports; ++port_no) {
cca3974e JG	415	struct ata_port *ap = host->ports[port_no];
edea3ab5 ML	416	struct adma_port_priv *pp;
edea3ab5 ML	417	struct ata_queued_cmd *qc;
5d728824	418	void __iomem *chan = ADMA_PORT_REGS(ap);
a7dac447	419	u8 status = readb(chan + ADMA_STATUS);
edea3ab5 ML	420
	421	if (status == 0)
	422	continue;
	423	handled = 1;
	424	adma_enter_reg_mode(ap);
edea3ab5 ML	425	pp = ap->private_data;
	426	if (!pp \|\| pp->state != adma_state_pkt)
	427	continue;
9af5c9c9	428	qc = ata_qc_from_tag(ap, ap->link.active_tag);
94ec1ef1	429	if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
640fdb50 JG	430	if (status & aPERR)
	431	qc->err_mask \|= AC_ERR_HOST_BUS;
	432	else if ((status & (aPSD \| aUIRQ)))
a22e2eb0	433	qc->err_mask \|= AC_ERR_OTHER;
640fdb50 JG	434
	435	if (pp->pkt[0] & cATERR)
	436	qc->err_mask \|= AC_ERR_DEV;
a21a84a3	437	else if (pp->pkt[0] != cDONE)
a22e2eb0	438	qc->err_mask \|= AC_ERR_OTHER;
a7dac447	439
640fdb50 JG	440	if (!qc->err_mask)
	441	ata_qc_complete(qc);
	442	else {
9af5c9c9	443	struct ata_eh_info *ehi = &ap->link.eh_info;
640fdb50 JG	444	ata_ehi_clear_desc(ehi);
	445	ata_ehi_push_desc(ehi,
	446	"ADMA-status 0x%02X", status);
	447	ata_ehi_push_desc(ehi,
	448	"pkt[0] 0x%02X", pp->pkt[0]);
	449
	450	if (qc->err_mask == AC_ERR_DEV)
	451	ata_port_abort(ap);
	452	else
	453	ata_port_freeze(ap);
	454	}
a21a84a3	455	}
edea3ab5 ML	456	}
	457	return handled;
	458	}
	459
cca3974e	460	static inline unsigned int adma_intr_mmio(struct ata_host *host)
edea3ab5 ML	461	{
	462	unsigned int handled = 0, port_no;
	463
cca3974e	464	for (port_no = 0; port_no < host->n_ports; ++port_no) {
3e4ec344 TH	465	struct ata_port *ap = host->ports[port_no];
	466	struct adma_port_priv *pp = ap->private_data;
	467	struct ata_queued_cmd *qc;
	468
	469	if (!pp \|\| pp->state != adma_state_mmio)
	470	continue;
	471	qc = ata_qc_from_tag(ap, ap->link.active_tag);
	472	if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
	473
	474	/* check main status, clearing INTRQ */
	475	u8 status = ata_sff_check_status(ap);
	476	if ((status & ATA_BUSY))
edea3ab5	477	continue;
3e4ec344 TH	478	DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
	479	ap->print_id, qc->tf.protocol, status);
	480
	481	/* complete taskfile transaction */
	482	pp->state = adma_state_idle;
	483	qc->err_mask \|= ac_err_mask(status);
	484	if (!qc->err_mask)
	485	ata_qc_complete(qc);
	486	else {
	487	struct ata_eh_info *ehi = &ap->link.eh_info;
	488	ata_ehi_clear_desc(ehi);
	489	ata_ehi_push_desc(ehi, "status 0x%02X", status);
	490
	491	if (qc->err_mask == AC_ERR_DEV)
	492	ata_port_abort(ap);
	493	else
	494	ata_port_freeze(ap);
edea3ab5	495	}
3e4ec344	496	handled = 1;
edea3ab5 ML	497	}
	498	}
	499	return handled;
	500	}
	501
7d12e780	502	static irqreturn_t adma_intr(int irq, void *dev_instance)
edea3ab5	503	{
cca3974e	504	struct ata_host *host = dev_instance;
edea3ab5 ML	505	unsigned int handled = 0;
	506
	507	VPRINTK("ENTER\n");
	508
cca3974e JG	509	spin_lock(&host->lock);
	510	handled = adma_intr_pkt(host) \| adma_intr_mmio(host);
	511	spin_unlock(&host->lock);
edea3ab5 ML	512
	513	VPRINTK("EXIT\n");
	514
	515	return IRQ_RETVAL(handled);
	516	}
	517
0d5ff566	518	static void adma_ata_setup_port(struct ata_ioports port, void __iomem base)
edea3ab5 ML	519	{
	520	port->cmd_addr =
	521	port->data_addr = base + 0x000;
	522	port->error_addr =
	523	port->feature_addr = base + 0x004;
	524	port->nsect_addr = base + 0x008;
	525	port->lbal_addr = base + 0x00c;
	526	port->lbam_addr = base + 0x010;
	527	port->lbah_addr = base + 0x014;
	528	port->device_addr = base + 0x018;
	529	port->status_addr =
	530	port->command_addr = base + 0x01c;
	531	port->altstatus_addr =
	532	port->ctl_addr = base + 0x038;
	533	}
	534
	535	static int adma_port_start(struct ata_port *ap)
	536	{
cca3974e	537	struct device *dev = ap->host->dev;
edea3ab5	538	struct adma_port_priv *pp;
edea3ab5	539
edea3ab5	540	adma_enter_reg_mode(ap);
24dc5f33	541	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
edea3ab5	542	if (!pp)
24dc5f33 TH	543	return -ENOMEM;
	544	pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
	545	GFP_KERNEL);
edea3ab5	546	if (!pp->pkt)
24dc5f33	547	return -ENOMEM;
edea3ab5 ML	548	/* paranoia? */
edea3ab5 ML	549	if ((pp->pkt_dma & 7) != 0) {
5796d1c4	550	printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
edea3ab5	551	(u32)pp->pkt_dma);
24dc5f33	552	return -ENOMEM;
edea3ab5	553	}
edea3ab5 ML	554	ap->private_data = pp;
	555	adma_reinit_engine(ap);
	556	return 0;
edea3ab5 ML	557	}
	558
	559	static void adma_port_stop(struct ata_port *ap)
	560	{
5d728824	561	adma_reset_engine(ap);
edea3ab5 ML	562	}
edea3ab5 ML	563
5d728824	564	static void adma_host_init(struct ata_host *host, unsigned int chip_id)
edea3ab5 ML	565	{
edea3ab5 ML	566	unsigned int port_no;
edea3ab5 ML	567
edea3ab5 ML	568	/* enable/lock aGO operation */
5d728824	569	writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
edea3ab5 ML	570
	571	/* reset the ADMA logic */
	572	for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
5d728824	573	adma_reset_engine(host->ports[port_no]);
edea3ab5 ML	574	}
edea3ab5 ML	575
edea3ab5	576	static int adma_ata_init_one(struct pci_dev *pdev,
0d5ff566	577	const struct pci_device_id *ent)
edea3ab5	578	{
edea3ab5	579	unsigned int board_idx = (unsigned int) ent->driver_data;
5d728824 TH	580	const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
	581	struct ata_host *host;
	582	void __iomem *mmio_base;
edea3ab5 ML	583	int rc, port_no;
edea3ab5 ML	584
06296a1e	585	ata_print_version_once(&pdev->dev, DRV_VERSION);
edea3ab5	586
5d728824 TH	587	/* alloc host */
	588	host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
	589	if (!host)
	590	return -ENOMEM;
	591
	592	/* acquire resources and fill host */
24dc5f33	593	rc = pcim_enable_device(pdev);
edea3ab5 ML	594	if (rc)
	595	return rc;
	596
24dc5f33 TH	597	if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
24dc5f33 TH	598	return -ENODEV;
edea3ab5	599
0d5ff566 TH	600	rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
	601	if (rc)
	602	return rc;
5d728824 TH	603	host->iomap = pcim_iomap_table(pdev);
5d728824 TH	604	mmio_base = host->iomap[ADMA_MMIO_BAR];
edea3ab5	605
94c58148 CH	606	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
	607	if (rc) {
	608	dev_err(&pdev->dev, "32-bit DMA enable failed\n");
24dc5f33	609	return rc;
94c58148	610	}
edea3ab5	611
cbcdd875 TH	612	for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
	613	struct ata_port *ap = host->ports[port_no];
	614	void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
	615	unsigned int offset = port_base - mmio_base;
	616
	617	adma_ata_setup_port(&ap->ioaddr, port_base);
	618
	619	ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
	620	ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
	621	}
edea3ab5 ML	622
edea3ab5 ML	623	/* initialize adapter */
5d728824	624	adma_host_init(host, board_idx);
edea3ab5	625
5d728824 TH	626	pci_set_master(pdev);
	627	return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
	628	&adma_ata_sht);
edea3ab5 ML	629	}
edea3ab5 ML	630
2fc75da0	631	module_pci_driver(adma_ata_pci_driver);
edea3ab5 ML	632
	633	MODULE_AUTHOR("Mark Lord");
	634	MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
	635	MODULE_LICENSE("GPL");
	636	MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
	637	MODULE_VERSION(DRV_VERSION);