[linux-2.6-block.git] / drivers / ata / pata_cs5520.c

/*
 *	IDE tuning and bus mastering support for the CS5510/CS5520
 *	chipsets
 *
 *	The CS5510/CS5520 are slightly unusual devices. Unlike the
 *	typical IDE controllers they do bus mastering with the drive in
 *	PIO mode and smarter silicon.
 *
 *	The practical upshot of this is that we must always tune the
 *	drive for the right PIO mode. We must also ignore all the blacklists
 *	and the drive bus mastering DMA information. Also to confuse matters
 *	further we can do DMA on PIO only drives.
 *
 *	DMA on the 5510 also requires we disable_hlt() during DMA on early
 *	revisions.
 *
 *	*** This driver is strictly experimental ***
 *
 *	(c) Copyright Red Hat Inc 2002
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * Documentation:
 *	Not publicly available.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_cs5520"
#define DRV_VERSION	"0.6.6"

struct pio_clocks
{
	int address;
	int assert;
	int recovery;
};

static const struct pio_clocks cs5520_pio_clocks[]={
	{3, 6, 11},
	{2, 5, 6},
	{1, 4, 3},
	{1, 3, 2},
	{1, 2, 1}
};

/**
 *	cs5520_set_timings	-	program PIO timings
 *	@ap: ATA port
 *	@adev: ATA device
 *
 *	Program the PIO mode timings for the controller according to the pio
 *	clocking table.
 */

static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int slave = adev->devno;

	pio -= XFER_PIO_0;

	/* Channel command timing */
	pci_write_config_byte(pdev, 0x62 + ap->port_no,
				(cs5520_pio_clocks[pio].recovery << 4) |
				(cs5520_pio_clocks[pio].assert));
	/* FIXME: should these use address ? */
	/* Read command timing */
	pci_write_config_byte(pdev, 0x64 +  4*ap->port_no + slave,
				(cs5520_pio_clocks[pio].recovery << 4) |
				(cs5520_pio_clocks[pio].assert));
	/* Write command timing */
	pci_write_config_byte(pdev, 0x66 +  4*ap->port_no + slave,
				(cs5520_pio_clocks[pio].recovery << 4) |
				(cs5520_pio_clocks[pio].assert));
}

/**
 *	cs5520_set_piomode	-	program PIO timings
 *	@ap: ATA port
 *	@adev: ATA device
 *
 *	Program the PIO mode timings for the controller according to the pio
 *	clocking table.
 */

static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	cs5520_set_timings(ap, adev, adev->pio_mode);
}

static struct scsi_host_template cs5520_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
	.sg_tablesize		= LIBATA_DUMB_MAX_PRD,
};

static struct ata_port_operations cs5520_port_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.qc_prep		= ata_bmdma_dumb_qc_prep,
	.cable_detect		= ata_cable_40wire,
	.set_piomode		= cs5520_set_piomode,
};

static int cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const unsigned int cmd_port[] = { 0x1F0, 0x170 };
	static const unsigned int ctl_port[] = { 0x3F6, 0x376 };
	struct ata_port_info pi = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.port_ops	= &cs5520_port_ops,
	};
	const struct ata_port_info *ppi[2];
	u8 pcicfg;
	void __iomem *iomap[5];
	struct ata_host *host;
	struct ata_ioports *ioaddr;
	int i, rc;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* IDE port enable bits */
	pci_read_config_byte(pdev, 0x60, &pcicfg);

	/* Check if the ATA ports are enabled */
	if ((pcicfg & 3) == 0)
		return -ENODEV;

	ppi[0] = ppi[1] = &ata_dummy_port_info;
	if (pcicfg & 1)
		ppi[0] = &pi;
	if (pcicfg & 2)
		ppi[1] = &pi;

	if ((pcicfg & 0x40) == 0) {
		dev_warn(&pdev->dev, "DMA mode disabled. Enabling.\n");
		pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
	}

	pi.mwdma_mask = id->driver_data;

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	if (!host)
		return -ENOMEM;

	/* Perform set up for DMA */
	if (pci_enable_device_io(pdev)) {
		printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
		return -ENODEV;
	}

	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
		printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
		return -ENODEV;
	}
	if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
		printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
		return -ENODEV;
	}

	/* Map IO ports and initialize host accordingly */
	iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8);
	iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1);
	iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8);
	iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1);
	iomap[4] = pcim_iomap(pdev, 2, 0);

	if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4])
		return -ENOMEM;

	ioaddr = &host->ports[0]->ioaddr;
	ioaddr->cmd_addr = iomap[0];
	ioaddr->ctl_addr = iomap[1];
	ioaddr->altstatus_addr = iomap[1];
	ioaddr->bmdma_addr = iomap[4];
	ata_sff_std_ports(ioaddr);

	ata_port_desc(host->ports[0],
		      "cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]);
	ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma");

	ioaddr = &host->ports[1]->ioaddr;
	ioaddr->cmd_addr = iomap[2];
	ioaddr->ctl_addr = iomap[3];
	ioaddr->altstatus_addr = iomap[3];
	ioaddr->bmdma_addr = iomap[4] + 8;
	ata_sff_std_ports(ioaddr);

	ata_port_desc(host->ports[1],
		      "cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]);
	ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma");

	/* activate the host */
	pci_set_master(pdev);
	rc = ata_host_start(host);
	if (rc)
		return rc;

	for (i = 0; i < 2; i++) {
		static const int irq[] = { 14, 15 };
		struct ata_port *ap = host->ports[i];

		if (ata_port_is_dummy(ap))
			continue;

		rc = devm_request_irq(&pdev->dev, irq[ap->port_no],
				      ata_bmdma_interrupt, 0, DRV_NAME, host);
		if (rc)
			return rc;

		ata_port_desc(ap, "irq %d", irq[i]);
	}

	return ata_host_register(host, &cs5520_sht);
}

#ifdef CONFIG_PM_SLEEP
/**
 *	cs5520_reinit_one	-	device resume
 *	@pdev: PCI device
 *
 *	Do any reconfiguration work needed by a resume from RAM. We need
 *	to restore DMA mode support on BIOSen which disabled it
 */

static int cs5520_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = pci_get_drvdata(pdev);
	u8 pcicfg;
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	pci_read_config_byte(pdev, 0x60, &pcicfg);
	if ((pcicfg & 0x40) == 0)
		pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);

	ata_host_resume(host);
	return 0;
}

/**
 *	cs5520_pci_device_suspend	-	device suspend
 *	@pdev: PCI device
 *
 *	We have to cut and waste bits from the standard method because
 *	the 5520 is a bit odd and not just a pure ATA device. As a result
 *	we must not disable it. The needed code is short and this avoids
 *	chip specific mess in the core code.
 */

static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
{
	struct ata_host *host = pci_get_drvdata(pdev);
	int rc = 0;

	rc = ata_host_suspend(host, mesg);
	if (rc)
		return rc;

	pci_save_state(pdev);
	return 0;
}
#endif /* CONFIG_PM_SLEEP */

/* For now keep DMA off. We can set it for all but A rev CS5510 once the
   core ATA code can handle it */

static const struct pci_device_id pata_cs5520[] = {
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },

	{ },
};

static struct pci_driver cs5520_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= pata_cs5520,
	.probe 		= cs5520_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.suspend	= cs5520_pci_device_suspend,
	.resume		= cs5520_reinit_one,
#endif
};

module_pci_driver(cs5520_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, pata_cs5520);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* IDE tuning and bus mastering support for the CS5510/CS5520
	3	* chipsets
	4	*
	5	* The CS5510/CS5520 are slightly unusual devices. Unlike the
	6	* typical IDE controllers they do bus mastering with the drive in
	7	* PIO mode and smarter silicon.
	8	*
	9	* The practical upshot of this is that we must always tune the
	10	* drive for the right PIO mode. We must also ignore all the blacklists
	11	* and the drive bus mastering DMA information. Also to confuse matters
	12	* further we can do DMA on PIO only drives.
	13	*
	14	* DMA on the 5510 also requires we disable_hlt() during DMA on early
	15	* revisions.
	16	*
	17	* * This driver is strictly experimental *
	18	*
	19	* (c) Copyright Red Hat Inc 2002
	20	*
	21	* This program is free software; you can redistribute it and/or modify it
	22	* under the terms of the GNU General Public License as published by the
	23	* Free Software Foundation; either version 2, or (at your option) any
	24	* later version.
	25	*
	26	* This program is distributed in the hope that it will be useful, but
	27	* WITHOUT ANY WARRANTY; without even the implied warranty of
	28	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	29	* General Public License for more details.
	30	*
	31	* Documentation:
25985edc	32	* Not publicly available.
669a5db4 JG	33	*/
	34	#include <linux/kernel.h>
	35	#include <linux/module.h>
	36	#include <linux/pci.h>
669a5db4 JG	37	#include <linux/blkdev.h>
	38	#include <linux/delay.h>
	39	#include <scsi/scsi_host.h>
	40	#include <linux/libata.h>
	41
	42	#define DRV_NAME "pata_cs5520"
2a3103ce	43	#define DRV_VERSION "0.6.6"
669a5db4 JG	44
	45	struct pio_clocks
	46	{
	47	int address;
	48	int assert;
	49	int recovery;
	50	};
	51
	52	static const struct pio_clocks cs5520_pio_clocks[]={
	53	{3, 6, 11},
	54	{2, 5, 6},
	55	{1, 4, 3},
	56	{1, 3, 2},
	57	{1, 2, 1}
	58	};
	59
	60	/**
	61	* cs5520_set_timings - program PIO timings
	62	* @ap: ATA port
	63	* @adev: ATA device
	64	*
	65	* Program the PIO mode timings for the controller according to the pio
	66	* clocking table.
	67	*/
	68
	69	static void cs5520_set_timings(struct ata_port ap, struct ata_device adev, int pio)
	70	{
	71	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	72	int slave = adev->devno;
	73
	74	pio -= XFER_PIO_0;
	75
	76	/* Channel command timing */
	77	pci_write_config_byte(pdev, 0x62 + ap->port_no,
	78	(cs5520_pio_clocks[pio].recovery << 4) \|
	79	(cs5520_pio_clocks[pio].assert));
	80	/* FIXME: should these use address ? */
	81	/* Read command timing */
	82	pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave,
	83	(cs5520_pio_clocks[pio].recovery << 4) \|
	84	(cs5520_pio_clocks[pio].assert));
	85	/* Write command timing */
	86	pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave,
	87	(cs5520_pio_clocks[pio].recovery << 4) \|
	88	(cs5520_pio_clocks[pio].assert));
	89	}
	90
669a5db4 JG	91	/**
	92	* cs5520_set_piomode - program PIO timings
	93	* @ap: ATA port
	94	* @adev: ATA device
	95	*
	96	* Program the PIO mode timings for the controller according to the pio
940a68de	97	* clocking table.
669a5db4 JG	98	*/
	99
	100	static void cs5520_set_piomode(struct ata_port ap, struct ata_device adev)
	101	{
	102	cs5520_set_timings(ap, adev, adev->pio_mode);
	103	}
	104
669a5db4	105	static struct scsi_host_template cs5520_sht = {
68d1d07b	106	ATA_BMDMA_SHT(DRV_NAME),
d26fc955	107	.sg_tablesize = LIBATA_DUMB_MAX_PRD,
669a5db4 JG	108	};
	109
	110	static struct ata_port_operations cs5520_port_ops = {
029cfd6b	111	.inherits = &ata_bmdma_port_ops,
f47451c4	112	.qc_prep = ata_bmdma_dumb_qc_prep,
029cfd6b	113	.cable_detect = ata_cable_40wire,
669a5db4	114	.set_piomode = cs5520_set_piomode,
669a5db4 JG	115	};
669a5db4 JG	116
0ec24914	117	static int cs5520_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4	118	{
cbcdd875 TH	119	static const unsigned int cmd_port[] = { 0x1F0, 0x170 };
cbcdd875 TH	120	static const unsigned int ctl_port[] = { 0x3F6, 0x376 };
5d728824 TH	121	struct ata_port_info pi = {
5d728824 TH	122	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98	123	.pio_mask = ATA_PIO4,
5d728824 TH	124	.port_ops = &cs5520_port_ops,
	125	};
	126	const struct ata_port_info *ppi[2];
669a5db4	127	u8 pcicfg;
4ca4e439	128	void __iomem *iomap[5];
5d728824 TH	129	struct ata_host *host;
	130	struct ata_ioports *ioaddr;
	131	int i, rc;
669a5db4	132
f08048e9 TH	133	rc = pcim_enable_device(pdev);
	134	if (rc)
	135	return rc;
	136
669a5db4	137	/* IDE port enable bits */
5d728824	138	pci_read_config_byte(pdev, 0x60, &pcicfg);
669a5db4 JG	139
	140	/* Check if the ATA ports are enabled */
	141	if ((pcicfg & 3) == 0)
	142	return -ENODEV;
	143
5d728824 TH	144	ppi[0] = ppi[1] = &ata_dummy_port_info;
	145	if (pcicfg & 1)
	146	ppi[0] = π
	147	if (pcicfg & 2)
	148	ppi[1] = π
	149
669a5db4	150	if ((pcicfg & 0x40) == 0) {
a44fec1f	151	dev_warn(&pdev->dev, "DMA mode disabled. Enabling.\n");
5d728824	152	pci_write_config_byte(pdev, 0x60, pcicfg \| 0x40);
669a5db4 JG	153	}
669a5db4 JG	154
5d728824 TH	155	pi.mwdma_mask = id->driver_data;
	156
	157	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	158	if (!host)
	159	return -ENOMEM;
	160
669a5db4	161	/* Perform set up for DMA */
09483916	162	if (pci_enable_device_io(pdev)) {
669a5db4 JG	163	printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
	164	return -ENODEV;
	165	}
5d728824	166
c54c719b	167	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
669a5db4 JG	168	printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
	169	return -ENODEV;
	170	}
c54c719b	171	if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
669a5db4 JG	172	printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
	173	return -ENODEV;
	174	}
	175
5d728824	176	/* Map IO ports and initialize host accordingly */
cbcdd875 TH	177	iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8);
	178	iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1);
	179	iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8);
	180	iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1);
5d728824	181	iomap[4] = pcim_iomap(pdev, 2, 0);
0d5ff566 TH	182
	183	if (!iomap[0] \|\| !iomap[1] \|\| !iomap[2] \|\| !iomap[3] \|\| !iomap[4])
	184	return -ENOMEM;
	185
5d728824 TH	186	ioaddr = &host->ports[0]->ioaddr;
	187	ioaddr->cmd_addr = iomap[0];
	188	ioaddr->ctl_addr = iomap[1];
	189	ioaddr->altstatus_addr = iomap[1];
	190	ioaddr->bmdma_addr = iomap[4];
9363c382	191	ata_sff_std_ports(ioaddr);
5d728824	192
cbcdd875 TH	193	ata_port_desc(host->ports[0],
	194	"cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]);
	195	ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma");
	196
5d728824 TH	197	ioaddr = &host->ports[1]->ioaddr;
	198	ioaddr->cmd_addr = iomap[2];
	199	ioaddr->ctl_addr = iomap[3];
	200	ioaddr->altstatus_addr = iomap[3];
	201	ioaddr->bmdma_addr = iomap[4] + 8;
9363c382	202	ata_sff_std_ports(ioaddr);
5d728824	203
cbcdd875 TH	204	ata_port_desc(host->ports[1],
	205	"cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]);
	206	ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma");
	207
5d728824 TH	208	/* activate the host */
	209	pci_set_master(pdev);
	210	rc = ata_host_start(host);
	211	if (rc)
	212	return rc;
	213
	214	for (i = 0; i < 2; i++) {
	215	static const int irq[] = { 14, 15 };
8c6b065b	216	struct ata_port *ap = host->ports[i];
5d728824 TH	217
	218	if (ata_port_is_dummy(ap))
	219	continue;
	220
	221	rc = devm_request_irq(&pdev->dev, irq[ap->port_no],
c3b28894	222	ata_bmdma_interrupt, 0, DRV_NAME, host);
5d728824 TH	223	if (rc)
5d728824 TH	224	return rc;
4031826b	225
cbcdd875	226	ata_port_desc(ap, "irq %d", irq[i]);
5d728824 TH	227	}
	228
	229	return ata_host_register(host, &cs5520_sht);
669a5db4 JG	230	}
669a5db4 JG	231
58eb8cd5	232	#ifdef CONFIG_PM_SLEEP
8501120f A	233	/**
	234	* cs5520_reinit_one - device resume
	235	* @pdev: PCI device
	236	*
	237	* Do any reconfiguration work needed by a resume from RAM. We need
	238	* to restore DMA mode support on BIOSen which disabled it
	239	*/
f20b16ff	240
8501120f A	241	static int cs5520_reinit_one(struct pci_dev *pdev)
8501120f A	242	{
0a86e1c8	243	struct ata_host *host = pci_get_drvdata(pdev);
8501120f	244	u8 pcicfg;
f08048e9 TH	245	int rc;
	246
	247	rc = ata_pci_device_do_resume(pdev);
	248	if (rc)
	249	return rc;
	250
8501120f A	251	pci_read_config_byte(pdev, 0x60, &pcicfg);
	252	if ((pcicfg & 0x40) == 0)
	253	pci_write_config_byte(pdev, 0x60, pcicfg \| 0x40);
f08048e9 TH	254
	255	ata_host_resume(host);
	256	return 0;
8501120f	257	}
aa6de494 A	258
	259	/**
	260	* cs5520_pci_device_suspend - device suspend
	261	* @pdev: PCI device
	262	*
	263	* We have to cut and waste bits from the standard method because
	264	* the 5520 is a bit odd and not just a pure ATA device. As a result
	265	* we must not disable it. The needed code is short and this avoids
	266	* chip specific mess in the core code.
	267	*/
	268
	269	static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
	270	{
0a86e1c8	271	struct ata_host *host = pci_get_drvdata(pdev);
aa6de494 A	272	int rc = 0;
	273
	274	rc = ata_host_suspend(host, mesg);
	275	if (rc)
	276	return rc;
	277
	278	pci_save_state(pdev);
	279	return 0;
	280	}
58eb8cd5	281	#endif /* CONFIG_PM_SLEEP */
a84471fe	282
669a5db4 JG	283	/* For now keep DMA off. We can set it for all but A rev CS5510 once the
	284	core ATA code can handle it */
	285
2d2744fc JG	286	static const struct pci_device_id pata_cs5520[] = {
	287	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
	288	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
	289
	290	{ },
669a5db4 JG	291	};
	292
	293	static struct pci_driver cs5520_pci_driver = {
	294	.name = DRV_NAME,
	295	.id_table = pata_cs5520,
	296	.probe = cs5520_init_one,
2855568b	297	.remove = ata_pci_remove_one,
58eb8cd5	298	#ifdef CONFIG_PM_SLEEP
aa6de494	299	.suspend = cs5520_pci_device_suspend,
8501120f	300	.resume = cs5520_reinit_one,
438ac6d5	301	#endif
669a5db4 JG	302	};
669a5db4 JG	303
2fc75da0	304	module_pci_driver(cs5520_pci_driver);
669a5db4 JG	305
	306	MODULE_AUTHOR("Alan Cox");
	307	MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
	308	MODULE_LICENSE("GPL");
	309	MODULE_DEVICE_TABLE(pci, pata_cs5520);
	310	MODULE_VERSION(DRV_VERSION);