[linux-2.6-block.git] / drivers / ata / ahci_qoriq.c

/*
 * Freescale QorIQ AHCI SATA platform driver
 *
 * Copyright 2015 Freescale, Inc.
 *   Tang Yuantian <Yuantian.Tang@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/ahci_platform.h>
#include <linux/device.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include "ahci.h"

#define DRV_NAME "ahci-qoriq"

/* port register definition */
#define PORT_PHY1	0xA8
#define PORT_PHY2	0xAC
#define PORT_PHY3	0xB0
#define PORT_PHY4	0xB4
#define PORT_PHY5	0xB8
#define PORT_AXICC	0xBC
#define PORT_TRANS	0xC8

/* port register default value */
#define AHCI_PORT_PHY_1_CFG	0xa003fffe
#define AHCI_PORT_PHY2_CFG	0x28184d1f
#define AHCI_PORT_PHY3_CFG	0x0e081509
#define AHCI_PORT_TRANS_CFG	0x08000029
#define AHCI_PORT_AXICC_CFG	0x3fffffff

/* for ls1021a */
#define LS1021A_PORT_PHY2	0x28183414
#define LS1021A_PORT_PHY3	0x0e080e06
#define LS1021A_PORT_PHY4	0x064a080b
#define LS1021A_PORT_PHY5	0x2aa86470
#define LS1021A_AXICC_ADDR	0xC0

#define SATA_ECC_DISABLE	0x00020000
#define ECC_DIS_ARMV8_CH2	0x80000000
#define ECC_DIS_LS1088A		0x40000000

enum ahci_qoriq_type {
	AHCI_LS1021A,
	AHCI_LS1043A,
	AHCI_LS2080A,
	AHCI_LS1046A,
	AHCI_LS1088A,
	AHCI_LS2088A,
};

struct ahci_qoriq_priv {
	struct ccsr_ahci *reg_base;
	enum ahci_qoriq_type type;
	void __iomem *ecc_addr;
	bool is_dmacoherent;
};

static const struct of_device_id ahci_qoriq_of_match[] = {
	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
	{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);

static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline)
{
	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u32 px_cmd, px_is, px_val;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	int rc;
	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);

	DPRINTK("ENTER\n");

	hpriv->stop_engine(ap);

	/*
	 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	 * A-009042: The device detection initialization sequence
	 * mistakenly resets some registers.
	 *
	 * Workaround for this is:
	 * The software should read and store PxCMD and PxIS values
	 * before issuing the device detection initialization sequence.
	 * After the sequence is complete, software should restore the
	 * PxCMD and PxIS with the stored values.
	 */
	if (ls1021a_workaround) {
		px_cmd = readl(port_mmio + PORT_CMD);
		px_is = readl(port_mmio + PORT_IRQ_STAT);
	}

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	rc = sata_link_hardreset(link, timing, deadline, &online,
				 ahci_check_ready);

	/* restore the PxCMD and PxIS on ls1021 */
	if (ls1021a_workaround) {
		px_val = readl(port_mmio + PORT_CMD);
		if (px_val != px_cmd)
			writel(px_cmd, port_mmio + PORT_CMD);

		px_val = readl(port_mmio + PORT_IRQ_STAT);
		if (px_val != px_is)
			writel(px_is, port_mmio + PORT_IRQ_STAT);
	}

	hpriv->start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);

	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	return rc;
}

static struct ata_port_operations ahci_qoriq_ops = {
	.inherits	= &ahci_ops,
	.hardreset	= ahci_qoriq_hardreset,
};

static const struct ata_port_info ahci_qoriq_port_info = {
	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_qoriq_ops,
};

static struct scsi_host_template ahci_qoriq_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
{
	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	void __iomem *reg_base = hpriv->mmio;

	switch (qpriv->type) {
	case AHCI_LS1021A:
		if (!qpriv->ecc_addr)
			return -EINVAL;
		writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
		writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG,
					reg_base + LS1021A_AXICC_ADDR);
		break;

	case AHCI_LS1043A:
		if (!qpriv->ecc_addr)
			return -EINVAL;
		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
				qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2080A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1046A:
		if (!qpriv->ecc_addr)
			return -EINVAL;
		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
				qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1088A:
		if (!qpriv->ecc_addr)
			return -EINVAL;
		writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
		       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2088A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;
	}

	return 0;
}

static int ahci_qoriq_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ahci_qoriq_priv *qoriq_priv;
	const struct of_device_id *of_id;
	struct resource *res;
	int rc;

	hpriv = ahci_platform_get_resources(pdev, 0);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	of_id = of_match_node(ahci_qoriq_of_match, np);
	if (!of_id)
		return -ENODEV;

	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	if (!qoriq_priv)
		return -ENOMEM;

	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
			"sata-ecc");
	if (res) {
		qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
		if (IS_ERR(qoriq_priv->ecc_addr))
			return PTR_ERR(qoriq_priv->ecc_addr);
	}
	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	hpriv->plat_data = qoriq_priv;
	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
				     &ahci_qoriq_sht);
	if (rc)
		goto disable_resources;

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_qoriq_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int rc;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_resume_host(dev);
	if (rc)
		goto disable_resources;

	/* We resumed so update PM runtime state */
	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
			 ahci_qoriq_resume);

static struct platform_driver ahci_qoriq_driver = {
	.probe = ahci_qoriq_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_qoriq_of_match,
		.pm = &ahci_qoriq_pm_ops,
	},
};
module_platform_driver(ahci_qoriq_driver);

MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
ecfb4598 TY	1	/*
	2	* Freescale QorIQ AHCI SATA platform driver
	3	*
	4	* Copyright 2015 Freescale, Inc.
	5	* Tang Yuantian <Yuantian.Tang@freescale.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2, or (at your option)
	10	* any later version.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/pm.h>
	16	#include <linux/ahci_platform.h>
	17	#include <linux/device.h>
	18	#include <linux/of_address.h>
	19	#include <linux/of.h>
	20	#include <linux/of_device.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/libata.h>
	23	#include "ahci.h"
	24
	25	#define DRV_NAME "ahci-qoriq"
	26
	27	/* port register definition */
	28	#define PORT_PHY1 0xA8
	29	#define PORT_PHY2 0xAC
	30	#define PORT_PHY3 0xB0
	31	#define PORT_PHY4 0xB4
	32	#define PORT_PHY5 0xB8
16af080e	33	#define PORT_AXICC 0xBC
ecfb4598 TY	34	#define PORT_TRANS 0xC8
	35
	36	/* port register default value */
	37	#define AHCI_PORT_PHY_1_CFG 0xa003fffe
ce179cbd YT	38	#define AHCI_PORT_PHY2_CFG 0x28184d1f
ce179cbd YT	39	#define AHCI_PORT_PHY3_CFG 0x0e081509
e3a6dadc	40	#define AHCI_PORT_TRANS_CFG 0x08000029
16af080e	41	#define AHCI_PORT_AXICC_CFG 0x3fffffff
dfcdc5fe TY	42
	43	/* for ls1021a */
	44	#define LS1021A_PORT_PHY2 0x28183414
	45	#define LS1021A_PORT_PHY3 0x0e080e06
	46	#define LS1021A_PORT_PHY4 0x064a080b
	47	#define LS1021A_PORT_PHY5 0x2aa86470
16af080e	48	#define LS1021A_AXICC_ADDR 0xC0
ecfb4598 TY	49
ecfb4598 TY	50	#define SATA_ECC_DISABLE 0x00020000
01f2901a	51	#define ECC_DIS_ARMV8_CH2 0x80000000
0cee73f7	52	#define ECC_DIS_LS1088A 0x40000000
ecfb4598 TY	53
	54	enum ahci_qoriq_type {
	55	AHCI_LS1021A,
	56	AHCI_LS1043A,
d19f9aaf	57	AHCI_LS2080A,
2facc6da	58	AHCI_LS1046A,
0cee73f7	59	AHCI_LS1088A,
ce8f4537	60	AHCI_LS2088A,
ecfb4598 TY	61	};
	62
	63	struct ahci_qoriq_priv {
	64	struct ccsr_ahci *reg_base;
	65	enum ahci_qoriq_type type;
	66	void __iomem *ecc_addr;
386dc3b8	67	bool is_dmacoherent;
ecfb4598 TY	68	};
	69
	70	static const struct of_device_id ahci_qoriq_of_match[] = {
	71	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	72	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
d19f9aaf	73	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
2facc6da	74	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
0cee73f7	75	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
ce8f4537	76	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
ecfb4598 TY	77	{},
	78	};
	79	MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
	80
	81	static int ahci_qoriq_hardreset(struct ata_link link, unsigned int class,
	82	unsigned long deadline)
	83	{
	84	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	85	void __iomem *port_mmio = ahci_port_base(link->ap);
	86	u32 px_cmd, px_is, px_val;
	87	struct ata_port *ap = link->ap;
	88	struct ahci_port_priv *pp = ap->private_data;
	89	struct ahci_host_priv *hpriv = ap->host->private_data;
	90	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	91	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	92	struct ata_taskfile tf;
	93	bool online;
	94	int rc;
eb351031	95	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
ecfb4598 TY	96
	97	DPRINTK("ENTER\n");
	98
fa89f53b	99	hpriv->stop_engine(ap);
ecfb4598 TY	100
	101	/*
	102	* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	103	* A-009042: The device detection initialization sequence
	104	* mistakenly resets some registers.
	105	*
	106	* Workaround for this is:
	107	* The software should read and store PxCMD and PxIS values
	108	* before issuing the device detection initialization sequence.
	109	* After the sequence is complete, software should restore the
	110	* PxCMD and PxIS with the stored values.
	111	*/
eb351031	112	if (ls1021a_workaround) {
ecfb4598 TY	113	px_cmd = readl(port_mmio + PORT_CMD);
	114	px_is = readl(port_mmio + PORT_IRQ_STAT);
	115	}
	116
	117	/* clear D2H reception area to properly wait for D2H FIS */
	118	ata_tf_init(link->device, &tf);
	119	tf.command = ATA_BUSY;
	120	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	121
	122	rc = sata_link_hardreset(link, timing, deadline, &online,
	123	ahci_check_ready);
	124
	125	/* restore the PxCMD and PxIS on ls1021 */
eb351031	126	if (ls1021a_workaround) {
ecfb4598 TY	127	px_val = readl(port_mmio + PORT_CMD);
	128	if (px_val != px_cmd)
	129	writel(px_cmd, port_mmio + PORT_CMD);
	130
	131	px_val = readl(port_mmio + PORT_IRQ_STAT);
	132	if (px_val != px_is)
	133	writel(px_is, port_mmio + PORT_IRQ_STAT);
	134	}
	135
	136	hpriv->start_engine(ap);
	137
	138	if (online)
	139	*class = ahci_dev_classify(ap);
	140
	141	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	142	return rc;
	143	}
	144
	145	static struct ata_port_operations ahci_qoriq_ops = {
	146	.inherits = &ahci_ops,
	147	.hardreset = ahci_qoriq_hardreset,
	148	};
	149
1ce788d2	150	static const struct ata_port_info ahci_qoriq_port_info = {
ecfb4598 TY	151	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_NCQ,
	152	.pio_mask = ATA_PIO4,
	153	.udma_mask = ATA_UDMA6,
	154	.port_ops = &ahci_qoriq_ops,
	155	};
	156
	157	static struct scsi_host_template ahci_qoriq_sht = {
	158	AHCI_SHT(DRV_NAME),
	159	};
	160
	161	static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
	162	{
	163	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	164	void __iomem *reg_base = hpriv->mmio;
	165
	166	switch (qpriv->type) {
	167	case AHCI_LS1021A:
01f2901a TY	168	if (!qpriv->ecc_addr)
01f2901a TY	169	return -EINVAL;
ecfb4598 TY	170	writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
ecfb4598 TY	171	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
dfcdc5fe TY	172	writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
	173	writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
	174	writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
	175	writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
ecfb4598	176	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	177	if (qpriv->is_dmacoherent)
	178	writel(AHCI_PORT_AXICC_CFG,
	179	reg_base + LS1021A_AXICC_ADDR);
ecfb4598 TY	180	break;
	181
	182	case AHCI_LS1043A:
01f2901a TY	183	if (!qpriv->ecc_addr)
01f2901a TY	184	return -EINVAL;
6022c5ca YT	185	writel(readl(qpriv->ecc_addr) \| ECC_DIS_ARMV8_CH2,
6022c5ca YT	186	qpriv->ecc_addr);
ef0cc7fe	187	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	188	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	189	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ef0cc7fe	190	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	191	if (qpriv->is_dmacoherent)
386dc3b8 TY	192	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ef0cc7fe TY	193	break;
ef0cc7fe TY	194
d19f9aaf	195	case AHCI_LS2080A:
ecfb4598	196	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	197	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	198	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
e3a6dadc	199	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	200	if (qpriv->is_dmacoherent)
386dc3b8 TY	201	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ecfb4598	202	break;
2facc6da TY	203
2facc6da TY	204	case AHCI_LS1046A:
01f2901a TY	205	if (!qpriv->ecc_addr)
01f2901a TY	206	return -EINVAL;
6022c5ca YT	207	writel(readl(qpriv->ecc_addr) \| ECC_DIS_ARMV8_CH2,
6022c5ca YT	208	qpriv->ecc_addr);
2facc6da	209	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	210	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	211	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
2facc6da	212	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	213	if (qpriv->is_dmacoherent)
386dc3b8 TY	214	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
2facc6da	215	break;
ce8f4537	216
0cee73f7 YT	217	case AHCI_LS1088A:
	218	if (!qpriv->ecc_addr)
	219	return -EINVAL;
	220	writel(readl(qpriv->ecc_addr) \| ECC_DIS_LS1088A,
	221	qpriv->ecc_addr);
	222	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	223	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	224	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0cee73f7 YT	225	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	226	if (qpriv->is_dmacoherent)
	227	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	228	break;
	229
ce8f4537 TY	230	case AHCI_LS2088A:
ce8f4537 TY	231	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ce179cbd YT	232	writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
ce179cbd YT	233	writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
ce8f4537 TY	234	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
	235	if (qpriv->is_dmacoherent)
	236	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
	237	break;
ecfb4598 TY	238	}
	239
	240	return 0;
	241	}
	242
	243	static int ahci_qoriq_probe(struct platform_device *pdev)
	244	{
	245	struct device_node *np = pdev->dev.of_node;
	246	struct device *dev = &pdev->dev;
	247	struct ahci_host_priv *hpriv;
	248	struct ahci_qoriq_priv *qoriq_priv;
	249	const struct of_device_id *of_id;
	250	struct resource *res;
	251	int rc;
	252
16af2d65	253	hpriv = ahci_platform_get_resources(pdev, 0);
ecfb4598 TY	254	if (IS_ERR(hpriv))
	255	return PTR_ERR(hpriv);
	256
	257	of_id = of_match_node(ahci_qoriq_of_match, np);
	258	if (!of_id)
	259	return -ENODEV;
	260
	261	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	262	if (!qoriq_priv)
	263	return -ENOMEM;
	264
	265	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
	266
2facc6da TY	267	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	268	"sata-ecc");
	269	if (res) {
ecfb4598 TY	270	qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
	271	if (IS_ERR(qoriq_priv->ecc_addr))
	272	return PTR_ERR(qoriq_priv->ecc_addr);
	273	}
386dc3b8	274	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
ecfb4598 TY	275
	276	rc = ahci_platform_enable_resources(hpriv);
	277	if (rc)
	278	return rc;
	279
	280	hpriv->plat_data = qoriq_priv;
	281	rc = ahci_qoriq_phy_init(hpriv);
	282	if (rc)
	283	goto disable_resources;
	284
	285	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
	286	&ahci_qoriq_sht);
	287	if (rc)
	288	goto disable_resources;
	289
	290	return 0;
	291
	292	disable_resources:
	293	ahci_platform_disable_resources(hpriv);
	294
	295	return rc;
	296	}
	297
	298	#ifdef CONFIG_PM_SLEEP
	299	static int ahci_qoriq_resume(struct device *dev)
	300	{
	301	struct ata_host *host = dev_get_drvdata(dev);
	302	struct ahci_host_priv *hpriv = host->private_data;
	303	int rc;
	304
	305	rc = ahci_platform_enable_resources(hpriv);
	306	if (rc)
	307	return rc;
	308
	309	rc = ahci_qoriq_phy_init(hpriv);
	310	if (rc)
	311	goto disable_resources;
	312
	313	rc = ahci_platform_resume_host(dev);
	314	if (rc)
	315	goto disable_resources;
	316
	317	/* We resumed so update PM runtime state */
	318	pm_runtime_disable(dev);
	319	pm_runtime_set_active(dev);
	320	pm_runtime_enable(dev);
	321
	322	return 0;
	323
	324	disable_resources:
	325	ahci_platform_disable_resources(hpriv);
	326
	327	return rc;
	328	}
	329	#endif
	330
	331	static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
	332	ahci_qoriq_resume);
	333
	334	static struct platform_driver ahci_qoriq_driver = {
	335	.probe = ahci_qoriq_probe,
	336	.remove = ata_platform_remove_one,
	337	.driver = {
	338	.name = DRV_NAME,
339	.of_match_table = ahci_qoriq_of_match,
340	.pm = &ahci_qoriq_pm_ops,
341	},
342	};
343	module_platform_driver(ahci_qoriq_driver);
344
345	MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
346	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
347	MODULE_LICENSE("GPL");