[linux-2.6-block.git] / drivers / amba / tegra-ahb.c

/*
 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 * Copyright (C) 2011 Google, Inc.
 *
 * Author:
 *	Jay Cheng <jacheng@nvidia.com>
 *	James Wylder <james.wylder@motorola.com>
 *	Benoit Goby <benoit@android.com>
 *	Colin Cross <ccross@android.com>
 *	Hiroshi DOYU <hdoyu@nvidia.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/of.h>

#include <soc/tegra/ahb.h>

#define DRV_NAME "tegra-ahb"

#define AHB_ARBITRATION_DISABLE		0x04
#define AHB_ARBITRATION_PRIORITY_CTRL	0x08
#define   AHB_PRIORITY_WEIGHT(x)	(((x) & 0x7) << 29)
#define   PRIORITY_SELECT_USB BIT(6)
#define   PRIORITY_SELECT_USB2 BIT(18)
#define   PRIORITY_SELECT_USB3 BIT(17)

#define AHB_GIZMO_AHB_MEM		0x10
#define   ENB_FAST_REARBITRATE BIT(2)
#define   DONT_SPLIT_AHB_WR     BIT(7)

#define AHB_GIZMO_APB_DMA		0x14
#define AHB_GIZMO_IDE			0x1c
#define AHB_GIZMO_USB			0x20
#define AHB_GIZMO_AHB_XBAR_BRIDGE	0x24
#define AHB_GIZMO_CPU_AHB_BRIDGE	0x28
#define AHB_GIZMO_COP_AHB_BRIDGE	0x2c
#define AHB_GIZMO_XBAR_APB_CTLR		0x30
#define AHB_GIZMO_VCP_AHB_BRIDGE	0x34
#define AHB_GIZMO_NAND			0x40
#define AHB_GIZMO_SDMMC4		0x48
#define AHB_GIZMO_XIO			0x4c
#define AHB_GIZMO_BSEV			0x64
#define AHB_GIZMO_BSEA			0x74
#define AHB_GIZMO_NOR			0x78
#define AHB_GIZMO_USB2			0x7c
#define AHB_GIZMO_USB3			0x80
#define   IMMEDIATE	BIT(18)

#define AHB_GIZMO_SDMMC1		0x84
#define AHB_GIZMO_SDMMC2		0x88
#define AHB_GIZMO_SDMMC3		0x8c
#define AHB_MEM_PREFETCH_CFG_X		0xdc
#define AHB_ARBITRATION_XBAR_CTRL	0xe0
#define AHB_MEM_PREFETCH_CFG3		0xe4
#define AHB_MEM_PREFETCH_CFG4		0xe8
#define AHB_MEM_PREFETCH_CFG1		0xf0
#define AHB_MEM_PREFETCH_CFG2		0xf4
#define   PREFETCH_ENB	BIT(31)
#define   MST_ID(x)	(((x) & 0x1f) << 26)
#define   AHBDMA_MST_ID	MST_ID(5)
#define   USB_MST_ID	MST_ID(6)
#define   USB2_MST_ID	MST_ID(18)
#define   USB3_MST_ID	MST_ID(17)
#define   ADDR_BNDRY(x)	(((x) & 0xf) << 21)
#define   INACTIVITY_TIMEOUT(x)	(((x) & 0xffff) << 0)

#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID	0xfc

#define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)

/*
 * INCORRECT_BASE_ADDR_LOW_BYTE: Legacy kernel DT files for Tegra SoCs
 * prior to Tegra124 generally use a physical base address ending in
 * 0x4 for the AHB IP block.  According to the TRM, the low byte
 * should be 0x0.  During device probing, this macro is used to detect
 * whether the passed-in physical address is incorrect, and if so, to
 * correct it.
 */
#define INCORRECT_BASE_ADDR_LOW_BYTE		0x4

static struct platform_driver tegra_ahb_driver;

static const u32 tegra_ahb_gizmo[] = {
	AHB_ARBITRATION_DISABLE,
	AHB_ARBITRATION_PRIORITY_CTRL,
	AHB_GIZMO_AHB_MEM,
	AHB_GIZMO_APB_DMA,
	AHB_GIZMO_IDE,
	AHB_GIZMO_USB,
	AHB_GIZMO_AHB_XBAR_BRIDGE,
	AHB_GIZMO_CPU_AHB_BRIDGE,
	AHB_GIZMO_COP_AHB_BRIDGE,
	AHB_GIZMO_XBAR_APB_CTLR,
	AHB_GIZMO_VCP_AHB_BRIDGE,
	AHB_GIZMO_NAND,
	AHB_GIZMO_SDMMC4,
	AHB_GIZMO_XIO,
	AHB_GIZMO_BSEV,
	AHB_GIZMO_BSEA,
	AHB_GIZMO_NOR,
	AHB_GIZMO_USB2,
	AHB_GIZMO_USB3,
	AHB_GIZMO_SDMMC1,
	AHB_GIZMO_SDMMC2,
	AHB_GIZMO_SDMMC3,
	AHB_MEM_PREFETCH_CFG_X,
	AHB_ARBITRATION_XBAR_CTRL,
	AHB_MEM_PREFETCH_CFG3,
	AHB_MEM_PREFETCH_CFG4,
	AHB_MEM_PREFETCH_CFG1,
	AHB_MEM_PREFETCH_CFG2,
	AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
};

struct tegra_ahb {
	void __iomem	*regs;
	struct device	*dev;
	u32		ctx[0];
};

static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
{
	return readl(ahb->regs + offset);
}

static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
{
	writel(value, ahb->regs + offset);
}

#ifdef CONFIG_TEGRA_IOMMU_SMMU
static int tegra_ahb_match_by_smmu(struct device *dev, void *data)
{
	struct tegra_ahb *ahb = dev_get_drvdata(dev);
	struct device_node *dn = data;

	return (ahb->dev->of_node == dn) ? 1 : 0;
}

int tegra_ahb_enable_smmu(struct device_node *dn)
{
	struct device *dev;
	u32 val;
	struct tegra_ahb *ahb;

	dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
				 tegra_ahb_match_by_smmu);
	if (!dev)
		return -EPROBE_DEFER;
	ahb = dev_get_drvdata(dev);
	val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
	val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
	gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
	return 0;
}
EXPORT_SYMBOL(tegra_ahb_enable_smmu);
#endif

#ifdef CONFIG_PM
static int tegra_ahb_suspend(struct device *dev)
{
	int i;
	struct tegra_ahb *ahb = dev_get_drvdata(dev);

	for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
		ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
	return 0;
}

static int tegra_ahb_resume(struct device *dev)
{
	int i;
	struct tegra_ahb *ahb = dev_get_drvdata(dev);

	for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
		gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
	return 0;
}
#endif

static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
			    tegra_ahb_suspend,
			    tegra_ahb_resume, NULL);

static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
{
	u32 val;

	val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
	val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
	gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);

	val = gizmo_readl(ahb, AHB_GIZMO_USB);
	val |= IMMEDIATE;
	gizmo_writel(ahb, val, AHB_GIZMO_USB);

	val = gizmo_readl(ahb, AHB_GIZMO_USB2);
	val |= IMMEDIATE;
	gizmo_writel(ahb, val, AHB_GIZMO_USB2);

	val = gizmo_readl(ahb, AHB_GIZMO_USB3);
	val |= IMMEDIATE;
	gizmo_writel(ahb, val, AHB_GIZMO_USB3);

	val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
	val |= PRIORITY_SELECT_USB |
		PRIORITY_SELECT_USB2 |
		PRIORITY_SELECT_USB3 |
		AHB_PRIORITY_WEIGHT(7);
	gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);

	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
	val &= ~MST_ID(~0);
	val |= PREFETCH_ENB |
		AHBDMA_MST_ID |
		ADDR_BNDRY(0xc) |
		INACTIVITY_TIMEOUT(0x1000);
	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);

	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
	val &= ~MST_ID(~0);
	val |= PREFETCH_ENB |
		USB_MST_ID |
		ADDR_BNDRY(0xc) |
		INACTIVITY_TIMEOUT(0x1000);
	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);

	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
	val &= ~MST_ID(~0);
	val |= PREFETCH_ENB |
		USB3_MST_ID |
		ADDR_BNDRY(0xc) |
		INACTIVITY_TIMEOUT(0x1000);
	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);

	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
	val &= ~MST_ID(~0);
	val |= PREFETCH_ENB |
		USB2_MST_ID |
		ADDR_BNDRY(0xc) |
		INACTIVITY_TIMEOUT(0x1000);
	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
}

static int tegra_ahb_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct tegra_ahb *ahb;
	size_t bytes;

	bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
	ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
	if (!ahb)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	/* Correct the IP block base address if necessary */
	if (res &&
	    (res->start & INCORRECT_BASE_ADDR_LOW_BYTE) ==
	    INCORRECT_BASE_ADDR_LOW_BYTE) {
		dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n");
		res->start -= INCORRECT_BASE_ADDR_LOW_BYTE;
	}

	ahb->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ahb->regs))
		return PTR_ERR(ahb->regs);

	ahb->dev = &pdev->dev;
	platform_set_drvdata(pdev, ahb);
	tegra_ahb_gizmo_init(ahb);
	return 0;
}

static const struct of_device_id tegra_ahb_of_match[] = {
	{ .compatible = "nvidia,tegra30-ahb", },
	{ .compatible = "nvidia,tegra20-ahb", },
	{},
};

static struct platform_driver tegra_ahb_driver = {
	.probe = tegra_ahb_probe,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = tegra_ahb_of_match,
		.pm = &tegra_ahb_pm,
	},
};
module_platform_driver(tegra_ahb_driver);

MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
MODULE_DESCRIPTION("Tegra AHB driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
87d0bab2 HD	1	/*
	2	* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
	3	* Copyright (C) 2011 Google, Inc.
	4	*
	5	* Author:
	6	* Jay Cheng <jacheng@nvidia.com>
	7	* James Wylder <james.wylder@motorola.com>
	8	* Benoit Goby <benoit@android.com>
	9	* Colin Cross <ccross@android.com>
	10	* Hiroshi DOYU <hdoyu@nvidia.com>
	11	*
	12	* This software is licensed under the terms of the GNU General Public
	13	* License version 2, as published by the Free Software Foundation, and
	14	* may be copied, distributed, and modified under those terms.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	*/
	22
903b33e0	23	#include <linux/err.h>
87d0bab2 HD	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/io.h>
049e4b3f	28	#include <linux/of.h>
306a7f91 TR	29
306a7f91 TR	30	#include <soc/tegra/ahb.h>
87d0bab2 HD	31
	32	#define DRV_NAME "tegra-ahb"
	33
049e4b3f PW	34	#define AHB_ARBITRATION_DISABLE 0x04
049e4b3f PW	35	#define AHB_ARBITRATION_PRIORITY_CTRL 0x08
87d0bab2 HD	36	#define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
	37	#define PRIORITY_SELECT_USB BIT(6)
	38	#define PRIORITY_SELECT_USB2 BIT(18)
	39	#define PRIORITY_SELECT_USB3 BIT(17)
	40
049e4b3f	41	#define AHB_GIZMO_AHB_MEM 0x10
87d0bab2 HD	42	#define ENB_FAST_REARBITRATE BIT(2)
	43	#define DONT_SPLIT_AHB_WR BIT(7)
	44
049e4b3f PW	45	#define AHB_GIZMO_APB_DMA 0x14
	46	#define AHB_GIZMO_IDE 0x1c
	47	#define AHB_GIZMO_USB 0x20
	48	#define AHB_GIZMO_AHB_XBAR_BRIDGE 0x24
	49	#define AHB_GIZMO_CPU_AHB_BRIDGE 0x28
	50	#define AHB_GIZMO_COP_AHB_BRIDGE 0x2c
	51	#define AHB_GIZMO_XBAR_APB_CTLR 0x30
	52	#define AHB_GIZMO_VCP_AHB_BRIDGE 0x34
	53	#define AHB_GIZMO_NAND 0x40
	54	#define AHB_GIZMO_SDMMC4 0x48
	55	#define AHB_GIZMO_XIO 0x4c
	56	#define AHB_GIZMO_BSEV 0x64
	57	#define AHB_GIZMO_BSEA 0x74
	58	#define AHB_GIZMO_NOR 0x78
	59	#define AHB_GIZMO_USB2 0x7c
	60	#define AHB_GIZMO_USB3 0x80
87d0bab2 HD	61	#define IMMEDIATE BIT(18)
87d0bab2 HD	62
049e4b3f PW	63	#define AHB_GIZMO_SDMMC1 0x84
	64	#define AHB_GIZMO_SDMMC2 0x88
	65	#define AHB_GIZMO_SDMMC3 0x8c
	66	#define AHB_MEM_PREFETCH_CFG_X 0xdc
	67	#define AHB_ARBITRATION_XBAR_CTRL 0xe0
	68	#define AHB_MEM_PREFETCH_CFG3 0xe4
	69	#define AHB_MEM_PREFETCH_CFG4 0xe8
	70	#define AHB_MEM_PREFETCH_CFG1 0xf0
	71	#define AHB_MEM_PREFETCH_CFG2 0xf4
87d0bab2 HD	72	#define PREFETCH_ENB BIT(31)
	73	#define MST_ID(x) (((x) & 0x1f) << 26)
	74	#define AHBDMA_MST_ID MST_ID(5)
	75	#define USB_MST_ID MST_ID(6)
	76	#define USB2_MST_ID MST_ID(18)
	77	#define USB3_MST_ID MST_ID(17)
	78	#define ADDR_BNDRY(x) (((x) & 0xf) << 21)
	79	#define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
	80
049e4b3f	81	#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xfc
87d0bab2	82
89c788ba HD	83	#define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
89c788ba HD	84
ce7a10b0 PW	85	/*
	86	* INCORRECT_BASE_ADDR_LOW_BYTE: Legacy kernel DT files for Tegra SoCs
	87	* prior to Tegra124 generally use a physical base address ending in
	88	* 0x4 for the AHB IP block. According to the TRM, the low byte
	89	* should be 0x0. During device probing, this macro is used to detect
	90	* whether the passed-in physical address is incorrect, and if so, to
	91	* correct it.
	92	*/
	93	#define INCORRECT_BASE_ADDR_LOW_BYTE 0x4
	94
89c788ba HD	95	static struct platform_driver tegra_ahb_driver;
89c788ba HD	96
87d0bab2 HD	97	static const u32 tegra_ahb_gizmo[] = {
	98	AHB_ARBITRATION_DISABLE,
	99	AHB_ARBITRATION_PRIORITY_CTRL,
	100	AHB_GIZMO_AHB_MEM,
	101	AHB_GIZMO_APB_DMA,
	102	AHB_GIZMO_IDE,
	103	AHB_GIZMO_USB,
	104	AHB_GIZMO_AHB_XBAR_BRIDGE,
	105	AHB_GIZMO_CPU_AHB_BRIDGE,
	106	AHB_GIZMO_COP_AHB_BRIDGE,
	107	AHB_GIZMO_XBAR_APB_CTLR,
	108	AHB_GIZMO_VCP_AHB_BRIDGE,
	109	AHB_GIZMO_NAND,
	110	AHB_GIZMO_SDMMC4,
	111	AHB_GIZMO_XIO,
	112	AHB_GIZMO_BSEV,
	113	AHB_GIZMO_BSEA,
	114	AHB_GIZMO_NOR,
	115	AHB_GIZMO_USB2,
	116	AHB_GIZMO_USB3,
	117	AHB_GIZMO_SDMMC1,
	118	AHB_GIZMO_SDMMC2,
	119	AHB_GIZMO_SDMMC3,
	120	AHB_MEM_PREFETCH_CFG_X,
	121	AHB_ARBITRATION_XBAR_CTRL,
	122	AHB_MEM_PREFETCH_CFG3,
	123	AHB_MEM_PREFETCH_CFG4,
	124	AHB_MEM_PREFETCH_CFG1,
	125	AHB_MEM_PREFETCH_CFG2,
	126	AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
	127	};
	128
	129	struct tegra_ahb {
	130	void __iomem *regs;
	131	struct device *dev;
	132	u32 ctx[0];
	133	};
	134
	135	static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
	136	{
ce7a10b0	137	return readl(ahb->regs + offset);
87d0bab2 HD	138	}
	139
	140	static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
	141	{
ce7a10b0	142	writel(value, ahb->regs + offset);
87d0bab2 HD	143	}
87d0bab2 HD	144
b44bf43b	145	#ifdef CONFIG_TEGRA_IOMMU_SMMU
89c788ba HD	146	static int tegra_ahb_match_by_smmu(struct device dev, void data)
	147	{
	148	struct tegra_ahb *ahb = dev_get_drvdata(dev);
	149	struct device_node *dn = data;
	150
	151	return (ahb->dev->of_node == dn) ? 1 : 0;
	152	}
	153
	154	int tegra_ahb_enable_smmu(struct device_node *dn)
	155	{
	156	struct device *dev;
	157	u32 val;
	158	struct tegra_ahb *ahb;
	159
	160	dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
	161	tegra_ahb_match_by_smmu);
	162	if (!dev)
	163	return -EPROBE_DEFER;
	164	ahb = dev_get_drvdata(dev);
	165	val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
	166	val \|= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
	167	gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
	168	return 0;
	169	}
	170	EXPORT_SYMBOL(tegra_ahb_enable_smmu);
	171	#endif
	172
2c36af0e	173	#ifdef CONFIG_PM
87d0bab2 HD	174	static int tegra_ahb_suspend(struct device *dev)
	175	{
	176	int i;
	177	struct tegra_ahb *ahb = dev_get_drvdata(dev);
	178
	179	for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
	180	ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
	181	return 0;
	182	}
	183
	184	static int tegra_ahb_resume(struct device *dev)
	185	{
	186	int i;
	187	struct tegra_ahb *ahb = dev_get_drvdata(dev);
	188
	189	for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
	190	gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
	191	return 0;
	192	}
f1101749	193	#endif
87d0bab2 HD	194
	195	static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
	196	tegra_ahb_suspend,
	197	tegra_ahb_resume, NULL);
	198
	199	static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
	200	{
	201	u32 val;
	202
	203	val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
	204	val \|= ENB_FAST_REARBITRATE \| IMMEDIATE \| DONT_SPLIT_AHB_WR;
	205	gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
	206
	207	val = gizmo_readl(ahb, AHB_GIZMO_USB);
	208	val \|= IMMEDIATE;
	209	gizmo_writel(ahb, val, AHB_GIZMO_USB);
	210
	211	val = gizmo_readl(ahb, AHB_GIZMO_USB2);
	212	val \|= IMMEDIATE;
	213	gizmo_writel(ahb, val, AHB_GIZMO_USB2);
	214
	215	val = gizmo_readl(ahb, AHB_GIZMO_USB3);
	216	val \|= IMMEDIATE;
	217	gizmo_writel(ahb, val, AHB_GIZMO_USB3);
	218
	219	val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
	220	val \|= PRIORITY_SELECT_USB \|
	221	PRIORITY_SELECT_USB2 \|
	222	PRIORITY_SELECT_USB3 \|
	223	AHB_PRIORITY_WEIGHT(7);
	224	gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
	225
	226	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
	227	val &= ~MST_ID(~0);
	228	val \|= PREFETCH_ENB \|
	229	AHBDMA_MST_ID \|
	230	ADDR_BNDRY(0xc) \|
	231	INACTIVITY_TIMEOUT(0x1000);
	232	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
	233
	234	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
	235	val &= ~MST_ID(~0);
	236	val \|= PREFETCH_ENB \|
	237	USB_MST_ID \|
	238	ADDR_BNDRY(0xc) \|
	239	INACTIVITY_TIMEOUT(0x1000);
	240	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
	241
	242	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
	243	val &= ~MST_ID(~0);
	244	val \|= PREFETCH_ENB \|
	245	USB3_MST_ID \|
	246	ADDR_BNDRY(0xc) \|
	247	INACTIVITY_TIMEOUT(0x1000);
	248	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
	249
	250	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
	251	val &= ~MST_ID(~0);
	252	val \|= PREFETCH_ENB \|
	253	USB2_MST_ID \|
	254	ADDR_BNDRY(0xc) \|
	255	INACTIVITY_TIMEOUT(0x1000);
	256	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
	257	}
258
c571b211	259	static int tegra_ahb_probe(struct platform_device *pdev)
87d0bab2 HD	260	{
	261	struct resource *res;
	262	struct tegra_ahb *ahb;
	263	size_t bytes;
	264
	265	bytes = sizeof(ahb) + sizeof(u32) ARRAY_SIZE(tegra_ahb_gizmo);
	266	ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
	267	if (!ahb)
	268	return -ENOMEM;
	269
	270	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ce7a10b0 PW	271
	272	/* Correct the IP block base address if necessary */
	273	if (res &&
	274	(res->start & INCORRECT_BASE_ADDR_LOW_BYTE) ==
	275	INCORRECT_BASE_ADDR_LOW_BYTE) {
	276	dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n");
	277	res->start -= INCORRECT_BASE_ADDR_LOW_BYTE;
	278	}
	279
903b33e0 TR	280	ahb->regs = devm_ioremap_resource(&pdev->dev, res);
	281	if (IS_ERR(ahb->regs))
	282	return PTR_ERR(ahb->regs);
87d0bab2 HD	283
	284	ahb->dev = &pdev->dev;
	285	platform_set_drvdata(pdev, ahb);
	286	tegra_ahb_gizmo_init(ahb);
	287	return 0;
	288	}
	289
c571b211	290	static const struct of_device_id tegra_ahb_of_match[] = {
87d0bab2 HD	291	{ .compatible = "nvidia,tegra30-ahb", },
	292	{ .compatible = "nvidia,tegra20-ahb", },
	293	{},
	294	};
	295
	296	static struct platform_driver tegra_ahb_driver = {
	297	.probe = tegra_ahb_probe,
87d0bab2 HD	298	.driver = {
87d0bab2 HD	299	.name = DRV_NAME,
87d0bab2 HD	300	.of_match_table = tegra_ahb_of_match,
	301	.pm = &tegra_ahb_pm,
	302	},
	303	};
	304	module_platform_driver(tegra_ahb_driver);
	305
	306	MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
	307	MODULE_DESCRIPTION("Tegra AHB driver");
	308	MODULE_LICENSE("GPL v2");
	309	MODULE_ALIAS("platform:" DRV_NAME);