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5a0015d6 CZ |
1 | /* |
2 | * arch/xtensa/kernel/time.c | |
3 | * | |
4 | * Timer and clock support. | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | * | |
10 | * Copyright (C) 2005 Tensilica Inc. | |
11 | * | |
12 | * Chris Zankel <chris@zankel.net> | |
13 | */ | |
14 | ||
5a0015d6 | 15 | #include <linux/errno.h> |
d43c36dc | 16 | #include <linux/sched.h> |
5a0015d6 | 17 | #include <linux/time.h> |
fcc8f0f8 | 18 | #include <linux/clocksource.h> |
925f5532 | 19 | #include <linux/clockchips.h> |
5a0015d6 CZ |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/profile.h> | |
25 | #include <linux/delay.h> | |
2206d5dd | 26 | #include <linux/irqdomain.h> |
e3f43291 | 27 | #include <linux/sched_clock.h> |
5a0015d6 CZ |
28 | |
29 | #include <asm/timex.h> | |
30 | #include <asm/platform.h> | |
31 | ||
e504c4b6 | 32 | unsigned long ccount_freq; /* ccount Hz */ |
5a0015d6 | 33 | |
09378d7c | 34 | static cycle_t ccount_read(struct clocksource *cs) |
fcc8f0f8 JW |
35 | { |
36 | return (cycle_t)get_ccount(); | |
37 | } | |
38 | ||
e3f43291 BS |
39 | static u32 notrace ccount_sched_clock_read(void) |
40 | { | |
41 | return get_ccount(); | |
42 | } | |
43 | ||
fcc8f0f8 JW |
44 | static struct clocksource ccount_clocksource = { |
45 | .name = "ccount", | |
46 | .rating = 200, | |
47 | .read = ccount_read, | |
48 | .mask = CLOCKSOURCE_MASK(32), | |
fcc8f0f8 JW |
49 | }; |
50 | ||
925f5532 BS |
51 | static int ccount_timer_set_next_event(unsigned long delta, |
52 | struct clock_event_device *dev); | |
53 | static void ccount_timer_set_mode(enum clock_event_mode mode, | |
54 | struct clock_event_device *evt); | |
55 | static struct ccount_timer_t { | |
56 | struct clock_event_device evt; | |
57 | int irq_enabled; | |
58 | } ccount_timer = { | |
59 | .evt = { | |
60 | .name = "ccount_clockevent", | |
61 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
62 | .rating = 300, | |
63 | .set_next_event = ccount_timer_set_next_event, | |
64 | .set_mode = ccount_timer_set_mode, | |
65 | }, | |
66 | }; | |
67 | ||
68 | static int ccount_timer_set_next_event(unsigned long delta, | |
69 | struct clock_event_device *dev) | |
70 | { | |
71 | unsigned long flags, next; | |
72 | int ret = 0; | |
73 | ||
74 | local_irq_save(flags); | |
75 | next = get_ccount() + delta; | |
76 | set_linux_timer(next); | |
77 | if (next - get_ccount() > delta) | |
78 | ret = -ETIME; | |
79 | local_irq_restore(flags); | |
80 | ||
81 | return ret; | |
82 | } | |
83 | ||
84 | static void ccount_timer_set_mode(enum clock_event_mode mode, | |
85 | struct clock_event_device *evt) | |
86 | { | |
87 | struct ccount_timer_t *timer = | |
88 | container_of(evt, struct ccount_timer_t, evt); | |
89 | ||
90 | /* | |
91 | * There is no way to disable the timer interrupt at the device level, | |
92 | * only at the intenable register itself. Since enable_irq/disable_irq | |
93 | * calls are nested, we need to make sure that these calls are | |
94 | * balanced. | |
95 | */ | |
96 | switch (mode) { | |
97 | case CLOCK_EVT_MODE_SHUTDOWN: | |
98 | case CLOCK_EVT_MODE_UNUSED: | |
99 | if (timer->irq_enabled) { | |
100 | disable_irq(evt->irq); | |
101 | timer->irq_enabled = 0; | |
102 | } | |
103 | break; | |
104 | case CLOCK_EVT_MODE_RESUME: | |
105 | case CLOCK_EVT_MODE_ONESHOT: | |
106 | if (!timer->irq_enabled) { | |
107 | enable_irq(evt->irq); | |
108 | timer->irq_enabled = 1; | |
109 | } | |
110 | default: | |
111 | break; | |
112 | } | |
113 | } | |
114 | ||
fd43fe19 | 115 | static irqreturn_t timer_interrupt(int irq, void *dev_id); |
5a0015d6 CZ |
116 | static struct irqaction timer_irqaction = { |
117 | .handler = timer_interrupt, | |
925f5532 | 118 | .flags = IRQF_TIMER, |
5a0015d6 | 119 | .name = "timer", |
925f5532 | 120 | .dev_id = &ccount_timer, |
5a0015d6 CZ |
121 | }; |
122 | ||
123 | void __init time_init(void) | |
124 | { | |
288a60cf | 125 | #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT |
5a0015d6 CZ |
126 | printk("Calibrating CPU frequency "); |
127 | platform_calibrate_ccount(); | |
e504c4b6 BS |
128 | printk("%d.%02d MHz\n", (int)ccount_freq/1000000, |
129 | (int)(ccount_freq/10000)%100); | |
fedc21dc BS |
130 | #else |
131 | ccount_freq = CONFIG_XTENSA_CPU_CLOCK*1000000UL; | |
5a0015d6 | 132 | #endif |
8d5e1d8e | 133 | clocksource_register_hz(&ccount_clocksource, ccount_freq); |
5a0015d6 | 134 | |
925f5532 BS |
135 | ccount_timer.evt.cpumask = cpumask_of(0); |
136 | ccount_timer.evt.irq = irq_create_mapping(NULL, LINUX_TIMER_INT); | |
137 | if (WARN(!ccount_timer.evt.irq, "error: can't map timer irq")) | |
138 | return; | |
139 | clockevents_config_and_register(&ccount_timer.evt, ccount_freq, 0xf, | |
140 | 0xffffffff); | |
141 | setup_irq(ccount_timer.evt.irq, &timer_irqaction); | |
142 | ccount_timer.irq_enabled = 1; | |
e3f43291 BS |
143 | |
144 | setup_sched_clock(ccount_sched_clock_read, 32, ccount_freq); | |
5a0015d6 CZ |
145 | } |
146 | ||
5a0015d6 CZ |
147 | /* |
148 | * The timer interrupt is called HZ times per second. | |
149 | */ | |
150 | ||
fd43fe19 | 151 | irqreturn_t timer_interrupt (int irq, void *dev_id) |
5a0015d6 | 152 | { |
925f5532 BS |
153 | struct ccount_timer_t *timer = dev_id; |
154 | struct clock_event_device *evt = &timer->evt; | |
5a0015d6 | 155 | |
925f5532 | 156 | evt->event_handler(evt); |
5a0015d6 | 157 | |
2b8aea74 | 158 | /* Allow platform to do something useful (Wdog). */ |
2b8aea74 | 159 | platform_heartbeat(); |
5a0015d6 | 160 | |
5a0015d6 CZ |
161 | return IRQ_HANDLED; |
162 | } | |
163 | ||
164 | #ifndef CONFIG_GENERIC_CALIBRATE_DELAY | |
6cb4c159 | 165 | void calibrate_delay(void) |
5a0015d6 | 166 | { |
8d5e1d8e | 167 | loops_per_jiffy = ccount_freq / HZ; |
5a0015d6 CZ |
168 | printk("Calibrating delay loop (skipped)... " |
169 | "%lu.%02lu BogoMIPS preset\n", | |
170 | loops_per_jiffy/(1000000/HZ), | |
171 | (loops_per_jiffy/(10000/HZ)) % 100); | |
172 | } | |
173 | #endif |