Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support for AMD Hammer. | |
3 | * | |
4 | * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. | |
5 | * This allows to use PCI devices that only support 32bit addresses on systems | |
6 | * with more than 4GB. | |
7 | * | |
8 | * See Documentation/DMA-mapping.txt for the interface specification. | |
9 | * | |
10 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
11 | */ | |
12 | ||
13 | #include <linux/config.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/ctype.h> | |
16 | #include <linux/agp_backend.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/topology.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/bitops.h> | |
26 | #include <asm/atomic.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/mtrr.h> | |
29 | #include <asm/pgtable.h> | |
30 | #include <asm/proto.h> | |
31 | #include <asm/cacheflush.h> | |
32 | #include <asm/kdebug.h> | |
17a941d8 MBY |
33 | #include <asm/swiotlb.h> |
34 | #include <asm/dma.h> | |
1da177e4 LT |
35 | |
36 | unsigned long iommu_bus_base; /* GART remapping area (physical) */ | |
37 | static unsigned long iommu_size; /* size of remapping area bytes */ | |
38 | static unsigned long iommu_pages; /* .. and in pages */ | |
39 | ||
40 | u32 *iommu_gatt_base; /* Remapping table */ | |
41 | ||
1da177e4 LT |
42 | /* If this is disabled the IOMMU will use an optimized flushing strategy |
43 | of only flushing when an mapping is reused. With it true the GART is flushed | |
44 | for every mapping. Problem is that doing the lazy flush seems to trigger | |
45 | bugs with some popular PCI cards, in particular 3ware (but has been also | |
46 | also seen with Qlogic at least). */ | |
47 | int iommu_fullflush = 1; | |
48 | ||
1da177e4 LT |
49 | #define MAX_NB 8 |
50 | ||
51 | /* Allocation bitmap for the remapping area */ | |
52 | static DEFINE_SPINLOCK(iommu_bitmap_lock); | |
53 | static unsigned long *iommu_gart_bitmap; /* guarded by iommu_bitmap_lock */ | |
54 | ||
55 | static u32 gart_unmapped_entry; | |
56 | ||
57 | #define GPTE_VALID 1 | |
58 | #define GPTE_COHERENT 2 | |
59 | #define GPTE_ENCODE(x) \ | |
60 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) | |
61 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) | |
62 | ||
63 | #define to_pages(addr,size) \ | |
64 | (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT) | |
65 | ||
66 | #define for_all_nb(dev) \ | |
67 | dev = NULL; \ | |
9c01dda0 | 68 | while ((dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1103, dev))!=NULL) |
1da177e4 LT |
69 | |
70 | static struct pci_dev *northbridges[MAX_NB]; | |
71 | static u32 northbridge_flush_word[MAX_NB]; | |
72 | ||
73 | #define EMERGENCY_PAGES 32 /* = 128KB */ | |
74 | ||
75 | #ifdef CONFIG_AGP | |
76 | #define AGPEXTERN extern | |
77 | #else | |
78 | #define AGPEXTERN | |
79 | #endif | |
80 | ||
81 | /* backdoor interface to AGP driver */ | |
82 | AGPEXTERN int agp_memory_reserved; | |
83 | AGPEXTERN __u32 *agp_gatt_table; | |
84 | ||
85 | static unsigned long next_bit; /* protected by iommu_bitmap_lock */ | |
86 | static int need_flush; /* global flush state. set for each gart wrap */ | |
1da177e4 LT |
87 | |
88 | static unsigned long alloc_iommu(int size) | |
89 | { | |
90 | unsigned long offset, flags; | |
91 | ||
92 | spin_lock_irqsave(&iommu_bitmap_lock, flags); | |
93 | offset = find_next_zero_string(iommu_gart_bitmap,next_bit,iommu_pages,size); | |
94 | if (offset == -1) { | |
95 | need_flush = 1; | |
f5adc9c7 | 96 | offset = find_next_zero_string(iommu_gart_bitmap,0,iommu_pages,size); |
1da177e4 LT |
97 | } |
98 | if (offset != -1) { | |
99 | set_bit_string(iommu_gart_bitmap, offset, size); | |
100 | next_bit = offset+size; | |
101 | if (next_bit >= iommu_pages) { | |
102 | next_bit = 0; | |
103 | need_flush = 1; | |
104 | } | |
105 | } | |
106 | if (iommu_fullflush) | |
107 | need_flush = 1; | |
108 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); | |
109 | return offset; | |
110 | } | |
111 | ||
112 | static void free_iommu(unsigned long offset, int size) | |
113 | { | |
114 | unsigned long flags; | |
1da177e4 LT |
115 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
116 | __clear_bit_string(iommu_gart_bitmap, offset, size); | |
117 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); | |
118 | } | |
119 | ||
120 | /* | |
121 | * Use global flush state to avoid races with multiple flushers. | |
122 | */ | |
123 | static void flush_gart(struct device *dev) | |
124 | { | |
125 | unsigned long flags; | |
126 | int flushed = 0; | |
127 | int i, max; | |
128 | ||
129 | spin_lock_irqsave(&iommu_bitmap_lock, flags); | |
130 | if (need_flush) { | |
131 | max = 0; | |
132 | for (i = 0; i < MAX_NB; i++) { | |
133 | if (!northbridges[i]) | |
134 | continue; | |
135 | pci_write_config_dword(northbridges[i], 0x9c, | |
136 | northbridge_flush_word[i] | 1); | |
137 | flushed++; | |
138 | max = i; | |
139 | } | |
140 | for (i = 0; i <= max; i++) { | |
141 | u32 w; | |
142 | if (!northbridges[i]) | |
143 | continue; | |
144 | /* Make sure the hardware actually executed the flush. */ | |
85f9eebc | 145 | for (;;) { |
1da177e4 | 146 | pci_read_config_dword(northbridges[i], 0x9c, &w); |
85f9eebc AK |
147 | if (!(w & 1)) |
148 | break; | |
149 | cpu_relax(); | |
150 | } | |
1da177e4 LT |
151 | } |
152 | if (!flushed) | |
153 | printk("nothing to flush?\n"); | |
154 | need_flush = 0; | |
155 | } | |
156 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); | |
157 | } | |
158 | ||
1da177e4 | 159 | |
1da177e4 LT |
160 | |
161 | #ifdef CONFIG_IOMMU_LEAK | |
162 | ||
163 | #define SET_LEAK(x) if (iommu_leak_tab) \ | |
164 | iommu_leak_tab[x] = __builtin_return_address(0); | |
165 | #define CLEAR_LEAK(x) if (iommu_leak_tab) \ | |
166 | iommu_leak_tab[x] = NULL; | |
167 | ||
168 | /* Debugging aid for drivers that don't free their IOMMU tables */ | |
169 | static void **iommu_leak_tab; | |
170 | static int leak_trace; | |
171 | int iommu_leak_pages = 20; | |
172 | void dump_leak(void) | |
173 | { | |
174 | int i; | |
175 | static int dump; | |
176 | if (dump || !iommu_leak_tab) return; | |
177 | dump = 1; | |
178 | show_stack(NULL,NULL); | |
179 | /* Very crude. dump some from the end of the table too */ | |
180 | printk("Dumping %d pages from end of IOMMU:\n", iommu_leak_pages); | |
181 | for (i = 0; i < iommu_leak_pages; i+=2) { | |
182 | printk("%lu: ", iommu_pages-i); | |
183 | printk_address((unsigned long) iommu_leak_tab[iommu_pages-i]); | |
184 | printk("%c", (i+1)%2 == 0 ? '\n' : ' '); | |
185 | } | |
186 | printk("\n"); | |
187 | } | |
188 | #else | |
189 | #define SET_LEAK(x) | |
190 | #define CLEAR_LEAK(x) | |
191 | #endif | |
192 | ||
17a941d8 | 193 | static void iommu_full(struct device *dev, size_t size, int dir) |
1da177e4 LT |
194 | { |
195 | /* | |
196 | * Ran out of IOMMU space for this operation. This is very bad. | |
197 | * Unfortunately the drivers cannot handle this operation properly. | |
198 | * Return some non mapped prereserved space in the aperture and | |
199 | * let the Northbridge deal with it. This will result in garbage | |
200 | * in the IO operation. When the size exceeds the prereserved space | |
201 | * memory corruption will occur or random memory will be DMAed | |
202 | * out. Hopefully no network devices use single mappings that big. | |
203 | */ | |
204 | ||
205 | printk(KERN_ERR | |
206 | "PCI-DMA: Out of IOMMU space for %lu bytes at device %s\n", | |
207 | size, dev->bus_id); | |
208 | ||
17a941d8 | 209 | if (size > PAGE_SIZE*EMERGENCY_PAGES) { |
1da177e4 LT |
210 | if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
211 | panic("PCI-DMA: Memory would be corrupted\n"); | |
212 | if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) | |
17a941d8 | 213 | panic(KERN_ERR "PCI-DMA: Random memory would be DMAed\n"); |
1da177e4 LT |
214 | } |
215 | ||
216 | #ifdef CONFIG_IOMMU_LEAK | |
217 | dump_leak(); | |
218 | #endif | |
219 | } | |
220 | ||
221 | static inline int need_iommu(struct device *dev, unsigned long addr, size_t size) | |
222 | { | |
223 | u64 mask = *dev->dma_mask; | |
224 | int high = addr + size >= mask; | |
225 | int mmu = high; | |
226 | if (force_iommu) | |
227 | mmu = 1; | |
1da177e4 LT |
228 | return mmu; |
229 | } | |
230 | ||
231 | static inline int nonforced_iommu(struct device *dev, unsigned long addr, size_t size) | |
232 | { | |
233 | u64 mask = *dev->dma_mask; | |
234 | int high = addr + size >= mask; | |
235 | int mmu = high; | |
1da177e4 LT |
236 | return mmu; |
237 | } | |
238 | ||
239 | /* Map a single continuous physical area into the IOMMU. | |
240 | * Caller needs to check if the iommu is needed and flush. | |
241 | */ | |
17a941d8 MBY |
242 | static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, |
243 | size_t size, int dir) | |
1da177e4 LT |
244 | { |
245 | unsigned long npages = to_pages(phys_mem, size); | |
246 | unsigned long iommu_page = alloc_iommu(npages); | |
247 | int i; | |
248 | if (iommu_page == -1) { | |
249 | if (!nonforced_iommu(dev, phys_mem, size)) | |
250 | return phys_mem; | |
251 | if (panic_on_overflow) | |
252 | panic("dma_map_area overflow %lu bytes\n", size); | |
17a941d8 | 253 | iommu_full(dev, size, dir); |
1da177e4 LT |
254 | return bad_dma_address; |
255 | } | |
256 | ||
257 | for (i = 0; i < npages; i++) { | |
258 | iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem); | |
259 | SET_LEAK(iommu_page + i); | |
260 | phys_mem += PAGE_SIZE; | |
261 | } | |
262 | return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); | |
263 | } | |
264 | ||
17a941d8 MBY |
265 | static dma_addr_t gart_map_simple(struct device *dev, char *buf, |
266 | size_t size, int dir) | |
267 | { | |
268 | dma_addr_t map = dma_map_area(dev, virt_to_bus(buf), size, dir); | |
269 | flush_gart(dev); | |
270 | return map; | |
271 | } | |
272 | ||
1da177e4 | 273 | /* Map a single area into the IOMMU */ |
17a941d8 | 274 | dma_addr_t gart_map_single(struct device *dev, void *addr, size_t size, int dir) |
1da177e4 LT |
275 | { |
276 | unsigned long phys_mem, bus; | |
277 | ||
278 | BUG_ON(dir == DMA_NONE); | |
279 | ||
1da177e4 LT |
280 | if (!dev) |
281 | dev = &fallback_dev; | |
282 | ||
283 | phys_mem = virt_to_phys(addr); | |
284 | if (!need_iommu(dev, phys_mem, size)) | |
285 | return phys_mem; | |
286 | ||
17a941d8 | 287 | bus = gart_map_simple(dev, addr, size, dir); |
1da177e4 | 288 | return bus; |
17a941d8 MBY |
289 | } |
290 | ||
291 | /* | |
292 | * Wrapper for pci_unmap_single working with scatterlists. | |
293 | */ | |
294 | void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir) | |
295 | { | |
296 | int i; | |
297 | ||
298 | for (i = 0; i < nents; i++) { | |
299 | struct scatterlist *s = &sg[i]; | |
60b08c67 | 300 | if (!s->dma_length || !s->length) |
17a941d8 MBY |
301 | break; |
302 | dma_unmap_single(dev, s->dma_address, s->dma_length, dir); | |
303 | } | |
304 | } | |
1da177e4 LT |
305 | |
306 | /* Fallback for dma_map_sg in case of overflow */ | |
307 | static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, | |
308 | int nents, int dir) | |
309 | { | |
310 | int i; | |
311 | ||
312 | #ifdef CONFIG_IOMMU_DEBUG | |
313 | printk(KERN_DEBUG "dma_map_sg overflow\n"); | |
314 | #endif | |
315 | ||
316 | for (i = 0; i < nents; i++ ) { | |
317 | struct scatterlist *s = &sg[i]; | |
318 | unsigned long addr = page_to_phys(s->page) + s->offset; | |
319 | if (nonforced_iommu(dev, addr, s->length)) { | |
17a941d8 | 320 | addr = dma_map_area(dev, addr, s->length, dir); |
1da177e4 LT |
321 | if (addr == bad_dma_address) { |
322 | if (i > 0) | |
17a941d8 | 323 | gart_unmap_sg(dev, sg, i, dir); |
1da177e4 LT |
324 | nents = 0; |
325 | sg[0].dma_length = 0; | |
326 | break; | |
327 | } | |
328 | } | |
329 | s->dma_address = addr; | |
330 | s->dma_length = s->length; | |
331 | } | |
332 | flush_gart(dev); | |
333 | return nents; | |
334 | } | |
335 | ||
336 | /* Map multiple scatterlist entries continuous into the first. */ | |
337 | static int __dma_map_cont(struct scatterlist *sg, int start, int stopat, | |
338 | struct scatterlist *sout, unsigned long pages) | |
339 | { | |
340 | unsigned long iommu_start = alloc_iommu(pages); | |
341 | unsigned long iommu_page = iommu_start; | |
342 | int i; | |
343 | ||
344 | if (iommu_start == -1) | |
345 | return -1; | |
346 | ||
347 | for (i = start; i < stopat; i++) { | |
348 | struct scatterlist *s = &sg[i]; | |
349 | unsigned long pages, addr; | |
350 | unsigned long phys_addr = s->dma_address; | |
351 | ||
352 | BUG_ON(i > start && s->offset); | |
353 | if (i == start) { | |
60b08c67 | 354 | *sout = *s; |
1da177e4 LT |
355 | sout->dma_address = iommu_bus_base; |
356 | sout->dma_address += iommu_page*PAGE_SIZE + s->offset; | |
357 | sout->dma_length = s->length; | |
358 | } else { | |
359 | sout->dma_length += s->length; | |
360 | } | |
361 | ||
362 | addr = phys_addr; | |
363 | pages = to_pages(s->offset, s->length); | |
364 | while (pages--) { | |
365 | iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); | |
366 | SET_LEAK(iommu_page); | |
367 | addr += PAGE_SIZE; | |
368 | iommu_page++; | |
0d541064 | 369 | } |
1da177e4 LT |
370 | } |
371 | BUG_ON(iommu_page - iommu_start != pages); | |
372 | return 0; | |
373 | } | |
374 | ||
375 | static inline int dma_map_cont(struct scatterlist *sg, int start, int stopat, | |
376 | struct scatterlist *sout, | |
377 | unsigned long pages, int need) | |
378 | { | |
379 | if (!need) { | |
380 | BUG_ON(stopat - start != 1); | |
60b08c67 | 381 | *sout = sg[start]; |
1da177e4 LT |
382 | sout->dma_length = sg[start].length; |
383 | return 0; | |
384 | } | |
385 | return __dma_map_cont(sg, start, stopat, sout, pages); | |
386 | } | |
387 | ||
388 | /* | |
389 | * DMA map all entries in a scatterlist. | |
390 | * Merge chunks that have page aligned sizes into a continuous mapping. | |
391 | */ | |
17a941d8 | 392 | int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir) |
1da177e4 LT |
393 | { |
394 | int i; | |
395 | int out; | |
396 | int start; | |
397 | unsigned long pages = 0; | |
398 | int need = 0, nextneed; | |
399 | ||
400 | BUG_ON(dir == DMA_NONE); | |
401 | if (nents == 0) | |
402 | return 0; | |
403 | ||
1da177e4 LT |
404 | if (!dev) |
405 | dev = &fallback_dev; | |
406 | ||
407 | out = 0; | |
408 | start = 0; | |
409 | for (i = 0; i < nents; i++) { | |
410 | struct scatterlist *s = &sg[i]; | |
411 | dma_addr_t addr = page_to_phys(s->page) + s->offset; | |
412 | s->dma_address = addr; | |
413 | BUG_ON(s->length == 0); | |
414 | ||
415 | nextneed = need_iommu(dev, addr, s->length); | |
416 | ||
417 | /* Handle the previous not yet processed entries */ | |
418 | if (i > start) { | |
419 | struct scatterlist *ps = &sg[i-1]; | |
420 | /* Can only merge when the last chunk ends on a page | |
421 | boundary and the new one doesn't have an offset. */ | |
422 | if (!iommu_merge || !nextneed || !need || s->offset || | |
423 | (ps->offset + ps->length) % PAGE_SIZE) { | |
424 | if (dma_map_cont(sg, start, i, sg+out, pages, | |
425 | need) < 0) | |
426 | goto error; | |
427 | out++; | |
428 | pages = 0; | |
429 | start = i; | |
430 | } | |
431 | } | |
432 | ||
433 | need = nextneed; | |
434 | pages += to_pages(s->offset, s->length); | |
435 | } | |
436 | if (dma_map_cont(sg, start, i, sg+out, pages, need) < 0) | |
437 | goto error; | |
438 | out++; | |
439 | flush_gart(dev); | |
440 | if (out < nents) | |
441 | sg[out].dma_length = 0; | |
442 | return out; | |
443 | ||
444 | error: | |
445 | flush_gart(NULL); | |
17a941d8 | 446 | gart_unmap_sg(dev, sg, nents, dir); |
a1002a48 KV |
447 | /* When it was forced or merged try again in a dumb way */ |
448 | if (force_iommu || iommu_merge) { | |
449 | out = dma_map_sg_nonforce(dev, sg, nents, dir); | |
450 | if (out > 0) | |
451 | return out; | |
452 | } | |
1da177e4 LT |
453 | if (panic_on_overflow) |
454 | panic("dma_map_sg: overflow on %lu pages\n", pages); | |
17a941d8 | 455 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
1da177e4 LT |
456 | for (i = 0; i < nents; i++) |
457 | sg[i].dma_address = bad_dma_address; | |
458 | return 0; | |
459 | } | |
460 | ||
461 | /* | |
462 | * Free a DMA mapping. | |
463 | */ | |
17a941d8 | 464 | void gart_unmap_single(struct device *dev, dma_addr_t dma_addr, |
1da177e4 LT |
465 | size_t size, int direction) |
466 | { | |
467 | unsigned long iommu_page; | |
468 | int npages; | |
469 | int i; | |
470 | ||
1da177e4 LT |
471 | if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || |
472 | dma_addr >= iommu_bus_base + iommu_size) | |
473 | return; | |
474 | iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; | |
475 | npages = to_pages(dma_addr, size); | |
476 | for (i = 0; i < npages; i++) { | |
477 | iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; | |
478 | CLEAR_LEAK(iommu_page + i); | |
479 | } | |
480 | free_iommu(iommu_page, npages); | |
481 | } | |
482 | ||
17a941d8 | 483 | static int no_agp; |
1da177e4 LT |
484 | |
485 | static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) | |
486 | { | |
487 | unsigned long a; | |
488 | if (!iommu_size) { | |
489 | iommu_size = aper_size; | |
490 | if (!no_agp) | |
491 | iommu_size /= 2; | |
492 | } | |
493 | ||
494 | a = aper + iommu_size; | |
495 | iommu_size -= round_up(a, LARGE_PAGE_SIZE) - a; | |
496 | ||
497 | if (iommu_size < 64*1024*1024) | |
498 | printk(KERN_WARNING | |
499 | "PCI-DMA: Warning: Small IOMMU %luMB. Consider increasing the AGP aperture in BIOS\n",iommu_size>>20); | |
500 | ||
501 | return iommu_size; | |
502 | } | |
503 | ||
504 | static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) | |
505 | { | |
506 | unsigned aper_size = 0, aper_base_32; | |
507 | u64 aper_base; | |
508 | unsigned aper_order; | |
509 | ||
510 | pci_read_config_dword(dev, 0x94, &aper_base_32); | |
511 | pci_read_config_dword(dev, 0x90, &aper_order); | |
512 | aper_order = (aper_order >> 1) & 7; | |
513 | ||
514 | aper_base = aper_base_32 & 0x7fff; | |
515 | aper_base <<= 25; | |
516 | ||
517 | aper_size = (32 * 1024 * 1024) << aper_order; | |
518 | if (aper_base + aper_size >= 0xffffffff || !aper_size) | |
519 | aper_base = 0; | |
520 | ||
521 | *size = aper_size; | |
522 | return aper_base; | |
523 | } | |
524 | ||
525 | /* | |
526 | * Private Northbridge GATT initialization in case we cannot use the | |
527 | * AGP driver for some reason. | |
528 | */ | |
529 | static __init int init_k8_gatt(struct agp_kern_info *info) | |
530 | { | |
531 | struct pci_dev *dev; | |
532 | void *gatt; | |
533 | unsigned aper_base, new_aper_base; | |
534 | unsigned aper_size, gatt_size, new_aper_size; | |
535 | ||
536 | printk(KERN_INFO "PCI-DMA: Disabling AGP.\n"); | |
537 | aper_size = aper_base = info->aper_size = 0; | |
538 | for_all_nb(dev) { | |
539 | new_aper_base = read_aperture(dev, &new_aper_size); | |
540 | if (!new_aper_base) | |
541 | goto nommu; | |
542 | ||
543 | if (!aper_base) { | |
544 | aper_size = new_aper_size; | |
545 | aper_base = new_aper_base; | |
546 | } | |
547 | if (aper_size != new_aper_size || aper_base != new_aper_base) | |
548 | goto nommu; | |
549 | } | |
550 | if (!aper_base) | |
551 | goto nommu; | |
552 | info->aper_base = aper_base; | |
553 | info->aper_size = aper_size>>20; | |
554 | ||
555 | gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); | |
556 | gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size)); | |
557 | if (!gatt) | |
558 | panic("Cannot allocate GATT table"); | |
559 | memset(gatt, 0, gatt_size); | |
560 | agp_gatt_table = gatt; | |
561 | ||
562 | for_all_nb(dev) { | |
563 | u32 ctl; | |
564 | u32 gatt_reg; | |
565 | ||
566 | gatt_reg = __pa(gatt) >> 12; | |
567 | gatt_reg <<= 4; | |
568 | pci_write_config_dword(dev, 0x98, gatt_reg); | |
569 | pci_read_config_dword(dev, 0x90, &ctl); | |
570 | ||
571 | ctl |= 1; | |
572 | ctl &= ~((1<<4) | (1<<5)); | |
573 | ||
574 | pci_write_config_dword(dev, 0x90, ctl); | |
575 | } | |
576 | flush_gart(NULL); | |
577 | ||
578 | printk("PCI-DMA: aperture base @ %x size %u KB\n",aper_base, aper_size>>10); | |
579 | return 0; | |
580 | ||
581 | nommu: | |
582 | /* Should not happen anymore */ | |
583 | printk(KERN_ERR "PCI-DMA: More than 4GB of RAM and no IOMMU\n" | |
f46ace69 | 584 | KERN_ERR "PCI-DMA: 32bit PCI IO may malfunction.\n"); |
1da177e4 LT |
585 | return -1; |
586 | } | |
587 | ||
588 | extern int agp_amd64_init(void); | |
589 | ||
17a941d8 MBY |
590 | static struct dma_mapping_ops gart_dma_ops = { |
591 | .mapping_error = NULL, | |
592 | .map_single = gart_map_single, | |
593 | .map_simple = gart_map_simple, | |
594 | .unmap_single = gart_unmap_single, | |
595 | .sync_single_for_cpu = NULL, | |
596 | .sync_single_for_device = NULL, | |
597 | .sync_single_range_for_cpu = NULL, | |
598 | .sync_single_range_for_device = NULL, | |
599 | .sync_sg_for_cpu = NULL, | |
600 | .sync_sg_for_device = NULL, | |
601 | .map_sg = gart_map_sg, | |
602 | .unmap_sg = gart_unmap_sg, | |
603 | }; | |
604 | ||
1da177e4 LT |
605 | static int __init pci_iommu_init(void) |
606 | { | |
607 | struct agp_kern_info info; | |
608 | unsigned long aper_size; | |
609 | unsigned long iommu_start; | |
610 | struct pci_dev *dev; | |
611 | unsigned long scratch; | |
612 | long i; | |
613 | ||
614 | #ifndef CONFIG_AGP_AMD64 | |
615 | no_agp = 1; | |
616 | #else | |
617 | /* Makefile puts PCI initialization via subsys_initcall first. */ | |
618 | /* Add other K8 AGP bridge drivers here */ | |
619 | no_agp = no_agp || | |
620 | (agp_amd64_init() < 0) || | |
621 | (agp_copy_info(agp_bridge, &info) < 0); | |
622 | #endif | |
623 | ||
60b08c67 | 624 | if (swiotlb) |
1da177e4 | 625 | return -1; |
60b08c67 | 626 | |
1da177e4 | 627 | if (no_iommu || |
17a941d8 | 628 | (!force_iommu && end_pfn <= MAX_DMA32_PFN) || |
1da177e4 LT |
629 | !iommu_aperture || |
630 | (no_agp && init_k8_gatt(&info) < 0)) { | |
5b7b644c JM |
631 | printk(KERN_INFO "PCI-DMA: Disabling IOMMU.\n"); |
632 | if (end_pfn > MAX_DMA32_PFN) { | |
633 | printk(KERN_ERR "WARNING more than 4GB of memory " | |
dc9a7195 AK |
634 | "but IOMMU not available.\n" |
635 | KERN_ERR "WARNING 32bit PCI may malfunction.\n"); | |
5b7b644c | 636 | } |
1da177e4 LT |
637 | return -1; |
638 | } | |
639 | ||
5192d84e AK |
640 | i = 0; |
641 | for_all_nb(dev) | |
642 | i++; | |
643 | if (i > MAX_NB) { | |
644 | printk(KERN_ERR "PCI-GART: Too many northbridges (%ld). Disabled\n", i); | |
645 | return -1; | |
646 | } | |
647 | ||
5b7b644c | 648 | printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n"); |
1da177e4 LT |
649 | aper_size = info.aper_size * 1024 * 1024; |
650 | iommu_size = check_iommu_size(info.aper_base, aper_size); | |
651 | iommu_pages = iommu_size >> PAGE_SHIFT; | |
652 | ||
653 | iommu_gart_bitmap = (void*)__get_free_pages(GFP_KERNEL, | |
654 | get_order(iommu_pages/8)); | |
655 | if (!iommu_gart_bitmap) | |
656 | panic("Cannot allocate iommu bitmap\n"); | |
657 | memset(iommu_gart_bitmap, 0, iommu_pages/8); | |
658 | ||
659 | #ifdef CONFIG_IOMMU_LEAK | |
660 | if (leak_trace) { | |
661 | iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL, | |
662 | get_order(iommu_pages*sizeof(void *))); | |
663 | if (iommu_leak_tab) | |
664 | memset(iommu_leak_tab, 0, iommu_pages * 8); | |
665 | else | |
666 | printk("PCI-DMA: Cannot allocate leak trace area\n"); | |
667 | } | |
668 | #endif | |
669 | ||
670 | /* | |
671 | * Out of IOMMU space handling. | |
672 | * Reserve some invalid pages at the beginning of the GART. | |
673 | */ | |
674 | set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES); | |
675 | ||
676 | agp_memory_reserved = iommu_size; | |
677 | printk(KERN_INFO | |
678 | "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", | |
679 | iommu_size>>20); | |
680 | ||
681 | iommu_start = aper_size - iommu_size; | |
682 | iommu_bus_base = info.aper_base + iommu_start; | |
683 | bad_dma_address = iommu_bus_base; | |
684 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); | |
685 | ||
686 | /* | |
687 | * Unmap the IOMMU part of the GART. The alias of the page is | |
688 | * always mapped with cache enabled and there is no full cache | |
689 | * coherency across the GART remapping. The unmapping avoids | |
690 | * automatic prefetches from the CPU allocating cache lines in | |
691 | * there. All CPU accesses are done via the direct mapping to | |
692 | * the backing memory. The GART address is only used by PCI | |
693 | * devices. | |
694 | */ | |
695 | clear_kernel_mapping((unsigned long)__va(iommu_bus_base), iommu_size); | |
696 | ||
697 | /* | |
698 | * Try to workaround a bug (thanks to BenH) | |
699 | * Set unmapped entries to a scratch page instead of 0. | |
700 | * Any prefetches that hit unmapped entries won't get an bus abort | |
701 | * then. | |
702 | */ | |
703 | scratch = get_zeroed_page(GFP_KERNEL); | |
704 | if (!scratch) | |
705 | panic("Cannot allocate iommu scratch page"); | |
706 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); | |
707 | for (i = EMERGENCY_PAGES; i < iommu_pages; i++) | |
708 | iommu_gatt_base[i] = gart_unmapped_entry; | |
709 | ||
710 | for_all_nb(dev) { | |
711 | u32 flag; | |
712 | int cpu = PCI_SLOT(dev->devfn) - 24; | |
713 | if (cpu >= MAX_NB) | |
714 | continue; | |
715 | northbridges[cpu] = dev; | |
716 | pci_read_config_dword(dev, 0x9c, &flag); /* cache flush word */ | |
717 | northbridge_flush_word[cpu] = flag; | |
718 | } | |
719 | ||
720 | flush_gart(NULL); | |
721 | ||
17a941d8 MBY |
722 | dma_ops = &gart_dma_ops; |
723 | ||
1da177e4 LT |
724 | return 0; |
725 | } | |
726 | ||
727 | /* Must execute after PCI subsystem */ | |
728 | fs_initcall(pci_iommu_init); | |
729 | ||
17a941d8 MBY |
730 | void gart_parse_options(char *p) |
731 | { | |
732 | int arg; | |
733 | ||
1da177e4 | 734 | #ifdef CONFIG_IOMMU_LEAK |
17a941d8 MBY |
735 | if (!strncmp(p,"leak",4)) { |
736 | leak_trace = 1; | |
737 | p += 4; | |
738 | if (*p == '=') ++p; | |
739 | if (isdigit(*p) && get_option(&p, &arg)) | |
740 | iommu_leak_pages = arg; | |
741 | } | |
1da177e4 | 742 | #endif |
17a941d8 MBY |
743 | if (isdigit(*p) && get_option(&p, &arg)) |
744 | iommu_size = arg; | |
745 | if (!strncmp(p, "fullflush",8)) | |
746 | iommu_fullflush = 1; | |
747 | if (!strncmp(p, "nofullflush",11)) | |
748 | iommu_fullflush = 0; | |
749 | if (!strncmp(p,"noagp",5)) | |
750 | no_agp = 1; | |
751 | if (!strncmp(p, "noaperture",10)) | |
752 | fix_aperture = 0; | |
753 | /* duplicated from pci-dma.c */ | |
754 | if (!strncmp(p,"force",5)) | |
755 | iommu_aperture_allowed = 1; | |
756 | if (!strncmp(p,"allowed",7)) | |
757 | iommu_aperture_allowed = 1; | |
758 | if (!strncmp(p, "memaper", 7)) { | |
759 | fallback_aper_force = 1; | |
760 | p += 7; | |
761 | if (*p == '=') { | |
762 | ++p; | |
763 | if (get_option(&p, &arg)) | |
764 | fallback_aper_order = arg; | |
765 | } | |
766 | } | |
767 | } |