[linux-2.6-block.git] / arch / x86 / platform / intel-mid / mfld.c

/*
 * mfld.c: Intel Medfield platform setup code
 *
 * (C) Copyright 2013 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2
 * of the License.
 */

#include <linux/init.h>

#include <asm/apic.h>
#include <asm/intel-mid.h>
#include <asm/intel_mid_vrtc.h>

#include "intel_mid_weak_decls.h"

static void penwell_arch_setup(void);
/* penwell arch ops */
static struct intel_mid_ops penwell_ops = {
	.arch_setup = penwell_arch_setup,
};

static void mfld_power_off(void)
{
}

static unsigned long __init mfld_calibrate_tsc(void)
{
	unsigned long fast_calibrate;
	u32 lo, hi, ratio, fsb;

	rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
	pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
	ratio = (hi >> 8) & 0x1f;
	pr_debug("ratio is %d\n", ratio);
	if (!ratio) {
		pr_err("read a zero ratio, should be incorrect!\n");
		pr_err("force tsc ratio to 16 ...\n");
		ratio = 16;
	}
	rdmsr(MSR_FSB_FREQ, lo, hi);
	if ((lo & 0x7) == 0x7)
		fsb = FSB_FREQ_83SKU;
	else
		fsb = FSB_FREQ_100SKU;
	fast_calibrate = ratio * fsb;
	pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
	lapic_timer_frequency = fsb * 1000 / HZ;
	/* mark tsc clocksource as reliable */
	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);

	return fast_calibrate;
}

static void __init penwell_arch_setup(void)
{
	x86_platform.calibrate_tsc = mfld_calibrate_tsc;
	pm_power_off = mfld_power_off;
}

void *get_penwell_ops(void)
{
	return &penwell_ops;
}

void *get_cloverview_ops(void)
{
	return &penwell_ops;
}
Commit	Line	Data
ecd6910d DC	1	/*
	2	* mfld.c: Intel Medfield platform setup code
	3	*
	4	* (C) Copyright 2013 Intel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; version 2
	9	* of the License.
	10	*/
	11
	12	#include <linux/init.h>
	13
	14	#include <asm/apic.h>
	15	#include <asm/intel-mid.h>
	16	#include <asm/intel_mid_vrtc.h>
	17
85611e3f KS	18	#include "intel_mid_weak_decls.h"
	19
	20	static void penwell_arch_setup(void);
	21	/* penwell arch ops */
	22	static struct intel_mid_ops penwell_ops = {
	23	.arch_setup = penwell_arch_setup,
	24	};
	25
	26	static void mfld_power_off(void)
ecd6910d DC	27	{
	28	}
	29
85611e3f	30	static unsigned long __init mfld_calibrate_tsc(void)
ecd6910d DC	31	{
	32	unsigned long fast_calibrate;
	33	u32 lo, hi, ratio, fsb;
	34
	35	rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
	36	pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
	37	ratio = (hi >> 8) & 0x1f;
	38	pr_debug("ratio is %d\n", ratio);
	39	if (!ratio) {
	40	pr_err("read a zero ratio, should be incorrect!\n");
	41	pr_err("force tsc ratio to 16 ...\n");
	42	ratio = 16;
	43	}
	44	rdmsr(MSR_FSB_FREQ, lo, hi);
	45	if ((lo & 0x7) == 0x7)
85611e3f	46	fsb = FSB_FREQ_83SKU;
ecd6910d	47	else
85611e3f	48	fsb = FSB_FREQ_100SKU;
ecd6910d DC	49	fast_calibrate = ratio * fsb;
	50	pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
	51	lapic_timer_frequency = fsb * 1000 / HZ;
	52	/* mark tsc clocksource as reliable */
	53	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
	54
8f8e2aec	55	return fast_calibrate;
ecd6910d	56	}
85611e3f	57
48102ca7	58	static void __init penwell_arch_setup(void)
85611e3f KS	59	{
	60	x86_platform.calibrate_tsc = mfld_calibrate_tsc;
	61	pm_power_off = mfld_power_off;
	62	}
	63
48102ca7	64	void *get_penwell_ops(void)
85611e3f KS	65	{
	66	return &penwell_ops;
	67	}
	68
48102ca7	69	void *get_cloverview_ops(void)
85611e3f KS	70	{
	71	return &penwell_ops;
	72	}