[linux-2.6-block.git] / arch / x86 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>

#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec const *model;
static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);

static int nmi_start(void);
static void nmi_stop(void);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	if (nmi_enabled == 1)
		nmi_stop();
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_start();
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch (val) {
	case DIE_NMI:
		if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
			ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			rdmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			rdmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}
}

static void nmi_save_registers(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	nmi_cpu_save_registers(msrs);
}

static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).counters);
		per_cpu(cpu_msrs, i).counters = NULL;
		kfree(per_cpu(cpu_msrs, i).controls);
		per_cpu(cpu_msrs, i).controls = NULL;
	}
}

static int allocate_msrs(void)
{
	int success = 1;
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).counters) {
			success = 0;
			break;
		}
		per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).controls) {
			success = 0;
			break;
		}
	}

	if (!success)
		free_msrs();

	return success;
}

static void nmi_cpu_setup(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(msrs);
	spin_unlock(&oprofilefs_lock);
	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 0
};

static int nmi_setup(void)
{
	int err = 0;
	int cpu;

	if (!allocate_msrs())
		return -ENOMEM;

	err = register_die_notifier(&profile_exceptions_nb);
	if (err) {
		free_msrs();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */

	/* Assume saved/restored counters are the same on all CPUs */
	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
	for_each_possible_cpu(cpu) {
		if (cpu != 0) {
			memcpy(per_cpu(cpu_msrs, cpu).counters,
				per_cpu(cpu_msrs, 0).counters,
				sizeof(struct op_msr) * model->num_counters);

			memcpy(per_cpu(cpu_msrs, cpu).controls,
				per_cpu(cpu_msrs, 0).controls,
				sizeof(struct op_msr) * model->num_controls);
		}

	}
	on_each_cpu(nmi_save_registers, NULL, 1);
	on_each_cpu(nmi_cpu_setup, NULL, 1);
	nmi_enabled = 1;
	return 0;
}

static void nmi_restore_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			wrmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			wrmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}
}

static void nmi_cpu_shutdown(void *dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);

	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
	apic_write(APIC_LVTERR, v);
	nmi_restore_registers(msrs);
}

static void nmi_shutdown(void)
{
	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	model->shutdown(msrs);
	free_msrs();
}

static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->start(msrs);
}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->stop(msrs);
}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 1);
}

struct op_counter_config counter_config[OP_MAX_COUNTER];

static int nmi_create_files(struct super_block *sb, struct dentry *root)
{
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		struct dentry *dir;
		char buf[4];

		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	}

	return 0;
}

static int p4force;
module_param(p4force, int, 0);

static int __init p4_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (!p4force && (cpu_model > 6 || cpu_model == 5))
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

static int __init ppro_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (cpu_model == 14)
		*cpu_type = "i386/core";
	else if (cpu_model == 15 || cpu_model == 23)
		*cpu_type = "i386/core_2";
	else if (cpu_model > 0xd)
		return 0;
	else if (cpu_model == 9) {
		*cpu_type = "i386/p6_mobile";
	} else if (cpu_model > 5) {
		*cpu_type = "i386/piii";
	} else if (cpu_model > 2) {
		*cpu_type = "i386/pii";
	} else {
		*cpu_type = "i386/ppro";
	}

	model = &op_ppro_spec;
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type;

	if (!cpu_has_apic)
		return -ENODEV;

	switch (vendor) {
	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */

		switch (family) {
		default:
			return -ENODEV;
		case 6:
			model = &op_athlon_spec;
			cpu_type = "i386/athlon";
			break;
		case 0xf:
			model = &op_athlon_spec;
			/* Actually it could be i386/hammer too, but give
			 user space an consistent name. */
			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			model = &op_athlon_spec;
			cpu_type = "x86-64/family10";
			break;
		}
		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
			if (!p4_init(&cpu_type))
				return -ENODEV;
			break;

			/* A P6-class processor */
		case 6:
			if (!ppro_init(&cpu_type))
				return -ENODEV;
			break;

		default:
			return -ENODEV;
		}
		break;

	default:
		return -ENODEV;
	}

	init_sysfs();
	using_nmi = 1;
	ops->create_files = nmi_create_files;
	ops->setup = nmi_setup;
	ops->shutdown = nmi_shutdown;
	ops->start = nmi_start;
	ops->stop = nmi_stop;
	ops->cpu_type = cpu_type;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

void op_nmi_exit(void)
{
	if (using_nmi)
		exit_sysfs();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
	4	* @remark Copyright 2002 OProfile authors
	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/notifier.h>
	12	#include <linux/smp.h>
	13	#include <linux/oprofile.h>
	14	#include <linux/sysdev.h>
	15	#include <linux/slab.h>
1cfcea1b	16	#include <linux/moduleparam.h>
1eeb66a1	17	#include <linux/kdebug.h>
1da177e4 LT	18	#include <asm/nmi.h>
	19	#include <asm/msr.h>
	20	#include <asm/apic.h>
b75f53db	21
1da177e4 LT	22	#include "op_counter.h"
1da177e4 LT	23	#include "op_x86_model.h"
2fbe7b25	24
b75f53db	25	static struct op_x86_model_spec const *model;
d18d00f5 MT	26	static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
d18d00f5 MT	27	static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
2fbe7b25	28
1da177e4 LT	29	static int nmi_start(void);
	30	static void nmi_stop(void);
	31
	32	/* 0 == registered but off, 1 == registered and on */
	33	static int nmi_enabled = 0;
	34
	35	#ifdef CONFIG_PM
	36
438510f6	37	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	38	{
	39	if (nmi_enabled == 1)
	40	nmi_stop();
	41	return 0;
	42	}
	43
1da177e4 LT	44	static int nmi_resume(struct sys_device *dev)
	45	{
	46	if (nmi_enabled == 1)
	47	nmi_start();
	48	return 0;
	49	}
	50
1da177e4	51	static struct sysdev_class oprofile_sysclass = {
af5ca3f4	52	.name = "oprofile",
1da177e4 LT	53	.resume = nmi_resume,
	54	.suspend = nmi_suspend,
	55	};
	56
1da177e4 LT	57	static struct sys_device device_oprofile = {
	58	.id = 0,
	59	.cls = &oprofile_sysclass,
	60	};
	61
405ae7d3	62	static int __init init_sysfs(void)
1da177e4 LT	63	{
1da177e4 LT	64	int error;
b75f53db CM	65
	66	error = sysdev_class_register(&oprofile_sysclass);
	67	if (!error)
1da177e4 LT	68	error = sysdev_register(&device_oprofile);
	69	return error;
	70	}
	71
405ae7d3	72	static void exit_sysfs(void)
1da177e4 LT	73	{
	74	sysdev_unregister(&device_oprofile);
	75	sysdev_class_unregister(&oprofile_sysclass);
	76	}
	77
	78	#else
405ae7d3 RD	79	#define init_sysfs() do { } while (0)
405ae7d3 RD	80	#define exit_sysfs() do { } while (0)
1da177e4 LT	81	#endif /* CONFIG_PM */
1da177e4 LT	82
c7c19f8e AB	83	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	84	unsigned long val, void *data)
1da177e4	85	{
2fbe7b25 DZ	86	struct die_args args = (struct die_args )data;
	87	int ret = NOTIFY_DONE;
	88	int cpu = smp_processor_id();
	89
b75f53db	90	switch (val) {
2fbe7b25	91	case DIE_NMI:
d18d00f5	92	if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
2fbe7b25 DZ	93	ret = NOTIFY_STOP;
	94	break;
	95	default:
	96	break;
	97	}
	98	return ret;
1da177e4	99	}
2fbe7b25	100
b75f53db	101	static void nmi_cpu_save_registers(struct op_msrs *msrs)
1da177e4 LT	102	{
1da177e4 LT	103	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	104	unsigned int const nr_ctrls = model->num_controls;
	105	struct op_msr *counters = msrs->counters;
	106	struct op_msr *controls = msrs->controls;
1da177e4 LT	107	unsigned int i;
	108
	109	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	110	if (counters[i].addr) {
cb9c448c DZ	111	rdmsr(counters[i].addr,
	112	counters[i].saved.low,
	113	counters[i].saved.high);
	114	}
1da177e4	115	}
b75f53db	116
1da177e4	117	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	118	if (controls[i].addr) {
cb9c448c DZ	119	rdmsr(controls[i].addr,
	120	controls[i].saved.low,
	121	controls[i].saved.high);
	122	}
1da177e4 LT	123	}
	124	}
	125
b75f53db	126	static void nmi_save_registers(void *dummy)
1da177e4 LT	127	{
1da177e4 LT	128	int cpu = smp_processor_id();
d18d00f5	129	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	130	nmi_cpu_save_registers(msrs);
	131	}
	132
1da177e4 LT	133	static void free_msrs(void)
	134	{
	135	int i;
c8912599	136	for_each_possible_cpu(i) {
d18d00f5 MT	137	kfree(per_cpu(cpu_msrs, i).counters);
	138	per_cpu(cpu_msrs, i).counters = NULL;
	139	kfree(per_cpu(cpu_msrs, i).controls);
	140	per_cpu(cpu_msrs, i).controls = NULL;
1da177e4 LT	141	}
	142	}
	143
1da177e4 LT	144	static int allocate_msrs(void)
	145	{
	146	int success = 1;
	147	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	148	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	149
	150	int i;
0939c17c	151	for_each_possible_cpu(i) {
d18d00f5 MT	152	per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
	153	GFP_KERNEL);
	154	if (!per_cpu(cpu_msrs, i).counters) {
1da177e4 LT	155	success = 0;
	156	break;
	157	}
d18d00f5 MT	158	per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
	159	GFP_KERNEL);
	160	if (!per_cpu(cpu_msrs, i).controls) {
1da177e4 LT	161	success = 0;
	162	break;
	163	}
	164	}
	165
	166	if (!success)
	167	free_msrs();
	168
	169	return success;
	170	}
	171
b75f53db	172	static void nmi_cpu_setup(void *dummy)
1da177e4 LT	173	{
1da177e4 LT	174	int cpu = smp_processor_id();
d18d00f5	175	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	176	spin_lock(&oprofilefs_lock);
	177	model->setup_ctrs(msrs);
	178	spin_unlock(&oprofilefs_lock);
d18d00f5	179	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
1da177e4 LT	180	apic_write(APIC_LVTPC, APIC_DM_NMI);
	181	}
	182
2fbe7b25 DZ	183	static struct notifier_block profile_exceptions_nb = {
	184	.notifier_call = profile_exceptions_notify,
	185	.next = NULL,
	186	.priority = 0
	187	};
1da177e4 LT	188
	189	static int nmi_setup(void)
	190	{
b75f53db	191	int err = 0;
6c977aad	192	int cpu;
2fbe7b25	193
1da177e4 LT	194	if (!allocate_msrs())
	195	return -ENOMEM;
	196
b75f53db CM	197	err = register_die_notifier(&profile_exceptions_nb);
b75f53db CM	198	if (err) {
1da177e4	199	free_msrs();
2fbe7b25	200	return err;
1da177e4	201	}
2fbe7b25	202
1da177e4 LT	203	/* We need to serialize save and setup for HT because the subset
	204	* of msrs are distinct for save and setup operations
	205	*/
6c977aad AK	206
6c977aad AK	207	/* Assume saved/restored counters are the same on all CPUs */
d18d00f5	208	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
b75f53db	209	for_each_possible_cpu(cpu) {
0939c17c	210	if (cpu != 0) {
d18d00f5 MT	211	memcpy(per_cpu(cpu_msrs, cpu).counters,
d18d00f5 MT	212	per_cpu(cpu_msrs, 0).counters,
0939c17c CW	213	sizeof(struct op_msr) * model->num_counters);
0939c17c CW	214
d18d00f5 MT	215	memcpy(per_cpu(cpu_msrs, cpu).controls,
d18d00f5 MT	216	per_cpu(cpu_msrs, 0).controls,
0939c17c CW	217	sizeof(struct op_msr) * model->num_controls);
	218	}
	219
6c977aad	220	}
15c8b6c1 JA	221	on_each_cpu(nmi_save_registers, NULL, 1);
15c8b6c1 JA	222	on_each_cpu(nmi_cpu_setup, NULL, 1);
1da177e4 LT	223	nmi_enabled = 1;
	224	return 0;
	225	}
	226
b75f53db	227	static void nmi_restore_registers(struct op_msrs *msrs)
1da177e4 LT	228	{
1da177e4 LT	229	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	230	unsigned int const nr_ctrls = model->num_controls;
	231	struct op_msr *counters = msrs->counters;
	232	struct op_msr *controls = msrs->controls;
1da177e4 LT	233	unsigned int i;
	234
	235	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	236	if (controls[i].addr) {
cb9c448c DZ	237	wrmsr(controls[i].addr,
	238	controls[i].saved.low,
	239	controls[i].saved.high);
	240	}
1da177e4	241	}
b75f53db	242
1da177e4	243	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	244	if (counters[i].addr) {
cb9c448c DZ	245	wrmsr(counters[i].addr,
	246	counters[i].saved.low,
	247	counters[i].saved.high);
	248	}
1da177e4 LT	249	}
1da177e4 LT	250	}
1da177e4	251
b75f53db	252	static void nmi_cpu_shutdown(void *dummy)
1da177e4 LT	253	{
	254	unsigned int v;
	255	int cpu = smp_processor_id();
d18d00f5	256	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
b75f53db	257
1da177e4 LT	258	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	259	* mode and vector nr combination can be illegal. That's by design: on
	260	* power on apic lvt contain a zero vector nr which are legal only for
	261	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	262	*/
	263	v = apic_read(APIC_LVTERR);
	264	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
d18d00f5	265	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
1da177e4 LT	266	apic_write(APIC_LVTERR, v);
	267	nmi_restore_registers(msrs);
	268	}
	269
1da177e4 LT	270	static void nmi_shutdown(void)
1da177e4 LT	271	{
d18d00f5	272	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
1da177e4	273	nmi_enabled = 0;
15c8b6c1	274	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
2fbe7b25	275	unregister_die_notifier(&profile_exceptions_nb);
d18d00f5	276	model->shutdown(msrs);
1da177e4 LT	277	free_msrs();
	278	}
	279
b75f53db	280	static void nmi_cpu_start(void *dummy)
1da177e4	281	{
d18d00f5	282	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	283	model->start(msrs);
1da177e4 LT	284	}
1da177e4 LT	285
	286	static int nmi_start(void)
	287	{
15c8b6c1	288	on_each_cpu(nmi_cpu_start, NULL, 1);
1da177e4 LT	289	return 0;
1da177e4 LT	290	}
b75f53db CM	291
b75f53db CM	292	static void nmi_cpu_stop(void *dummy)
1da177e4	293	{
d18d00f5	294	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	295	model->stop(msrs);
1da177e4 LT	296	}
b75f53db	297
1da177e4 LT	298	static void nmi_stop(void)
1da177e4 LT	299	{
15c8b6c1	300	on_each_cpu(nmi_cpu_stop, NULL, 1);
1da177e4 LT	301	}
1da177e4 LT	302
1da177e4 LT	303	struct op_counter_config counter_config[OP_MAX_COUNTER];
1da177e4 LT	304
b75f53db	305	static int nmi_create_files(struct super_block sb, struct dentry root)
1da177e4 LT	306	{
	307	unsigned int i;
	308
	309	for (i = 0; i < model->num_counters; ++i) {
b75f53db	310	struct dentry *dir;
0c6856f7	311	char buf[4];
b75f53db CM	312
b75f53db CM	313	/* quick little hack to _not_ expose a counter if it is not
cb9c448c DZ	314	* available for use. This should protect userspace app.
	315	* NOTE: assumes 1:1 mapping here (that counters are organized
	316	* sequentially in their struct assignment).
	317	*/
	318	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	319	continue;
	320
0c6856f7	321	snprintf(buf, sizeof(buf), "%d", i);
1da177e4	322	dir = oprofilefs_mkdir(sb, root, buf);
b75f53db CM	323	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	324	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	325	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	326	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	327	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	328	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
1da177e4 LT	329	}
	330
	331	return 0;
	332	}
b75f53db	333
1cfcea1b AK	334	static int p4force;
1cfcea1b AK	335	module_param(p4force, int, 0);
b75f53db CM	336
b75f53db CM	337	static int __init p4_init(char **cpu_type)
1da177e4 LT	338	{
	339	__u8 cpu_model = boot_cpu_data.x86_model;
	340
1cfcea1b	341	if (!p4force && (cpu_model > 6 \|\| cpu_model == 5))
1da177e4 LT	342	return 0;
	343
	344	#ifndef CONFIG_SMP
	345	*cpu_type = "i386/p4";
	346	model = &op_p4_spec;
	347	return 1;
	348	#else
	349	switch (smp_num_siblings) {
b75f53db CM	350	case 1:
	351	*cpu_type = "i386/p4";
	352	model = &op_p4_spec;
	353	return 1;
	354
	355	case 2:
	356	*cpu_type = "i386/p4-ht";
	357	model = &op_p4_ht2_spec;
	358	return 1;
1da177e4 LT	359	}
	360	#endif
	361
	362	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	363	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	364	return 0;
	365	}
	366
b75f53db	367	static int __init ppro_init(char **cpu_type)
1da177e4 LT	368	{
	369	__u8 cpu_model = boot_cpu_data.x86_model;
	370
64471ebe BL	371	if (cpu_model == 14)
64471ebe BL	372	*cpu_type = "i386/core";
e107ebe0	373	else if (cpu_model == 15 \|\| cpu_model == 23)
f04b92e9	374	*cpu_type = "i386/core_2";
64471ebe	375	else if (cpu_model > 0xd)
1da177e4	376	return 0;
64471ebe	377	else if (cpu_model == 9) {
1da177e4 LT	378	*cpu_type = "i386/p6_mobile";
	379	} else if (cpu_model > 5) {
	380	*cpu_type = "i386/piii";
	381	} else if (cpu_model > 2) {
	382	*cpu_type = "i386/pii";
	383	} else {
	384	*cpu_type = "i386/ppro";
	385	}
	386
	387	model = &op_ppro_spec;
	388	return 1;
	389	}
	390
405ae7d3	391	/* in order to get sysfs right */
1da177e4 LT	392	static int using_nmi;
1da177e4 LT	393
96d0821c	394	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	395	{
	396	__u8 vendor = boot_cpu_data.x86_vendor;
	397	__u8 family = boot_cpu_data.x86;
	398	char *cpu_type;
	399
	400	if (!cpu_has_apic)
	401	return -ENODEV;
b75f53db	402
1da177e4	403	switch (vendor) {
b75f53db CM	404	case X86_VENDOR_AMD:
b75f53db CM	405	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
1da177e4	406
b75f53db CM	407	switch (family) {
	408	default:
	409	return -ENODEV;
	410	case 6:
	411	model = &op_athlon_spec;
	412	cpu_type = "i386/athlon";
	413	break;
	414	case 0xf:
	415	model = &op_athlon_spec;
	416	/* Actually it could be i386/hammer too, but give
	417	user space an consistent name. */
	418	cpu_type = "x86-64/hammer";
	419	break;
	420	case 0x10:
	421	model = &op_athlon_spec;
	422	cpu_type = "x86-64/family10";
	423	break;
	424	}
	425	break;
	426
	427	case X86_VENDOR_INTEL:
	428	switch (family) {
	429	/* Pentium IV */
	430	case 0xf:
	431	if (!p4_init(&cpu_type))
1da177e4	432	return -ENODEV;
1da177e4	433	break;
b75f53db CM	434
	435	/* A P6-class processor */
	436	case 6:
	437	if (!ppro_init(&cpu_type))
	438	return -ENODEV;
1da177e4 LT	439	break;
	440
	441	default:
	442	return -ENODEV;
b75f53db CM	443	}
	444	break;
	445
	446	default:
	447	return -ENODEV;
1da177e4 LT	448	}
1da177e4 LT	449
405ae7d3	450	init_sysfs();
1da177e4 LT	451	using_nmi = 1;
	452	ops->create_files = nmi_create_files;
	453	ops->setup = nmi_setup;
	454	ops->shutdown = nmi_shutdown;
	455	ops->start = nmi_start;
	456	ops->stop = nmi_stop;
	457	ops->cpu_type = cpu_type;
	458	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	459	return 0;
	460	}
	461
96d0821c	462	void op_nmi_exit(void)
1da177e4 LT	463	{
1da177e4 LT	464	if (using_nmi)
405ae7d3	465	exit_sysfs();
1da177e4	466	}