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KVM: x86: optimize steal time calculation
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
52004014
FW		 126static bool __read_mostly vector_hashing = true;
127module_param(vector_hashing, bool, S_IRUGO);
128
893590c7 129static bool __read_mostly backwards_tsc_observed = false;
16a96021 130
18863bdd
AK		 131#define KVM_NR_SHARED_MSRS 16
132
133struct kvm_shared_msrs_global {
134 int nr;
2bf78fa7 135 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 136};
137
138struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
2bf78fa7
SY		 141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 145};
146
147static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 148static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 149
417bc304 150struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 161 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 164 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 165 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 166 { "request_irq", VCPU_STAT(request_irq_exits) },
167 { "irq_exits", VCPU_STAT(irq_exits) },
168 { "host_state_reload", VCPU_STAT(host_state_reload) },
169 { "efer_reload", VCPU_STAT(efer_reload) },
170 { "fpu_reload", VCPU_STAT(fpu_reload) },
171 { "insn_emulation", VCPU_STAT(insn_emulation) },
172 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 173 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 174 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 175 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
176 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
177 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
178 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
179 { "mmu_flooded", VM_STAT(mmu_flooded) },
180 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 181 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 182 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 183 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 184 { "largepages", VM_STAT(lpages) },
417bc304
HB		 185 { NULL }
186};
187
2acf923e
DC		 188u64 __read_mostly host_xcr0;
189
b6785def 190static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 191
af585b92
GN		 192static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
193{
194 int i;
195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
196 vcpu->arch.apf.gfns[i] = ~0;
197}
198
18863bdd
AK		 199static void kvm_on_user_return(struct user_return_notifier *urn)
200{
201 unsigned slot;
18863bdd
AK		 202 struct kvm_shared_msrs *locals
203 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 204 struct kvm_shared_msr_values *values;
18863bdd
AK		 205
206 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 207 values = &locals->values[slot];
208 if (values->host != values->curr) {
209 wrmsrl(shared_msrs_global.msrs[slot], values->host);
210 values->curr = values->host;
18863bdd
AK		 211 }
212 }
213 locals->registered = false;
214 user_return_notifier_unregister(urn);
215}
216
2bf78fa7 217static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 218{
18863bdd 219 u64 value;
013f6a5d
MT		 220 unsigned int cpu = smp_processor_id();
221 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 222
2bf78fa7
SY		 223 /* only read, and nobody should modify it at this time,
224 * so don't need lock */
225 if (slot >= shared_msrs_global.nr) {
226 printk(KERN_ERR "kvm: invalid MSR slot!");
227 return;
228 }
229 rdmsrl_safe(msr, &value);
230 smsr->values[slot].host = value;
231 smsr->values[slot].curr = value;
232}
233
234void kvm_define_shared_msr(unsigned slot, u32 msr)
235{
0123be42 236 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 237 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 238 if (slot >= shared_msrs_global.nr)
239 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 240}
241EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
242
243static void kvm_shared_msr_cpu_online(void)
244{
245 unsigned i;
18863bdd
AK		 246
247 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 248 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 249}
250
8b3c3104 251int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 252{
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 255 int err;
18863bdd 256
2bf78fa7 257 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 258 return 0;
2bf78fa7 259 smsr->values[slot].curr = value;
8b3c3104
AH		 260 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
261 if (err)
262 return 1;
263
18863bdd
AK		 264 if (!smsr->registered) {
265 smsr->urn.on_user_return = kvm_on_user_return;
266 user_return_notifier_register(&smsr->urn);
267 smsr->registered = true;
268 }
8b3c3104 269 return 0;
18863bdd
AK		 270}
271EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
272
13a34e06 273static void drop_user_return_notifiers(void)
3548bab5 274{
013f6a5d
MT		 275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 277
278 if (smsr->registered)
279 kvm_on_user_return(&smsr->urn);
280}
281
6866b83e
CO		 282u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
283{
8a5a87d9 284 return vcpu->arch.apic_base;
6866b83e
CO		 285}
286EXPORT_SYMBOL_GPL(kvm_get_apic_base);
287
58cb628d
JK		 288int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
289{
290 u64 old_state = vcpu->arch.apic_base &
291 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
292 u64 new_state = msr_info->data &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
295 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
296
297 if (!msr_info->host_initiated &&
298 ((msr_info->data & reserved_bits) != 0 ||
299 new_state == X2APIC_ENABLE ||
300 (new_state == MSR_IA32_APICBASE_ENABLE &&
301 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
302 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
303 old_state == 0)))
304 return 1;
305
306 kvm_lapic_set_base(vcpu, msr_info->data);
307 return 0;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_set_apic_base);
310
2605fc21 311asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 312{
313 /* Fault while not rebooting. We want the trace. */
314 BUG();
315}
316EXPORT_SYMBOL_GPL(kvm_spurious_fault);
317
3fd28fce
ED		 318#define EXCPT_BENIGN 0
319#define EXCPT_CONTRIBUTORY 1
320#define EXCPT_PF 2
321
322static int exception_class(int vector)
323{
324 switch (vector) {
325 case PF_VECTOR:
326 return EXCPT_PF;
327 case DE_VECTOR:
328 case TS_VECTOR:
329 case NP_VECTOR:
330 case SS_VECTOR:
331 case GP_VECTOR:
332 return EXCPT_CONTRIBUTORY;
333 default:
334 break;
335 }
336 return EXCPT_BENIGN;
337}
338
d6e8c854
NA		 339#define EXCPT_FAULT 0
340#define EXCPT_TRAP 1
341#define EXCPT_ABORT 2
342#define EXCPT_INTERRUPT 3
343
344static int exception_type(int vector)
345{
346 unsigned int mask;
347
348 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
349 return EXCPT_INTERRUPT;
350
351 mask = 1 << vector;
352
353 /* #DB is trap, as instruction watchpoints are handled elsewhere */
354 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
355 return EXCPT_TRAP;
356
357 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
358 return EXCPT_ABORT;
359
360 /* Reserved exceptions will result in fault */
361 return EXCPT_FAULT;
362}
363
3fd28fce 364static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 365 unsigned nr, bool has_error, u32 error_code,
366 bool reinject)
3fd28fce
ED		 367{
368 u32 prev_nr;
369 int class1, class2;
370
3842d135
AK		 371 kvm_make_request(KVM_REQ_EVENT, vcpu);
372
3fd28fce
ED		 373 if (!vcpu->arch.exception.pending) {
374 queue:
3ffb2468
NA		 375 if (has_error && !is_protmode(vcpu))
376 has_error = false;
3fd28fce
ED		 377 vcpu->arch.exception.pending = true;
378 vcpu->arch.exception.has_error_code = has_error;
379 vcpu->arch.exception.nr = nr;
380 vcpu->arch.exception.error_code = error_code;
3f0fd292 381 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 382 return;
383 }
384
385 /* to check exception */
386 prev_nr = vcpu->arch.exception.nr;
387 if (prev_nr == DF_VECTOR) {
388 /* triple fault -> shutdown */
a8eeb04a 389 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 390 return;
391 }
392 class1 = exception_class(prev_nr);
393 class2 = exception_class(nr);
394 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
395 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
396 /* generate double fault per SDM Table 5-5 */
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = true;
399 vcpu->arch.exception.nr = DF_VECTOR;
400 vcpu->arch.exception.error_code = 0;
401 } else
402 /* replace previous exception with a new one in a hope
403 that instruction re-execution will regenerate lost
404 exception */
405 goto queue;
406}
407
298101da
AK		 408void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
409{
ce7ddec4 410 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 411}
412EXPORT_SYMBOL_GPL(kvm_queue_exception);
413
ce7ddec4
JR		 414void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
415{
416 kvm_multiple_exception(vcpu, nr, false, 0, true);
417}
418EXPORT_SYMBOL_GPL(kvm_requeue_exception);
419
db8fcefa 420void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 421{
db8fcefa
AP		 422 if (err)
423 kvm_inject_gp(vcpu, 0);
424 else
425 kvm_x86_ops->skip_emulated_instruction(vcpu);
426}
427EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 428
6389ee94 429void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 430{
431 ++vcpu->stat.pf_guest;
6389ee94
AK		 432 vcpu->arch.cr2 = fault->address;
433 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 434}
27d6c865 435EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 436
ef54bcfe 437static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 438{
6389ee94
AK		 439 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
440 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 441 else
6389ee94 442 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 443
444 return fault->nested_page_fault;
d4f8cf66
JR		 445}
446
3419ffc8
SY		 447void kvm_inject_nmi(struct kvm_vcpu *vcpu)
448{
7460fb4a
AK		 449 atomic_inc(&vcpu->arch.nmi_queued);
450 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 451}
452EXPORT_SYMBOL_GPL(kvm_inject_nmi);
453
298101da
AK		 454void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
455{
ce7ddec4 456 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 457}
458EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
459
ce7ddec4
JR		 460void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
461{
462 kvm_multiple_exception(vcpu, nr, true, error_code, true);
463}
464EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
465
0a79b009
AK		 466/*
467 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
468 * a #GP and return false.
469 */
470bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 471{
0a79b009
AK		 472 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
473 return true;
474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
475 return false;
298101da 476}
0a79b009 477EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 478
16f8a6f9
NA		 479bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
480{
481 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
482 return true;
483
484 kvm_queue_exception(vcpu, UD_VECTOR);
485 return false;
486}
487EXPORT_SYMBOL_GPL(kvm_require_dr);
488
ec92fe44
JR		 489/*
490 * This function will be used to read from the physical memory of the currently
54bf36aa 491 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 492 * can read from guest physical or from the guest's guest physical memory.
493 */
494int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
495 gfn_t ngfn, void *data, int offset, int len,
496 u32 access)
497{
54987b7a 498 struct x86_exception exception;
ec92fe44
JR		 499 gfn_t real_gfn;
500 gpa_t ngpa;
501
502 ngpa = gfn_to_gpa(ngfn);
54987b7a 503 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 504 if (real_gfn == UNMAPPED_GVA)
505 return -EFAULT;
506
507 real_gfn = gpa_to_gfn(real_gfn);
508
54bf36aa 509 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 510}
511EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
512
69b0049a 513static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 514 void *data, int offset, int len, u32 access)
515{
516 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
517 data, offset, len, access);
518}
519
a03490ed
CO		 520/*
521 * Load the pae pdptrs. Return true is they are all valid.
522 */
ff03a073 523int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 524{
525 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
526 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
527 int i;
528 int ret;
ff03a073 529 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 530
ff03a073
JR		 531 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
532 offset * sizeof(u64), sizeof(pdpte),
533 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 534 if (ret < 0) {
535 ret = 0;
536 goto out;
537 }
538 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 539 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 540 (pdpte[i] &
541 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 542 ret = 0;
543 goto out;
544 }
545 }
546 ret = 1;
547
ff03a073 548 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 549 __set_bit(VCPU_EXREG_PDPTR,
550 (unsigned long *)&vcpu->arch.regs_avail);
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 553out:
a03490ed
CO		 554
555 return ret;
556}
cc4b6871 557EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 558
d835dfec
AK		 559static bool pdptrs_changed(struct kvm_vcpu *vcpu)
560{
ff03a073 561 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 562 bool changed = true;
3d06b8bf
JR		 563 int offset;
564 gfn_t gfn;
d835dfec
AK		 565 int r;
566
567 if (is_long_mode(vcpu) || !is_pae(vcpu))
568 return false;
569
6de4f3ad
AK		 570 if (!test_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail))
572 return true;
573
9f8fe504
AK		 574 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
575 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 576 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
577 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 578 if (r < 0)
579 goto out;
ff03a073 580 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 581out:
d835dfec
AK		 582
583 return changed;
584}
585
49a9b07e 586int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 587{
aad82703 588 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 589 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 590
f9a48e6a
AK		 591 cr0 |= X86_CR0_ET;
592
ab344828 593#ifdef CONFIG_X86_64
0f12244f
GN		 594 if (cr0 & 0xffffffff00000000UL)
595 return 1;
ab344828
GN		 596#endif
597
598 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
601 return 1;
a03490ed 602
0f12244f
GN		 603 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
604 return 1;
a03490ed
CO		 605
606 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
607#ifdef CONFIG_X86_64
f6801dff 608 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 609 int cs_db, cs_l;
610
0f12244f
GN		 611 if (!is_pae(vcpu))
612 return 1;
a03490ed 613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 614 if (cs_l)
615 return 1;
a03490ed
CO		 616 } else
617#endif
ff03a073 618 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 619 kvm_read_cr3(vcpu)))
0f12244f 620 return 1;
a03490ed
CO		 621 }
622
ad756a16
MJ		 623 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
624 return 1;
625
a03490ed 626 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 627
d170c419 628 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 629 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 630 kvm_async_pf_hash_reset(vcpu);
631 }
e5f3f027 632
aad82703
SY		 633 if ((cr0 ^ old_cr0) & update_bits)
634 kvm_mmu_reset_context(vcpu);
b18d5431 635
879ae188
LE		 636 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
637 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
638 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 639 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
640
0f12244f
GN		 641 return 0;
642}
2d3ad1f4 643EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 644
2d3ad1f4 645void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 646{
49a9b07e 647 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 648}
2d3ad1f4 649EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 650
42bdf991
MT		 651static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
652{
653 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
654 !vcpu->guest_xcr0_loaded) {
655 /* kvm_set_xcr() also depends on this */
656 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
657 vcpu->guest_xcr0_loaded = 1;
658 }
659}
660
661static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
662{
663 if (vcpu->guest_xcr0_loaded) {
664 if (vcpu->arch.xcr0 != host_xcr0)
665 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
666 vcpu->guest_xcr0_loaded = 0;
667 }
668}
669
69b0049a 670static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 671{
56c103ec
LJ		 672 u64 xcr0 = xcr;
673 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 674 u64 valid_bits;
2acf923e
DC		 675
676 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
677 if (index != XCR_XFEATURE_ENABLED_MASK)
678 return 1;
d91cab78 679 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 680 return 1;
d91cab78 681 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 682 return 1;
46c34cb0
PB		 683
684 /*
685 * Do not allow the guest to set bits that we do not support
686 * saving. However, xcr0 bit 0 is always set, even if the
687 * emulated CPU does not support XSAVE (see fx_init).
688 */
d91cab78 689 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 690 if (xcr0 & ~valid_bits)
2acf923e 691 return 1;
46c34cb0 692
d91cab78
DH		 693 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
694 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 695 return 1;
696
d91cab78
DH		 697 if (xcr0 & XFEATURE_MASK_AVX512) {
698 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 699 return 1;
d91cab78 700 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 701 return 1;
702 }
2acf923e 703 vcpu->arch.xcr0 = xcr0;
56c103ec 704
d91cab78 705 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 706 kvm_update_cpuid(vcpu);
2acf923e
DC		 707 return 0;
708}
709
710int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
711{
764bcbc5
Z		 712 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
713 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 714 kvm_inject_gp(vcpu, 0);
715 return 1;
716 }
717 return 0;
718}
719EXPORT_SYMBOL_GPL(kvm_set_xcr);
720
a83b29c6 721int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 722{
fc78f519 723 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 724 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 725 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 726
0f12244f
GN		 727 if (cr4 & CR4_RESERVED_BITS)
728 return 1;
a03490ed 729
2acf923e
DC		 730 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
731 return 1;
732
c68b734f
YW		 733 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
734 return 1;
735
97ec8c06
FW		 736 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
737 return 1;
738
afcbf13f 739 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 740 return 1;
741
b9baba86
HH		 742 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
743 return 1;
744
a03490ed 745 if (is_long_mode(vcpu)) {
0f12244f
GN		 746 if (!(cr4 & X86_CR4_PAE))
747 return 1;
a2edf57f
AK		 748 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
749 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 750 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
751 kvm_read_cr3(vcpu)))
0f12244f
GN		 752 return 1;
753
ad756a16
MJ		 754 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
755 if (!guest_cpuid_has_pcid(vcpu))
756 return 1;
757
758 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
759 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
760 return 1;
761 }
762
5e1746d6 763 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 764 return 1;
a03490ed 765
ad756a16
MJ		 766 if (((cr4 ^ old_cr4) & pdptr_bits) ||
767 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 768 kvm_mmu_reset_context(vcpu);
0f12244f 769
b9baba86 770 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 771 kvm_update_cpuid(vcpu);
2acf923e 772
0f12244f
GN		 773 return 0;
774}
2d3ad1f4 775EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 776
2390218b 777int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 778{
ac146235 779#ifdef CONFIG_X86_64
9d88fca7 780 cr3 &= ~CR3_PCID_INVD;
ac146235 781#endif
9d88fca7 782
9f8fe504 783 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 784 kvm_mmu_sync_roots(vcpu);
77c3913b 785 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 786 return 0;
d835dfec
AK		 787 }
788
a03490ed 789 if (is_long_mode(vcpu)) {
d9f89b88
JK		 790 if (cr3 & CR3_L_MODE_RESERVED_BITS)
791 return 1;
792 } else if (is_pae(vcpu) && is_paging(vcpu) &&
793 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 794 return 1;
a03490ed 795
0f12244f 796 vcpu->arch.cr3 = cr3;
aff48baa 797 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 798 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 799 return 0;
800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 802
eea1cff9 803int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 804{
0f12244f
GN		 805 if (cr8 & CR8_RESERVED_BITS)
806 return 1;
35754c98 807 if (lapic_in_kernel(vcpu))
a03490ed
CO		 808 kvm_lapic_set_tpr(vcpu, cr8);
809 else
ad312c7c 810 vcpu->arch.cr8 = cr8;
0f12244f
GN		 811 return 0;
812}
2d3ad1f4 813EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 814
2d3ad1f4 815unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 816{
35754c98 817 if (lapic_in_kernel(vcpu))
a03490ed
CO		 818 return kvm_lapic_get_cr8(vcpu);
819 else
ad312c7c 820 return vcpu->arch.cr8;
a03490ed 821}
2d3ad1f4 822EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 823
ae561ede
NA		 824static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
825{
826 int i;
827
828 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
829 for (i = 0; i < KVM_NR_DB_REGS; i++)
830 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
831 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
832 }
833}
834
73aaf249
JK		 835static void kvm_update_dr6(struct kvm_vcpu *vcpu)
836{
837 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
838 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
839}
840
c8639010
JK		 841static void kvm_update_dr7(struct kvm_vcpu *vcpu)
842{
843 unsigned long dr7;
844
845 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
846 dr7 = vcpu->arch.guest_debug_dr7;
847 else
848 dr7 = vcpu->arch.dr7;
849 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 850 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
851 if (dr7 & DR7_BP_EN_MASK)
852 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 853}
854
6f43ed01
NA		 855static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
856{
857 u64 fixed = DR6_FIXED_1;
858
859 if (!guest_cpuid_has_rtm(vcpu))
860 fixed |= DR6_RTM;
861 return fixed;
862}
863
338dbc97 864static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 865{
866 switch (dr) {
867 case 0 ... 3:
868 vcpu->arch.db[dr] = val;
869 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
870 vcpu->arch.eff_db[dr] = val;
871 break;
872 case 4:
020df079
GN		 873 /* fall through */
874 case 6:
338dbc97
GN		 875 if (val & 0xffffffff00000000ULL)
876 return -1; /* #GP */
6f43ed01 877 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 878 kvm_update_dr6(vcpu);
020df079
GN		 879 break;
880 case 5:
020df079
GN		 881 /* fall through */
882 default: /* 7 */
338dbc97
GN		 883 if (val & 0xffffffff00000000ULL)
884 return -1; /* #GP */
020df079 885 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 886 kvm_update_dr7(vcpu);
020df079
GN		 887 break;
888 }
889
890 return 0;
891}
338dbc97
GN		 892
893int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
894{
16f8a6f9 895 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 896 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 897 return 1;
898 }
899 return 0;
338dbc97 900}
020df079
GN		 901EXPORT_SYMBOL_GPL(kvm_set_dr);
902
16f8a6f9 903int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 904{
905 switch (dr) {
906 case 0 ... 3:
907 *val = vcpu->arch.db[dr];
908 break;
909 case 4:
020df079
GN		 910 /* fall through */
911 case 6:
73aaf249
JK		 912 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
913 *val = vcpu->arch.dr6;
914 else
915 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 916 break;
917 case 5:
020df079
GN		 918 /* fall through */
919 default: /* 7 */
920 *val = vcpu->arch.dr7;
921 break;
922 }
338dbc97
GN		 923 return 0;
924}
020df079
GN		 925EXPORT_SYMBOL_GPL(kvm_get_dr);
926
022cd0e8
AK		 927bool kvm_rdpmc(struct kvm_vcpu *vcpu)
928{
929 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
930 u64 data;
931 int err;
932
c6702c9d 933 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 934 if (err)
935 return err;
936 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
937 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
938 return err;
939}
940EXPORT_SYMBOL_GPL(kvm_rdpmc);
941
043405e1
CO		 942/*
943 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
944 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
945 *
946 * This list is modified at module load time to reflect the
e3267cbb 947 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 948 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
949 * may depend on host virtualization features rather than host cpu features.
043405e1 950 */
e3267cbb 951
043405e1
CO		 952static u32 msrs_to_save[] = {
953 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 954 MSR_STAR,
043405e1
CO		 955#ifdef CONFIG_X86_64
956 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
957#endif
b3897a49 958 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 959 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 960};
961
962static unsigned num_msrs_to_save;
963
62ef68bb
PB		 964static u32 emulated_msrs[] = {
965 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
966 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
967 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
968 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 969 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
970 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 971 HV_X64_MSR_RESET,
11c4b1ca 972 HV_X64_MSR_VP_INDEX,
9eec50b8 973 HV_X64_MSR_VP_RUNTIME,
5c919412 974 HV_X64_MSR_SCONTROL,
1f4b34f8 975 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 976 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
977 MSR_KVM_PV_EOI_EN,
978
ba904635 979 MSR_IA32_TSC_ADJUST,
a3e06bbe 980 MSR_IA32_TSCDEADLINE,
043405e1 981 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 982 MSR_IA32_MCG_STATUS,
983 MSR_IA32_MCG_CTL,
64d60670 984 MSR_IA32_SMBASE,
043405e1
CO		 985};
986
62ef68bb
PB		 987static unsigned num_emulated_msrs;
988
384bb783 989bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 990{
b69e8cae 991 if (efer & efer_reserved_bits)
384bb783 992 return false;
15c4a640 993
1b2fd70c
AG		 994 if (efer & EFER_FFXSR) {
995 struct kvm_cpuid_entry2 *feat;
996
997 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 998 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 999 return false;
1b2fd70c
AG		 1000 }
1001
d8017474
AG		 1002 if (efer & EFER_SVME) {
1003 struct kvm_cpuid_entry2 *feat;
1004
1005 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1006 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1007 return false;
d8017474
AG		 1008 }
1009
384bb783
JK		 1010 return true;
1011}
1012EXPORT_SYMBOL_GPL(kvm_valid_efer);
1013
1014static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1015{
1016 u64 old_efer = vcpu->arch.efer;
1017
1018 if (!kvm_valid_efer(vcpu, efer))
1019 return 1;
1020
1021 if (is_paging(vcpu)
1022 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1023 return 1;
1024
15c4a640 1025 efer &= ~EFER_LMA;
f6801dff 1026 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1027
a3d204e2
SY		 1028 kvm_x86_ops->set_efer(vcpu, efer);
1029
aad82703
SY		 1030 /* Update reserved bits */
1031 if ((efer ^ old_efer) & EFER_NX)
1032 kvm_mmu_reset_context(vcpu);
1033
b69e8cae 1034 return 0;
15c4a640
CO		 1035}
1036
f2b4b7dd
JR		 1037void kvm_enable_efer_bits(u64 mask)
1038{
1039 efer_reserved_bits &= ~mask;
1040}
1041EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1042
15c4a640
CO		 1043/*
1044 * Writes msr value into into the appropriate "register".
1045 * Returns 0 on success, non-0 otherwise.
1046 * Assumes vcpu_load() was already called.
1047 */
8fe8ab46 1048int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1049{
854e8bb1
NA		 1050 switch (msr->index) {
1051 case MSR_FS_BASE:
1052 case MSR_GS_BASE:
1053 case MSR_KERNEL_GS_BASE:
1054 case MSR_CSTAR:
1055 case MSR_LSTAR:
1056 if (is_noncanonical_address(msr->data))
1057 return 1;
1058 break;
1059 case MSR_IA32_SYSENTER_EIP:
1060 case MSR_IA32_SYSENTER_ESP:
1061 /*
1062 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1063 * non-canonical address is written on Intel but not on
1064 * AMD (which ignores the top 32-bits, because it does
1065 * not implement 64-bit SYSENTER).
1066 *
1067 * 64-bit code should hence be able to write a non-canonical
1068 * value on AMD. Making the address canonical ensures that
1069 * vmentry does not fail on Intel after writing a non-canonical
1070 * value, and that something deterministic happens if the guest
1071 * invokes 64-bit SYSENTER.
1072 */
1073 msr->data = get_canonical(msr->data);
1074 }
8fe8ab46 1075 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1076}
854e8bb1 1077EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1078
313a3dc7
CO		 1079/*
1080 * Adapt set_msr() to msr_io()'s calling convention
1081 */
609e36d3
PB		 1082static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1083{
1084 struct msr_data msr;
1085 int r;
1086
1087 msr.index = index;
1088 msr.host_initiated = true;
1089 r = kvm_get_msr(vcpu, &msr);
1090 if (r)
1091 return r;
1092
1093 *data = msr.data;
1094 return 0;
1095}
1096
313a3dc7
CO		 1097static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1098{
8fe8ab46
WA		 1099 struct msr_data msr;
1100
1101 msr.data = *data;
1102 msr.index = index;
1103 msr.host_initiated = true;
1104 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1105}
1106
16e8d74d
MT		 1107#ifdef CONFIG_X86_64
1108struct pvclock_gtod_data {
1109 seqcount_t seq;
1110
1111 struct { /* extract of a clocksource struct */
1112 int vclock_mode;
1113 cycle_t cycle_last;
1114 cycle_t mask;
1115 u32 mult;
1116 u32 shift;
1117 } clock;
1118
cbcf2dd3
TG		 1119 u64 boot_ns;
1120 u64 nsec_base;
16e8d74d
MT		 1121};
1122
1123static struct pvclock_gtod_data pvclock_gtod_data;
1124
1125static void update_pvclock_gtod(struct timekeeper *tk)
1126{
1127 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1128 u64 boot_ns;
1129
876e7881 1130 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1131
1132 write_seqcount_begin(&vdata->seq);
1133
1134 /* copy pvclock gtod data */
876e7881
PZ		 1135 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1136 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1137 vdata->clock.mask = tk->tkr_mono.mask;
1138 vdata->clock.mult = tk->tkr_mono.mult;
1139 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1140
cbcf2dd3 1141 vdata->boot_ns = boot_ns;
876e7881 1142 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1143
1144 write_seqcount_end(&vdata->seq);
1145}
1146#endif
1147
bab5bb39
NK		 1148void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1149{
1150 /*
1151 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1152 * vcpu_enter_guest. This function is only called from
1153 * the physical CPU that is running vcpu.
1154 */
1155 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1156}
16e8d74d 1157
18068523
GOC		 1158static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1159{
9ed3c444
AK		 1160 int version;
1161 int r;
50d0a0f9 1162 struct pvclock_wall_clock wc;
923de3cf 1163 struct timespec boot;
18068523
GOC		 1164
1165 if (!wall_clock)
1166 return;
1167
9ed3c444
AK		 1168 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1169 if (r)
1170 return;
1171
1172 if (version & 1)
1173 ++version; /* first time write, random junk */
1174
1175 ++version;
18068523 1176
1dab1345
NK		 1177 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1178 return;
18068523 1179
50d0a0f9
GH		 1180 /*
1181 * The guest calculates current wall clock time by adding
34c238a1 1182 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1183 * wall clock specified here. guest system time equals host
1184 * system time for us, thus we must fill in host boot time here.
1185 */
923de3cf 1186 getboottime(&boot);
50d0a0f9 1187
4b648665
BR		 1188 if (kvm->arch.kvmclock_offset) {
1189 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1190 boot = timespec_sub(boot, ts);
1191 }
50d0a0f9
GH		 1192 wc.sec = boot.tv_sec;
1193 wc.nsec = boot.tv_nsec;
1194 wc.version = version;
18068523
GOC		 1195
1196 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1197
1198 version++;
1199 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1200}
1201
50d0a0f9
GH		 1202static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1203{
b51012de
PB		 1204 do_shl32_div32(dividend, divisor);
1205 return dividend;
50d0a0f9
GH		 1206}
1207
3ae13faa 1208static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1209 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1210{
5f4e3f88 1211 uint64_t scaled64;
50d0a0f9
GH		 1212 int32_t shift = 0;
1213 uint64_t tps64;
1214 uint32_t tps32;
1215
3ae13faa
PB		 1216 tps64 = base_hz;
1217 scaled64 = scaled_hz;
50933623 1218 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1219 tps64 >>= 1;
1220 shift--;
1221 }
1222
1223 tps32 = (uint32_t)tps64;
50933623
JK		 1224 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1225 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1226 scaled64 >>= 1;
1227 else
1228 tps32 <<= 1;
50d0a0f9
GH		 1229 shift++;
1230 }
1231
5f4e3f88
ZA		 1232 *pshift = shift;
1233 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1234
3ae13faa
PB		 1235 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1236 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1237}
1238
d828199e 1239#ifdef CONFIG_X86_64
16e8d74d 1240static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1241#endif
16e8d74d 1242
c8076604 1243static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1244static unsigned long max_tsc_khz;
c8076604 1245
cc578287 1246static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1247{
cc578287
ZA		 1248 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1249 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1250}
1251
cc578287 1252static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1253{
cc578287
ZA		 1254 u64 v = (u64)khz * (1000000 + ppm);
1255 do_div(v, 1000000);
1256 return v;
1e993611
JR		 1257}
1258
381d585c
HZ		 1259static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1260{
1261 u64 ratio;
1262
1263 /* Guest TSC same frequency as host TSC? */
1264 if (!scale) {
1265 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1266 return 0;
1267 }
1268
1269 /* TSC scaling supported? */
1270 if (!kvm_has_tsc_control) {
1271 if (user_tsc_khz > tsc_khz) {
1272 vcpu->arch.tsc_catchup = 1;
1273 vcpu->arch.tsc_always_catchup = 1;
1274 return 0;
1275 } else {
1276 WARN(1, "user requested TSC rate below hardware speed\n");
1277 return -1;
1278 }
1279 }
1280
1281 /* TSC scaling required - calculate ratio */
1282 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1283 user_tsc_khz, tsc_khz);
1284
1285 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1286 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1287 user_tsc_khz);
1288 return -1;
1289 }
1290
1291 vcpu->arch.tsc_scaling_ratio = ratio;
1292 return 0;
1293}
1294
4941b8cb 1295static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1296{
cc578287
ZA		 1297 u32 thresh_lo, thresh_hi;
1298 int use_scaling = 0;
217fc9cf 1299
03ba32ca 1300 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1301 if (user_tsc_khz == 0) {
ad721883
HZ		 1302 /* set tsc_scaling_ratio to a safe value */
1303 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1304 return -1;
ad721883 1305 }
03ba32ca 1306
c285545f 1307 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1308 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1309 &vcpu->arch.virtual_tsc_shift,
1310 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1311 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1312
1313 /*
1314 * Compute the variation in TSC rate which is acceptable
1315 * within the range of tolerance and decide if the
1316 * rate being applied is within that bounds of the hardware
1317 * rate. If so, no scaling or compensation need be done.
1318 */
1319 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1320 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1321 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1322 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1323 use_scaling = 1;
1324 }
4941b8cb 1325 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1326}
1327
1328static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1329{
e26101b1 1330 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1331 vcpu->arch.virtual_tsc_mult,
1332 vcpu->arch.virtual_tsc_shift);
e26101b1 1333 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1334 return tsc;
1335}
1336
69b0049a 1337static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1338{
1339#ifdef CONFIG_X86_64
1340 bool vcpus_matched;
b48aa97e
MT		 1341 struct kvm_arch *ka = &vcpu->kvm->arch;
1342 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1343
1344 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1345 atomic_read(&vcpu->kvm->online_vcpus));
1346
7f187922
MT		 1347 /*
1348 * Once the masterclock is enabled, always perform request in
1349 * order to update it.
1350 *
1351 * In order to enable masterclock, the host clocksource must be TSC
1352 * and the vcpus need to have matched TSCs. When that happens,
1353 * perform request to enable masterclock.
1354 */
1355 if (ka->use_master_clock ||
1356 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1357 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1358
1359 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1360 atomic_read(&vcpu->kvm->online_vcpus),
1361 ka->use_master_clock, gtod->clock.vclock_mode);
1362#endif
1363}
1364
ba904635
WA		 1365static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1366{
1367 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1368 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1369}
1370
35181e86
HZ		 1371/*
1372 * Multiply tsc by a fixed point number represented by ratio.
1373 *
1374 * The most significant 64-N bits (mult) of ratio represent the
1375 * integral part of the fixed point number; the remaining N bits
1376 * (frac) represent the fractional part, ie. ratio represents a fixed
1377 * point number (mult + frac * 2^(-N)).
1378 *
1379 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1380 */
1381static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1382{
1383 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1384}
1385
1386u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1387{
1388 u64 _tsc = tsc;
1389 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1390
1391 if (ratio != kvm_default_tsc_scaling_ratio)
1392 _tsc = __scale_tsc(ratio, tsc);
1393
1394 return _tsc;
1395}
1396EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1397
07c1419a
HZ		 1398static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1399{
1400 u64 tsc;
1401
1402 tsc = kvm_scale_tsc(vcpu, rdtsc());
1403
1404 return target_tsc - tsc;
1405}
1406
4ba76538
HZ		 1407u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1408{
1409 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1410}
1411EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1412
8fe8ab46 1413void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1414{
1415 struct kvm *kvm = vcpu->kvm;
f38e098f 1416 u64 offset, ns, elapsed;
99e3e30a 1417 unsigned long flags;
02626b6a 1418 s64 usdiff;
b48aa97e 1419 bool matched;
0d3da0d2 1420 bool already_matched;
8fe8ab46 1421 u64 data = msr->data;
99e3e30a 1422
038f8c11 1423 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1424 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1425 ns = get_kernel_ns();
f38e098f 1426 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1427
03ba32ca 1428 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1429 int faulted = 0;
1430
03ba32ca
MT		 1431 /* n.b - signed multiplication and division required */
1432 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1433#ifdef CONFIG_X86_64
03ba32ca 1434 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1435#else
03ba32ca 1436 /* do_div() only does unsigned */
8915aa27
MT		 1437 asm("1: idivl %[divisor]\n"
1438 "2: xor %%edx, %%edx\n"
1439 " movl $0, %[faulted]\n"
1440 "3:\n"
1441 ".section .fixup,\"ax\"\n"
1442 "4: movl $1, %[faulted]\n"
1443 " jmp 3b\n"
1444 ".previous\n"
1445
1446 _ASM_EXTABLE(1b, 4b)
1447
1448 : "=A"(usdiff), [faulted] "=r" (faulted)
1449 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1450
5d3cb0f6 1451#endif
03ba32ca
MT		 1452 do_div(elapsed, 1000);
1453 usdiff -= elapsed;
1454 if (usdiff < 0)
1455 usdiff = -usdiff;
8915aa27
MT		 1456
1457 /* idivl overflow => difference is larger than USEC_PER_SEC */
1458 if (faulted)
1459 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1460 } else
1461 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1462
1463 /*
5d3cb0f6
ZA		 1464 * Special case: TSC write with a small delta (1 second) of virtual
1465 * cycle time against real time is interpreted as an attempt to
1466 * synchronize the CPU.
1467 *
1468 * For a reliable TSC, we can match TSC offsets, and for an unstable
1469 * TSC, we add elapsed time in this computation. We could let the
1470 * compensation code attempt to catch up if we fall behind, but
1471 * it's better to try to match offsets from the beginning.
1472 */
02626b6a 1473 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1474 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1475 if (!check_tsc_unstable()) {
e26101b1 1476 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1477 pr_debug("kvm: matched tsc offset for %llu\n", data);
1478 } else {
857e4099 1479 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1480 data += delta;
07c1419a 1481 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1482 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1483 }
b48aa97e 1484 matched = true;
0d3da0d2 1485 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1486 } else {
1487 /*
1488 * We split periods of matched TSC writes into generations.
1489 * For each generation, we track the original measured
1490 * nanosecond time, offset, and write, so if TSCs are in
1491 * sync, we can match exact offset, and if not, we can match
4a969980 1492 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1493 *
1494 * These values are tracked in kvm->arch.cur_xxx variables.
1495 */
1496 kvm->arch.cur_tsc_generation++;
1497 kvm->arch.cur_tsc_nsec = ns;
1498 kvm->arch.cur_tsc_write = data;
1499 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1500 matched = false;
0d3da0d2 1501 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1502 kvm->arch.cur_tsc_generation, data);
f38e098f 1503 }
e26101b1
ZA		 1504
1505 /*
1506 * We also track th most recent recorded KHZ, write and time to
1507 * allow the matching interval to be extended at each write.
1508 */
f38e098f
ZA		 1509 kvm->arch.last_tsc_nsec = ns;
1510 kvm->arch.last_tsc_write = data;
5d3cb0f6 1511 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1512
b183aa58 1513 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1514
1515 /* Keep track of which generation this VCPU has synchronized to */
1516 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1517 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1518 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1519
ba904635
WA		 1520 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1521 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1522 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1523 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1524
1525 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1526 if (!matched) {
b48aa97e 1527 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1528 } else if (!already_matched) {
1529 kvm->arch.nr_vcpus_matched_tsc++;
1530 }
b48aa97e
MT		 1531
1532 kvm_track_tsc_matching(vcpu);
1533 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1534}
e26101b1 1535
99e3e30a
ZA		 1536EXPORT_SYMBOL_GPL(kvm_write_tsc);
1537
58ea6767
HZ		 1538static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1539 s64 adjustment)
1540{
1541 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1542}
1543
1544static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1545{
1546 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1547 WARN_ON(adjustment < 0);
1548 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1549 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1550}
1551
d828199e
MT		 1552#ifdef CONFIG_X86_64
1553
1554static cycle_t read_tsc(void)
1555{
03b9730b
AL		 1556 cycle_t ret = (cycle_t)rdtsc_ordered();
1557 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1558
1559 if (likely(ret >= last))
1560 return ret;
1561
1562 /*
1563 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1564 * predictable (it's just a function of time and the likely is
d828199e
MT		 1565 * very likely) and there's a data dependence, so force GCC
1566 * to generate a branch instead. I don't barrier() because
1567 * we don't actually need a barrier, and if this function
1568 * ever gets inlined it will generate worse code.
1569 */
1570 asm volatile ("");
1571 return last;
1572}
1573
1574static inline u64 vgettsc(cycle_t *cycle_now)
1575{
1576 long v;
1577 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1578
1579 *cycle_now = read_tsc();
1580
1581 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1582 return v * gtod->clock.mult;
1583}
1584
cbcf2dd3 1585static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1586{
cbcf2dd3 1587 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1588 unsigned long seq;
d828199e 1589 int mode;
cbcf2dd3 1590 u64 ns;
d828199e 1591
d828199e
MT		 1592 do {
1593 seq = read_seqcount_begin(&gtod->seq);
1594 mode = gtod->clock.vclock_mode;
cbcf2dd3 1595 ns = gtod->nsec_base;
d828199e
MT		 1596 ns += vgettsc(cycle_now);
1597 ns >>= gtod->clock.shift;
cbcf2dd3 1598 ns += gtod->boot_ns;
d828199e 1599 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1600 *t = ns;
d828199e
MT		 1601
1602 return mode;
1603}
1604
1605/* returns true if host is using tsc clocksource */
1606static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1607{
d828199e
MT		 1608 /* checked again under seqlock below */
1609 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1610 return false;
1611
cbcf2dd3 1612 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1613}
1614#endif
1615
1616/*
1617 *
b48aa97e
MT		 1618 * Assuming a stable TSC across physical CPUS, and a stable TSC
1619 * across virtual CPUs, the following condition is possible.
1620 * Each numbered line represents an event visible to both
d828199e
MT		 1621 * CPUs at the next numbered event.
1622 *
1623 * "timespecX" represents host monotonic time. "tscX" represents
1624 * RDTSC value.
1625 *
1626 * VCPU0 on CPU0 | VCPU1 on CPU1
1627 *
1628 * 1. read timespec0,tsc0
1629 * 2. | timespec1 = timespec0 + N
1630 * | tsc1 = tsc0 + M
1631 * 3. transition to guest | transition to guest
1632 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1633 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1634 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1635 *
1636 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1637 *
1638 * - ret0 < ret1
1639 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1640 * ...
1641 * - 0 < N - M => M < N
1642 *
1643 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1644 * always the case (the difference between two distinct xtime instances
1645 * might be smaller then the difference between corresponding TSC reads,
1646 * when updating guest vcpus pvclock areas).
1647 *
1648 * To avoid that problem, do not allow visibility of distinct
1649 * system_timestamp/tsc_timestamp values simultaneously: use a master
1650 * copy of host monotonic time values. Update that master copy
1651 * in lockstep.
1652 *
b48aa97e 1653 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1654 *
1655 */
1656
1657static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1658{
1659#ifdef CONFIG_X86_64
1660 struct kvm_arch *ka = &kvm->arch;
1661 int vclock_mode;
b48aa97e
MT		 1662 bool host_tsc_clocksource, vcpus_matched;
1663
1664 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1665 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1666
1667 /*
1668 * If the host uses TSC clock, then passthrough TSC as stable
1669 * to the guest.
1670 */
b48aa97e 1671 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1672 &ka->master_kernel_ns,
1673 &ka->master_cycle_now);
1674
16a96021 1675 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1676 && !backwards_tsc_observed
1677 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1678
d828199e
MT		 1679 if (ka->use_master_clock)
1680 atomic_set(&kvm_guest_has_master_clock, 1);
1681
1682 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1683 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1684 vcpus_matched);
d828199e
MT		 1685#endif
1686}
1687
2860c4b1
PB		 1688void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1689{
1690 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1691}
1692
2e762ff7
MT		 1693static void kvm_gen_update_masterclock(struct kvm *kvm)
1694{
1695#ifdef CONFIG_X86_64
1696 int i;
1697 struct kvm_vcpu *vcpu;
1698 struct kvm_arch *ka = &kvm->arch;
1699
1700 spin_lock(&ka->pvclock_gtod_sync_lock);
1701 kvm_make_mclock_inprogress_request(kvm);
1702 /* no guest entries from this point */
1703 pvclock_update_vm_gtod_copy(kvm);
1704
1705 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1706 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1707
1708 /* guest entries allowed */
1709 kvm_for_each_vcpu(i, vcpu, kvm)
1710 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1711
1712 spin_unlock(&ka->pvclock_gtod_sync_lock);
1713#endif
1714}
1715
34c238a1 1716static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1717{
78db6a50 1718 unsigned long flags, tgt_tsc_khz;
18068523 1719 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1720 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1721 s64 kernel_ns;
d828199e 1722 u64 tsc_timestamp, host_tsc;
0b79459b 1723 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1724 u8 pvclock_flags;
d828199e
MT		 1725 bool use_master_clock;
1726
1727 kernel_ns = 0;
1728 host_tsc = 0;
18068523 1729
d828199e
MT		 1730 /*
1731 * If the host uses TSC clock, then passthrough TSC as stable
1732 * to the guest.
1733 */
1734 spin_lock(&ka->pvclock_gtod_sync_lock);
1735 use_master_clock = ka->use_master_clock;
1736 if (use_master_clock) {
1737 host_tsc = ka->master_cycle_now;
1738 kernel_ns = ka->master_kernel_ns;
1739 }
1740 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1741
1742 /* Keep irq disabled to prevent changes to the clock */
1743 local_irq_save(flags);
78db6a50
PB		 1744 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1745 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1746 local_irq_restore(flags);
1747 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1748 return 1;
1749 }
d828199e 1750 if (!use_master_clock) {
4ea1636b 1751 host_tsc = rdtsc();
d828199e
MT		 1752 kernel_ns = get_kernel_ns();
1753 }
1754
4ba76538 1755 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1756
c285545f
ZA		 1757 /*
1758 * We may have to catch up the TSC to match elapsed wall clock
1759 * time for two reasons, even if kvmclock is used.
1760 * 1) CPU could have been running below the maximum TSC rate
1761 * 2) Broken TSC compensation resets the base at each VCPU
1762 * entry to avoid unknown leaps of TSC even when running
1763 * again on the same CPU. This may cause apparent elapsed
1764 * time to disappear, and the guest to stand still or run
1765 * very slowly.
1766 */
1767 if (vcpu->tsc_catchup) {
1768 u64 tsc = compute_guest_tsc(v, kernel_ns);
1769 if (tsc > tsc_timestamp) {
f1e2b260 1770 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1771 tsc_timestamp = tsc;
1772 }
50d0a0f9
GH		 1773 }
1774
18068523
GOC		 1775 local_irq_restore(flags);
1776
0b79459b 1777 if (!vcpu->pv_time_enabled)
c285545f 1778 return 0;
18068523 1779
78db6a50
PB		 1780 if (kvm_has_tsc_control)
1781 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1782
1783 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1784 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1785 &vcpu->hv_clock.tsc_shift,
1786 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1787 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1788 }
1789
1790 /* With all the info we got, fill in the values */
1d5f066e 1791 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1792 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1793 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1794
09a0c3f1
OH		 1795 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1796 &guest_hv_clock, sizeof(guest_hv_clock))))
1797 return 0;
1798
5dca0d91
RK		 1799 /* This VCPU is paused, but it's legal for a guest to read another
1800 * VCPU's kvmclock, so we really have to follow the specification where
1801 * it says that version is odd if data is being modified, and even after
1802 * it is consistent.
1803 *
1804 * Version field updates must be kept separate. This is because
1805 * kvm_write_guest_cached might use a "rep movs" instruction, and
1806 * writes within a string instruction are weakly ordered. So there
1807 * are three writes overall.
1808 *
1809 * As a small optimization, only write the version field in the first
1810 * and third write. The vcpu->pv_time cache is still valid, because the
1811 * version field is the first in the struct.
18068523 1812 */
5dca0d91
RK		 1813 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1814
1815 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1816 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1817 &vcpu->hv_clock,
1818 sizeof(vcpu->hv_clock.version));
1819
1820 smp_wmb();
78c0337a
MT		 1821
1822 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1823 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1824
1825 if (vcpu->pvclock_set_guest_stopped_request) {
1826 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1827 vcpu->pvclock_set_guest_stopped_request = false;
1828 }
1829
d828199e
MT		 1830 /* If the host uses TSC clocksource, then it is stable */
1831 if (use_master_clock)
1832 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1833
78c0337a
MT		 1834 vcpu->hv_clock.flags = pvclock_flags;
1835
ce1a5e60
DM		 1836 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1837
0b79459b
AH		 1838 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1839 &vcpu->hv_clock,
1840 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1841
1842 smp_wmb();
1843
1844 vcpu->hv_clock.version++;
1845 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1846 &vcpu->hv_clock,
1847 sizeof(vcpu->hv_clock.version));
8cfdc000 1848 return 0;
c8076604
GH		 1849}
1850
0061d53d
MT		 1851/*
1852 * kvmclock updates which are isolated to a given vcpu, such as
1853 * vcpu->cpu migration, should not allow system_timestamp from
1854 * the rest of the vcpus to remain static. Otherwise ntp frequency
1855 * correction applies to one vcpu's system_timestamp but not
1856 * the others.
1857 *
1858 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1859 * We need to rate-limit these requests though, as they can
1860 * considerably slow guests that have a large number of vcpus.
1861 * The time for a remote vcpu to update its kvmclock is bound
1862 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1863 */
1864
7e44e449
AJ		 1865#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1866
1867static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1868{
1869 int i;
7e44e449
AJ		 1870 struct delayed_work *dwork = to_delayed_work(work);
1871 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1872 kvmclock_update_work);
1873 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1874 struct kvm_vcpu *vcpu;
1875
1876 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1878 kvm_vcpu_kick(vcpu);
1879 }
1880}
1881
7e44e449
AJ		 1882static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1883{
1884 struct kvm *kvm = v->kvm;
1885
105b21bb 1886 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1887 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1888 KVMCLOCK_UPDATE_DELAY);
1889}
1890
332967a3
AJ		 1891#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1892
1893static void kvmclock_sync_fn(struct work_struct *work)
1894{
1895 struct delayed_work *dwork = to_delayed_work(work);
1896 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1897 kvmclock_sync_work);
1898 struct kvm *kvm = container_of(ka, struct kvm, arch);
1899
630994b3
MT		 1900 if (!kvmclock_periodic_sync)
1901 return;
1902
332967a3
AJ		 1903 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1904 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1905 KVMCLOCK_SYNC_PERIOD);
1906}
1907
890ca9ae 1908static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1909{
890ca9ae
HY		 1910 u64 mcg_cap = vcpu->arch.mcg_cap;
1911 unsigned bank_num = mcg_cap & 0xff;
1912
15c4a640 1913 switch (msr) {
15c4a640 1914 case MSR_IA32_MCG_STATUS:
890ca9ae 1915 vcpu->arch.mcg_status = data;
15c4a640 1916 break;
c7ac679c 1917 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1918 if (!(mcg_cap & MCG_CTL_P))
1919 return 1;
1920 if (data != 0 && data != ~(u64)0)
1921 return -1;
1922 vcpu->arch.mcg_ctl = data;
1923 break;
1924 default:
1925 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1926 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1927 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1928 /* only 0 or all 1s can be written to IA32_MCi_CTL
1929 * some Linux kernels though clear bit 10 in bank 4 to
1930 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1931 * this to avoid an uncatched #GP in the guest
1932 */
890ca9ae 1933 if ((offset & 0x3) == 0 &&
114be429 1934 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1935 return -1;
1936 vcpu->arch.mce_banks[offset] = data;
1937 break;
1938 }
1939 return 1;
1940 }
1941 return 0;
1942}
1943
ffde22ac
ES		 1944static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1945{
1946 struct kvm *kvm = vcpu->kvm;
1947 int lm = is_long_mode(vcpu);
1948 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1949 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1950 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1951 : kvm->arch.xen_hvm_config.blob_size_32;
1952 u32 page_num = data & ~PAGE_MASK;
1953 u64 page_addr = data & PAGE_MASK;
1954 u8 *page;
1955 int r;
1956
1957 r = -E2BIG;
1958 if (page_num >= blob_size)
1959 goto out;
1960 r = -ENOMEM;
ff5c2c03
SL		 1961 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1962 if (IS_ERR(page)) {
1963 r = PTR_ERR(page);
ffde22ac 1964 goto out;
ff5c2c03 1965 }
54bf36aa 1966 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1967 goto out_free;
1968 r = 0;
1969out_free:
1970 kfree(page);
1971out:
1972 return r;
1973}
1974
344d9588
GN		 1975static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1976{
1977 gpa_t gpa = data & ~0x3f;
1978
4a969980 1979 /* Bits 2:5 are reserved, Should be zero */
6adba527 1980 if (data & 0x3c)
344d9588
GN		 1981 return 1;
1982
1983 vcpu->arch.apf.msr_val = data;
1984
1985 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1986 kvm_clear_async_pf_completion_queue(vcpu);
1987 kvm_async_pf_hash_reset(vcpu);
1988 return 0;
1989 }
1990
8f964525
AH		 1991 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1992 sizeof(u32)))
344d9588
GN		 1993 return 1;
1994
6adba527 1995 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1996 kvm_async_pf_wakeup_all(vcpu);
1997 return 0;
1998}
1999
12f9a48f
GC		 2000static void kvmclock_reset(struct kvm_vcpu *vcpu)
2001{
0b79459b 2002 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2003}
2004
c9aaa895
GC		 2005static void record_steal_time(struct kvm_vcpu *vcpu)
2006{
2007 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2008 return;
2009
2010 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2011 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2012 return;
2013
c54cdf14
LC		 2014 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2015 vcpu->arch.st.last_steal;
2016 vcpu->arch.st.last_steal = current->sched_info.run_delay;
c9aaa895 2017 vcpu->arch.st.steal.version += 2;
c9aaa895
GC		 2018
2019 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2020 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2021}
2022
8fe8ab46 2023int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2024{
5753785f 2025 bool pr = false;
8fe8ab46
WA		 2026 u32 msr = msr_info->index;
2027 u64 data = msr_info->data;
5753785f 2028
15c4a640 2029 switch (msr) {
2e32b719
BP		 2030 case MSR_AMD64_NB_CFG:
2031 case MSR_IA32_UCODE_REV:
2032 case MSR_IA32_UCODE_WRITE:
2033 case MSR_VM_HSAVE_PA:
2034 case MSR_AMD64_PATCH_LOADER:
2035 case MSR_AMD64_BU_CFG2:
2036 break;
2037
15c4a640 2038 case MSR_EFER:
b69e8cae 2039 return set_efer(vcpu, data);
8f1589d9
AP		 2040 case MSR_K7_HWCR:
2041 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2042 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2043 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2044 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2045 if (data != 0) {
a737f256
CD		 2046 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2047 data);
8f1589d9
AP		 2048 return 1;
2049 }
15c4a640 2050 break;
f7c6d140
AP		 2051 case MSR_FAM10H_MMIO_CONF_BASE:
2052 if (data != 0) {
a737f256
CD		 2053 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2054 "0x%llx\n", data);
f7c6d140
AP		 2055 return 1;
2056 }
15c4a640 2057 break;
b5e2fec0
AG		 2058 case MSR_IA32_DEBUGCTLMSR:
2059 if (!data) {
2060 /* We support the non-activated case already */
2061 break;
2062 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2063 /* Values other than LBR and BTF are vendor-specific,
2064 thus reserved and should throw a #GP */
2065 return 1;
2066 }
a737f256
CD		 2067 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2068 __func__, data);
b5e2fec0 2069 break;
9ba075a6 2070 case 0x200 ... 0x2ff:
ff53604b 2071 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2072 case MSR_IA32_APICBASE:
58cb628d 2073 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2074 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2075 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2076 case MSR_IA32_TSCDEADLINE:
2077 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2078 break;
ba904635
WA		 2079 case MSR_IA32_TSC_ADJUST:
2080 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2081 if (!msr_info->host_initiated) {
d913b904 2082 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2083 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2084 }
2085 vcpu->arch.ia32_tsc_adjust_msr = data;
2086 }
2087 break;
15c4a640 2088 case MSR_IA32_MISC_ENABLE:
ad312c7c 2089 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2090 break;
64d60670
PB		 2091 case MSR_IA32_SMBASE:
2092 if (!msr_info->host_initiated)
2093 return 1;
2094 vcpu->arch.smbase = data;
2095 break;
11c6bffa 2096 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2097 case MSR_KVM_WALL_CLOCK:
2098 vcpu->kvm->arch.wall_clock = data;
2099 kvm_write_wall_clock(vcpu->kvm, data);
2100 break;
11c6bffa 2101 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2102 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2103 u64 gpa_offset;
54750f2c
MT		 2104 struct kvm_arch *ka = &vcpu->kvm->arch;
2105
12f9a48f 2106 kvmclock_reset(vcpu);
18068523 2107
54750f2c
MT		 2108 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2109 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2110
2111 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2112 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2113 &vcpu->requests);
2114
2115 ka->boot_vcpu_runs_old_kvmclock = tmp;
2116 }
2117
18068523 2118 vcpu->arch.time = data;
0061d53d 2119 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2120
2121 /* we verify if the enable bit is set... */
2122 if (!(data & 1))
2123 break;
2124
0b79459b 2125 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2126
0b79459b 2127 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2128 &vcpu->arch.pv_time, data & ~1ULL,
2129 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2130 vcpu->arch.pv_time_enabled = false;
2131 else
2132 vcpu->arch.pv_time_enabled = true;
32cad84f 2133
18068523
GOC		 2134 break;
2135 }
344d9588
GN		 2136 case MSR_KVM_ASYNC_PF_EN:
2137 if (kvm_pv_enable_async_pf(vcpu, data))
2138 return 1;
2139 break;
c9aaa895
GC		 2140 case MSR_KVM_STEAL_TIME:
2141
2142 if (unlikely(!sched_info_on()))
2143 return 1;
2144
2145 if (data & KVM_STEAL_RESERVED_MASK)
2146 return 1;
2147
2148 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2149 data & KVM_STEAL_VALID_BITS,
2150 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2151 return 1;
2152
2153 vcpu->arch.st.msr_val = data;
2154
2155 if (!(data & KVM_MSR_ENABLED))
2156 break;
2157
c9aaa895
GC		 2158 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2159
2160 break;
ae7a2a3f
MT		 2161 case MSR_KVM_PV_EOI_EN:
2162 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2163 return 1;
2164 break;
c9aaa895 2165
890ca9ae
HY		 2166 case MSR_IA32_MCG_CTL:
2167 case MSR_IA32_MCG_STATUS:
81760dcc 2168 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2169 return set_msr_mce(vcpu, msr, data);
71db6023 2170
6912ac32
WH		 2171 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2172 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2173 pr = true; /* fall through */
2174 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2175 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2176 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2177 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2178
2179 if (pr || data != 0)
a737f256
CD		 2180 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2181 "0x%x data 0x%llx\n", msr, data);
5753785f 2182 break;
84e0cefa
JS		 2183 case MSR_K7_CLK_CTL:
2184 /*
2185 * Ignore all writes to this no longer documented MSR.
2186 * Writes are only relevant for old K7 processors,
2187 * all pre-dating SVM, but a recommended workaround from
4a969980 2188 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2189 * affected processor models on the command line, hence
2190 * the need to ignore the workaround.
2191 */
2192 break;
55cd8e5a 2193 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2194 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2195 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2196 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2197 return kvm_hv_set_msr_common(vcpu, msr, data,
2198 msr_info->host_initiated);
91c9c3ed 2199 case MSR_IA32_BBL_CR_CTL3:
2200 /* Drop writes to this legacy MSR -- see rdmsr
2201 * counterpart for further detail.
2202 */
a737f256 2203 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2204 break;
2b036c6b
BO		 2205 case MSR_AMD64_OSVW_ID_LENGTH:
2206 if (!guest_cpuid_has_osvw(vcpu))
2207 return 1;
2208 vcpu->arch.osvw.length = data;
2209 break;
2210 case MSR_AMD64_OSVW_STATUS:
2211 if (!guest_cpuid_has_osvw(vcpu))
2212 return 1;
2213 vcpu->arch.osvw.status = data;
2214 break;
15c4a640 2215 default:
ffde22ac
ES		 2216 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2217 return xen_hvm_config(vcpu, data);
c6702c9d 2218 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2219 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2220 if (!ignore_msrs) {
a737f256
CD		 2221 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2222 msr, data);
ed85c068
AP		 2223 return 1;
2224 } else {
a737f256
CD		 2225 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2226 msr, data);
ed85c068
AP		 2227 break;
2228 }
15c4a640
CO		 2229 }
2230 return 0;
2231}
2232EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2233
2234
2235/*
2236 * Reads an msr value (of 'msr_index') into 'pdata'.
2237 * Returns 0 on success, non-0 otherwise.
2238 * Assumes vcpu_load() was already called.
2239 */
609e36d3 2240int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2241{
609e36d3 2242 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2243}
ff651cb6 2244EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2245
890ca9ae 2246static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2247{
2248 u64 data;
890ca9ae
HY		 2249 u64 mcg_cap = vcpu->arch.mcg_cap;
2250 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2251
2252 switch (msr) {
15c4a640
CO		 2253 case MSR_IA32_P5_MC_ADDR:
2254 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2255 data = 0;
2256 break;
15c4a640 2257 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2258 data = vcpu->arch.mcg_cap;
2259 break;
c7ac679c 2260 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2261 if (!(mcg_cap & MCG_CTL_P))
2262 return 1;
2263 data = vcpu->arch.mcg_ctl;
2264 break;
2265 case MSR_IA32_MCG_STATUS:
2266 data = vcpu->arch.mcg_status;
2267 break;
2268 default:
2269 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2270 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2271 u32 offset = msr - MSR_IA32_MC0_CTL;
2272 data = vcpu->arch.mce_banks[offset];
2273 break;
2274 }
2275 return 1;
2276 }
2277 *pdata = data;
2278 return 0;
2279}
2280
609e36d3 2281int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2282{
609e36d3 2283 switch (msr_info->index) {
890ca9ae 2284 case MSR_IA32_PLATFORM_ID:
15c4a640 2285 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2286 case MSR_IA32_DEBUGCTLMSR:
2287 case MSR_IA32_LASTBRANCHFROMIP:
2288 case MSR_IA32_LASTBRANCHTOIP:
2289 case MSR_IA32_LASTINTFROMIP:
2290 case MSR_IA32_LASTINTTOIP:
60af2ecd 2291 case MSR_K8_SYSCFG:
3afb1121
PB		 2292 case MSR_K8_TSEG_ADDR:
2293 case MSR_K8_TSEG_MASK:
60af2ecd 2294 case MSR_K7_HWCR:
61a6bd67 2295 case MSR_VM_HSAVE_PA:
1fdbd48c 2296 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2297 case MSR_AMD64_NB_CFG:
f7c6d140 2298 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2299 case MSR_AMD64_BU_CFG2:
609e36d3 2300 msr_info->data = 0;
15c4a640 2301 break;
6912ac32
WH		 2302 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2303 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2304 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2305 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2306 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2307 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2308 msr_info->data = 0;
5753785f 2309 break;
742bc670 2310 case MSR_IA32_UCODE_REV:
609e36d3 2311 msr_info->data = 0x100000000ULL;
742bc670 2312 break;
9ba075a6 2313 case MSR_MTRRcap:
9ba075a6 2314 case 0x200 ... 0x2ff:
ff53604b 2315 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2316 case 0xcd: /* fsb frequency */
609e36d3 2317 msr_info->data = 3;
15c4a640 2318 break;
7b914098
JS		 2319 /*
2320 * MSR_EBC_FREQUENCY_ID
2321 * Conservative value valid for even the basic CPU models.
2322 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2323 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2324 * and 266MHz for model 3, or 4. Set Core Clock
2325 * Frequency to System Bus Frequency Ratio to 1 (bits
2326 * 31:24) even though these are only valid for CPU
2327 * models > 2, however guests may end up dividing or
2328 * multiplying by zero otherwise.
2329 */
2330 case MSR_EBC_FREQUENCY_ID:
609e36d3 2331 msr_info->data = 1 << 24;
7b914098 2332 break;
15c4a640 2333 case MSR_IA32_APICBASE:
609e36d3 2334 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2335 break;
0105d1a5 2336 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2337 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2338 break;
a3e06bbe 2339 case MSR_IA32_TSCDEADLINE:
609e36d3 2340 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2341 break;
ba904635 2342 case MSR_IA32_TSC_ADJUST:
609e36d3 2343 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2344 break;
15c4a640 2345 case MSR_IA32_MISC_ENABLE:
609e36d3 2346 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2347 break;
64d60670
PB		 2348 case MSR_IA32_SMBASE:
2349 if (!msr_info->host_initiated)
2350 return 1;
2351 msr_info->data = vcpu->arch.smbase;
15c4a640 2352 break;
847f0ad8
AG		 2353 case MSR_IA32_PERF_STATUS:
2354 /* TSC increment by tick */
609e36d3 2355 msr_info->data = 1000ULL;
847f0ad8 2356 /* CPU multiplier */
b0996ae4 2357 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2358 break;
15c4a640 2359 case MSR_EFER:
609e36d3 2360 msr_info->data = vcpu->arch.efer;
15c4a640 2361 break;
18068523 2362 case MSR_KVM_WALL_CLOCK:
11c6bffa 2363 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2364 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2365 break;
2366 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2367 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2368 msr_info->data = vcpu->arch.time;
18068523 2369 break;
344d9588 2370 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2371 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2372 break;
c9aaa895 2373 case MSR_KVM_STEAL_TIME:
609e36d3 2374 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2375 break;
1d92128f 2376 case MSR_KVM_PV_EOI_EN:
609e36d3 2377 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2378 break;
890ca9ae
HY		 2379 case MSR_IA32_P5_MC_ADDR:
2380 case MSR_IA32_P5_MC_TYPE:
2381 case MSR_IA32_MCG_CAP:
2382 case MSR_IA32_MCG_CTL:
2383 case MSR_IA32_MCG_STATUS:
81760dcc 2384 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2385 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2386 case MSR_K7_CLK_CTL:
2387 /*
2388 * Provide expected ramp-up count for K7. All other
2389 * are set to zero, indicating minimum divisors for
2390 * every field.
2391 *
2392 * This prevents guest kernels on AMD host with CPU
2393 * type 6, model 8 and higher from exploding due to
2394 * the rdmsr failing.
2395 */
609e36d3 2396 msr_info->data = 0x20000000;
84e0cefa 2397 break;
55cd8e5a 2398 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2399 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2400 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2401 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2402 return kvm_hv_get_msr_common(vcpu,
2403 msr_info->index, &msr_info->data);
55cd8e5a 2404 break;
91c9c3ed 2405 case MSR_IA32_BBL_CR_CTL3:
2406 /* This legacy MSR exists but isn't fully documented in current
2407 * silicon. It is however accessed by winxp in very narrow
2408 * scenarios where it sets bit #19, itself documented as
2409 * a "reserved" bit. Best effort attempt to source coherent
2410 * read data here should the balance of the register be
2411 * interpreted by the guest:
2412 *
2413 * L2 cache control register 3: 64GB range, 256KB size,
2414 * enabled, latency 0x1, configured
2415 */
609e36d3 2416 msr_info->data = 0xbe702111;
91c9c3ed 2417 break;
2b036c6b
BO		 2418 case MSR_AMD64_OSVW_ID_LENGTH:
2419 if (!guest_cpuid_has_osvw(vcpu))
2420 return 1;
609e36d3 2421 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2422 break;
2423 case MSR_AMD64_OSVW_STATUS:
2424 if (!guest_cpuid_has_osvw(vcpu))
2425 return 1;
609e36d3 2426 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2427 break;
15c4a640 2428 default:
c6702c9d 2429 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2430 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2431 if (!ignore_msrs) {
609e36d3 2432 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2433 return 1;
2434 } else {
609e36d3
PB		 2435 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2436 msr_info->data = 0;
ed85c068
AP		 2437 }
2438 break;
15c4a640 2439 }
15c4a640
CO		 2440 return 0;
2441}
2442EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2443
313a3dc7
CO		 2444/*
2445 * Read or write a bunch of msrs. All parameters are kernel addresses.
2446 *
2447 * @return number of msrs set successfully.
2448 */
2449static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2450 struct kvm_msr_entry *entries,
2451 int (*do_msr)(struct kvm_vcpu *vcpu,
2452 unsigned index, u64 *data))
2453{
f656ce01 2454 int i, idx;
313a3dc7 2455
f656ce01 2456 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2457 for (i = 0; i < msrs->nmsrs; ++i)
2458 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2459 break;
f656ce01 2460 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2461
313a3dc7
CO		 2462 return i;
2463}
2464
2465/*
2466 * Read or write a bunch of msrs. Parameters are user addresses.
2467 *
2468 * @return number of msrs set successfully.
2469 */
2470static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2471 int (*do_msr)(struct kvm_vcpu *vcpu,
2472 unsigned index, u64 *data),
2473 int writeback)
2474{
2475 struct kvm_msrs msrs;
2476 struct kvm_msr_entry *entries;
2477 int r, n;
2478 unsigned size;
2479
2480 r = -EFAULT;
2481 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2482 goto out;
2483
2484 r = -E2BIG;
2485 if (msrs.nmsrs >= MAX_IO_MSRS)
2486 goto out;
2487
313a3dc7 2488 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2489 entries = memdup_user(user_msrs->entries, size);
2490 if (IS_ERR(entries)) {
2491 r = PTR_ERR(entries);
313a3dc7 2492 goto out;
ff5c2c03 2493 }
313a3dc7
CO		 2494
2495 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2496 if (r < 0)
2497 goto out_free;
2498
2499 r = -EFAULT;
2500 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2501 goto out_free;
2502
2503 r = n;
2504
2505out_free:
7a73c028 2506 kfree(entries);
313a3dc7
CO		 2507out:
2508 return r;
2509}
2510
784aa3d7 2511int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2512{
2513 int r;
2514
2515 switch (ext) {
2516 case KVM_CAP_IRQCHIP:
2517 case KVM_CAP_HLT:
2518 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2519 case KVM_CAP_SET_TSS_ADDR:
07716717 2520 case KVM_CAP_EXT_CPUID:
9c15bb1d 2521 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2522 case KVM_CAP_CLOCKSOURCE:
7837699f 2523 case KVM_CAP_PIT:
a28e4f5a 2524 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2525 case KVM_CAP_MP_STATE:
ed848624 2526 case KVM_CAP_SYNC_MMU:
a355c85c 2527 case KVM_CAP_USER_NMI:
52d939a0 2528 case KVM_CAP_REINJECT_CONTROL:
4925663a 2529 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2530 case KVM_CAP_IOEVENTFD:
f848a5a8 2531 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2532 case KVM_CAP_PIT2:
e9f42757 2533 case KVM_CAP_PIT_STATE2:
b927a3ce 2534 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2535 case KVM_CAP_XEN_HVM:
afbcf7ab 2536 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2537 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2538 case KVM_CAP_HYPERV:
10388a07 2539 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2540 case KVM_CAP_HYPERV_SPIN:
5c919412 2541 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2542 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2543 case KVM_CAP_DEBUGREGS:
d2be1651 2544 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2545 case KVM_CAP_XSAVE:
344d9588 2546 case KVM_CAP_ASYNC_PF:
92a1f12d 2547 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2548 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2549 case KVM_CAP_READONLY_MEM:
5f66b620 2550 case KVM_CAP_HYPERV_TIME:
100943c5 2551 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2552 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2553 case KVM_CAP_ENABLE_CAP_VM:
2554 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2555 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2556 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2557#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2558 case KVM_CAP_ASSIGN_DEV_IRQ:
2559 case KVM_CAP_PCI_2_3:
2560#endif
018d00d2
ZX		 2561 r = 1;
2562 break;
6d396b55
PB		 2563 case KVM_CAP_X86_SMM:
2564 /* SMBASE is usually relocated above 1M on modern chipsets,
2565 * and SMM handlers might indeed rely on 4G segment limits,
2566 * so do not report SMM to be available if real mode is
2567 * emulated via vm86 mode. Still, do not go to great lengths
2568 * to avoid userspace's usage of the feature, because it is a
2569 * fringe case that is not enabled except via specific settings
2570 * of the module parameters.
2571 */
2572 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2573 break;
542472b5
LV		 2574 case KVM_CAP_COALESCED_MMIO:
2575 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2576 break;
774ead3a
AK		 2577 case KVM_CAP_VAPIC:
2578 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2579 break;
f725230a 2580 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2581 r = KVM_SOFT_MAX_VCPUS;
2582 break;
2583 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2584 r = KVM_MAX_VCPUS;
2585 break;
a988b910 2586 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2587 r = KVM_USER_MEM_SLOTS;
a988b910 2588 break;
a68a6a72
MT		 2589 case KVM_CAP_PV_MMU: /* obsolete */
2590 r = 0;
2f333bcb 2591 break;
4cee4b72 2592#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2593 case KVM_CAP_IOMMU:
a1b60c1c 2594 r = iommu_present(&pci_bus_type);
62c476c7 2595 break;
4cee4b72 2596#endif
890ca9ae
HY		 2597 case KVM_CAP_MCE:
2598 r = KVM_MAX_MCE_BANKS;
2599 break;
2d5b5a66
SY		 2600 case KVM_CAP_XCRS:
2601 r = cpu_has_xsave;
2602 break;
92a1f12d
JR		 2603 case KVM_CAP_TSC_CONTROL:
2604 r = kvm_has_tsc_control;
2605 break;
018d00d2
ZX		 2606 default:
2607 r = 0;
2608 break;
2609 }
2610 return r;
2611
2612}
2613
043405e1
CO		 2614long kvm_arch_dev_ioctl(struct file *filp,
2615 unsigned int ioctl, unsigned long arg)
2616{
2617 void __user *argp = (void __user *)arg;
2618 long r;
2619
2620 switch (ioctl) {
2621 case KVM_GET_MSR_INDEX_LIST: {
2622 struct kvm_msr_list __user *user_msr_list = argp;
2623 struct kvm_msr_list msr_list;
2624 unsigned n;
2625
2626 r = -EFAULT;
2627 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2628 goto out;
2629 n = msr_list.nmsrs;
62ef68bb 2630 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2631 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2632 goto out;
2633 r = -E2BIG;
e125e7b6 2634 if (n < msr_list.nmsrs)
043405e1
CO		 2635 goto out;
2636 r = -EFAULT;
2637 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2638 num_msrs_to_save * sizeof(u32)))
2639 goto out;
e125e7b6 2640 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2641 &emulated_msrs,
62ef68bb 2642 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2643 goto out;
2644 r = 0;
2645 break;
2646 }
9c15bb1d
BP		 2647 case KVM_GET_SUPPORTED_CPUID:
2648 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2649 struct kvm_cpuid2 __user *cpuid_arg = argp;
2650 struct kvm_cpuid2 cpuid;
2651
2652 r = -EFAULT;
2653 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2654 goto out;
9c15bb1d
BP		 2655
2656 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2657 ioctl);
674eea0f
AK		 2658 if (r)
2659 goto out;
2660
2661 r = -EFAULT;
2662 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2663 goto out;
2664 r = 0;
2665 break;
2666 }
890ca9ae
HY		 2667 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2668 u64 mce_cap;
2669
2670 mce_cap = KVM_MCE_CAP_SUPPORTED;
2671 r = -EFAULT;
2672 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2673 goto out;
2674 r = 0;
2675 break;
2676 }
043405e1
CO		 2677 default:
2678 r = -EINVAL;
2679 }
2680out:
2681 return r;
2682}
2683
f5f48ee1
SY		 2684static void wbinvd_ipi(void *garbage)
2685{
2686 wbinvd();
2687}
2688
2689static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2690{
e0f0bbc5 2691 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2692}
2693
2860c4b1
PB		 2694static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2695{
2696 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2697}
2698
313a3dc7
CO		 2699void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2700{
f5f48ee1
SY		 2701 /* Address WBINVD may be executed by guest */
2702 if (need_emulate_wbinvd(vcpu)) {
2703 if (kvm_x86_ops->has_wbinvd_exit())
2704 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2705 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2706 smp_call_function_single(vcpu->cpu,
2707 wbinvd_ipi, NULL, 1);
2708 }
2709
313a3dc7 2710 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2711
0dd6a6ed
ZA		 2712 /* Apply any externally detected TSC adjustments (due to suspend) */
2713 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2714 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2715 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2716 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2717 }
8f6055cb 2718
48434c20 2719 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2720 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2721 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2722 if (tsc_delta < 0)
2723 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2724 if (check_tsc_unstable()) {
07c1419a 2725 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2726 vcpu->arch.last_guest_tsc);
2727 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2728 vcpu->arch.tsc_catchup = 1;
c285545f 2729 }
d98d07ca
MT		 2730 /*
2731 * On a host with synchronized TSC, there is no need to update
2732 * kvmclock on vcpu->cpu migration
2733 */
2734 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2735 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2736 if (vcpu->cpu != cpu)
2737 kvm_migrate_timers(vcpu);
e48672fa 2738 vcpu->cpu = cpu;
6b7d7e76 2739 }
c9aaa895 2740
c9aaa895 2741 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2742}
2743
2744void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2745{
02daab21 2746 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2747 kvm_put_guest_fpu(vcpu);
4ea1636b 2748 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2749}
2750
313a3dc7
CO		 2751static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2752 struct kvm_lapic_state *s)
2753{
d62caabb
AS		 2754 if (vcpu->arch.apicv_active)
2755 kvm_x86_ops->sync_pir_to_irr(vcpu);
2756
ad312c7c 2757 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2758
2759 return 0;
2760}
2761
2762static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2763 struct kvm_lapic_state *s)
2764{
64eb0620 2765 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2766 update_cr8_intercept(vcpu);
313a3dc7
CO		 2767
2768 return 0;
2769}
2770
127a457a
MG		 2771static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2772{
2773 return (!lapic_in_kernel(vcpu) ||
2774 kvm_apic_accept_pic_intr(vcpu));
2775}
2776
782d422b
MG		 2777/*
2778 * if userspace requested an interrupt window, check that the
2779 * interrupt window is open.
2780 *
2781 * No need to exit to userspace if we already have an interrupt queued.
2782 */
2783static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2784{
2785 return kvm_arch_interrupt_allowed(vcpu) &&
2786 !kvm_cpu_has_interrupt(vcpu) &&
2787 !kvm_event_needs_reinjection(vcpu) &&
2788 kvm_cpu_accept_dm_intr(vcpu);
2789}
2790
f77bc6a4
ZX		 2791static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2792 struct kvm_interrupt *irq)
2793{
02cdb50f 2794 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2795 return -EINVAL;
1c1a9ce9
SR		 2796
2797 if (!irqchip_in_kernel(vcpu->kvm)) {
2798 kvm_queue_interrupt(vcpu, irq->irq, false);
2799 kvm_make_request(KVM_REQ_EVENT, vcpu);
2800 return 0;
2801 }
2802
2803 /*
2804 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2805 * fail for in-kernel 8259.
2806 */
2807 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2808 return -ENXIO;
f77bc6a4 2809
1c1a9ce9
SR		 2810 if (vcpu->arch.pending_external_vector != -1)
2811 return -EEXIST;
f77bc6a4 2812
1c1a9ce9 2813 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2814 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2815 return 0;
2816}
2817
c4abb7c9
JK		 2818static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2819{
c4abb7c9 2820 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2821
2822 return 0;
2823}
2824
f077825a
PB		 2825static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2826{
64d60670
PB		 2827 kvm_make_request(KVM_REQ_SMI, vcpu);
2828
f077825a
PB		 2829 return 0;
2830}
2831
b209749f
AK		 2832static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2833 struct kvm_tpr_access_ctl *tac)
2834{
2835 if (tac->flags)
2836 return -EINVAL;
2837 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2838 return 0;
2839}
2840
890ca9ae
HY		 2841static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2842 u64 mcg_cap)
2843{
2844 int r;
2845 unsigned bank_num = mcg_cap & 0xff, bank;
2846
2847 r = -EINVAL;
a9e38c3e 2848 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2849 goto out;
2850 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2851 goto out;
2852 r = 0;
2853 vcpu->arch.mcg_cap = mcg_cap;
2854 /* Init IA32_MCG_CTL to all 1s */
2855 if (mcg_cap & MCG_CTL_P)
2856 vcpu->arch.mcg_ctl = ~(u64)0;
2857 /* Init IA32_MCi_CTL to all 1s */
2858 for (bank = 0; bank < bank_num; bank++)
2859 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2860out:
2861 return r;
2862}
2863
2864static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2865 struct kvm_x86_mce *mce)
2866{
2867 u64 mcg_cap = vcpu->arch.mcg_cap;
2868 unsigned bank_num = mcg_cap & 0xff;
2869 u64 *banks = vcpu->arch.mce_banks;
2870
2871 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2872 return -EINVAL;
2873 /*
2874 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2875 * reporting is disabled
2876 */
2877 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2878 vcpu->arch.mcg_ctl != ~(u64)0)
2879 return 0;
2880 banks += 4 * mce->bank;
2881 /*
2882 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2883 * reporting is disabled for the bank
2884 */
2885 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2886 return 0;
2887 if (mce->status & MCI_STATUS_UC) {
2888 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2889 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2890 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2891 return 0;
2892 }
2893 if (banks[1] & MCI_STATUS_VAL)
2894 mce->status |= MCI_STATUS_OVER;
2895 banks[2] = mce->addr;
2896 banks[3] = mce->misc;
2897 vcpu->arch.mcg_status = mce->mcg_status;
2898 banks[1] = mce->status;
2899 kvm_queue_exception(vcpu, MC_VECTOR);
2900 } else if (!(banks[1] & MCI_STATUS_VAL)
2901 || !(banks[1] & MCI_STATUS_UC)) {
2902 if (banks[1] & MCI_STATUS_VAL)
2903 mce->status |= MCI_STATUS_OVER;
2904 banks[2] = mce->addr;
2905 banks[3] = mce->misc;
2906 banks[1] = mce->status;
2907 } else
2908 banks[1] |= MCI_STATUS_OVER;
2909 return 0;
2910}
2911
3cfc3092
JK		 2912static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2913 struct kvm_vcpu_events *events)
2914{
7460fb4a 2915 process_nmi(vcpu);
03b82a30
JK		 2916 events->exception.injected =
2917 vcpu->arch.exception.pending &&
2918 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2919 events->exception.nr = vcpu->arch.exception.nr;
2920 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2921 events->exception.pad = 0;
3cfc3092
JK		 2922 events->exception.error_code = vcpu->arch.exception.error_code;
2923
03b82a30
JK		 2924 events->interrupt.injected =
2925 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2926 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2927 events->interrupt.soft = 0;
37ccdcbe 2928 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2929
2930 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2931 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2932 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2933 events->nmi.pad = 0;
3cfc3092 2934
66450a21 2935 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2936
f077825a
PB		 2937 events->smi.smm = is_smm(vcpu);
2938 events->smi.pending = vcpu->arch.smi_pending;
2939 events->smi.smm_inside_nmi =
2940 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2941 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2942
dab4b911 2943 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2944 | KVM_VCPUEVENT_VALID_SHADOW
2945 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2946 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2947}
2948
2949static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2950 struct kvm_vcpu_events *events)
2951{
dab4b911 2952 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2953 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2954 | KVM_VCPUEVENT_VALID_SHADOW
2955 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2956 return -EINVAL;
2957
7460fb4a 2958 process_nmi(vcpu);
3cfc3092
JK		 2959 vcpu->arch.exception.pending = events->exception.injected;
2960 vcpu->arch.exception.nr = events->exception.nr;
2961 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2962 vcpu->arch.exception.error_code = events->exception.error_code;
2963
2964 vcpu->arch.interrupt.pending = events->interrupt.injected;
2965 vcpu->arch.interrupt.nr = events->interrupt.nr;
2966 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2967 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2968 kvm_x86_ops->set_interrupt_shadow(vcpu,
2969 events->interrupt.shadow);
3cfc3092
JK		 2970
2971 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2972 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2973 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2974 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2975
66450a21 2976 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 2977 lapic_in_kernel(vcpu))
66450a21 2978 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2979
f077825a
PB		 2980 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2981 if (events->smi.smm)
2982 vcpu->arch.hflags |= HF_SMM_MASK;
2983 else
2984 vcpu->arch.hflags &= ~HF_SMM_MASK;
2985 vcpu->arch.smi_pending = events->smi.pending;
2986 if (events->smi.smm_inside_nmi)
2987 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2988 else
2989 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 2990 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 2991 if (events->smi.latched_init)
2992 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2993 else
2994 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2995 }
2996 }
2997
3842d135
AK		 2998 kvm_make_request(KVM_REQ_EVENT, vcpu);
2999
3cfc3092
JK		 3000 return 0;
3001}
3002
a1efbe77
JK		 3003static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3004 struct kvm_debugregs *dbgregs)
3005{
73aaf249
JK		 3006 unsigned long val;
3007
a1efbe77 3008 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3009 kvm_get_dr(vcpu, 6, &val);
73aaf249 3010 dbgregs->dr6 = val;
a1efbe77
JK		 3011 dbgregs->dr7 = vcpu->arch.dr7;
3012 dbgregs->flags = 0;
97e69aa6 3013 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3014}
3015
3016static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3017 struct kvm_debugregs *dbgregs)
3018{
3019 if (dbgregs->flags)
3020 return -EINVAL;
3021
a1efbe77 3022 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3023 kvm_update_dr0123(vcpu);
a1efbe77 3024 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3025 kvm_update_dr6(vcpu);
a1efbe77 3026 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3027 kvm_update_dr7(vcpu);
a1efbe77 3028
a1efbe77
JK		 3029 return 0;
3030}
3031
df1daba7
PB		 3032#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3033
3034static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3035{
c47ada30 3036 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3037 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3038 u64 valid;
3039
3040 /*
3041 * Copy legacy XSAVE area, to avoid complications with CPUID
3042 * leaves 0 and 1 in the loop below.
3043 */
3044 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3045
3046 /* Set XSTATE_BV */
3047 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3048
3049 /*
3050 * Copy each region from the possibly compacted offset to the
3051 * non-compacted offset.
3052 */
d91cab78 3053 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3054 while (valid) {
3055 u64 feature = valid & -valid;
3056 int index = fls64(feature) - 1;
3057 void *src = get_xsave_addr(xsave, feature);
3058
3059 if (src) {
3060 u32 size, offset, ecx, edx;
3061 cpuid_count(XSTATE_CPUID, index,
3062 &size, &offset, &ecx, &edx);
3063 memcpy(dest + offset, src, size);
3064 }
3065
3066 valid -= feature;
3067 }
3068}
3069
3070static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3071{
c47ada30 3072 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3073 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3074 u64 valid;
3075
3076 /*
3077 * Copy legacy XSAVE area, to avoid complications with CPUID
3078 * leaves 0 and 1 in the loop below.
3079 */
3080 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3081
3082 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3083 xsave->header.xfeatures = xstate_bv;
df1daba7 3084 if (cpu_has_xsaves)
3a54450b 3085 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3086
3087 /*
3088 * Copy each region from the non-compacted offset to the
3089 * possibly compacted offset.
3090 */
d91cab78 3091 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3092 while (valid) {
3093 u64 feature = valid & -valid;
3094 int index = fls64(feature) - 1;
3095 void *dest = get_xsave_addr(xsave, feature);
3096
3097 if (dest) {
3098 u32 size, offset, ecx, edx;
3099 cpuid_count(XSTATE_CPUID, index,
3100 &size, &offset, &ecx, &edx);
3101 memcpy(dest, src + offset, size);
ee4100da 3102 }
df1daba7
PB		 3103
3104 valid -= feature;
3105 }
3106}
3107
2d5b5a66
SY		 3108static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3109 struct kvm_xsave *guest_xsave)
3110{
4344ee98 3111 if (cpu_has_xsave) {
df1daba7
PB		 3112 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3113 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3114 } else {
2d5b5a66 3115 memcpy(guest_xsave->region,
7366ed77 3116 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3117 sizeof(struct fxregs_state));
2d5b5a66 3118 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3119 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3120 }
3121}
3122
3123static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3124 struct kvm_xsave *guest_xsave)
3125{
3126 u64 xstate_bv =
3127 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3128
d7876f1b
PB		 3129 if (cpu_has_xsave) {
3130 /*
3131 * Here we allow setting states that are not present in
3132 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3133 * with old userspace.
3134 */
4ff41732 3135 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3136 return -EINVAL;
df1daba7 3137 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3138 } else {
d91cab78 3139 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3140 return -EINVAL;
7366ed77 3141 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3142 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3143 }
3144 return 0;
3145}
3146
3147static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3148 struct kvm_xcrs *guest_xcrs)
3149{
3150 if (!cpu_has_xsave) {
3151 guest_xcrs->nr_xcrs = 0;
3152 return;
3153 }
3154
3155 guest_xcrs->nr_xcrs = 1;
3156 guest_xcrs->flags = 0;
3157 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3158 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3159}
3160
3161static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3162 struct kvm_xcrs *guest_xcrs)
3163{
3164 int i, r = 0;
3165
3166 if (!cpu_has_xsave)
3167 return -EINVAL;
3168
3169 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3170 return -EINVAL;
3171
3172 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3173 /* Only support XCR0 currently */
c67a04cb 3174 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3175 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3176 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3177 break;
3178 }
3179 if (r)
3180 r = -EINVAL;
3181 return r;
3182}
3183
1c0b28c2
EM		 3184/*
3185 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3186 * stopped by the hypervisor. This function will be called from the host only.
3187 * EINVAL is returned when the host attempts to set the flag for a guest that
3188 * does not support pv clocks.
3189 */
3190static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3191{
0b79459b 3192 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3193 return -EINVAL;
51d59c6b 3194 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3195 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3196 return 0;
3197}
3198
5c919412
AS		 3199static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3200 struct kvm_enable_cap *cap)
3201{
3202 if (cap->flags)
3203 return -EINVAL;
3204
3205 switch (cap->cap) {
3206 case KVM_CAP_HYPERV_SYNIC:
3207 return kvm_hv_activate_synic(vcpu);
3208 default:
3209 return -EINVAL;
3210 }
3211}
3212
313a3dc7
CO		 3213long kvm_arch_vcpu_ioctl(struct file *filp,
3214 unsigned int ioctl, unsigned long arg)
3215{
3216 struct kvm_vcpu *vcpu = filp->private_data;
3217 void __user *argp = (void __user *)arg;
3218 int r;
d1ac91d8
AK		 3219 union {
3220 struct kvm_lapic_state *lapic;
3221 struct kvm_xsave *xsave;
3222 struct kvm_xcrs *xcrs;
3223 void *buffer;
3224 } u;
3225
3226 u.buffer = NULL;
313a3dc7
CO		 3227 switch (ioctl) {
3228 case KVM_GET_LAPIC: {
2204ae3c 3229 r = -EINVAL;
bce87cce 3230 if (!lapic_in_kernel(vcpu))
2204ae3c 3231 goto out;
d1ac91d8 3232 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3233
b772ff36 3234 r = -ENOMEM;
d1ac91d8 3235 if (!u.lapic)
b772ff36 3236 goto out;
d1ac91d8 3237 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3238 if (r)
3239 goto out;
3240 r = -EFAULT;
d1ac91d8 3241 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3242 goto out;
3243 r = 0;
3244 break;
3245 }
3246 case KVM_SET_LAPIC: {
2204ae3c 3247 r = -EINVAL;
bce87cce 3248 if (!lapic_in_kernel(vcpu))
2204ae3c 3249 goto out;
ff5c2c03 3250 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3251 if (IS_ERR(u.lapic))
3252 return PTR_ERR(u.lapic);
ff5c2c03 3253
d1ac91d8 3254 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3255 break;
3256 }
f77bc6a4
ZX		 3257 case KVM_INTERRUPT: {
3258 struct kvm_interrupt irq;
3259
3260 r = -EFAULT;
3261 if (copy_from_user(&irq, argp, sizeof irq))
3262 goto out;
3263 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3264 break;
3265 }
c4abb7c9
JK		 3266 case KVM_NMI: {
3267 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3268 break;
3269 }
f077825a
PB		 3270 case KVM_SMI: {
3271 r = kvm_vcpu_ioctl_smi(vcpu);
3272 break;
3273 }
313a3dc7
CO		 3274 case KVM_SET_CPUID: {
3275 struct kvm_cpuid __user *cpuid_arg = argp;
3276 struct kvm_cpuid cpuid;
3277
3278 r = -EFAULT;
3279 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3280 goto out;
3281 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3282 break;
3283 }
07716717
DK		 3284 case KVM_SET_CPUID2: {
3285 struct kvm_cpuid2 __user *cpuid_arg = argp;
3286 struct kvm_cpuid2 cpuid;
3287
3288 r = -EFAULT;
3289 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3290 goto out;
3291 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3292 cpuid_arg->entries);
07716717
DK		 3293 break;
3294 }
3295 case KVM_GET_CPUID2: {
3296 struct kvm_cpuid2 __user *cpuid_arg = argp;
3297 struct kvm_cpuid2 cpuid;
3298
3299 r = -EFAULT;
3300 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3301 goto out;
3302 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3303 cpuid_arg->entries);
07716717
DK		 3304 if (r)
3305 goto out;
3306 r = -EFAULT;
3307 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3308 goto out;
3309 r = 0;
3310 break;
3311 }
313a3dc7 3312 case KVM_GET_MSRS:
609e36d3 3313 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3314 break;
3315 case KVM_SET_MSRS:
3316 r = msr_io(vcpu, argp, do_set_msr, 0);
3317 break;
b209749f
AK		 3318 case KVM_TPR_ACCESS_REPORTING: {
3319 struct kvm_tpr_access_ctl tac;
3320
3321 r = -EFAULT;
3322 if (copy_from_user(&tac, argp, sizeof tac))
3323 goto out;
3324 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3325 if (r)
3326 goto out;
3327 r = -EFAULT;
3328 if (copy_to_user(argp, &tac, sizeof tac))
3329 goto out;
3330 r = 0;
3331 break;
3332 };
b93463aa
AK		 3333 case KVM_SET_VAPIC_ADDR: {
3334 struct kvm_vapic_addr va;
3335
3336 r = -EINVAL;
35754c98 3337 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3338 goto out;
3339 r = -EFAULT;
3340 if (copy_from_user(&va, argp, sizeof va))
3341 goto out;
fda4e2e8 3342 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3343 break;
3344 }
890ca9ae
HY		 3345 case KVM_X86_SETUP_MCE: {
3346 u64 mcg_cap;
3347
3348 r = -EFAULT;
3349 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3350 goto out;
3351 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3352 break;
3353 }
3354 case KVM_X86_SET_MCE: {
3355 struct kvm_x86_mce mce;
3356
3357 r = -EFAULT;
3358 if (copy_from_user(&mce, argp, sizeof mce))
3359 goto out;
3360 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3361 break;
3362 }
3cfc3092
JK		 3363 case KVM_GET_VCPU_EVENTS: {
3364 struct kvm_vcpu_events events;
3365
3366 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3367
3368 r = -EFAULT;
3369 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3370 break;
3371 r = 0;
3372 break;
3373 }
3374 case KVM_SET_VCPU_EVENTS: {
3375 struct kvm_vcpu_events events;
3376
3377 r = -EFAULT;
3378 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3379 break;
3380
3381 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3382 break;
3383 }
a1efbe77
JK		 3384 case KVM_GET_DEBUGREGS: {
3385 struct kvm_debugregs dbgregs;
3386
3387 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3388
3389 r = -EFAULT;
3390 if (copy_to_user(argp, &dbgregs,
3391 sizeof(struct kvm_debugregs)))
3392 break;
3393 r = 0;
3394 break;
3395 }
3396 case KVM_SET_DEBUGREGS: {
3397 struct kvm_debugregs dbgregs;
3398
3399 r = -EFAULT;
3400 if (copy_from_user(&dbgregs, argp,
3401 sizeof(struct kvm_debugregs)))
3402 break;
3403
3404 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3405 break;
3406 }
2d5b5a66 3407 case KVM_GET_XSAVE: {
d1ac91d8 3408 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3409 r = -ENOMEM;
d1ac91d8 3410 if (!u.xsave)
2d5b5a66
SY		 3411 break;
3412
d1ac91d8 3413 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3414
3415 r = -EFAULT;
d1ac91d8 3416 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3417 break;
3418 r = 0;
3419 break;
3420 }
3421 case KVM_SET_XSAVE: {
ff5c2c03 3422 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3423 if (IS_ERR(u.xsave))
3424 return PTR_ERR(u.xsave);
2d5b5a66 3425
d1ac91d8 3426 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3427 break;
3428 }
3429 case KVM_GET_XCRS: {
d1ac91d8 3430 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3431 r = -ENOMEM;
d1ac91d8 3432 if (!u.xcrs)
2d5b5a66
SY		 3433 break;
3434
d1ac91d8 3435 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3436
3437 r = -EFAULT;
d1ac91d8 3438 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3439 sizeof(struct kvm_xcrs)))
3440 break;
3441 r = 0;
3442 break;
3443 }
3444 case KVM_SET_XCRS: {
ff5c2c03 3445 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3446 if (IS_ERR(u.xcrs))
3447 return PTR_ERR(u.xcrs);
2d5b5a66 3448
d1ac91d8 3449 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3450 break;
3451 }
92a1f12d
JR		 3452 case KVM_SET_TSC_KHZ: {
3453 u32 user_tsc_khz;
3454
3455 r = -EINVAL;
92a1f12d
JR		 3456 user_tsc_khz = (u32)arg;
3457
3458 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3459 goto out;
3460
cc578287
ZA		 3461 if (user_tsc_khz == 0)
3462 user_tsc_khz = tsc_khz;
3463
381d585c
HZ		 3464 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3465 r = 0;
92a1f12d 3466
92a1f12d
JR		 3467 goto out;
3468 }
3469 case KVM_GET_TSC_KHZ: {
cc578287 3470 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3471 goto out;
3472 }
1c0b28c2
EM		 3473 case KVM_KVMCLOCK_CTRL: {
3474 r = kvm_set_guest_paused(vcpu);
3475 goto out;
3476 }
5c919412
AS		 3477 case KVM_ENABLE_CAP: {
3478 struct kvm_enable_cap cap;
3479
3480 r = -EFAULT;
3481 if (copy_from_user(&cap, argp, sizeof(cap)))
3482 goto out;
3483 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3484 break;
3485 }
313a3dc7
CO		 3486 default:
3487 r = -EINVAL;
3488 }
3489out:
d1ac91d8 3490 kfree(u.buffer);
313a3dc7
CO		 3491 return r;
3492}
3493
5b1c1493
CO		 3494int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3495{
3496 return VM_FAULT_SIGBUS;
3497}
3498
1fe779f8
CO		 3499static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3500{
3501 int ret;
3502
3503 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3504 return -EINVAL;
1fe779f8
CO		 3505 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3506 return ret;
3507}
3508
b927a3ce
SY		 3509static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3510 u64 ident_addr)
3511{
3512 kvm->arch.ept_identity_map_addr = ident_addr;
3513 return 0;
3514}
3515
1fe779f8
CO		 3516static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3517 u32 kvm_nr_mmu_pages)
3518{
3519 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3520 return -EINVAL;
3521
79fac95e 3522 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3523
3524 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3525 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3526
79fac95e 3527 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3528 return 0;
3529}
3530
3531static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3532{
39de71ec 3533 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3534}
3535
1fe779f8
CO		 3536static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3537{
3538 int r;
3539
3540 r = 0;
3541 switch (chip->chip_id) {
3542 case KVM_IRQCHIP_PIC_MASTER:
3543 memcpy(&chip->chip.pic,
3544 &pic_irqchip(kvm)->pics[0],
3545 sizeof(struct kvm_pic_state));
3546 break;
3547 case KVM_IRQCHIP_PIC_SLAVE:
3548 memcpy(&chip->chip.pic,
3549 &pic_irqchip(kvm)->pics[1],
3550 sizeof(struct kvm_pic_state));
3551 break;
3552 case KVM_IRQCHIP_IOAPIC:
eba0226b 3553 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3554 break;
3555 default:
3556 r = -EINVAL;
3557 break;
3558 }
3559 return r;
3560}
3561
3562static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3563{
3564 int r;
3565
3566 r = 0;
3567 switch (chip->chip_id) {
3568 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3569 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3570 memcpy(&pic_irqchip(kvm)->pics[0],
3571 &chip->chip.pic,
3572 sizeof(struct kvm_pic_state));
f4f51050 3573 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3574 break;
3575 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3576 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3577 memcpy(&pic_irqchip(kvm)->pics[1],
3578 &chip->chip.pic,
3579 sizeof(struct kvm_pic_state));
f4f51050 3580 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3581 break;
3582 case KVM_IRQCHIP_IOAPIC:
eba0226b 3583 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3584 break;
3585 default:
3586 r = -EINVAL;
3587 break;
3588 }
3589 kvm_pic_update_irq(pic_irqchip(kvm));
3590 return r;
3591}
3592
e0f63cb9
SY		 3593static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3594{
34f3941c
RK		 3595 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3596
3597 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3598
3599 mutex_lock(&kps->lock);
3600 memcpy(ps, &kps->channels, sizeof(*ps));
3601 mutex_unlock(&kps->lock);
2da29bcc 3602 return 0;
e0f63cb9
SY		 3603}
3604
3605static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3606{
0185604c 3607 int i;
09edea72
RK		 3608 struct kvm_pit *pit = kvm->arch.vpit;
3609
3610 mutex_lock(&pit->pit_state.lock);
34f3941c 3611 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3612 for (i = 0; i < 3; i++)
09edea72
RK		 3613 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3614 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3615 return 0;
e9f42757
BK		 3616}
3617
3618static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3619{
e9f42757
BK		 3620 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3621 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3622 sizeof(ps->channels));
3623 ps->flags = kvm->arch.vpit->pit_state.flags;
3624 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3625 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3626 return 0;
e9f42757
BK		 3627}
3628
3629static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3630{
2da29bcc 3631 int start = 0;
0185604c 3632 int i;
e9f42757 3633 u32 prev_legacy, cur_legacy;
09edea72
RK		 3634 struct kvm_pit *pit = kvm->arch.vpit;
3635
3636 mutex_lock(&pit->pit_state.lock);
3637 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3638 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3639 if (!prev_legacy && cur_legacy)
3640 start = 1;
09edea72
RK		 3641 memcpy(&pit->pit_state.channels, &ps->channels,
3642 sizeof(pit->pit_state.channels));
3643 pit->pit_state.flags = ps->flags;
0185604c 3644 for (i = 0; i < 3; i++)
09edea72 3645 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3646 start && i == 0);
09edea72 3647 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3648 return 0;
e0f63cb9
SY		 3649}
3650
52d939a0
MT		 3651static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3652 struct kvm_reinject_control *control)
3653{
71474e2f
RK		 3654 struct kvm_pit *pit = kvm->arch.vpit;
3655
3656 if (!pit)
52d939a0 3657 return -ENXIO;
b39c90b6 3658
71474e2f
RK		 3659 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3660 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3661 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3662 */
3663 mutex_lock(&pit->pit_state.lock);
3664 kvm_pit_set_reinject(pit, control->pit_reinject);
3665 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3666
52d939a0
MT		 3667 return 0;
3668}
3669
95d4c16c 3670/**
60c34612
TY		 3671 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3672 * @kvm: kvm instance
3673 * @log: slot id and address to which we copy the log
95d4c16c 3674 *
e108ff2f
PB		 3675 * Steps 1-4 below provide general overview of dirty page logging. See
3676 * kvm_get_dirty_log_protect() function description for additional details.
3677 *
3678 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3679 * always flush the TLB (step 4) even if previous step failed and the dirty
3680 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3681 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3682 * writes will be marked dirty for next log read.
95d4c16c 3683 *
60c34612
TY		 3684 * 1. Take a snapshot of the bit and clear it if needed.
3685 * 2. Write protect the corresponding page.
e108ff2f
PB		 3686 * 3. Copy the snapshot to the userspace.
3687 * 4. Flush TLB's if needed.
5bb064dc 3688 */
60c34612 3689int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3690{
60c34612 3691 bool is_dirty = false;
e108ff2f 3692 int r;
5bb064dc 3693
79fac95e 3694 mutex_lock(&kvm->slots_lock);
5bb064dc 3695
88178fd4
KH		 3696 /*
3697 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3698 */
3699 if (kvm_x86_ops->flush_log_dirty)
3700 kvm_x86_ops->flush_log_dirty(kvm);
3701
e108ff2f 3702 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3703
3704 /*
3705 * All the TLBs can be flushed out of mmu lock, see the comments in
3706 * kvm_mmu_slot_remove_write_access().
3707 */
e108ff2f 3708 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3709 if (is_dirty)
3710 kvm_flush_remote_tlbs(kvm);
3711
79fac95e 3712 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3713 return r;
3714}
3715
aa2fbe6d
YZ		 3716int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3717 bool line_status)
23d43cf9
CD		 3718{
3719 if (!irqchip_in_kernel(kvm))
3720 return -ENXIO;
3721
3722 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3723 irq_event->irq, irq_event->level,
3724 line_status);
23d43cf9
CD		 3725 return 0;
3726}
3727
90de4a18
NA		 3728static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3729 struct kvm_enable_cap *cap)
3730{
3731 int r;
3732
3733 if (cap->flags)
3734 return -EINVAL;
3735
3736 switch (cap->cap) {
3737 case KVM_CAP_DISABLE_QUIRKS:
3738 kvm->arch.disabled_quirks = cap->args[0];
3739 r = 0;
3740 break;
49df6397
SR		 3741 case KVM_CAP_SPLIT_IRQCHIP: {
3742 mutex_lock(&kvm->lock);
b053b2ae
SR		 3743 r = -EINVAL;
3744 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3745 goto split_irqchip_unlock;
49df6397
SR		 3746 r = -EEXIST;
3747 if (irqchip_in_kernel(kvm))
3748 goto split_irqchip_unlock;
3749 if (atomic_read(&kvm->online_vcpus))
3750 goto split_irqchip_unlock;
3751 r = kvm_setup_empty_irq_routing(kvm);
3752 if (r)
3753 goto split_irqchip_unlock;
3754 /* Pairs with irqchip_in_kernel. */
3755 smp_wmb();
3756 kvm->arch.irqchip_split = true;
b053b2ae 3757 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3758 r = 0;
3759split_irqchip_unlock:
3760 mutex_unlock(&kvm->lock);
3761 break;
3762 }
90de4a18
NA		 3763 default:
3764 r = -EINVAL;
3765 break;
3766 }
3767 return r;
3768}
3769
1fe779f8
CO		 3770long kvm_arch_vm_ioctl(struct file *filp,
3771 unsigned int ioctl, unsigned long arg)
3772{
3773 struct kvm *kvm = filp->private_data;
3774 void __user *argp = (void __user *)arg;
367e1319 3775 int r = -ENOTTY;
f0d66275
DH		 3776 /*
3777 * This union makes it completely explicit to gcc-3.x
3778 * that these two variables' stack usage should be
3779 * combined, not added together.
3780 */
3781 union {
3782 struct kvm_pit_state ps;
e9f42757 3783 struct kvm_pit_state2 ps2;
c5ff41ce 3784 struct kvm_pit_config pit_config;
f0d66275 3785 } u;
1fe779f8
CO		 3786
3787 switch (ioctl) {
3788 case KVM_SET_TSS_ADDR:
3789 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3790 break;
b927a3ce
SY		 3791 case KVM_SET_IDENTITY_MAP_ADDR: {
3792 u64 ident_addr;
3793
3794 r = -EFAULT;
3795 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3796 goto out;
3797 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3798 break;
3799 }
1fe779f8
CO		 3800 case KVM_SET_NR_MMU_PAGES:
3801 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3802 break;
3803 case KVM_GET_NR_MMU_PAGES:
3804 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3805 break;
3ddea128
MT		 3806 case KVM_CREATE_IRQCHIP: {
3807 struct kvm_pic *vpic;
3808
3809 mutex_lock(&kvm->lock);
3810 r = -EEXIST;
3811 if (kvm->arch.vpic)
3812 goto create_irqchip_unlock;
3e515705
AK		 3813 r = -EINVAL;
3814 if (atomic_read(&kvm->online_vcpus))
3815 goto create_irqchip_unlock;
1fe779f8 3816 r = -ENOMEM;
3ddea128
MT		 3817 vpic = kvm_create_pic(kvm);
3818 if (vpic) {
1fe779f8
CO		 3819 r = kvm_ioapic_init(kvm);
3820 if (r) {
175504cd 3821 mutex_lock(&kvm->slots_lock);
71ba994c 3822 kvm_destroy_pic(vpic);
175504cd 3823 mutex_unlock(&kvm->slots_lock);
3ddea128 3824 goto create_irqchip_unlock;
1fe779f8
CO		 3825 }
3826 } else
3ddea128 3827 goto create_irqchip_unlock;
399ec807
AK		 3828 r = kvm_setup_default_irq_routing(kvm);
3829 if (r) {
175504cd 3830 mutex_lock(&kvm->slots_lock);
3ddea128 3831 mutex_lock(&kvm->irq_lock);
72bb2fcd 3832 kvm_ioapic_destroy(kvm);
71ba994c 3833 kvm_destroy_pic(vpic);
3ddea128 3834 mutex_unlock(&kvm->irq_lock);
175504cd 3835 mutex_unlock(&kvm->slots_lock);
71ba994c 3836 goto create_irqchip_unlock;
399ec807 3837 }
71ba994c
PB		 3838 /* Write kvm->irq_routing before kvm->arch.vpic. */
3839 smp_wmb();
3840 kvm->arch.vpic = vpic;
3ddea128
MT		 3841 create_irqchip_unlock:
3842 mutex_unlock(&kvm->lock);
1fe779f8 3843 break;
3ddea128 3844 }
7837699f 3845 case KVM_CREATE_PIT:
c5ff41ce
JK		 3846 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3847 goto create_pit;
3848 case KVM_CREATE_PIT2:
3849 r = -EFAULT;
3850 if (copy_from_user(&u.pit_config, argp,
3851 sizeof(struct kvm_pit_config)))
3852 goto out;
3853 create_pit:
79fac95e 3854 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3855 r = -EEXIST;
3856 if (kvm->arch.vpit)
3857 goto create_pit_unlock;
7837699f 3858 r = -ENOMEM;
c5ff41ce 3859 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3860 if (kvm->arch.vpit)
3861 r = 0;
269e05e4 3862 create_pit_unlock:
79fac95e 3863 mutex_unlock(&kvm->slots_lock);
7837699f 3864 break;
1fe779f8
CO		 3865 case KVM_GET_IRQCHIP: {
3866 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3867 struct kvm_irqchip *chip;
1fe779f8 3868
ff5c2c03
SL		 3869 chip = memdup_user(argp, sizeof(*chip));
3870 if (IS_ERR(chip)) {
3871 r = PTR_ERR(chip);
1fe779f8 3872 goto out;
ff5c2c03
SL		 3873 }
3874
1fe779f8 3875 r = -ENXIO;
49df6397 3876 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3877 goto get_irqchip_out;
3878 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3879 if (r)
f0d66275 3880 goto get_irqchip_out;
1fe779f8 3881 r = -EFAULT;
f0d66275
DH		 3882 if (copy_to_user(argp, chip, sizeof *chip))
3883 goto get_irqchip_out;
1fe779f8 3884 r = 0;
f0d66275
DH		 3885 get_irqchip_out:
3886 kfree(chip);
1fe779f8
CO		 3887 break;
3888 }
3889 case KVM_SET_IRQCHIP: {
3890 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3891 struct kvm_irqchip *chip;
1fe779f8 3892
ff5c2c03
SL		 3893 chip = memdup_user(argp, sizeof(*chip));
3894 if (IS_ERR(chip)) {
3895 r = PTR_ERR(chip);
1fe779f8 3896 goto out;
ff5c2c03
SL		 3897 }
3898
1fe779f8 3899 r = -ENXIO;
49df6397 3900 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3901 goto set_irqchip_out;
3902 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3903 if (r)
f0d66275 3904 goto set_irqchip_out;
1fe779f8 3905 r = 0;
f0d66275
DH		 3906 set_irqchip_out:
3907 kfree(chip);
1fe779f8
CO		 3908 break;
3909 }
e0f63cb9 3910 case KVM_GET_PIT: {
e0f63cb9 3911 r = -EFAULT;
f0d66275 3912 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3913 goto out;
3914 r = -ENXIO;
3915 if (!kvm->arch.vpit)
3916 goto out;
f0d66275 3917 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3918 if (r)
3919 goto out;
3920 r = -EFAULT;
f0d66275 3921 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3922 goto out;
3923 r = 0;
3924 break;
3925 }
3926 case KVM_SET_PIT: {
e0f63cb9 3927 r = -EFAULT;
f0d66275 3928 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3929 goto out;
3930 r = -ENXIO;
3931 if (!kvm->arch.vpit)
3932 goto out;
f0d66275 3933 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3934 break;
3935 }
e9f42757
BK		 3936 case KVM_GET_PIT2: {
3937 r = -ENXIO;
3938 if (!kvm->arch.vpit)
3939 goto out;
3940 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3941 if (r)
3942 goto out;
3943 r = -EFAULT;
3944 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3945 goto out;
3946 r = 0;
3947 break;
3948 }
3949 case KVM_SET_PIT2: {
3950 r = -EFAULT;
3951 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3952 goto out;
3953 r = -ENXIO;
3954 if (!kvm->arch.vpit)
3955 goto out;
3956 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3957 break;
3958 }
52d939a0
MT		 3959 case KVM_REINJECT_CONTROL: {
3960 struct kvm_reinject_control control;
3961 r = -EFAULT;
3962 if (copy_from_user(&control, argp, sizeof(control)))
3963 goto out;
3964 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3965 break;
3966 }
d71ba788
PB		 3967 case KVM_SET_BOOT_CPU_ID:
3968 r = 0;
3969 mutex_lock(&kvm->lock);
3970 if (atomic_read(&kvm->online_vcpus) != 0)
3971 r = -EBUSY;
3972 else
3973 kvm->arch.bsp_vcpu_id = arg;
3974 mutex_unlock(&kvm->lock);
3975 break;
ffde22ac
ES		 3976 case KVM_XEN_HVM_CONFIG: {
3977 r = -EFAULT;
3978 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3979 sizeof(struct kvm_xen_hvm_config)))
3980 goto out;
3981 r = -EINVAL;
3982 if (kvm->arch.xen_hvm_config.flags)
3983 goto out;
3984 r = 0;
3985 break;
3986 }
afbcf7ab 3987 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3988 struct kvm_clock_data user_ns;
3989 u64 now_ns;
3990 s64 delta;
3991
3992 r = -EFAULT;
3993 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3994 goto out;
3995
3996 r = -EINVAL;
3997 if (user_ns.flags)
3998 goto out;
3999
4000 r = 0;
395c6b0a 4001 local_irq_disable();
759379dd 4002 now_ns = get_kernel_ns();
afbcf7ab 4003 delta = user_ns.clock - now_ns;
395c6b0a 4004 local_irq_enable();
afbcf7ab 4005 kvm->arch.kvmclock_offset = delta;
2e762ff7 4006 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4007 break;
4008 }
4009 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4010 struct kvm_clock_data user_ns;
4011 u64 now_ns;
4012
395c6b0a 4013 local_irq_disable();
759379dd 4014 now_ns = get_kernel_ns();
afbcf7ab 4015 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4016 local_irq_enable();
afbcf7ab 4017 user_ns.flags = 0;
97e69aa6 4018 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4019
4020 r = -EFAULT;
4021 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4022 goto out;
4023 r = 0;
4024 break;
4025 }
90de4a18
NA		 4026 case KVM_ENABLE_CAP: {
4027 struct kvm_enable_cap cap;
afbcf7ab 4028
90de4a18
NA		 4029 r = -EFAULT;
4030 if (copy_from_user(&cap, argp, sizeof(cap)))
4031 goto out;
4032 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4033 break;
4034 }
1fe779f8 4035 default:
c274e03a 4036 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4037 }
4038out:
4039 return r;
4040}
4041
a16b043c 4042static void kvm_init_msr_list(void)
043405e1
CO		 4043{
4044 u32 dummy[2];
4045 unsigned i, j;
4046
62ef68bb 4047 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4048 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4049 continue;
93c4adc7
PB		 4050
4051 /*
4052 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4053 * to the guests in some cases.
93c4adc7
PB		 4054 */
4055 switch (msrs_to_save[i]) {
4056 case MSR_IA32_BNDCFGS:
4057 if (!kvm_x86_ops->mpx_supported())
4058 continue;
4059 break;
9dbe6cf9
PB		 4060 case MSR_TSC_AUX:
4061 if (!kvm_x86_ops->rdtscp_supported())
4062 continue;
4063 break;
93c4adc7
PB		 4064 default:
4065 break;
4066 }
4067
043405e1
CO		 4068 if (j < i)
4069 msrs_to_save[j] = msrs_to_save[i];
4070 j++;
4071 }
4072 num_msrs_to_save = j;
62ef68bb
PB		 4073
4074 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4075 switch (emulated_msrs[i]) {
6d396b55
PB		 4076 case MSR_IA32_SMBASE:
4077 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4078 continue;
4079 break;
62ef68bb
PB		 4080 default:
4081 break;
4082 }
4083
4084 if (j < i)
4085 emulated_msrs[j] = emulated_msrs[i];
4086 j++;
4087 }
4088 num_emulated_msrs = j;
043405e1
CO		 4089}
4090
bda9020e
MT		 4091static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4092 const void *v)
bbd9b64e 4093{
70252a10
AK		 4094 int handled = 0;
4095 int n;
4096
4097 do {
4098 n = min(len, 8);
bce87cce 4099 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4100 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4101 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4102 break;
4103 handled += n;
4104 addr += n;
4105 len -= n;
4106 v += n;
4107 } while (len);
bbd9b64e 4108
70252a10 4109 return handled;
bbd9b64e
CO		 4110}
4111
bda9020e 4112static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4113{
70252a10
AK		 4114 int handled = 0;
4115 int n;
4116
4117 do {
4118 n = min(len, 8);
bce87cce 4119 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4120 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4121 addr, n, v))
4122 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4123 break;
4124 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4125 handled += n;
4126 addr += n;
4127 len -= n;
4128 v += n;
4129 } while (len);
bbd9b64e 4130
70252a10 4131 return handled;
bbd9b64e
CO		 4132}
4133
2dafc6c2
GN		 4134static void kvm_set_segment(struct kvm_vcpu *vcpu,
4135 struct kvm_segment *var, int seg)
4136{
4137 kvm_x86_ops->set_segment(vcpu, var, seg);
4138}
4139
4140void kvm_get_segment(struct kvm_vcpu *vcpu,
4141 struct kvm_segment *var, int seg)
4142{
4143 kvm_x86_ops->get_segment(vcpu, var, seg);
4144}
4145
54987b7a
PB		 4146gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4147 struct x86_exception *exception)
02f59dc9
JR		 4148{
4149 gpa_t t_gpa;
02f59dc9
JR		 4150
4151 BUG_ON(!mmu_is_nested(vcpu));
4152
4153 /* NPT walks are always user-walks */
4154 access |= PFERR_USER_MASK;
54987b7a 4155 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4156
4157 return t_gpa;
4158}
4159
ab9ae313
AK		 4160gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4161 struct x86_exception *exception)
1871c602
GN		 4162{
4163 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4164 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4165}
4166
ab9ae313
AK		 4167 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4168 struct x86_exception *exception)
1871c602
GN		 4169{
4170 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4171 access |= PFERR_FETCH_MASK;
ab9ae313 4172 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4173}
4174
ab9ae313
AK		 4175gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4176 struct x86_exception *exception)
1871c602
GN		 4177{
4178 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4179 access |= PFERR_WRITE_MASK;
ab9ae313 4180 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4181}
4182
4183/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4184gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4185 struct x86_exception *exception)
1871c602 4186{
ab9ae313 4187 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4188}
4189
4190static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4191 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4192 struct x86_exception *exception)
bbd9b64e
CO		 4193{
4194 void *data = val;
10589a46 4195 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4196
4197 while (bytes) {
14dfe855 4198 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4199 exception);
bbd9b64e 4200 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4201 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4202 int ret;
4203
bcc55cba 4204 if (gpa == UNMAPPED_GVA)
ab9ae313 4205 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4206 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4207 offset, toread);
10589a46 4208 if (ret < 0) {
c3cd7ffa 4209 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4210 goto out;
4211 }
bbd9b64e 4212
77c2002e
IE		 4213 bytes -= toread;
4214 data += toread;
4215 addr += toread;
bbd9b64e 4216 }
10589a46 4217out:
10589a46 4218 return r;
bbd9b64e 4219}
77c2002e 4220
1871c602 4221/* used for instruction fetching */
0f65dd70
AK		 4222static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4223 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4224 struct x86_exception *exception)
1871c602 4225{
0f65dd70 4226 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4227 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4228 unsigned offset;
4229 int ret;
0f65dd70 4230
44583cba
PB		 4231 /* Inline kvm_read_guest_virt_helper for speed. */
4232 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4233 exception);
4234 if (unlikely(gpa == UNMAPPED_GVA))
4235 return X86EMUL_PROPAGATE_FAULT;
4236
4237 offset = addr & (PAGE_SIZE-1);
4238 if (WARN_ON(offset + bytes > PAGE_SIZE))
4239 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4240 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4241 offset, bytes);
44583cba
PB		 4242 if (unlikely(ret < 0))
4243 return X86EMUL_IO_NEEDED;
4244
4245 return X86EMUL_CONTINUE;
1871c602
GN		 4246}
4247
064aea77 4248int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4249 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4250 struct x86_exception *exception)
1871c602 4251{
0f65dd70 4252 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4253 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4254
1871c602 4255 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4256 exception);
1871c602 4257}
064aea77 4258EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4259
0f65dd70
AK		 4260static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4261 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4262 struct x86_exception *exception)
1871c602 4263{
0f65dd70 4264 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4265 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4266}
4267
7a036a6f
RK		 4268static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4269 unsigned long addr, void *val, unsigned int bytes)
4270{
4271 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4272 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4273
4274 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4275}
4276
6a4d7550 4277int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4278 gva_t addr, void *val,
2dafc6c2 4279 unsigned int bytes,
bcc55cba 4280 struct x86_exception *exception)
77c2002e 4281{
0f65dd70 4282 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4283 void *data = val;
4284 int r = X86EMUL_CONTINUE;
4285
4286 while (bytes) {
14dfe855
JR		 4287 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4288 PFERR_WRITE_MASK,
ab9ae313 4289 exception);
77c2002e
IE		 4290 unsigned offset = addr & (PAGE_SIZE-1);
4291 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4292 int ret;
4293
bcc55cba 4294 if (gpa == UNMAPPED_GVA)
ab9ae313 4295 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4296 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4297 if (ret < 0) {
c3cd7ffa 4298 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4299 goto out;
4300 }
4301
4302 bytes -= towrite;
4303 data += towrite;
4304 addr += towrite;
4305 }
4306out:
4307 return r;
4308}
6a4d7550 4309EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4310
af7cc7d1
XG		 4311static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4312 gpa_t *gpa, struct x86_exception *exception,
4313 bool write)
4314{
97d64b78
AK		 4315 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4316 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4317
be94f6b7
HH		 4318 /*
4319 * currently PKRU is only applied to ept enabled guest so
4320 * there is no pkey in EPT page table for L1 guest or EPT
4321 * shadow page table for L2 guest.
4322 */
97d64b78 4323 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4324 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4325 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4326 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4327 (gva & (PAGE_SIZE - 1));
4f022648 4328 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4329 return 1;
4330 }
4331
af7cc7d1
XG		 4332 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4333
4334 if (*gpa == UNMAPPED_GVA)
4335 return -1;
4336
4337 /* For APIC access vmexit */
4338 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4339 return 1;
4340
4f022648
XG		 4341 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4342 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4343 return 1;
4f022648 4344 }
bebb106a 4345
af7cc7d1
XG		 4346 return 0;
4347}
4348
3200f405 4349int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4350 const void *val, int bytes)
bbd9b64e
CO		 4351{
4352 int ret;
4353
54bf36aa 4354 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4355 if (ret < 0)
bbd9b64e 4356 return 0;
0eb05bf2 4357 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4358 return 1;
4359}
4360
77d197b2
XG		 4361struct read_write_emulator_ops {
4362 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4363 int bytes);
4364 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4365 void *val, int bytes);
4366 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4367 int bytes, void *val);
4368 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4369 void *val, int bytes);
4370 bool write;
4371};
4372
4373static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4374{
4375 if (vcpu->mmio_read_completed) {
77d197b2 4376 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4377 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4378 vcpu->mmio_read_completed = 0;
4379 return 1;
4380 }
4381
4382 return 0;
4383}
4384
4385static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4386 void *val, int bytes)
4387{
54bf36aa 4388 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4389}
4390
4391static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4392 void *val, int bytes)
4393{
4394 return emulator_write_phys(vcpu, gpa, val, bytes);
4395}
4396
4397static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4398{
4399 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4400 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4401}
4402
4403static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4404 void *val, int bytes)
4405{
4406 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4407 return X86EMUL_IO_NEEDED;
4408}
4409
4410static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4411 void *val, int bytes)
4412{
f78146b0
AK		 4413 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4414
87da7e66 4415 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4416 return X86EMUL_CONTINUE;
4417}
4418
0fbe9b0b 4419static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4420 .read_write_prepare = read_prepare,
4421 .read_write_emulate = read_emulate,
4422 .read_write_mmio = vcpu_mmio_read,
4423 .read_write_exit_mmio = read_exit_mmio,
4424};
4425
0fbe9b0b 4426static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4427 .read_write_emulate = write_emulate,
4428 .read_write_mmio = write_mmio,
4429 .read_write_exit_mmio = write_exit_mmio,
4430 .write = true,
4431};
4432
22388a3c
XG		 4433static int emulator_read_write_onepage(unsigned long addr, void *val,
4434 unsigned int bytes,
4435 struct x86_exception *exception,
4436 struct kvm_vcpu *vcpu,
0fbe9b0b 4437 const struct read_write_emulator_ops *ops)
bbd9b64e 4438{
af7cc7d1
XG		 4439 gpa_t gpa;
4440 int handled, ret;
22388a3c 4441 bool write = ops->write;
f78146b0 4442 struct kvm_mmio_fragment *frag;
10589a46 4443
22388a3c 4444 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4445
af7cc7d1 4446 if (ret < 0)
bbd9b64e 4447 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4448
4449 /* For APIC access vmexit */
af7cc7d1 4450 if (ret)
bbd9b64e
CO		 4451 goto mmio;
4452
22388a3c 4453 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4454 return X86EMUL_CONTINUE;
4455
4456mmio:
4457 /*
4458 * Is this MMIO handled locally?
4459 */
22388a3c 4460 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4461 if (handled == bytes)
bbd9b64e 4462 return X86EMUL_CONTINUE;
bbd9b64e 4463
70252a10
AK		 4464 gpa += handled;
4465 bytes -= handled;
4466 val += handled;
4467
87da7e66
XG		 4468 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4469 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4470 frag->gpa = gpa;
4471 frag->data = val;
4472 frag->len = bytes;
f78146b0 4473 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4474}
4475
52eb5a6d
XL		 4476static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4477 unsigned long addr,
22388a3c
XG		 4478 void *val, unsigned int bytes,
4479 struct x86_exception *exception,
0fbe9b0b 4480 const struct read_write_emulator_ops *ops)
bbd9b64e 4481{
0f65dd70 4482 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4483 gpa_t gpa;
4484 int rc;
4485
4486 if (ops->read_write_prepare &&
4487 ops->read_write_prepare(vcpu, val, bytes))
4488 return X86EMUL_CONTINUE;
4489
4490 vcpu->mmio_nr_fragments = 0;
0f65dd70 4491
bbd9b64e
CO		 4492 /* Crossing a page boundary? */
4493 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4494 int now;
bbd9b64e
CO		 4495
4496 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4497 rc = emulator_read_write_onepage(addr, val, now, exception,
4498 vcpu, ops);
4499
bbd9b64e
CO		 4500 if (rc != X86EMUL_CONTINUE)
4501 return rc;
4502 addr += now;
bac15531
NA		 4503 if (ctxt->mode != X86EMUL_MODE_PROT64)
4504 addr = (u32)addr;
bbd9b64e
CO		 4505 val += now;
4506 bytes -= now;
4507 }
22388a3c 4508
f78146b0
AK		 4509 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4510 vcpu, ops);
4511 if (rc != X86EMUL_CONTINUE)
4512 return rc;
4513
4514 if (!vcpu->mmio_nr_fragments)
4515 return rc;
4516
4517 gpa = vcpu->mmio_fragments[0].gpa;
4518
4519 vcpu->mmio_needed = 1;
4520 vcpu->mmio_cur_fragment = 0;
4521
87da7e66 4522 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4523 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4524 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4525 vcpu->run->mmio.phys_addr = gpa;
4526
4527 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4528}
4529
4530static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4531 unsigned long addr,
4532 void *val,
4533 unsigned int bytes,
4534 struct x86_exception *exception)
4535{
4536 return emulator_read_write(ctxt, addr, val, bytes,
4537 exception, &read_emultor);
4538}
4539
52eb5a6d 4540static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4541 unsigned long addr,
4542 const void *val,
4543 unsigned int bytes,
4544 struct x86_exception *exception)
4545{
4546 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4547 exception, &write_emultor);
bbd9b64e 4548}
bbd9b64e 4549
daea3e73
AK		 4550#define CMPXCHG_TYPE(t, ptr, old, new) \
4551 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4552
4553#ifdef CONFIG_X86_64
4554# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4555#else
4556# define CMPXCHG64(ptr, old, new) \
9749a6c0 4557 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4558#endif
4559
0f65dd70
AK		 4560static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4561 unsigned long addr,
bbd9b64e
CO		 4562 const void *old,
4563 const void *new,
4564 unsigned int bytes,
0f65dd70 4565 struct x86_exception *exception)
bbd9b64e 4566{
0f65dd70 4567 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4568 gpa_t gpa;
4569 struct page *page;
4570 char *kaddr;
4571 bool exchanged;
2bacc55c 4572
daea3e73
AK		 4573 /* guests cmpxchg8b have to be emulated atomically */
4574 if (bytes > 8 || (bytes & (bytes - 1)))
4575 goto emul_write;
10589a46 4576
daea3e73 4577 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4578
daea3e73
AK		 4579 if (gpa == UNMAPPED_GVA ||
4580 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4581 goto emul_write;
2bacc55c 4582
daea3e73
AK		 4583 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4584 goto emul_write;
72dc67a6 4585
54bf36aa 4586 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4587 if (is_error_page(page))
c19b8bd6 4588 goto emul_write;
72dc67a6 4589
8fd75e12 4590 kaddr = kmap_atomic(page);
daea3e73
AK		 4591 kaddr += offset_in_page(gpa);
4592 switch (bytes) {
4593 case 1:
4594 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4595 break;
4596 case 2:
4597 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4598 break;
4599 case 4:
4600 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4601 break;
4602 case 8:
4603 exchanged = CMPXCHG64(kaddr, old, new);
4604 break;
4605 default:
4606 BUG();
2bacc55c 4607 }
8fd75e12 4608 kunmap_atomic(kaddr);
daea3e73
AK		 4609 kvm_release_page_dirty(page);
4610
4611 if (!exchanged)
4612 return X86EMUL_CMPXCHG_FAILED;
4613
54bf36aa 4614 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4615 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4616
4617 return X86EMUL_CONTINUE;
4a5f48f6 4618
3200f405 4619emul_write:
daea3e73 4620 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4621
0f65dd70 4622 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4623}
4624
cf8f70bf
GN		 4625static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4626{
4627 /* TODO: String I/O for in kernel device */
4628 int r;
4629
4630 if (vcpu->arch.pio.in)
e32edf4f 4631 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4632 vcpu->arch.pio.size, pd);
4633 else
e32edf4f 4634 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4635 vcpu->arch.pio.port, vcpu->arch.pio.size,
4636 pd);
4637 return r;
4638}
4639
6f6fbe98
XG		 4640static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4641 unsigned short port, void *val,
4642 unsigned int count, bool in)
cf8f70bf 4643{
cf8f70bf 4644 vcpu->arch.pio.port = port;
6f6fbe98 4645 vcpu->arch.pio.in = in;
7972995b 4646 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4647 vcpu->arch.pio.size = size;
4648
4649 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4650 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4651 return 1;
4652 }
4653
4654 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4655 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4656 vcpu->run->io.size = size;
4657 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4658 vcpu->run->io.count = count;
4659 vcpu->run->io.port = port;
4660
4661 return 0;
4662}
4663
6f6fbe98
XG		 4664static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4665 int size, unsigned short port, void *val,
4666 unsigned int count)
cf8f70bf 4667{
ca1d4a9e 4668 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4669 int ret;
ca1d4a9e 4670
6f6fbe98
XG		 4671 if (vcpu->arch.pio.count)
4672 goto data_avail;
cf8f70bf 4673
6f6fbe98
XG		 4674 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4675 if (ret) {
4676data_avail:
4677 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4678 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4679 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4680 return 1;
4681 }
4682
cf8f70bf
GN		 4683 return 0;
4684}
4685
6f6fbe98
XG		 4686static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4687 int size, unsigned short port,
4688 const void *val, unsigned int count)
4689{
4690 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4691
4692 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4693 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4694 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4695}
4696
bbd9b64e
CO		 4697static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4698{
4699 return kvm_x86_ops->get_segment_base(vcpu, seg);
4700}
4701
3cb16fe7 4702static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4703{
3cb16fe7 4704 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4705}
4706
5cb56059 4707int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4708{
4709 if (!need_emulate_wbinvd(vcpu))
4710 return X86EMUL_CONTINUE;
4711
4712 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4713 int cpu = get_cpu();
4714
4715 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4716 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4717 wbinvd_ipi, NULL, 1);
2eec7343 4718 put_cpu();
f5f48ee1 4719 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4720 } else
4721 wbinvd();
f5f48ee1
SY		 4722 return X86EMUL_CONTINUE;
4723}
5cb56059
JS		 4724
4725int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4726{
4727 kvm_x86_ops->skip_emulated_instruction(vcpu);
4728 return kvm_emulate_wbinvd_noskip(vcpu);
4729}
f5f48ee1
SY		 4730EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4731
5cb56059
JS		 4732
4733
bcaf5cc5
AK		 4734static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4735{
5cb56059 4736 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4737}
4738
52eb5a6d
XL		 4739static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4740 unsigned long *dest)
bbd9b64e 4741{
16f8a6f9 4742 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4743}
4744
52eb5a6d
XL		 4745static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4746 unsigned long value)
bbd9b64e 4747{
338dbc97 4748
717746e3 4749 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4750}
4751
52a46617 4752static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4753{
52a46617 4754 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4755}
4756
717746e3 4757static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4758{
717746e3 4759 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4760 unsigned long value;
4761
4762 switch (cr) {
4763 case 0:
4764 value = kvm_read_cr0(vcpu);
4765 break;
4766 case 2:
4767 value = vcpu->arch.cr2;
4768 break;
4769 case 3:
9f8fe504 4770 value = kvm_read_cr3(vcpu);
52a46617
GN		 4771 break;
4772 case 4:
4773 value = kvm_read_cr4(vcpu);
4774 break;
4775 case 8:
4776 value = kvm_get_cr8(vcpu);
4777 break;
4778 default:
a737f256 4779 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4780 return 0;
4781 }
4782
4783 return value;
4784}
4785
717746e3 4786static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4787{
717746e3 4788 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4789 int res = 0;
4790
52a46617
GN		 4791 switch (cr) {
4792 case 0:
49a9b07e 4793 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4794 break;
4795 case 2:
4796 vcpu->arch.cr2 = val;
4797 break;
4798 case 3:
2390218b 4799 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4800 break;
4801 case 4:
a83b29c6 4802 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4803 break;
4804 case 8:
eea1cff9 4805 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4806 break;
4807 default:
a737f256 4808 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4809 res = -1;
52a46617 4810 }
0f12244f
GN		 4811
4812 return res;
52a46617
GN		 4813}
4814
717746e3 4815static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4816{
717746e3 4817 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4818}
4819
4bff1e86 4820static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4821{
4bff1e86 4822 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4823}
4824
4bff1e86 4825static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4826{
4bff1e86 4827 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4828}
4829
1ac9d0cf
AK		 4830static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4831{
4832 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4833}
4834
4835static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4836{
4837 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4838}
4839
4bff1e86
AK		 4840static unsigned long emulator_get_cached_segment_base(
4841 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4842{
4bff1e86 4843 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4844}
4845
1aa36616
AK		 4846static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4847 struct desc_struct *desc, u32 *base3,
4848 int seg)
2dafc6c2
GN		 4849{
4850 struct kvm_segment var;
4851
4bff1e86 4852 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4853 *selector = var.selector;
2dafc6c2 4854
378a8b09
GN		 4855 if (var.unusable) {
4856 memset(desc, 0, sizeof(*desc));
2dafc6c2 4857 return false;
378a8b09 4858 }
2dafc6c2
GN		 4859
4860 if (var.g)
4861 var.limit >>= 12;
4862 set_desc_limit(desc, var.limit);
4863 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4864#ifdef CONFIG_X86_64
4865 if (base3)
4866 *base3 = var.base >> 32;
4867#endif
2dafc6c2
GN		 4868 desc->type = var.type;
4869 desc->s = var.s;
4870 desc->dpl = var.dpl;
4871 desc->p = var.present;
4872 desc->avl = var.avl;
4873 desc->l = var.l;
4874 desc->d = var.db;
4875 desc->g = var.g;
4876
4877 return true;
4878}
4879
1aa36616
AK		 4880static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4881 struct desc_struct *desc, u32 base3,
4882 int seg)
2dafc6c2 4883{
4bff1e86 4884 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4885 struct kvm_segment var;
4886
1aa36616 4887 var.selector = selector;
2dafc6c2 4888 var.base = get_desc_base(desc);
5601d05b
GN		 4889#ifdef CONFIG_X86_64
4890 var.base |= ((u64)base3) << 32;
4891#endif
2dafc6c2
GN		 4892 var.limit = get_desc_limit(desc);
4893 if (desc->g)
4894 var.limit = (var.limit << 12) | 0xfff;
4895 var.type = desc->type;
2dafc6c2
GN		 4896 var.dpl = desc->dpl;
4897 var.db = desc->d;
4898 var.s = desc->s;
4899 var.l = desc->l;
4900 var.g = desc->g;
4901 var.avl = desc->avl;
4902 var.present = desc->p;
4903 var.unusable = !var.present;
4904 var.padding = 0;
4905
4906 kvm_set_segment(vcpu, &var, seg);
4907 return;
4908}
4909
717746e3
AK		 4910static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4911 u32 msr_index, u64 *pdata)
4912{
609e36d3
PB		 4913 struct msr_data msr;
4914 int r;
4915
4916 msr.index = msr_index;
4917 msr.host_initiated = false;
4918 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4919 if (r)
4920 return r;
4921
4922 *pdata = msr.data;
4923 return 0;
717746e3
AK		 4924}
4925
4926static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4927 u32 msr_index, u64 data)
4928{
8fe8ab46
WA		 4929 struct msr_data msr;
4930
4931 msr.data = data;
4932 msr.index = msr_index;
4933 msr.host_initiated = false;
4934 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4935}
4936
64d60670
PB		 4937static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4938{
4939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4940
4941 return vcpu->arch.smbase;
4942}
4943
4944static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4945{
4946 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4947
4948 vcpu->arch.smbase = smbase;
4949}
4950
67f4d428
NA		 4951static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4952 u32 pmc)
4953{
c6702c9d 4954 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4955}
4956
222d21aa
AK		 4957static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4958 u32 pmc, u64 *pdata)
4959{
c6702c9d 4960 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4961}
4962
6c3287f7
AK		 4963static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4964{
4965 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4966}
4967
5037f6f3
AK		 4968static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4969{
4970 preempt_disable();
5197b808 4971 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4972 /*
4973 * CR0.TS may reference the host fpu state, not the guest fpu state,
4974 * so it may be clear at this point.
4975 */
4976 clts();
4977}
4978
4979static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4980{
4981 preempt_enable();
4982}
4983
2953538e 4984static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4985 struct x86_instruction_info *info,
c4f035c6
AK		 4986 enum x86_intercept_stage stage)
4987{
2953538e 4988 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4989}
4990
0017f93a 4991static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4992 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4993{
0017f93a 4994 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4995}
4996
dd856efa
AK		 4997static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4998{
4999 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5000}
5001
5002static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5003{
5004 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5005}
5006
801806d9
NA		 5007static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5008{
5009 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5010}
5011
0225fb50 5012static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5013 .read_gpr = emulator_read_gpr,
5014 .write_gpr = emulator_write_gpr,
1871c602 5015 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5016 .write_std = kvm_write_guest_virt_system,
7a036a6f 5017 .read_phys = kvm_read_guest_phys_system,
1871c602 5018 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5019 .read_emulated = emulator_read_emulated,
5020 .write_emulated = emulator_write_emulated,
5021 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5022 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5023 .pio_in_emulated = emulator_pio_in_emulated,
5024 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5025 .get_segment = emulator_get_segment,
5026 .set_segment = emulator_set_segment,
5951c442 5027 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5028 .get_gdt = emulator_get_gdt,
160ce1f1 5029 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5030 .set_gdt = emulator_set_gdt,
5031 .set_idt = emulator_set_idt,
52a46617
GN		 5032 .get_cr = emulator_get_cr,
5033 .set_cr = emulator_set_cr,
9c537244 5034 .cpl = emulator_get_cpl,
35aa5375
GN		 5035 .get_dr = emulator_get_dr,
5036 .set_dr = emulator_set_dr,
64d60670
PB		 5037 .get_smbase = emulator_get_smbase,
5038 .set_smbase = emulator_set_smbase,
717746e3
AK		 5039 .set_msr = emulator_set_msr,
5040 .get_msr = emulator_get_msr,
67f4d428 5041 .check_pmc = emulator_check_pmc,
222d21aa 5042 .read_pmc = emulator_read_pmc,
6c3287f7 5043 .halt = emulator_halt,
bcaf5cc5 5044 .wbinvd = emulator_wbinvd,
d6aa1000 5045 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5046 .get_fpu = emulator_get_fpu,
5047 .put_fpu = emulator_put_fpu,
c4f035c6 5048 .intercept = emulator_intercept,
bdb42f5a 5049 .get_cpuid = emulator_get_cpuid,
801806d9 5050 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5051};
5052
95cb2295
GN		 5053static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5054{
37ccdcbe 5055 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5056 /*
5057 * an sti; sti; sequence only disable interrupts for the first
5058 * instruction. So, if the last instruction, be it emulated or
5059 * not, left the system with the INT_STI flag enabled, it
5060 * means that the last instruction is an sti. We should not
5061 * leave the flag on in this case. The same goes for mov ss
5062 */
37ccdcbe
PB		 5063 if (int_shadow & mask)
5064 mask = 0;
6addfc42 5065 if (unlikely(int_shadow || mask)) {
95cb2295 5066 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5067 if (!mask)
5068 kvm_make_request(KVM_REQ_EVENT, vcpu);
5069 }
95cb2295
GN		 5070}
5071
ef54bcfe 5072static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5073{
5074 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5075 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5076 return kvm_propagate_fault(vcpu, &ctxt->exception);
5077
5078 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5079 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5080 ctxt->exception.error_code);
54b8486f 5081 else
da9cb575 5082 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5083 return false;
54b8486f
GN		 5084}
5085
8ec4722d
MG		 5086static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5087{
adf52235 5088 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5089 int cs_db, cs_l;
5090
8ec4722d
MG		 5091 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5092
adf52235
TY		 5093 ctxt->eflags = kvm_get_rflags(vcpu);
5094 ctxt->eip = kvm_rip_read(vcpu);
5095 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5096 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5097 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5098 cs_db ? X86EMUL_MODE_PROT32 :
5099 X86EMUL_MODE_PROT16;
a584539b 5100 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5101 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5102 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5103 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5104
dd856efa 5105 init_decode_cache(ctxt);
7ae441ea 5106 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5107}
5108
71f9833b 5109int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5110{
9d74191a 5111 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5112 int ret;
5113
5114 init_emulate_ctxt(vcpu);
5115
9dac77fa
AK		 5116 ctxt->op_bytes = 2;
5117 ctxt->ad_bytes = 2;
5118 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5119 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5120
5121 if (ret != X86EMUL_CONTINUE)
5122 return EMULATE_FAIL;
5123
9dac77fa 5124 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5125 kvm_rip_write(vcpu, ctxt->eip);
5126 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5127
5128 if (irq == NMI_VECTOR)
7460fb4a 5129 vcpu->arch.nmi_pending = 0;
63995653
MG		 5130 else
5131 vcpu->arch.interrupt.pending = false;
5132
5133 return EMULATE_DONE;
5134}
5135EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5136
6d77dbfc
GN		 5137static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5138{
fc3a9157
JR		 5139 int r = EMULATE_DONE;
5140
6d77dbfc
GN		 5141 ++vcpu->stat.insn_emulation_fail;
5142 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5143 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5144 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5145 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5146 vcpu->run->internal.ndata = 0;
5147 r = EMULATE_FAIL;
5148 }
6d77dbfc 5149 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5150
5151 return r;
6d77dbfc
GN		 5152}
5153
93c05d3e 5154static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5155 bool write_fault_to_shadow_pgtable,
5156 int emulation_type)
a6f177ef 5157{
95b3cf69 5158 gpa_t gpa = cr2;
ba049e93 5159 kvm_pfn_t pfn;
a6f177ef 5160
991eebf9
GN		 5161 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5162 return false;
5163
95b3cf69
XG		 5164 if (!vcpu->arch.mmu.direct_map) {
5165 /*
5166 * Write permission should be allowed since only
5167 * write access need to be emulated.
5168 */
5169 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5170
95b3cf69
XG		 5171 /*
5172 * If the mapping is invalid in guest, let cpu retry
5173 * it to generate fault.
5174 */
5175 if (gpa == UNMAPPED_GVA)
5176 return true;
5177 }
a6f177ef 5178
8e3d9d06
XG		 5179 /*
5180 * Do not retry the unhandleable instruction if it faults on the
5181 * readonly host memory, otherwise it will goto a infinite loop:
5182 * retry instruction -> write #PF -> emulation fail -> retry
5183 * instruction -> ...
5184 */
5185 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5186
5187 /*
5188 * If the instruction failed on the error pfn, it can not be fixed,
5189 * report the error to userspace.
5190 */
5191 if (is_error_noslot_pfn(pfn))
5192 return false;
5193
5194 kvm_release_pfn_clean(pfn);
5195
5196 /* The instructions are well-emulated on direct mmu. */
5197 if (vcpu->arch.mmu.direct_map) {
5198 unsigned int indirect_shadow_pages;
5199
5200 spin_lock(&vcpu->kvm->mmu_lock);
5201 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5202 spin_unlock(&vcpu->kvm->mmu_lock);
5203
5204 if (indirect_shadow_pages)
5205 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5206
a6f177ef 5207 return true;
8e3d9d06 5208 }
a6f177ef 5209
95b3cf69
XG		 5210 /*
5211 * if emulation was due to access to shadowed page table
5212 * and it failed try to unshadow page and re-enter the
5213 * guest to let CPU execute the instruction.
5214 */
5215 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5216
5217 /*
5218 * If the access faults on its page table, it can not
5219 * be fixed by unprotecting shadow page and it should
5220 * be reported to userspace.
5221 */
5222 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5223}
5224
1cb3f3ae
XG		 5225static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5226 unsigned long cr2, int emulation_type)
5227{
5228 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5229 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5230
5231 last_retry_eip = vcpu->arch.last_retry_eip;
5232 last_retry_addr = vcpu->arch.last_retry_addr;
5233
5234 /*
5235 * If the emulation is caused by #PF and it is non-page_table
5236 * writing instruction, it means the VM-EXIT is caused by shadow
5237 * page protected, we can zap the shadow page and retry this
5238 * instruction directly.
5239 *
5240 * Note: if the guest uses a non-page-table modifying instruction
5241 * on the PDE that points to the instruction, then we will unmap
5242 * the instruction and go to an infinite loop. So, we cache the
5243 * last retried eip and the last fault address, if we meet the eip
5244 * and the address again, we can break out of the potential infinite
5245 * loop.
5246 */
5247 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5248
5249 if (!(emulation_type & EMULTYPE_RETRY))
5250 return false;
5251
5252 if (x86_page_table_writing_insn(ctxt))
5253 return false;
5254
5255 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5256 return false;
5257
5258 vcpu->arch.last_retry_eip = ctxt->eip;
5259 vcpu->arch.last_retry_addr = cr2;
5260
5261 if (!vcpu->arch.mmu.direct_map)
5262 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5263
22368028 5264 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5265
5266 return true;
5267}
5268
716d51ab
GN		 5269static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5270static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5271
64d60670 5272static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5273{
64d60670 5274 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5275 /* This is a good place to trace that we are exiting SMM. */
5276 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5277
64d60670
PB		 5278 if (unlikely(vcpu->arch.smi_pending)) {
5279 kvm_make_request(KVM_REQ_SMI, vcpu);
5280 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5281 } else {
5282 /* Process a latched INIT, if any. */
5283 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5284 }
5285 }
699023e2
PB		 5286
5287 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5288}
5289
5290static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5291{
5292 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5293
a584539b 5294 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5295
5296 if (changed & HF_SMM_MASK)
5297 kvm_smm_changed(vcpu);
a584539b
PB		 5298}
5299
4a1e10d5
PB		 5300static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5301 unsigned long *db)
5302{
5303 u32 dr6 = 0;
5304 int i;
5305 u32 enable, rwlen;
5306
5307 enable = dr7;
5308 rwlen = dr7 >> 16;
5309 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5310 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5311 dr6 |= (1 << i);
5312 return dr6;
5313}
5314
6addfc42 5315static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5316{
5317 struct kvm_run *kvm_run = vcpu->run;
5318
5319 /*
6addfc42
PB		 5320 * rflags is the old, "raw" value of the flags. The new value has
5321 * not been saved yet.
663f4c61
PB		 5322 *
5323 * This is correct even for TF set by the guest, because "the
5324 * processor will not generate this exception after the instruction
5325 * that sets the TF flag".
5326 */
663f4c61
PB		 5327 if (unlikely(rflags & X86_EFLAGS_TF)) {
5328 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5329 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5330 DR6_RTM;
663f4c61
PB		 5331 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5332 kvm_run->debug.arch.exception = DB_VECTOR;
5333 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5334 *r = EMULATE_USER_EXIT;
5335 } else {
5336 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5337 /*
5338 * "Certain debug exceptions may clear bit 0-3. The
5339 * remaining contents of the DR6 register are never
5340 * cleared by the processor".
5341 */
5342 vcpu->arch.dr6 &= ~15;
6f43ed01 5343 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5344 kvm_queue_exception(vcpu, DB_VECTOR);
5345 }
5346 }
5347}
5348
4a1e10d5
PB		 5349static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5350{
4a1e10d5
PB		 5351 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5352 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5353 struct kvm_run *kvm_run = vcpu->run;
5354 unsigned long eip = kvm_get_linear_rip(vcpu);
5355 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5356 vcpu->arch.guest_debug_dr7,
5357 vcpu->arch.eff_db);
5358
5359 if (dr6 != 0) {
6f43ed01 5360 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5361 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5362 kvm_run->debug.arch.exception = DB_VECTOR;
5363 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5364 *r = EMULATE_USER_EXIT;
5365 return true;
5366 }
5367 }
5368
4161a569
NA		 5369 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5370 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5371 unsigned long eip = kvm_get_linear_rip(vcpu);
5372 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5373 vcpu->arch.dr7,
5374 vcpu->arch.db);
5375
5376 if (dr6 != 0) {
5377 vcpu->arch.dr6 &= ~15;
6f43ed01 5378 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5379 kvm_queue_exception(vcpu, DB_VECTOR);
5380 *r = EMULATE_DONE;
5381 return true;
5382 }
5383 }
5384
5385 return false;
5386}
5387
51d8b661
AP		 5388int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5389 unsigned long cr2,
dc25e89e
AP		 5390 int emulation_type,
5391 void *insn,
5392 int insn_len)
bbd9b64e 5393{
95cb2295 5394 int r;
9d74191a 5395 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5396 bool writeback = true;
93c05d3e 5397 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5398
93c05d3e
XG		 5399 /*
5400 * Clear write_fault_to_shadow_pgtable here to ensure it is
5401 * never reused.
5402 */
5403 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5404 kvm_clear_exception_queue(vcpu);
8d7d8102 5405
571008da 5406 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5407 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5408
5409 /*
5410 * We will reenter on the same instruction since
5411 * we do not set complete_userspace_io. This does not
5412 * handle watchpoints yet, those would be handled in
5413 * the emulate_ops.
5414 */
5415 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5416 return r;
5417
9d74191a
TY		 5418 ctxt->interruptibility = 0;
5419 ctxt->have_exception = false;
e0ad0b47 5420 ctxt->exception.vector = -1;
9d74191a 5421 ctxt->perm_ok = false;
bbd9b64e 5422
b51e974f 5423 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5424
9d74191a 5425 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5426
e46479f8 5427 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5428 ++vcpu->stat.insn_emulation;
1d2887e2 5429 if (r != EMULATION_OK) {
4005996e
AK		 5430 if (emulation_type & EMULTYPE_TRAP_UD)
5431 return EMULATE_FAIL;
991eebf9
GN		 5432 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5433 emulation_type))
bbd9b64e 5434 return EMULATE_DONE;
6d77dbfc
GN		 5435 if (emulation_type & EMULTYPE_SKIP)
5436 return EMULATE_FAIL;
5437 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5438 }
5439 }
5440
ba8afb6b 5441 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5442 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5443 if (ctxt->eflags & X86_EFLAGS_RF)
5444 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5445 return EMULATE_DONE;
5446 }
5447
1cb3f3ae
XG		 5448 if (retry_instruction(ctxt, cr2, emulation_type))
5449 return EMULATE_DONE;
5450
7ae441ea 5451 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5452 changes registers values during IO operation */
7ae441ea
GN		 5453 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5454 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5455 emulator_invalidate_register_cache(ctxt);
7ae441ea 5456 }
4d2179e1 5457
5cd21917 5458restart:
9d74191a 5459 r = x86_emulate_insn(ctxt);
bbd9b64e 5460
775fde86
JR		 5461 if (r == EMULATION_INTERCEPTED)
5462 return EMULATE_DONE;
5463
d2ddd1c4 5464 if (r == EMULATION_FAILED) {
991eebf9
GN		 5465 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5466 emulation_type))
c3cd7ffa
GN		 5467 return EMULATE_DONE;
5468
6d77dbfc 5469 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5470 }
5471
9d74191a 5472 if (ctxt->have_exception) {
d2ddd1c4 5473 r = EMULATE_DONE;
ef54bcfe
PB		 5474 if (inject_emulated_exception(vcpu))
5475 return r;
d2ddd1c4 5476 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5477 if (!vcpu->arch.pio.in) {
5478 /* FIXME: return into emulator if single-stepping. */
3457e419 5479 vcpu->arch.pio.count = 0;
0912c977 5480 } else {
7ae441ea 5481 writeback = false;
716d51ab
GN		 5482 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5483 }
ac0a48c3 5484 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5485 } else if (vcpu->mmio_needed) {
5486 if (!vcpu->mmio_is_write)
5487 writeback = false;
ac0a48c3 5488 r = EMULATE_USER_EXIT;
716d51ab 5489 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5490 } else if (r == EMULATION_RESTART)
5cd21917 5491 goto restart;
d2ddd1c4
GN		 5492 else
5493 r = EMULATE_DONE;
f850e2e6 5494
7ae441ea 5495 if (writeback) {
6addfc42 5496 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5497 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5498 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5499 if (vcpu->arch.hflags != ctxt->emul_flags)
5500 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5501 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5502 if (r == EMULATE_DONE)
6addfc42 5503 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5504 if (!ctxt->have_exception ||
5505 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5506 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5507
5508 /*
5509 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5510 * do nothing, and it will be requested again as soon as
5511 * the shadow expires. But we still need to check here,
5512 * because POPF has no interrupt shadow.
5513 */
5514 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5515 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5516 } else
5517 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5518
5519 return r;
de7d789a 5520}
51d8b661 5521EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5522
cf8f70bf 5523int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5524{
cf8f70bf 5525 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5526 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5527 size, port, &val, 1);
cf8f70bf 5528 /* do not return to emulator after return from userspace */
7972995b 5529 vcpu->arch.pio.count = 0;
de7d789a
CO		 5530 return ret;
5531}
cf8f70bf 5532EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5533
8cfdc000
ZA		 5534static void tsc_bad(void *info)
5535{
0a3aee0d 5536 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5537}
5538
5539static void tsc_khz_changed(void *data)
c8076604 5540{
8cfdc000
ZA		 5541 struct cpufreq_freqs *freq = data;
5542 unsigned long khz = 0;
5543
5544 if (data)
5545 khz = freq->new;
5546 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5547 khz = cpufreq_quick_get(raw_smp_processor_id());
5548 if (!khz)
5549 khz = tsc_khz;
0a3aee0d 5550 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5551}
5552
c8076604
GH		 5553static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5554 void *data)
5555{
5556 struct cpufreq_freqs *freq = data;
5557 struct kvm *kvm;
5558 struct kvm_vcpu *vcpu;
5559 int i, send_ipi = 0;
5560
8cfdc000
ZA		 5561 /*
5562 * We allow guests to temporarily run on slowing clocks,
5563 * provided we notify them after, or to run on accelerating
5564 * clocks, provided we notify them before. Thus time never
5565 * goes backwards.
5566 *
5567 * However, we have a problem. We can't atomically update
5568 * the frequency of a given CPU from this function; it is
5569 * merely a notifier, which can be called from any CPU.
5570 * Changing the TSC frequency at arbitrary points in time
5571 * requires a recomputation of local variables related to
5572 * the TSC for each VCPU. We must flag these local variables
5573 * to be updated and be sure the update takes place with the
5574 * new frequency before any guests proceed.
5575 *
5576 * Unfortunately, the combination of hotplug CPU and frequency
5577 * change creates an intractable locking scenario; the order
5578 * of when these callouts happen is undefined with respect to
5579 * CPU hotplug, and they can race with each other. As such,
5580 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5581 * undefined; you can actually have a CPU frequency change take
5582 * place in between the computation of X and the setting of the
5583 * variable. To protect against this problem, all updates of
5584 * the per_cpu tsc_khz variable are done in an interrupt
5585 * protected IPI, and all callers wishing to update the value
5586 * must wait for a synchronous IPI to complete (which is trivial
5587 * if the caller is on the CPU already). This establishes the
5588 * necessary total order on variable updates.
5589 *
5590 * Note that because a guest time update may take place
5591 * anytime after the setting of the VCPU's request bit, the
5592 * correct TSC value must be set before the request. However,
5593 * to ensure the update actually makes it to any guest which
5594 * starts running in hardware virtualization between the set
5595 * and the acquisition of the spinlock, we must also ping the
5596 * CPU after setting the request bit.
5597 *
5598 */
5599
c8076604
GH		 5600 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5601 return 0;
5602 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5603 return 0;
8cfdc000
ZA		 5604
5605 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5606
2f303b74 5607 spin_lock(&kvm_lock);
c8076604 5608 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5609 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5610 if (vcpu->cpu != freq->cpu)
5611 continue;
c285545f 5612 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5613 if (vcpu->cpu != smp_processor_id())
8cfdc000 5614 send_ipi = 1;
c8076604
GH		 5615 }
5616 }
2f303b74 5617 spin_unlock(&kvm_lock);
c8076604
GH		 5618
5619 if (freq->old < freq->new && send_ipi) {
5620 /*
5621 * We upscale the frequency. Must make the guest
5622 * doesn't see old kvmclock values while running with
5623 * the new frequency, otherwise we risk the guest sees
5624 * time go backwards.
5625 *
5626 * In case we update the frequency for another cpu
5627 * (which might be in guest context) send an interrupt
5628 * to kick the cpu out of guest context. Next time
5629 * guest context is entered kvmclock will be updated,
5630 * so the guest will not see stale values.
5631 */
8cfdc000 5632 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5633 }
5634 return 0;
5635}
5636
5637static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5638 .notifier_call = kvmclock_cpufreq_notifier
5639};
5640
5641static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5642 unsigned long action, void *hcpu)
5643{
5644 unsigned int cpu = (unsigned long)hcpu;
5645
5646 switch (action) {
5647 case CPU_ONLINE:
5648 case CPU_DOWN_FAILED:
5649 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5650 break;
5651 case CPU_DOWN_PREPARE:
5652 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5653 break;
5654 }
5655 return NOTIFY_OK;
5656}
5657
5658static struct notifier_block kvmclock_cpu_notifier_block = {
5659 .notifier_call = kvmclock_cpu_notifier,
5660 .priority = -INT_MAX
c8076604
GH		 5661};
5662
b820cc0c
ZA		 5663static void kvm_timer_init(void)
5664{
5665 int cpu;
5666
c285545f 5667 max_tsc_khz = tsc_khz;
460dd42e
SB		 5668
5669 cpu_notifier_register_begin();
b820cc0c 5670 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5671#ifdef CONFIG_CPU_FREQ
5672 struct cpufreq_policy policy;
5673 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5674 cpu = get_cpu();
5675 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5676 if (policy.cpuinfo.max_freq)
5677 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5678 put_cpu();
c285545f 5679#endif
b820cc0c
ZA		 5680 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5681 CPUFREQ_TRANSITION_NOTIFIER);
5682 }
c285545f 5683 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5684 for_each_online_cpu(cpu)
5685 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5686
5687 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5688 cpu_notifier_register_done();
5689
b820cc0c
ZA		 5690}
5691
ff9d07a0
ZY		 5692static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5693
f5132b01 5694int kvm_is_in_guest(void)
ff9d07a0 5695{
086c9855 5696 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5697}
5698
5699static int kvm_is_user_mode(void)
5700{
5701 int user_mode = 3;
dcf46b94 5702
086c9855
AS		 5703 if (__this_cpu_read(current_vcpu))
5704 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5705
ff9d07a0
ZY		 5706 return user_mode != 0;
5707}
5708
5709static unsigned long kvm_get_guest_ip(void)
5710{
5711 unsigned long ip = 0;
dcf46b94 5712
086c9855
AS		 5713 if (__this_cpu_read(current_vcpu))
5714 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5715
ff9d07a0
ZY		 5716 return ip;
5717}
5718
5719static struct perf_guest_info_callbacks kvm_guest_cbs = {
5720 .is_in_guest = kvm_is_in_guest,
5721 .is_user_mode = kvm_is_user_mode,
5722 .get_guest_ip = kvm_get_guest_ip,
5723};
5724
5725void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5726{
086c9855 5727 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5728}
5729EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5730
5731void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5732{
086c9855 5733 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5734}
5735EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5736
ce88decf
XG		 5737static void kvm_set_mmio_spte_mask(void)
5738{
5739 u64 mask;
5740 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5741
5742 /*
5743 * Set the reserved bits and the present bit of an paging-structure
5744 * entry to generate page fault with PFER.RSV = 1.
5745 */
885032b9 5746 /* Mask the reserved physical address bits. */
d1431483 5747 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5748
5749 /* Bit 62 is always reserved for 32bit host. */
5750 mask |= 0x3ull << 62;
5751
5752 /* Set the present bit. */
ce88decf
XG		 5753 mask |= 1ull;
5754
5755#ifdef CONFIG_X86_64
5756 /*
5757 * If reserved bit is not supported, clear the present bit to disable
5758 * mmio page fault.
5759 */
5760 if (maxphyaddr == 52)
5761 mask &= ~1ull;
5762#endif
5763
5764 kvm_mmu_set_mmio_spte_mask(mask);
5765}
5766
16e8d74d
MT		 5767#ifdef CONFIG_X86_64
5768static void pvclock_gtod_update_fn(struct work_struct *work)
5769{
d828199e
MT		 5770 struct kvm *kvm;
5771
5772 struct kvm_vcpu *vcpu;
5773 int i;
5774
2f303b74 5775 spin_lock(&kvm_lock);
d828199e
MT		 5776 list_for_each_entry(kvm, &vm_list, vm_list)
5777 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5778 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5779 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5780 spin_unlock(&kvm_lock);
16e8d74d
MT		 5781}
5782
5783static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5784
5785/*
5786 * Notification about pvclock gtod data update.
5787 */
5788static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5789 void *priv)
5790{
5791 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5792 struct timekeeper *tk = priv;
5793
5794 update_pvclock_gtod(tk);
5795
5796 /* disable master clock if host does not trust, or does not
5797 * use, TSC clocksource
5798 */
5799 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5800 atomic_read(&kvm_guest_has_master_clock) != 0)
5801 queue_work(system_long_wq, &pvclock_gtod_work);
5802
5803 return 0;
5804}
5805
5806static struct notifier_block pvclock_gtod_notifier = {
5807 .notifier_call = pvclock_gtod_notify,
5808};
5809#endif
5810
f8c16bba 5811int kvm_arch_init(void *opaque)
043405e1 5812{
b820cc0c 5813 int r;
6b61edf7 5814 struct kvm_x86_ops *ops = opaque;
f8c16bba 5815
f8c16bba
ZX		 5816 if (kvm_x86_ops) {
5817 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5818 r = -EEXIST;
5819 goto out;
f8c16bba
ZX		 5820 }
5821
5822 if (!ops->cpu_has_kvm_support()) {
5823 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5824 r = -EOPNOTSUPP;
5825 goto out;
f8c16bba
ZX		 5826 }
5827 if (ops->disabled_by_bios()) {
5828 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5829 r = -EOPNOTSUPP;
5830 goto out;
f8c16bba
ZX		 5831 }
5832
013f6a5d
MT		 5833 r = -ENOMEM;
5834 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5835 if (!shared_msrs) {
5836 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5837 goto out;
5838 }
5839
97db56ce
AK		 5840 r = kvm_mmu_module_init();
5841 if (r)
013f6a5d 5842 goto out_free_percpu;
97db56ce 5843
ce88decf 5844 kvm_set_mmio_spte_mask();
97db56ce 5845
f8c16bba 5846 kvm_x86_ops = ops;
920c8377 5847
7b52345e 5848 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5849 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5850
b820cc0c 5851 kvm_timer_init();
c8076604 5852
ff9d07a0
ZY		 5853 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5854
2acf923e
DC		 5855 if (cpu_has_xsave)
5856 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5857
c5cc421b 5858 kvm_lapic_init();
16e8d74d
MT		 5859#ifdef CONFIG_X86_64
5860 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5861#endif
5862
f8c16bba 5863 return 0;
56c6d28a 5864
013f6a5d
MT		 5865out_free_percpu:
5866 free_percpu(shared_msrs);
56c6d28a 5867out:
56c6d28a 5868 return r;
043405e1 5869}
8776e519 5870
f8c16bba
ZX		 5871void kvm_arch_exit(void)
5872{
ff9d07a0
ZY		 5873 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5874
888d256e
JK		 5875 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5876 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5877 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5878 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5879#ifdef CONFIG_X86_64
5880 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5881#endif
f8c16bba 5882 kvm_x86_ops = NULL;
56c6d28a 5883 kvm_mmu_module_exit();
013f6a5d 5884 free_percpu(shared_msrs);
56c6d28a 5885}
f8c16bba 5886
5cb56059 5887int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5888{
5889 ++vcpu->stat.halt_exits;
35754c98 5890 if (lapic_in_kernel(vcpu)) {
a4535290 5891 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5892 return 1;
5893 } else {
5894 vcpu->run->exit_reason = KVM_EXIT_HLT;
5895 return 0;
5896 }
5897}
5cb56059
JS		 5898EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5899
5900int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5901{
5902 kvm_x86_ops->skip_emulated_instruction(vcpu);
5903 return kvm_vcpu_halt(vcpu);
5904}
8776e519
HB		 5905EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5906
6aef266c
SV		 5907/*
5908 * kvm_pv_kick_cpu_op: Kick a vcpu.
5909 *
5910 * @apicid - apicid of vcpu to be kicked.
5911 */
5912static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5913{
24d2166b 5914 struct kvm_lapic_irq lapic_irq;
6aef266c 5915
24d2166b
R		 5916 lapic_irq.shorthand = 0;
5917 lapic_irq.dest_mode = 0;
5918 lapic_irq.dest_id = apicid;
93bbf0b8 5919 lapic_irq.msi_redir_hint = false;
6aef266c 5920
24d2166b 5921 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5922 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5923}
5924
d62caabb
AS		 5925void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5926{
5927 vcpu->arch.apicv_active = false;
5928 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5929}
5930
8776e519
HB		 5931int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5932{
5933 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5934 int op_64_bit, r = 1;
8776e519 5935
5cb56059
JS		 5936 kvm_x86_ops->skip_emulated_instruction(vcpu);
5937
55cd8e5a
GN		 5938 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5939 return kvm_hv_hypercall(vcpu);
5940
5fdbf976
MT		 5941 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5942 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5943 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5944 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5945 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5946
229456fc 5947 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5948
a449c7aa
NA		 5949 op_64_bit = is_64_bit_mode(vcpu);
5950 if (!op_64_bit) {
8776e519
HB		 5951 nr &= 0xFFFFFFFF;
5952 a0 &= 0xFFFFFFFF;
5953 a1 &= 0xFFFFFFFF;
5954 a2 &= 0xFFFFFFFF;
5955 a3 &= 0xFFFFFFFF;
5956 }
5957
07708c4a
JK		 5958 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5959 ret = -KVM_EPERM;
5960 goto out;
5961 }
5962
8776e519 5963 switch (nr) {
b93463aa
AK		 5964 case KVM_HC_VAPIC_POLL_IRQ:
5965 ret = 0;
5966 break;
6aef266c
SV		 5967 case KVM_HC_KICK_CPU:
5968 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5969 ret = 0;
5970 break;
8776e519
HB		 5971 default:
5972 ret = -KVM_ENOSYS;
5973 break;
5974 }
07708c4a 5975out:
a449c7aa
NA		 5976 if (!op_64_bit)
5977 ret = (u32)ret;
5fdbf976 5978 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5979 ++vcpu->stat.hypercalls;
2f333bcb 5980 return r;
8776e519
HB		 5981}
5982EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5983
b6785def 5984static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5985{
d6aa1000 5986 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5987 char instruction[3];
5fdbf976 5988 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5989
8776e519 5990 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5991
9d74191a 5992 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5993}
5994
851ba692 5995static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5996{
782d422b
MG		 5997 return vcpu->run->request_interrupt_window &&
5998 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 5999}
6000
851ba692 6001static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6002{
851ba692
AK		 6003 struct kvm_run *kvm_run = vcpu->run;
6004
91586a3b 6005 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6006 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6007 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6008 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6009 kvm_run->ready_for_interrupt_injection =
6010 pic_in_kernel(vcpu->kvm) ||
782d422b 6011 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6012}
6013
95ba8273
GN		 6014static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6015{
6016 int max_irr, tpr;
6017
6018 if (!kvm_x86_ops->update_cr8_intercept)
6019 return;
6020
bce87cce 6021 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6022 return;
6023
d62caabb
AS		 6024 if (vcpu->arch.apicv_active)
6025 return;
6026
8db3baa2
GN		 6027 if (!vcpu->arch.apic->vapic_addr)
6028 max_irr = kvm_lapic_find_highest_irr(vcpu);
6029 else
6030 max_irr = -1;
95ba8273
GN		 6031
6032 if (max_irr != -1)
6033 max_irr >>= 4;
6034
6035 tpr = kvm_lapic_get_cr8(vcpu);
6036
6037 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6038}
6039
b6b8a145 6040static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6041{
b6b8a145
JK		 6042 int r;
6043
95ba8273 6044 /* try to reinject previous events if any */
b59bb7bd 6045 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6046 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6047 vcpu->arch.exception.has_error_code,
6048 vcpu->arch.exception.error_code);
d6e8c854
NA		 6049
6050 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6051 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6052 X86_EFLAGS_RF);
6053
6bdf0662
NA		 6054 if (vcpu->arch.exception.nr == DB_VECTOR &&
6055 (vcpu->arch.dr7 & DR7_GD)) {
6056 vcpu->arch.dr7 &= ~DR7_GD;
6057 kvm_update_dr7(vcpu);
6058 }
6059
b59bb7bd
GN		 6060 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6061 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6062 vcpu->arch.exception.error_code,
6063 vcpu->arch.exception.reinject);
b6b8a145 6064 return 0;
b59bb7bd
GN		 6065 }
6066
95ba8273
GN		 6067 if (vcpu->arch.nmi_injected) {
6068 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6069 return 0;
95ba8273
GN		 6070 }
6071
6072 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6073 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6074 return 0;
6075 }
6076
6077 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6078 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6079 if (r != 0)
6080 return r;
95ba8273
GN		 6081 }
6082
6083 /* try to inject new event if pending */
321c5658
YS		 6084 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6085 --vcpu->arch.nmi_pending;
6086 vcpu->arch.nmi_injected = true;
6087 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6088 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6089 /*
6090 * Because interrupts can be injected asynchronously, we are
6091 * calling check_nested_events again here to avoid a race condition.
6092 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6093 * proposal and current concerns. Perhaps we should be setting
6094 * KVM_REQ_EVENT only on certain events and not unconditionally?
6095 */
6096 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6097 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6098 if (r != 0)
6099 return r;
6100 }
95ba8273 6101 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6102 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6103 false);
6104 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6105 }
6106 }
b6b8a145 6107 return 0;
95ba8273
GN		 6108}
6109
7460fb4a
AK		 6110static void process_nmi(struct kvm_vcpu *vcpu)
6111{
6112 unsigned limit = 2;
6113
6114 /*
6115 * x86 is limited to one NMI running, and one NMI pending after it.
6116 * If an NMI is already in progress, limit further NMIs to just one.
6117 * Otherwise, allow two (and we'll inject the first one immediately).
6118 */
6119 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6120 limit = 1;
6121
6122 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6123 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6124 kvm_make_request(KVM_REQ_EVENT, vcpu);
6125}
6126
660a5d51
PB		 6127#define put_smstate(type, buf, offset, val) \
6128 *(type *)((buf) + (offset) - 0x7e00) = val
6129
6130static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6131{
6132 u32 flags = 0;
6133 flags |= seg->g << 23;
6134 flags |= seg->db << 22;
6135 flags |= seg->l << 21;
6136 flags |= seg->avl << 20;
6137 flags |= seg->present << 15;
6138 flags |= seg->dpl << 13;
6139 flags |= seg->s << 12;
6140 flags |= seg->type << 8;
6141 return flags;
6142}
6143
6144static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6145{
6146 struct kvm_segment seg;
6147 int offset;
6148
6149 kvm_get_segment(vcpu, &seg, n);
6150 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6151
6152 if (n < 3)
6153 offset = 0x7f84 + n * 12;
6154 else
6155 offset = 0x7f2c + (n - 3) * 12;
6156
6157 put_smstate(u32, buf, offset + 8, seg.base);
6158 put_smstate(u32, buf, offset + 4, seg.limit);
6159 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6160}
6161
efbb288a 6162#ifdef CONFIG_X86_64
660a5d51
PB		 6163static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6164{
6165 struct kvm_segment seg;
6166 int offset;
6167 u16 flags;
6168
6169 kvm_get_segment(vcpu, &seg, n);
6170 offset = 0x7e00 + n * 16;
6171
6172 flags = process_smi_get_segment_flags(&seg) >> 8;
6173 put_smstate(u16, buf, offset, seg.selector);
6174 put_smstate(u16, buf, offset + 2, flags);
6175 put_smstate(u32, buf, offset + 4, seg.limit);
6176 put_smstate(u64, buf, offset + 8, seg.base);
6177}
efbb288a 6178#endif
660a5d51
PB		 6179
6180static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6181{
6182 struct desc_ptr dt;
6183 struct kvm_segment seg;
6184 unsigned long val;
6185 int i;
6186
6187 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6188 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6189 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6190 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6191
6192 for (i = 0; i < 8; i++)
6193 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6194
6195 kvm_get_dr(vcpu, 6, &val);
6196 put_smstate(u32, buf, 0x7fcc, (u32)val);
6197 kvm_get_dr(vcpu, 7, &val);
6198 put_smstate(u32, buf, 0x7fc8, (u32)val);
6199
6200 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6201 put_smstate(u32, buf, 0x7fc4, seg.selector);
6202 put_smstate(u32, buf, 0x7f64, seg.base);
6203 put_smstate(u32, buf, 0x7f60, seg.limit);
6204 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6205
6206 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6207 put_smstate(u32, buf, 0x7fc0, seg.selector);
6208 put_smstate(u32, buf, 0x7f80, seg.base);
6209 put_smstate(u32, buf, 0x7f7c, seg.limit);
6210 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6211
6212 kvm_x86_ops->get_gdt(vcpu, &dt);
6213 put_smstate(u32, buf, 0x7f74, dt.address);
6214 put_smstate(u32, buf, 0x7f70, dt.size);
6215
6216 kvm_x86_ops->get_idt(vcpu, &dt);
6217 put_smstate(u32, buf, 0x7f58, dt.address);
6218 put_smstate(u32, buf, 0x7f54, dt.size);
6219
6220 for (i = 0; i < 6; i++)
6221 process_smi_save_seg_32(vcpu, buf, i);
6222
6223 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6224
6225 /* revision id */
6226 put_smstate(u32, buf, 0x7efc, 0x00020000);
6227 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6228}
6229
6230static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6231{
6232#ifdef CONFIG_X86_64
6233 struct desc_ptr dt;
6234 struct kvm_segment seg;
6235 unsigned long val;
6236 int i;
6237
6238 for (i = 0; i < 16; i++)
6239 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6240
6241 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6242 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6243
6244 kvm_get_dr(vcpu, 6, &val);
6245 put_smstate(u64, buf, 0x7f68, val);
6246 kvm_get_dr(vcpu, 7, &val);
6247 put_smstate(u64, buf, 0x7f60, val);
6248
6249 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6250 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6251 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6252
6253 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6254
6255 /* revision id */
6256 put_smstate(u32, buf, 0x7efc, 0x00020064);
6257
6258 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6259
6260 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6261 put_smstate(u16, buf, 0x7e90, seg.selector);
6262 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6263 put_smstate(u32, buf, 0x7e94, seg.limit);
6264 put_smstate(u64, buf, 0x7e98, seg.base);
6265
6266 kvm_x86_ops->get_idt(vcpu, &dt);
6267 put_smstate(u32, buf, 0x7e84, dt.size);
6268 put_smstate(u64, buf, 0x7e88, dt.address);
6269
6270 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6271 put_smstate(u16, buf, 0x7e70, seg.selector);
6272 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6273 put_smstate(u32, buf, 0x7e74, seg.limit);
6274 put_smstate(u64, buf, 0x7e78, seg.base);
6275
6276 kvm_x86_ops->get_gdt(vcpu, &dt);
6277 put_smstate(u32, buf, 0x7e64, dt.size);
6278 put_smstate(u64, buf, 0x7e68, dt.address);
6279
6280 for (i = 0; i < 6; i++)
6281 process_smi_save_seg_64(vcpu, buf, i);
6282#else
6283 WARN_ON_ONCE(1);
6284#endif
6285}
6286
64d60670
PB		 6287static void process_smi(struct kvm_vcpu *vcpu)
6288{
660a5d51 6289 struct kvm_segment cs, ds;
18c3626e 6290 struct desc_ptr dt;
660a5d51
PB		 6291 char buf[512];
6292 u32 cr0;
6293
64d60670
PB		 6294 if (is_smm(vcpu)) {
6295 vcpu->arch.smi_pending = true;
6296 return;
6297 }
6298
660a5d51
PB		 6299 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6300 vcpu->arch.hflags |= HF_SMM_MASK;
6301 memset(buf, 0, 512);
6302 if (guest_cpuid_has_longmode(vcpu))
6303 process_smi_save_state_64(vcpu, buf);
6304 else
6305 process_smi_save_state_32(vcpu, buf);
6306
54bf36aa 6307 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6308
6309 if (kvm_x86_ops->get_nmi_mask(vcpu))
6310 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6311 else
6312 kvm_x86_ops->set_nmi_mask(vcpu, true);
6313
6314 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6315 kvm_rip_write(vcpu, 0x8000);
6316
6317 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6318 kvm_x86_ops->set_cr0(vcpu, cr0);
6319 vcpu->arch.cr0 = cr0;
6320
6321 kvm_x86_ops->set_cr4(vcpu, 0);
6322
18c3626e
PB		 6323 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6324 dt.address = dt.size = 0;
6325 kvm_x86_ops->set_idt(vcpu, &dt);
6326
660a5d51
PB		 6327 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6328
6329 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6330 cs.base = vcpu->arch.smbase;
6331
6332 ds.selector = 0;
6333 ds.base = 0;
6334
6335 cs.limit = ds.limit = 0xffffffff;
6336 cs.type = ds.type = 0x3;
6337 cs.dpl = ds.dpl = 0;
6338 cs.db = ds.db = 0;
6339 cs.s = ds.s = 1;
6340 cs.l = ds.l = 0;
6341 cs.g = ds.g = 1;
6342 cs.avl = ds.avl = 0;
6343 cs.present = ds.present = 1;
6344 cs.unusable = ds.unusable = 0;
6345 cs.padding = ds.padding = 0;
6346
6347 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6348 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6349 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6350 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6351 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6352 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6353
6354 if (guest_cpuid_has_longmode(vcpu))
6355 kvm_x86_ops->set_efer(vcpu, 0);
6356
6357 kvm_update_cpuid(vcpu);
6358 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6359}
6360
2860c4b1
PB		 6361void kvm_make_scan_ioapic_request(struct kvm *kvm)
6362{
6363 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6364}
6365
3d81bc7e 6366static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6367{
5c919412
AS		 6368 u64 eoi_exit_bitmap[4];
6369
3d81bc7e
YZ		 6370 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6371 return;
c7c9c56c 6372
6308630b 6373 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6374
b053b2ae 6375 if (irqchip_split(vcpu->kvm))
6308630b 6376 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6377 else {
d62caabb
AS		 6378 if (vcpu->arch.apicv_active)
6379 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6380 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6381 }
5c919412
AS		 6382 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6383 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6384 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6385}
6386
a70656b6
RK		 6387static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6388{
6389 ++vcpu->stat.tlb_flush;
6390 kvm_x86_ops->tlb_flush(vcpu);
6391}
6392
4256f43f
TC		 6393void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6394{
c24ae0dc
TC		 6395 struct page *page = NULL;
6396
35754c98 6397 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6398 return;
6399
4256f43f
TC		 6400 if (!kvm_x86_ops->set_apic_access_page_addr)
6401 return;
6402
c24ae0dc 6403 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6404 if (is_error_page(page))
6405 return;
c24ae0dc
TC		 6406 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6407
6408 /*
6409 * Do not pin apic access page in memory, the MMU notifier
6410 * will call us again if it is migrated or swapped out.
6411 */
6412 put_page(page);
4256f43f
TC		 6413}
6414EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6415
fe71557a
TC		 6416void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6417 unsigned long address)
6418{
c24ae0dc
TC		 6419 /*
6420 * The physical address of apic access page is stored in the VMCS.
6421 * Update it when it becomes invalid.
6422 */
6423 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6424 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6425}
6426
9357d939 6427/*
362c698f 6428 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6429 * exiting to the userspace. Otherwise, the value will be returned to the
6430 * userspace.
6431 */
851ba692 6432static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6433{
6434 int r;
62a193ed
MG		 6435 bool req_int_win =
6436 dm_request_for_irq_injection(vcpu) &&
6437 kvm_cpu_accept_dm_intr(vcpu);
6438
730dca42 6439 bool req_immediate_exit = false;
b6c7a5dc 6440
3e007509 6441 if (vcpu->requests) {
a8eeb04a 6442 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6443 kvm_mmu_unload(vcpu);
a8eeb04a 6444 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6445 __kvm_migrate_timers(vcpu);
d828199e
MT		 6446 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6447 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6448 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6449 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6450 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6451 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6452 if (unlikely(r))
6453 goto out;
6454 }
a8eeb04a 6455 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6456 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6457 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6458 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6459 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6460 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6461 r = 0;
6462 goto out;
6463 }
a8eeb04a 6464 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6465 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6466 r = 0;
6467 goto out;
6468 }
a8eeb04a 6469 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6470 vcpu->fpu_active = 0;
6471 kvm_x86_ops->fpu_deactivate(vcpu);
6472 }
af585b92
GN		 6473 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6474 /* Page is swapped out. Do synthetic halt */
6475 vcpu->arch.apf.halted = true;
6476 r = 1;
6477 goto out;
6478 }
c9aaa895
GC		 6479 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6480 record_steal_time(vcpu);
64d60670
PB		 6481 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6482 process_smi(vcpu);
7460fb4a
AK		 6483 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6484 process_nmi(vcpu);
f5132b01 6485 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6486 kvm_pmu_handle_event(vcpu);
f5132b01 6487 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6488 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6489 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6490 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6491 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6492 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6493 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6494 vcpu->run->eoi.vector =
6495 vcpu->arch.pending_ioapic_eoi;
6496 r = 0;
6497 goto out;
6498 }
6499 }
3d81bc7e
YZ		 6500 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6501 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6502 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6503 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6504 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6505 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6506 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6507 r = 0;
6508 goto out;
6509 }
e516cebb
AS		 6510 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6511 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6512 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6513 r = 0;
6514 goto out;
6515 }
db397571
AS		 6516 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6517 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6518 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6519 r = 0;
6520 goto out;
6521 }
f3b138c5
AS		 6522
6523 /*
6524 * KVM_REQ_HV_STIMER has to be processed after
6525 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6526 * depend on the guest clock being up-to-date
6527 */
1f4b34f8
AS		 6528 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6529 kvm_hv_process_stimers(vcpu);
2f52d58c 6530 }
b93463aa 6531
bf9f6ac8
FW		 6532 /*
6533 * KVM_REQ_EVENT is not set when posted interrupts are set by
6534 * VT-d hardware, so we have to update RVI unconditionally.
6535 */
6536 if (kvm_lapic_enabled(vcpu)) {
6537 /*
6538 * Update architecture specific hints for APIC
6539 * virtual interrupt delivery.
6540 */
d62caabb 6541 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6542 kvm_x86_ops->hwapic_irr_update(vcpu,
6543 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6544 }
b93463aa 6545
b463a6f7 6546 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6547 kvm_apic_accept_events(vcpu);
6548 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6549 r = 1;
6550 goto out;
6551 }
6552
b6b8a145
JK		 6553 if (inject_pending_event(vcpu, req_int_win) != 0)
6554 req_immediate_exit = true;
b463a6f7 6555 /* enable NMI/IRQ window open exits if needed */
321c5658
YS		 6556 else {
6557 if (vcpu->arch.nmi_pending)
6558 kvm_x86_ops->enable_nmi_window(vcpu);
6559 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6560 kvm_x86_ops->enable_irq_window(vcpu);
6561 }
b463a6f7
AK		 6562
6563 if (kvm_lapic_enabled(vcpu)) {
6564 update_cr8_intercept(vcpu);
6565 kvm_lapic_sync_to_vapic(vcpu);
6566 }
6567 }
6568
d8368af8
AK		 6569 r = kvm_mmu_reload(vcpu);
6570 if (unlikely(r)) {
d905c069 6571 goto cancel_injection;
d8368af8
AK		 6572 }
6573
b6c7a5dc
HB		 6574 preempt_disable();
6575
6576 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6577 if (vcpu->fpu_active)
6578 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6579 vcpu->mode = IN_GUEST_MODE;
6580
01b71917
MT		 6581 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6582
0f127d12
LT		 6583 /*
6584 * We should set ->mode before check ->requests,
6585 * Please see the comment in kvm_make_all_cpus_request.
6586 * This also orders the write to mode from any reads
6587 * to the page tables done while the VCPU is running.
6588 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6589 */
01b71917 6590 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6591
d94e1dc9 6592 local_irq_disable();
32f88400 6593
6b7e2d09 6594 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6595 || need_resched() || signal_pending(current)) {
6b7e2d09 6596 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6597 smp_wmb();
6c142801
AK		 6598 local_irq_enable();
6599 preempt_enable();
01b71917 6600 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6601 r = 1;
d905c069 6602 goto cancel_injection;
6c142801
AK		 6603 }
6604
fc5b7f3b
DM		 6605 kvm_load_guest_xcr0(vcpu);
6606
d6185f20
NHE		 6607 if (req_immediate_exit)
6608 smp_send_reschedule(vcpu->cpu);
6609
8b89fe1f
PB		 6610 trace_kvm_entry(vcpu->vcpu_id);
6611 wait_lapic_expire(vcpu);
ccf73aaf 6612 __kvm_guest_enter();
b6c7a5dc 6613
42dbaa5a 6614 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6615 set_debugreg(0, 7);
6616 set_debugreg(vcpu->arch.eff_db[0], 0);
6617 set_debugreg(vcpu->arch.eff_db[1], 1);
6618 set_debugreg(vcpu->arch.eff_db[2], 2);
6619 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6620 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6621 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6622 }
b6c7a5dc 6623
851ba692 6624 kvm_x86_ops->run(vcpu);
b6c7a5dc 6625
c77fb5fe
PB		 6626 /*
6627 * Do this here before restoring debug registers on the host. And
6628 * since we do this before handling the vmexit, a DR access vmexit
6629 * can (a) read the correct value of the debug registers, (b) set
6630 * KVM_DEBUGREG_WONT_EXIT again.
6631 */
6632 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6633 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6634 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6635 kvm_update_dr0123(vcpu);
6636 kvm_update_dr6(vcpu);
6637 kvm_update_dr7(vcpu);
6638 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6639 }
6640
24f1e32c
FW		 6641 /*
6642 * If the guest has used debug registers, at least dr7
6643 * will be disabled while returning to the host.
6644 * If we don't have active breakpoints in the host, we don't
6645 * care about the messed up debug address registers. But if
6646 * we have some of them active, restore the old state.
6647 */
59d8eb53 6648 if (hw_breakpoint_active())
24f1e32c 6649 hw_breakpoint_restore();
42dbaa5a 6650
4ba76538 6651 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6652
6b7e2d09 6653 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6654 smp_wmb();
a547c6db 6655
fc5b7f3b
DM		 6656 kvm_put_guest_xcr0(vcpu);
6657
a547c6db
YZ		 6658 /* Interrupt is enabled by handle_external_intr() */
6659 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6660
6661 ++vcpu->stat.exits;
6662
6663 /*
6664 * We must have an instruction between local_irq_enable() and
6665 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6666 * the interrupt shadow. The stat.exits increment will do nicely.
6667 * But we need to prevent reordering, hence this barrier():
6668 */
6669 barrier();
6670
6671 kvm_guest_exit();
6672
6673 preempt_enable();
6674
f656ce01 6675 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6676
b6c7a5dc
HB		 6677 /*
6678 * Profile KVM exit RIPs:
6679 */
6680 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6681 unsigned long rip = kvm_rip_read(vcpu);
6682 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6683 }
6684
cc578287
ZA		 6685 if (unlikely(vcpu->arch.tsc_always_catchup))
6686 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6687
5cfb1d5a
MT		 6688 if (vcpu->arch.apic_attention)
6689 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6690
851ba692 6691 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6692 return r;
6693
6694cancel_injection:
6695 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6696 if (unlikely(vcpu->arch.apic_attention))
6697 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6698out:
6699 return r;
6700}
b6c7a5dc 6701
362c698f
PB		 6702static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6703{
bf9f6ac8
FW		 6704 if (!kvm_arch_vcpu_runnable(vcpu) &&
6705 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6706 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6707 kvm_vcpu_block(vcpu);
6708 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6709
6710 if (kvm_x86_ops->post_block)
6711 kvm_x86_ops->post_block(vcpu);
6712
9c8fd1ba
PB		 6713 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6714 return 1;
6715 }
362c698f
PB		 6716
6717 kvm_apic_accept_events(vcpu);
6718 switch(vcpu->arch.mp_state) {
6719 case KVM_MP_STATE_HALTED:
6720 vcpu->arch.pv.pv_unhalted = false;
6721 vcpu->arch.mp_state =
6722 KVM_MP_STATE_RUNNABLE;
6723 case KVM_MP_STATE_RUNNABLE:
6724 vcpu->arch.apf.halted = false;
6725 break;
6726 case KVM_MP_STATE_INIT_RECEIVED:
6727 break;
6728 default:
6729 return -EINTR;
6730 break;
6731 }
6732 return 1;
6733}
09cec754 6734
5d9bc648
PB		 6735static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6736{
6737 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6738 !vcpu->arch.apf.halted);
6739}
6740
362c698f 6741static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6742{
6743 int r;
f656ce01 6744 struct kvm *kvm = vcpu->kvm;
d7690175 6745
f656ce01 6746 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6747
362c698f 6748 for (;;) {
58f800d5 6749 if (kvm_vcpu_running(vcpu)) {
851ba692 6750 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6751 } else {
362c698f 6752 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6753 }
6754
09cec754
GN		 6755 if (r <= 0)
6756 break;
6757
6758 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6759 if (kvm_cpu_has_pending_timer(vcpu))
6760 kvm_inject_pending_timer_irqs(vcpu);
6761
782d422b
MG		 6762 if (dm_request_for_irq_injection(vcpu) &&
6763 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6764 r = 0;
6765 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6766 ++vcpu->stat.request_irq_exits;
362c698f 6767 break;
09cec754 6768 }
af585b92
GN		 6769
6770 kvm_check_async_pf_completion(vcpu);
6771
09cec754
GN		 6772 if (signal_pending(current)) {
6773 r = -EINTR;
851ba692 6774 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6775 ++vcpu->stat.signal_exits;
362c698f 6776 break;
09cec754
GN		 6777 }
6778 if (need_resched()) {
f656ce01 6779 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6780 cond_resched();
f656ce01 6781 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6782 }
b6c7a5dc
HB		 6783 }
6784
f656ce01 6785 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6786
6787 return r;
6788}
6789
716d51ab
GN		 6790static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6791{
6792 int r;
6793 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6794 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6795 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6796 if (r != EMULATE_DONE)
6797 return 0;
6798 return 1;
6799}
6800
6801static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6802{
6803 BUG_ON(!vcpu->arch.pio.count);
6804
6805 return complete_emulated_io(vcpu);
6806}
6807
f78146b0
AK		 6808/*
6809 * Implements the following, as a state machine:
6810 *
6811 * read:
6812 * for each fragment
87da7e66
XG		 6813 * for each mmio piece in the fragment
6814 * write gpa, len
6815 * exit
6816 * copy data
f78146b0
AK		 6817 * execute insn
6818 *
6819 * write:
6820 * for each fragment
87da7e66
XG		 6821 * for each mmio piece in the fragment
6822 * write gpa, len
6823 * copy data
6824 * exit
f78146b0 6825 */
716d51ab 6826static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6827{
6828 struct kvm_run *run = vcpu->run;
f78146b0 6829 struct kvm_mmio_fragment *frag;
87da7e66 6830 unsigned len;
5287f194 6831
716d51ab 6832 BUG_ON(!vcpu->mmio_needed);
5287f194 6833
716d51ab 6834 /* Complete previous fragment */
87da7e66
XG		 6835 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6836 len = min(8u, frag->len);
716d51ab 6837 if (!vcpu->mmio_is_write)
87da7e66
XG		 6838 memcpy(frag->data, run->mmio.data, len);
6839
6840 if (frag->len <= 8) {
6841 /* Switch to the next fragment. */
6842 frag++;
6843 vcpu->mmio_cur_fragment++;
6844 } else {
6845 /* Go forward to the next mmio piece. */
6846 frag->data += len;
6847 frag->gpa += len;
6848 frag->len -= len;
6849 }
6850
a08d3b3b 6851 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6852 vcpu->mmio_needed = 0;
0912c977
PB		 6853
6854 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6855 if (vcpu->mmio_is_write)
716d51ab
GN		 6856 return 1;
6857 vcpu->mmio_read_completed = 1;
6858 return complete_emulated_io(vcpu);
6859 }
87da7e66 6860
716d51ab
GN		 6861 run->exit_reason = KVM_EXIT_MMIO;
6862 run->mmio.phys_addr = frag->gpa;
6863 if (vcpu->mmio_is_write)
87da7e66
XG		 6864 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6865 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6866 run->mmio.is_write = vcpu->mmio_is_write;
6867 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6868 return 0;
5287f194
AK		 6869}
6870
716d51ab 6871
b6c7a5dc
HB		 6872int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6873{
c5bedc68 6874 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6875 int r;
6876 sigset_t sigsaved;
6877
c4d72e2d 6878 fpu__activate_curr(fpu);
e5c30142 6879
ac9f6dc0
AK		 6880 if (vcpu->sigset_active)
6881 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6882
a4535290 6883 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6884 kvm_vcpu_block(vcpu);
66450a21 6885 kvm_apic_accept_events(vcpu);
d7690175 6886 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6887 r = -EAGAIN;
6888 goto out;
b6c7a5dc
HB		 6889 }
6890
b6c7a5dc 6891 /* re-sync apic's tpr */
35754c98 6892 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6893 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6894 r = -EINVAL;
6895 goto out;
6896 }
6897 }
b6c7a5dc 6898
716d51ab
GN		 6899 if (unlikely(vcpu->arch.complete_userspace_io)) {
6900 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6901 vcpu->arch.complete_userspace_io = NULL;
6902 r = cui(vcpu);
6903 if (r <= 0)
6904 goto out;
6905 } else
6906 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6907
362c698f 6908 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6909
6910out:
f1d86e46 6911 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6912 if (vcpu->sigset_active)
6913 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6914
b6c7a5dc
HB		 6915 return r;
6916}
6917
6918int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6919{
7ae441ea
GN		 6920 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6921 /*
6922 * We are here if userspace calls get_regs() in the middle of
6923 * instruction emulation. Registers state needs to be copied
4a969980 6924 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6925 * that usually, but some bad designed PV devices (vmware
6926 * backdoor interface) need this to work
6927 */
dd856efa 6928 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6929 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6930 }
5fdbf976
MT		 6931 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6932 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6933 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6934 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6935 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6936 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6937 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6938 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6939#ifdef CONFIG_X86_64
5fdbf976
MT		 6940 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6941 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6942 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6943 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6944 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6945 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6946 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6947 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6948#endif
6949
5fdbf976 6950 regs->rip = kvm_rip_read(vcpu);
91586a3b 6951 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6952
b6c7a5dc
HB		 6953 return 0;
6954}
6955
6956int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6957{
7ae441ea
GN		 6958 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6959 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6960
5fdbf976
MT		 6961 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6962 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6963 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6964 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6965 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6966 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6967 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6968 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6969#ifdef CONFIG_X86_64
5fdbf976
MT		 6970 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6971 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6972 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6973 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6974 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6975 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6976 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6977 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6978#endif
6979
5fdbf976 6980 kvm_rip_write(vcpu, regs->rip);
91586a3b 6981 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6982
b4f14abd
JK		 6983 vcpu->arch.exception.pending = false;
6984
3842d135
AK		 6985 kvm_make_request(KVM_REQ_EVENT, vcpu);
6986
b6c7a5dc
HB		 6987 return 0;
6988}
6989
b6c7a5dc
HB		 6990void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6991{
6992 struct kvm_segment cs;
6993
3e6e0aab 6994 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6995 *db = cs.db;
6996 *l = cs.l;
6997}
6998EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6999
7000int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7001 struct kvm_sregs *sregs)
7002{
89a27f4d 7003 struct desc_ptr dt;
b6c7a5dc 7004
3e6e0aab
GT		 7005 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7006 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7007 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7008 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7009 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7010 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7011
3e6e0aab
GT		 7012 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7013 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7014
7015 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7016 sregs->idt.limit = dt.size;
7017 sregs->idt.base = dt.address;
b6c7a5dc 7018 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7019 sregs->gdt.limit = dt.size;
7020 sregs->gdt.base = dt.address;
b6c7a5dc 7021
4d4ec087 7022 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7023 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7024 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7025 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7026 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7027 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7028 sregs->apic_base = kvm_get_apic_base(vcpu);
7029
923c61bb 7030 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7031
36752c9b 7032 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7033 set_bit(vcpu->arch.interrupt.nr,
7034 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7035
b6c7a5dc
HB		 7036 return 0;
7037}
7038
62d9f0db
MT		 7039int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7040 struct kvm_mp_state *mp_state)
7041{
66450a21 7042 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7043 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7044 vcpu->arch.pv.pv_unhalted)
7045 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7046 else
7047 mp_state->mp_state = vcpu->arch.mp_state;
7048
62d9f0db
MT		 7049 return 0;
7050}
7051
7052int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7053 struct kvm_mp_state *mp_state)
7054{
bce87cce 7055 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7056 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7057 return -EINVAL;
7058
7059 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7060 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7061 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7062 } else
7063 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7064 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7065 return 0;
7066}
7067
7f3d35fd
KW		 7068int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7069 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7070{
9d74191a 7071 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7072 int ret;
e01c2426 7073
8ec4722d 7074 init_emulate_ctxt(vcpu);
c697518a 7075
7f3d35fd 7076 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7077 has_error_code, error_code);
c697518a 7078
c697518a 7079 if (ret)
19d04437 7080 return EMULATE_FAIL;
37817f29 7081
9d74191a
TY		 7082 kvm_rip_write(vcpu, ctxt->eip);
7083 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7084 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7085 return EMULATE_DONE;
37817f29
IE		 7086}
7087EXPORT_SYMBOL_GPL(kvm_task_switch);
7088
b6c7a5dc
HB		 7089int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7090 struct kvm_sregs *sregs)
7091{
58cb628d 7092 struct msr_data apic_base_msr;
b6c7a5dc 7093 int mmu_reset_needed = 0;
63f42e02 7094 int pending_vec, max_bits, idx;
89a27f4d 7095 struct desc_ptr dt;
b6c7a5dc 7096
6d1068b3
PM		 7097 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7098 return -EINVAL;
7099
89a27f4d
GN		 7100 dt.size = sregs->idt.limit;
7101 dt.address = sregs->idt.base;
b6c7a5dc 7102 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7103 dt.size = sregs->gdt.limit;
7104 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7105 kvm_x86_ops->set_gdt(vcpu, &dt);
7106
ad312c7c 7107 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7108 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7109 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7110 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7111
2d3ad1f4 7112 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7113
f6801dff 7114 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7115 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7116 apic_base_msr.data = sregs->apic_base;
7117 apic_base_msr.host_initiated = true;
7118 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7119
4d4ec087 7120 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7121 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7122 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7123
fc78f519 7124 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7125 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7126 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7127 kvm_update_cpuid(vcpu);
63f42e02
XG		 7128
7129 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7130 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7131 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7132 mmu_reset_needed = 1;
7133 }
63f42e02 7134 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7135
7136 if (mmu_reset_needed)
7137 kvm_mmu_reset_context(vcpu);
7138
a50abc3b 7139 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7140 pending_vec = find_first_bit(
7141 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7142 if (pending_vec < max_bits) {
66fd3f7f 7143 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7144 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7145 }
7146
3e6e0aab
GT		 7147 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7148 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7149 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7150 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7151 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7152 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7153
3e6e0aab
GT		 7154 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7155 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7156
5f0269f5
ME		 7157 update_cr8_intercept(vcpu);
7158
9c3e4aab 7159 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7160 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7161 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7162 !is_protmode(vcpu))
9c3e4aab
MT		 7163 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7164
3842d135
AK		 7165 kvm_make_request(KVM_REQ_EVENT, vcpu);
7166
b6c7a5dc
HB		 7167 return 0;
7168}
7169
d0bfb940
JK		 7170int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7171 struct kvm_guest_debug *dbg)
b6c7a5dc 7172{
355be0b9 7173 unsigned long rflags;
ae675ef0 7174 int i, r;
b6c7a5dc 7175
4f926bf2
JK		 7176 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7177 r = -EBUSY;
7178 if (vcpu->arch.exception.pending)
2122ff5e 7179 goto out;
4f926bf2
JK		 7180 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7181 kvm_queue_exception(vcpu, DB_VECTOR);
7182 else
7183 kvm_queue_exception(vcpu, BP_VECTOR);
7184 }
7185
91586a3b
JK		 7186 /*
7187 * Read rflags as long as potentially injected trace flags are still
7188 * filtered out.
7189 */
7190 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7191
7192 vcpu->guest_debug = dbg->control;
7193 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7194 vcpu->guest_debug = 0;
7195
7196 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7197 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7198 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7199 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7200 } else {
7201 for (i = 0; i < KVM_NR_DB_REGS; i++)
7202 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7203 }
c8639010 7204 kvm_update_dr7(vcpu);
ae675ef0 7205
f92653ee
JK		 7206 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7207 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7208 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7209
91586a3b
JK		 7210 /*
7211 * Trigger an rflags update that will inject or remove the trace
7212 * flags.
7213 */
7214 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7215
a96036b8 7216 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7217
4f926bf2 7218 r = 0;
d0bfb940 7219
2122ff5e 7220out:
b6c7a5dc
HB		 7221
7222 return r;
7223}
7224
8b006791
ZX		 7225/*
7226 * Translate a guest virtual address to a guest physical address.
7227 */
7228int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7229 struct kvm_translation *tr)
7230{
7231 unsigned long vaddr = tr->linear_address;
7232 gpa_t gpa;
f656ce01 7233 int idx;
8b006791 7234
f656ce01 7235 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7236 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7237 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7238 tr->physical_address = gpa;
7239 tr->valid = gpa != UNMAPPED_GVA;
7240 tr->writeable = 1;
7241 tr->usermode = 0;
8b006791
ZX		 7242
7243 return 0;
7244}
7245
d0752060
HB		 7246int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7247{
c47ada30 7248 struct fxregs_state *fxsave =
7366ed77 7249 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7250
d0752060
HB		 7251 memcpy(fpu->fpr, fxsave->st_space, 128);
7252 fpu->fcw = fxsave->cwd;
7253 fpu->fsw = fxsave->swd;
7254 fpu->ftwx = fxsave->twd;
7255 fpu->last_opcode = fxsave->fop;
7256 fpu->last_ip = fxsave->rip;
7257 fpu->last_dp = fxsave->rdp;
7258 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7259
d0752060
HB		 7260 return 0;
7261}
7262
7263int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7264{
c47ada30 7265 struct fxregs_state *fxsave =
7366ed77 7266 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7267
d0752060
HB		 7268 memcpy(fxsave->st_space, fpu->fpr, 128);
7269 fxsave->cwd = fpu->fcw;
7270 fxsave->swd = fpu->fsw;
7271 fxsave->twd = fpu->ftwx;
7272 fxsave->fop = fpu->last_opcode;
7273 fxsave->rip = fpu->last_ip;
7274 fxsave->rdp = fpu->last_dp;
7275 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7276
d0752060
HB		 7277 return 0;
7278}
7279
0ee6a517 7280static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7281{
bf935b0b 7282 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7283 if (cpu_has_xsaves)
7366ed77 7284 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7285 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7286
2acf923e
DC		 7287 /*
7288 * Ensure guest xcr0 is valid for loading
7289 */
d91cab78 7290 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7291
ad312c7c 7292 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7293}
d0752060
HB		 7294
7295void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7296{
2608d7a1 7297 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7298 return;
7299
2acf923e
DC		 7300 /*
7301 * Restore all possible states in the guest,
7302 * and assume host would use all available bits.
7303 * Guest xcr0 would be loaded later.
7304 */
d0752060 7305 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7306 __kernel_fpu_begin();
003e2e8b 7307 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7308 trace_kvm_fpu(1);
d0752060 7309}
d0752060
HB		 7310
7311void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7312{
653f52c3
RR		 7313 if (!vcpu->guest_fpu_loaded) {
7314 vcpu->fpu_counter = 0;
d0752060 7315 return;
653f52c3 7316 }
d0752060
HB		 7317
7318 vcpu->guest_fpu_loaded = 0;
4f836347 7319 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7320 __kernel_fpu_end();
f096ed85 7321 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7322 /*
7323 * If using eager FPU mode, or if the guest is a frequent user
7324 * of the FPU, just leave the FPU active for next time.
7325 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7326 * the FPU in bursts will revert to loading it on demand.
7327 */
5a5fbdc0 7328 if (!use_eager_fpu()) {
653f52c3
RR		 7329 if (++vcpu->fpu_counter < 5)
7330 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7331 }
0c04851c 7332 trace_kvm_fpu(0);
d0752060 7333}
e9b11c17
ZX		 7334
7335void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7336{
12f9a48f 7337 kvmclock_reset(vcpu);
7f1ea208 7338
f5f48ee1 7339 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7340 kvm_x86_ops->vcpu_free(vcpu);
7341}
7342
7343struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7344 unsigned int id)
7345{
c447e76b
LL		 7346 struct kvm_vcpu *vcpu;
7347
6755bae8
ZA		 7348 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7349 printk_once(KERN_WARNING
7350 "kvm: SMP vm created on host with unstable TSC; "
7351 "guest TSC will not be reliable\n");
c447e76b
LL		 7352
7353 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7354
c447e76b 7355 return vcpu;
26e5215f 7356}
e9b11c17 7357
26e5215f
AK		 7358int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7359{
7360 int r;
e9b11c17 7361
19efffa2 7362 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7363 r = vcpu_load(vcpu);
7364 if (r)
7365 return r;
d28bc9dd 7366 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7367 kvm_mmu_setup(vcpu);
e9b11c17 7368 vcpu_put(vcpu);
26e5215f 7369 return r;
e9b11c17
ZX		 7370}
7371
31928aa5 7372void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7373{
8fe8ab46 7374 struct msr_data msr;
332967a3 7375 struct kvm *kvm = vcpu->kvm;
42897d86 7376
31928aa5
DD		 7377 if (vcpu_load(vcpu))
7378 return;
8fe8ab46
WA		 7379 msr.data = 0x0;
7380 msr.index = MSR_IA32_TSC;
7381 msr.host_initiated = true;
7382 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7383 vcpu_put(vcpu);
7384
630994b3
MT		 7385 if (!kvmclock_periodic_sync)
7386 return;
7387
332967a3
AJ		 7388 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7389 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7390}
7391
d40ccc62 7392void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7393{
9fc77441 7394 int r;
344d9588
GN		 7395 vcpu->arch.apf.msr_val = 0;
7396
9fc77441
MT		 7397 r = vcpu_load(vcpu);
7398 BUG_ON(r);
e9b11c17
ZX		 7399 kvm_mmu_unload(vcpu);
7400 vcpu_put(vcpu);
7401
7402 kvm_x86_ops->vcpu_free(vcpu);
7403}
7404
d28bc9dd 7405void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7406{
e69fab5d
PB		 7407 vcpu->arch.hflags = 0;
7408
7460fb4a
AK		 7409 atomic_set(&vcpu->arch.nmi_queued, 0);
7410 vcpu->arch.nmi_pending = 0;
448fa4a9 7411 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7412 kvm_clear_interrupt_queue(vcpu);
7413 kvm_clear_exception_queue(vcpu);
448fa4a9 7414
42dbaa5a 7415 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7416 kvm_update_dr0123(vcpu);
6f43ed01 7417 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7418 kvm_update_dr6(vcpu);
42dbaa5a 7419 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7420 kvm_update_dr7(vcpu);
42dbaa5a 7421
1119022c
NA		 7422 vcpu->arch.cr2 = 0;
7423
3842d135 7424 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7425 vcpu->arch.apf.msr_val = 0;
c9aaa895 7426 vcpu->arch.st.msr_val = 0;
3842d135 7427
12f9a48f
GC		 7428 kvmclock_reset(vcpu);
7429
af585b92
GN		 7430 kvm_clear_async_pf_completion_queue(vcpu);
7431 kvm_async_pf_hash_reset(vcpu);
7432 vcpu->arch.apf.halted = false;
3842d135 7433
64d60670 7434 if (!init_event) {
d28bc9dd 7435 kvm_pmu_reset(vcpu);
64d60670
PB		 7436 vcpu->arch.smbase = 0x30000;
7437 }
f5132b01 7438
66f7b72e
JS		 7439 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7440 vcpu->arch.regs_avail = ~0;
7441 vcpu->arch.regs_dirty = ~0;
7442
d28bc9dd 7443 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7444}
7445
2b4a273b 7446void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7447{
7448 struct kvm_segment cs;
7449
7450 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7451 cs.selector = vector << 8;
7452 cs.base = vector << 12;
7453 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7454 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7455}
7456
13a34e06 7457int kvm_arch_hardware_enable(void)
e9b11c17 7458{
ca84d1a2
ZA		 7459 struct kvm *kvm;
7460 struct kvm_vcpu *vcpu;
7461 int i;
0dd6a6ed
ZA		 7462 int ret;
7463 u64 local_tsc;
7464 u64 max_tsc = 0;
7465 bool stable, backwards_tsc = false;
18863bdd
AK		 7466
7467 kvm_shared_msr_cpu_online();
13a34e06 7468 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7469 if (ret != 0)
7470 return ret;
7471
4ea1636b 7472 local_tsc = rdtsc();
0dd6a6ed
ZA		 7473 stable = !check_tsc_unstable();
7474 list_for_each_entry(kvm, &vm_list, vm_list) {
7475 kvm_for_each_vcpu(i, vcpu, kvm) {
7476 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7477 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7478 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7479 backwards_tsc = true;
7480 if (vcpu->arch.last_host_tsc > max_tsc)
7481 max_tsc = vcpu->arch.last_host_tsc;
7482 }
7483 }
7484 }
7485
7486 /*
7487 * Sometimes, even reliable TSCs go backwards. This happens on
7488 * platforms that reset TSC during suspend or hibernate actions, but
7489 * maintain synchronization. We must compensate. Fortunately, we can
7490 * detect that condition here, which happens early in CPU bringup,
7491 * before any KVM threads can be running. Unfortunately, we can't
7492 * bring the TSCs fully up to date with real time, as we aren't yet far
7493 * enough into CPU bringup that we know how much real time has actually
7494 * elapsed; our helper function, get_kernel_ns() will be using boot
7495 * variables that haven't been updated yet.
7496 *
7497 * So we simply find the maximum observed TSC above, then record the
7498 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7499 * the adjustment will be applied. Note that we accumulate
7500 * adjustments, in case multiple suspend cycles happen before some VCPU
7501 * gets a chance to run again. In the event that no KVM threads get a
7502 * chance to run, we will miss the entire elapsed period, as we'll have
7503 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7504 * loose cycle time. This isn't too big a deal, since the loss will be
7505 * uniform across all VCPUs (not to mention the scenario is extremely
7506 * unlikely). It is possible that a second hibernate recovery happens
7507 * much faster than a first, causing the observed TSC here to be
7508 * smaller; this would require additional padding adjustment, which is
7509 * why we set last_host_tsc to the local tsc observed here.
7510 *
7511 * N.B. - this code below runs only on platforms with reliable TSC,
7512 * as that is the only way backwards_tsc is set above. Also note
7513 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7514 * have the same delta_cyc adjustment applied if backwards_tsc
7515 * is detected. Note further, this adjustment is only done once,
7516 * as we reset last_host_tsc on all VCPUs to stop this from being
7517 * called multiple times (one for each physical CPU bringup).
7518 *
4a969980 7519 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7520 * will be compensated by the logic in vcpu_load, which sets the TSC to
7521 * catchup mode. This will catchup all VCPUs to real time, but cannot
7522 * guarantee that they stay in perfect synchronization.
7523 */
7524 if (backwards_tsc) {
7525 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7526 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7527 list_for_each_entry(kvm, &vm_list, vm_list) {
7528 kvm_for_each_vcpu(i, vcpu, kvm) {
7529 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7530 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7531 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7532 }
7533
7534 /*
7535 * We have to disable TSC offset matching.. if you were
7536 * booting a VM while issuing an S4 host suspend....
7537 * you may have some problem. Solving this issue is
7538 * left as an exercise to the reader.
7539 */
7540 kvm->arch.last_tsc_nsec = 0;
7541 kvm->arch.last_tsc_write = 0;
7542 }
7543
7544 }
7545 return 0;
e9b11c17
ZX		 7546}
7547
13a34e06 7548void kvm_arch_hardware_disable(void)
e9b11c17 7549{
13a34e06
RK		 7550 kvm_x86_ops->hardware_disable();
7551 drop_user_return_notifiers();
e9b11c17
ZX		 7552}
7553
7554int kvm_arch_hardware_setup(void)
7555{
9e9c3fe4
NA		 7556 int r;
7557
7558 r = kvm_x86_ops->hardware_setup();
7559 if (r != 0)
7560 return r;
7561
35181e86
HZ		 7562 if (kvm_has_tsc_control) {
7563 /*
7564 * Make sure the user can only configure tsc_khz values that
7565 * fit into a signed integer.
7566 * A min value is not calculated needed because it will always
7567 * be 1 on all machines.
7568 */
7569 u64 max = min(0x7fffffffULL,
7570 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7571 kvm_max_guest_tsc_khz = max;
7572
ad721883 7573 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7574 }
ad721883 7575
9e9c3fe4
NA		 7576 kvm_init_msr_list();
7577 return 0;
e9b11c17
ZX		 7578}
7579
7580void kvm_arch_hardware_unsetup(void)
7581{
7582 kvm_x86_ops->hardware_unsetup();
7583}
7584
7585void kvm_arch_check_processor_compat(void *rtn)
7586{
7587 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7588}
7589
7590bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7591{
7592 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7593}
7594EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7595
7596bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7597{
7598 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7599}
7600
3e515705
AK		 7601bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7602{
35754c98 7603 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7604}
7605
54e9818f 7606struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7607EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7608
e9b11c17
ZX		 7609int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7610{
7611 struct page *page;
7612 struct kvm *kvm;
7613 int r;
7614
7615 BUG_ON(vcpu->kvm == NULL);
7616 kvm = vcpu->kvm;
7617
d62caabb 7618 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7619 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7620 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7621 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7622 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7623 else
a4535290 7624 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7625
7626 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7627 if (!page) {
7628 r = -ENOMEM;
7629 goto fail;
7630 }
ad312c7c 7631 vcpu->arch.pio_data = page_address(page);
e9b11c17 7632
cc578287 7633 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7634
e9b11c17
ZX		 7635 r = kvm_mmu_create(vcpu);
7636 if (r < 0)
7637 goto fail_free_pio_data;
7638
7639 if (irqchip_in_kernel(kvm)) {
7640 r = kvm_create_lapic(vcpu);
7641 if (r < 0)
7642 goto fail_mmu_destroy;
54e9818f
GN		 7643 } else
7644 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7645
890ca9ae
HY		 7646 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7647 GFP_KERNEL);
7648 if (!vcpu->arch.mce_banks) {
7649 r = -ENOMEM;
443c39bc 7650 goto fail_free_lapic;
890ca9ae
HY		 7651 }
7652 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7653
f1797359
WY		 7654 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7655 r = -ENOMEM;
f5f48ee1 7656 goto fail_free_mce_banks;
f1797359 7657 }
f5f48ee1 7658
0ee6a517 7659 fx_init(vcpu);
66f7b72e 7660
ba904635 7661 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7662 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7663
7664 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7665 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7666
5a4f55cd
EK		 7667 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7668
74545705
RK		 7669 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7670
af585b92 7671 kvm_async_pf_hash_reset(vcpu);
f5132b01 7672 kvm_pmu_init(vcpu);
af585b92 7673
1c1a9ce9
SR		 7674 vcpu->arch.pending_external_vector = -1;
7675
5c919412
AS		 7676 kvm_hv_vcpu_init(vcpu);
7677
e9b11c17 7678 return 0;
0ee6a517 7679
f5f48ee1
SY		 7680fail_free_mce_banks:
7681 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7682fail_free_lapic:
7683 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7684fail_mmu_destroy:
7685 kvm_mmu_destroy(vcpu);
7686fail_free_pio_data:
ad312c7c 7687 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7688fail:
7689 return r;
7690}
7691
7692void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7693{
f656ce01
MT		 7694 int idx;
7695
1f4b34f8 7696 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7697 kvm_pmu_destroy(vcpu);
36cb93fd 7698 kfree(vcpu->arch.mce_banks);
e9b11c17 7699 kvm_free_lapic(vcpu);
f656ce01 7700 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7701 kvm_mmu_destroy(vcpu);
f656ce01 7702 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7703 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7704 if (!lapic_in_kernel(vcpu))
54e9818f 7705 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7706}
d19a9cd2 7707
e790d9ef
RK		 7708void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7709{
ae97a3b8 7710 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7711}
7712
e08b9637 7713int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7714{
e08b9637
CO		 7715 if (type)
7716 return -EINVAL;
7717
6ef768fa 7718 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7719 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7720 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7721 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7722 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7723
5550af4d
SY		 7724 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7725 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7726 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7727 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7728 &kvm->arch.irq_sources_bitmap);
5550af4d 7729
038f8c11 7730 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7731 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7732 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7733
7734 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7735
7e44e449 7736 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7737 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7738
0eb05bf2 7739 kvm_page_track_init(kvm);
13d268ca 7740 kvm_mmu_init_vm(kvm);
0eb05bf2 7741
d89f5eff 7742 return 0;
d19a9cd2
ZX		 7743}
7744
7745static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7746{
9fc77441
MT		 7747 int r;
7748 r = vcpu_load(vcpu);
7749 BUG_ON(r);
d19a9cd2
ZX		 7750 kvm_mmu_unload(vcpu);
7751 vcpu_put(vcpu);
7752}
7753
7754static void kvm_free_vcpus(struct kvm *kvm)
7755{
7756 unsigned int i;
988a2cae 7757 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7758
7759 /*
7760 * Unpin any mmu pages first.
7761 */
af585b92
GN		 7762 kvm_for_each_vcpu(i, vcpu, kvm) {
7763 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7764 kvm_unload_vcpu_mmu(vcpu);
af585b92 7765 }
988a2cae
GN		 7766 kvm_for_each_vcpu(i, vcpu, kvm)
7767 kvm_arch_vcpu_free(vcpu);
7768
7769 mutex_lock(&kvm->lock);
7770 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7771 kvm->vcpus[i] = NULL;
d19a9cd2 7772
988a2cae
GN		 7773 atomic_set(&kvm->online_vcpus, 0);
7774 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7775}
7776
ad8ba2cd
SY		 7777void kvm_arch_sync_events(struct kvm *kvm)
7778{
332967a3 7779 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7780 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7781 kvm_free_all_assigned_devices(kvm);
aea924f6 7782 kvm_free_pit(kvm);
ad8ba2cd
SY		 7783}
7784
1d8007bd 7785int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7786{
7787 int i, r;
25188b99 7788 unsigned long hva;
f0d648bd
PB		 7789 struct kvm_memslots *slots = kvm_memslots(kvm);
7790 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7791
7792 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7793 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7794 return -EINVAL;
9da0e4d5 7795
f0d648bd
PB		 7796 slot = id_to_memslot(slots, id);
7797 if (size) {
7798 if (WARN_ON(slot->npages))
7799 return -EEXIST;
7800
7801 /*
7802 * MAP_SHARED to prevent internal slot pages from being moved
7803 * by fork()/COW.
7804 */
7805 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7806 MAP_SHARED | MAP_ANONYMOUS, 0);
7807 if (IS_ERR((void *)hva))
7808 return PTR_ERR((void *)hva);
7809 } else {
7810 if (!slot->npages)
7811 return 0;
7812
7813 hva = 0;
7814 }
7815
7816 old = *slot;
9da0e4d5 7817 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7818 struct kvm_userspace_memory_region m;
9da0e4d5 7819
1d8007bd
PB		 7820 m.slot = id | (i << 16);
7821 m.flags = 0;
7822 m.guest_phys_addr = gpa;
f0d648bd 7823 m.userspace_addr = hva;
1d8007bd 7824 m.memory_size = size;
9da0e4d5
PB		 7825 r = __kvm_set_memory_region(kvm, &m);
7826 if (r < 0)
7827 return r;
7828 }
7829
f0d648bd
PB		 7830 if (!size) {
7831 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7832 WARN_ON(r < 0);
7833 }
7834
9da0e4d5
PB		 7835 return 0;
7836}
7837EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7838
1d8007bd 7839int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7840{
7841 int r;
7842
7843 mutex_lock(&kvm->slots_lock);
1d8007bd 7844 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7845 mutex_unlock(&kvm->slots_lock);
7846
7847 return r;
7848}
7849EXPORT_SYMBOL_GPL(x86_set_memory_region);
7850
d19a9cd2
ZX		 7851void kvm_arch_destroy_vm(struct kvm *kvm)
7852{
27469d29
AH		 7853 if (current->mm == kvm->mm) {
7854 /*
7855 * Free memory regions allocated on behalf of userspace,
7856 * unless the the memory map has changed due to process exit
7857 * or fd copying.
7858 */
1d8007bd
PB		 7859 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7860 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7861 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7862 }
6eb55818 7863 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7864 kfree(kvm->arch.vpic);
7865 kfree(kvm->arch.vioapic);
d19a9cd2 7866 kvm_free_vcpus(kvm);
1e08ec4a 7867 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7868 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7869}
0de10343 7870
5587027c 7871void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7872 struct kvm_memory_slot *dont)
7873{
7874 int i;
7875
d89cc617
TY		 7876 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7877 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7878 kvfree(free->arch.rmap[i]);
d89cc617 7879 free->arch.rmap[i] = NULL;
77d11309 7880 }
d89cc617
TY		 7881 if (i == 0)
7882 continue;
7883
7884 if (!dont || free->arch.lpage_info[i - 1] !=
7885 dont->arch.lpage_info[i - 1]) {
548ef284 7886 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7887 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7888 }
7889 }
21ebbeda
XG		 7890
7891 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7892}
7893
5587027c
AK		 7894int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7895 unsigned long npages)
db3fe4eb
TY		 7896{
7897 int i;
7898
d89cc617 7899 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7900 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7901 unsigned long ugfn;
7902 int lpages;
d89cc617 7903 int level = i + 1;
db3fe4eb
TY		 7904
7905 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7906 slot->base_gfn, level) + 1;
7907
d89cc617
TY		 7908 slot->arch.rmap[i] =
7909 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7910 if (!slot->arch.rmap[i])
77d11309 7911 goto out_free;
d89cc617
TY		 7912 if (i == 0)
7913 continue;
77d11309 7914
92f94f1e
XG		 7915 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7916 if (!linfo)
db3fe4eb
TY		 7917 goto out_free;
7918
92f94f1e
XG		 7919 slot->arch.lpage_info[i - 1] = linfo;
7920
db3fe4eb 7921 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7922 linfo[0].disallow_lpage = 1;
db3fe4eb 7923 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7924 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7925 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7926 /*
7927 * If the gfn and userspace address are not aligned wrt each
7928 * other, or if explicitly asked to, disable large page
7929 * support for this slot
7930 */
7931 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7932 !kvm_largepages_enabled()) {
7933 unsigned long j;
7934
7935 for (j = 0; j < lpages; ++j)
92f94f1e 7936 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7937 }
7938 }
7939
21ebbeda
XG		 7940 if (kvm_page_track_create_memslot(slot, npages))
7941 goto out_free;
7942
db3fe4eb
TY		 7943 return 0;
7944
7945out_free:
d89cc617 7946 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7947 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7948 slot->arch.rmap[i] = NULL;
7949 if (i == 0)
7950 continue;
7951
548ef284 7952 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7953 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7954 }
7955 return -ENOMEM;
7956}
7957
15f46015 7958void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7959{
e6dff7d1
TY		 7960 /*
7961 * memslots->generation has been incremented.
7962 * mmio generation may have reached its maximum value.
7963 */
54bf36aa 7964 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7965}
7966
f7784b8e
MT		 7967int kvm_arch_prepare_memory_region(struct kvm *kvm,
7968 struct kvm_memory_slot *memslot,
09170a49 7969 const struct kvm_userspace_memory_region *mem,
7b6195a9 7970 enum kvm_mr_change change)
0de10343 7971{
f7784b8e
MT		 7972 return 0;
7973}
7974
88178fd4
KH		 7975static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7976 struct kvm_memory_slot *new)
7977{
7978 /* Still write protect RO slot */
7979 if (new->flags & KVM_MEM_READONLY) {
7980 kvm_mmu_slot_remove_write_access(kvm, new);
7981 return;
7982 }
7983
7984 /*
7985 * Call kvm_x86_ops dirty logging hooks when they are valid.
7986 *
7987 * kvm_x86_ops->slot_disable_log_dirty is called when:
7988 *
7989 * - KVM_MR_CREATE with dirty logging is disabled
7990 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7991 *
7992 * The reason is, in case of PML, we need to set D-bit for any slots
7993 * with dirty logging disabled in order to eliminate unnecessary GPA
7994 * logging in PML buffer (and potential PML buffer full VMEXT). This
7995 * guarantees leaving PML enabled during guest's lifetime won't have
7996 * any additonal overhead from PML when guest is running with dirty
7997 * logging disabled for memory slots.
7998 *
7999 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8000 * to dirty logging mode.
8001 *
8002 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8003 *
8004 * In case of write protect:
8005 *
8006 * Write protect all pages for dirty logging.
8007 *
8008 * All the sptes including the large sptes which point to this
8009 * slot are set to readonly. We can not create any new large
8010 * spte on this slot until the end of the logging.
8011 *
8012 * See the comments in fast_page_fault().
8013 */
8014 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8015 if (kvm_x86_ops->slot_enable_log_dirty)
8016 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8017 else
8018 kvm_mmu_slot_remove_write_access(kvm, new);
8019 } else {
8020 if (kvm_x86_ops->slot_disable_log_dirty)
8021 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8022 }
8023}
8024
f7784b8e 8025void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8026 const struct kvm_userspace_memory_region *mem,
8482644a 8027 const struct kvm_memory_slot *old,
f36f3f28 8028 const struct kvm_memory_slot *new,
8482644a 8029 enum kvm_mr_change change)
f7784b8e 8030{
8482644a 8031 int nr_mmu_pages = 0;
f7784b8e 8032
48c0e4e9
XG		 8033 if (!kvm->arch.n_requested_mmu_pages)
8034 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8035
48c0e4e9 8036 if (nr_mmu_pages)
0de10343 8037 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8038
3ea3b7fa
WL		 8039 /*
8040 * Dirty logging tracks sptes in 4k granularity, meaning that large
8041 * sptes have to be split. If live migration is successful, the guest
8042 * in the source machine will be destroyed and large sptes will be
8043 * created in the destination. However, if the guest continues to run
8044 * in the source machine (for example if live migration fails), small
8045 * sptes will remain around and cause bad performance.
8046 *
8047 * Scan sptes if dirty logging has been stopped, dropping those
8048 * which can be collapsed into a single large-page spte. Later
8049 * page faults will create the large-page sptes.
8050 */
8051 if ((change != KVM_MR_DELETE) &&
8052 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8053 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8054 kvm_mmu_zap_collapsible_sptes(kvm, new);
8055
c972f3b1 8056 /*
88178fd4 8057 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8058 *
88178fd4
KH		 8059 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8060 * been zapped so no dirty logging staff is needed for old slot. For
8061 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8062 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8063 *
8064 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8065 */
88178fd4 8066 if (change != KVM_MR_DELETE)
f36f3f28 8067 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8068}
1d737c8a 8069
2df72e9b 8070void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8071{
6ca18b69 8072 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8073}
8074
2df72e9b
MT		 8075void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8076 struct kvm_memory_slot *slot)
8077{
6ca18b69 8078 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8079}
8080
5d9bc648
PB		 8081static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8082{
8083 if (!list_empty_careful(&vcpu->async_pf.done))
8084 return true;
8085
8086 if (kvm_apic_has_events(vcpu))
8087 return true;
8088
8089 if (vcpu->arch.pv.pv_unhalted)
8090 return true;
8091
8092 if (atomic_read(&vcpu->arch.nmi_queued))
8093 return true;
8094
73917739
PB		 8095 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8096 return true;
8097
5d9bc648
PB		 8098 if (kvm_arch_interrupt_allowed(vcpu) &&
8099 kvm_cpu_has_interrupt(vcpu))
8100 return true;
8101
1f4b34f8
AS		 8102 if (kvm_hv_has_stimer_pending(vcpu))
8103 return true;
8104
5d9bc648
PB		 8105 return false;
8106}
8107
1d737c8a
ZX		 8108int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8109{
b6b8a145
JK		 8110 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8111 kvm_x86_ops->check_nested_events(vcpu, false);
8112
5d9bc648 8113 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8114}
5736199a 8115
b6d33834 8116int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8117{
b6d33834 8118 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8119}
78646121
GN		 8120
8121int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8122{
8123 return kvm_x86_ops->interrupt_allowed(vcpu);
8124}
229456fc 8125
82b32774 8126unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8127{
82b32774
NA		 8128 if (is_64_bit_mode(vcpu))
8129 return kvm_rip_read(vcpu);
8130 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8131 kvm_rip_read(vcpu));
8132}
8133EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8134
82b32774
NA		 8135bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8136{
8137 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8138}
8139EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8140
94fe45da
JK		 8141unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8142{
8143 unsigned long rflags;
8144
8145 rflags = kvm_x86_ops->get_rflags(vcpu);
8146 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8147 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8148 return rflags;
8149}
8150EXPORT_SYMBOL_GPL(kvm_get_rflags);
8151
6addfc42 8152static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8153{
8154 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8155 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8156 rflags |= X86_EFLAGS_TF;
94fe45da 8157 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8158}
8159
8160void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8161{
8162 __kvm_set_rflags(vcpu, rflags);
3842d135 8163 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8164}
8165EXPORT_SYMBOL_GPL(kvm_set_rflags);
8166
56028d08
GN		 8167void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8168{
8169 int r;
8170
fb67e14f 8171 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8172 work->wakeup_all)
56028d08
GN		 8173 return;
8174
8175 r = kvm_mmu_reload(vcpu);
8176 if (unlikely(r))
8177 return;
8178
fb67e14f
XG		 8179 if (!vcpu->arch.mmu.direct_map &&
8180 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8181 return;
8182
56028d08
GN		 8183 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8184}
8185
af585b92
GN		 8186static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8187{
8188 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8189}
8190
8191static inline u32 kvm_async_pf_next_probe(u32 key)
8192{
8193 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8194}
8195
8196static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8197{
8198 u32 key = kvm_async_pf_hash_fn(gfn);
8199
8200 while (vcpu->arch.apf.gfns[key] != ~0)
8201 key = kvm_async_pf_next_probe(key);
8202
8203 vcpu->arch.apf.gfns[key] = gfn;
8204}
8205
8206static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8207{
8208 int i;
8209 u32 key = kvm_async_pf_hash_fn(gfn);
8210
8211 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8212 (vcpu->arch.apf.gfns[key] != gfn &&
8213 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8214 key = kvm_async_pf_next_probe(key);
8215
8216 return key;
8217}
8218
8219bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8220{
8221 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8222}
8223
8224static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8225{
8226 u32 i, j, k;
8227
8228 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8229 while (true) {
8230 vcpu->arch.apf.gfns[i] = ~0;
8231 do {
8232 j = kvm_async_pf_next_probe(j);
8233 if (vcpu->arch.apf.gfns[j] == ~0)
8234 return;
8235 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8236 /*
8237 * k lies cyclically in ]i,j]
8238 * | i.k.j |
8239 * |....j i.k.| or |.k..j i...|
8240 */
8241 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8242 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8243 i = j;
8244 }
8245}
8246
7c90705b
GN		 8247static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8248{
8249
8250 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8251 sizeof(val));
8252}
8253
af585b92
GN		 8254void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8255 struct kvm_async_pf *work)
8256{
6389ee94
AK		 8257 struct x86_exception fault;
8258
7c90705b 8259 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8260 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8261
8262 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8263 (vcpu->arch.apf.send_user_only &&
8264 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8265 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8266 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8267 fault.vector = PF_VECTOR;
8268 fault.error_code_valid = true;
8269 fault.error_code = 0;
8270 fault.nested_page_fault = false;
8271 fault.address = work->arch.token;
8272 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8273 }
af585b92
GN		 8274}
8275
8276void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8277 struct kvm_async_pf *work)
8278{
6389ee94
AK		 8279 struct x86_exception fault;
8280
7c90705b 8281 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8282 if (work->wakeup_all)
7c90705b
GN		 8283 work->arch.token = ~0; /* broadcast wakeup */
8284 else
8285 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8286
8287 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8288 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8289 fault.vector = PF_VECTOR;
8290 fault.error_code_valid = true;
8291 fault.error_code = 0;
8292 fault.nested_page_fault = false;
8293 fault.address = work->arch.token;
8294 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8295 }
e6d53e3b 8296 vcpu->arch.apf.halted = false;
a4fa1635 8297 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8298}
8299
8300bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8301{
8302 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8303 return true;
8304 else
8305 return !kvm_event_needs_reinjection(vcpu) &&
8306 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8307}
8308
5544eb9b
PB		 8309void kvm_arch_start_assignment(struct kvm *kvm)
8310{
8311 atomic_inc(&kvm->arch.assigned_device_count);
8312}
8313EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8314
8315void kvm_arch_end_assignment(struct kvm *kvm)
8316{
8317 atomic_dec(&kvm->arch.assigned_device_count);
8318}
8319EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8320
8321bool kvm_arch_has_assigned_device(struct kvm *kvm)
8322{
8323 return atomic_read(&kvm->arch.assigned_device_count);
8324}
8325EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8326
e0f0bbc5
AW		 8327void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8328{
8329 atomic_inc(&kvm->arch.noncoherent_dma_count);
8330}
8331EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8332
8333void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8334{
8335 atomic_dec(&kvm->arch.noncoherent_dma_count);
8336}
8337EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8338
8339bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8340{
8341 return atomic_read(&kvm->arch.noncoherent_dma_count);
8342}
8343EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8344
87276880
FW		 8345int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8346 struct irq_bypass_producer *prod)
8347{
8348 struct kvm_kernel_irqfd *irqfd =
8349 container_of(cons, struct kvm_kernel_irqfd, consumer);
8350
8351 if (kvm_x86_ops->update_pi_irte) {
8352 irqfd->producer = prod;
8353 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8354 prod->irq, irqfd->gsi, 1);
8355 }
8356
8357 return -EINVAL;
8358}
8359
8360void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8361 struct irq_bypass_producer *prod)
8362{
8363 int ret;
8364 struct kvm_kernel_irqfd *irqfd =
8365 container_of(cons, struct kvm_kernel_irqfd, consumer);
8366
8367 if (!kvm_x86_ops->update_pi_irte) {
8368 WARN_ON(irqfd->producer != NULL);
8369 return;
8370 }
8371
8372 WARN_ON(irqfd->producer != prod);
8373 irqfd->producer = NULL;
8374
8375 /*
8376 * When producer of consumer is unregistered, we change back to
8377 * remapped mode, so we can re-use the current implementation
8378 * when the irq is masked/disabed or the consumer side (KVM
8379 * int this case doesn't want to receive the interrupts.
8380 */
8381 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8382 if (ret)
8383 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8384 " fails: %d\n", irqfd->consumer.token, ret);
8385}
8386
8387int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8388 uint32_t guest_irq, bool set)
8389{
8390 if (!kvm_x86_ops->update_pi_irte)
8391 return -EINVAL;
8392
8393 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8394}
8395
52004014
FW		 8396bool kvm_vector_hashing_enabled(void)
8397{
8398 return vector_hashing;
8399}
8400EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8401
229456fc 8402EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8403EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8404EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8405EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8406EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8407EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8408EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8409EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8410EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8411EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8412EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8413EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8414EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8415EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8416EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8417EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux 6.x block layer and io_uring tree(s)