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KVM: LAPIC: Inject timer interrupt via posted interrupt
[linux-2.6-block.git] / arch / x86 / kvm / vmx / vmx.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
6aa8b732
AK		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * Copyright (C) 2006 Qumranet, Inc.
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
6aa8b732
AK		 14 */
15
199b118a
SC		 16#include <linux/frame.h>
17#include <linux/highmem.h>
18#include <linux/hrtimer.h>
19#include <linux/kernel.h>
edf88417 20#include <linux/kvm_host.h>
6aa8b732 21#include <linux/module.h>
c7addb90 22#include <linux/moduleparam.h>
e9bda3b3 23#include <linux/mod_devicetable.h>
199b118a 24#include <linux/mm.h>
199b118a 25#include <linux/sched.h>
b284909a 26#include <linux/sched/smt.h>
5a0e3ad6 27#include <linux/slab.h>
cafd6659 28#include <linux/tboot.h>
199b118a 29#include <linux/trace_events.h>
e495606d 30
199b118a 31#include <asm/apic.h>
fd8ca6da 32#include <asm/asm.h>
28b835d6 33#include <asm/cpu.h>
199b118a 34#include <asm/debugreg.h>
3b3be0d1 35#include <asm/desc.h>
952f07ec 36#include <asm/fpu/internal.h>
199b118a 37#include <asm/io.h>
efc64404 38#include <asm/irq_remapping.h>
199b118a
SC		 39#include <asm/kexec.h>
40#include <asm/perf_event.h>
41#include <asm/mce.h>
d6e41f11 42#include <asm/mmu_context.h>
773e8a04 43#include <asm/mshyperv.h>
199b118a
SC		 44#include <asm/spec-ctrl.h>
45#include <asm/virtext.h>
46#include <asm/vmx.h>
6aa8b732 47
3077c191 48#include "capabilities.h"
199b118a 49#include "cpuid.h"
4cebd747 50#include "evmcs.h"
199b118a
SC		 51#include "irq.h"
52#include "kvm_cache_regs.h"
53#include "lapic.h"
54#include "mmu.h"
55d2375e 55#include "nested.h"
89b0c9f5 56#include "ops.h"
25462f7f 57#include "pmu.h"
199b118a 58#include "trace.h"
cb1d474b 59#include "vmcs.h"
609363cf 60#include "vmcs12.h"
89b0c9f5 61#include "vmx.h"
199b118a 62#include "x86.h"
229456fc 63
6aa8b732
AK		 64MODULE_AUTHOR("Qumranet");
65MODULE_LICENSE("GPL");
66
e9bda3b3
JT		 67static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
69 {}
70};
71MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
72
2c4fd91d 73bool __read_mostly enable_vpid = 1;
736caefe 74module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 75
d02fcf50
PB		 76static bool __read_mostly enable_vnmi = 1;
77module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
78
2c4fd91d 79bool __read_mostly flexpriority_enabled = 1;
736caefe 80module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 81
2c4fd91d 82bool __read_mostly enable_ept = 1;
736caefe 83module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 84
2c4fd91d 85bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 86module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
88
2c4fd91d 89bool __read_mostly enable_ept_ad_bits = 1;
83c3a331
XH		 90module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
91
a27685c3 92static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 93module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 94
476bc001 95static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 96module_param(fasteoi, bool, S_IRUGO);
97
5a71785d 98static bool __read_mostly enable_apicv = 1;
01e439be 99module_param(enable_apicv, bool, S_IRUGO);
83d4c286 100
801d3424
NHE		 101/*
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
105 */
1e58e5e5 106static bool __read_mostly nested = 1;
801d3424
NHE		 107module_param(nested, bool, S_IRUGO);
108
20300099
WL		 109static u64 __read_mostly host_xss;
110
2c4fd91d 111bool __read_mostly enable_pml = 1;
843e4330
KH		 112module_param_named(pml, enable_pml, bool, S_IRUGO);
113
6f2f8453
PB		 114static bool __read_mostly dump_invalid_vmcs = 0;
115module_param(dump_invalid_vmcs, bool, 0644);
116
904e14fb
PB		 117#define MSR_BITMAP_MODE_X2APIC 1
118#define MSR_BITMAP_MODE_X2APIC_APICV 2
904e14fb 119
64903d61
HZ		 120#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
121
64672c95
YJ		 122/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123static int __read_mostly cpu_preemption_timer_multi;
124static bool __read_mostly enable_preemption_timer = 1;
125#ifdef CONFIG_X86_64
126module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
127#endif
128
3de6347b 129#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
1706bd0c
SC		 130#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131#define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 134#define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
fd8cb433 136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
4c38609a 137
5dc1f044 138#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
cdc0e244
AK		 139#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
141
78ac8b47
AK		 142#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
143
bf8c55d8
CP		 144#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
148
149#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
151
4b8d54f9
ZE		 152/*
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 156 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
162 */
c8e88717 163static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
a87c99e6 164module_param(ple_gap, uint, 0444);
b4a2d31d 165
7fbc85a5
BM		 166static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167module_param(ple_window, uint, 0444);
4b8d54f9 168
b4a2d31d 169/* Default doubles per-vcpu window every exit. */
c8e88717 170static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
7fbc85a5 171module_param(ple_window_grow, uint, 0444);
b4a2d31d
RK		 172
173/* Default resets per-vcpu window every exit to ple_window. */
c8e88717 174static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
7fbc85a5 175module_param(ple_window_shrink, uint, 0444);
b4a2d31d
RK		 176
177/* Default is to compute the maximum so we can never overflow. */
7fbc85a5
BM		 178static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179module_param(ple_window_max, uint, 0444);
b4a2d31d 180
f99e3daf
CP		 181/* Default is SYSTEM mode, 1 for host-guest mode */
182int __read_mostly pt_mode = PT_MODE_SYSTEM;
183module_param(pt_mode, int, S_IRUGO);
184
a399477e 185static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
427362a1 186static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
dd4bfa73 187static DEFINE_MUTEX(vmx_l1d_flush_mutex);
a399477e 188
7db92e16
TG		 189/* Storage for pre module init parameter parsing */
190static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 191
192static const struct {
193 const char *option;
0027ff2a 194 bool for_parse;
a399477e 195} vmentry_l1d_param[] = {
0027ff2a
PB		 196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
a399477e
KRW		 202};
203
7db92e16
TG		 204#define L1D_CACHE_ORDER 4
205static void *vmx_l1d_flush_pages;
206
207static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
a399477e 208{
7db92e16 209 struct page *page;
288d152c 210 unsigned int i;
a399477e 211
7db92e16
TG		 212 if (!enable_ept) {
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
214 return 0;
a399477e
KRW		 215 }
216
d806afa4
YW		 217 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
218 u64 msr;
219
220 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
221 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
222 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
223 return 0;
224 }
225 }
8e0b2b91 226
d90a7a0e
JK		 227 /* If set to auto use the default l1tf mitigation method */
228 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
229 switch (l1tf_mitigation) {
230 case L1TF_MITIGATION_OFF:
231 l1tf = VMENTER_L1D_FLUSH_NEVER;
232 break;
233 case L1TF_MITIGATION_FLUSH_NOWARN:
234 case L1TF_MITIGATION_FLUSH:
235 case L1TF_MITIGATION_FLUSH_NOSMT:
236 l1tf = VMENTER_L1D_FLUSH_COND;
237 break;
238 case L1TF_MITIGATION_FULL:
239 case L1TF_MITIGATION_FULL_FORCE:
240 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
241 break;
242 }
243 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
244 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
245 }
246
7db92e16
TG		 247 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
248 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
41836839
BG		 249 /*
250 * This allocation for vmx_l1d_flush_pages is not tied to a VM
251 * lifetime and so should not be charged to a memcg.
252 */
7db92e16
TG		 253 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
254 if (!page)
255 return -ENOMEM;
256 vmx_l1d_flush_pages = page_address(page);
288d152c
NS		 257
258 /*
259 * Initialize each page with a different pattern in
260 * order to protect against KSM in the nested
261 * virtualization case.
262 */
263 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
264 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
265 PAGE_SIZE);
266 }
7db92e16
TG		 267 }
268
269 l1tf_vmx_mitigation = l1tf;
270
895ae47f
TG		 271 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
272 static_branch_enable(&vmx_l1d_should_flush);
273 else
274 static_branch_disable(&vmx_l1d_should_flush);
4c6523ec 275
427362a1
NS		 276 if (l1tf == VMENTER_L1D_FLUSH_COND)
277 static_branch_enable(&vmx_l1d_flush_cond);
895ae47f 278 else
427362a1 279 static_branch_disable(&vmx_l1d_flush_cond);
7db92e16
TG		 280 return 0;
281}
282
283static int vmentry_l1d_flush_parse(const char *s)
284{
285 unsigned int i;
286
287 if (s) {
288 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
0027ff2a
PB		 289 if (vmentry_l1d_param[i].for_parse &&
290 sysfs_streq(s, vmentry_l1d_param[i].option))
291 return i;
7db92e16
TG		 292 }
293 }
a399477e
KRW		 294 return -EINVAL;
295}
296
7db92e16
TG		 297static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
298{
dd4bfa73 299 int l1tf, ret;
7db92e16 300
7db92e16
TG		 301 l1tf = vmentry_l1d_flush_parse(s);
302 if (l1tf < 0)
303 return l1tf;
304
0027ff2a
PB		 305 if (!boot_cpu_has(X86_BUG_L1TF))
306 return 0;
307
7db92e16
TG		 308 /*
309 * Has vmx_init() run already? If not then this is the pre init
310 * parameter parsing. In that case just store the value and let
311 * vmx_init() do the proper setup after enable_ept has been
312 * established.
313 */
314 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
315 vmentry_l1d_flush_param = l1tf;
316 return 0;
317 }
318
dd4bfa73
TG		 319 mutex_lock(&vmx_l1d_flush_mutex);
320 ret = vmx_setup_l1d_flush(l1tf);
321 mutex_unlock(&vmx_l1d_flush_mutex);
322 return ret;
7db92e16
TG		 323}
324
a399477e
KRW		 325static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
326{
0027ff2a
PB		 327 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
328 return sprintf(s, "???\n");
329
7db92e16 330 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
a399477e
KRW		 331}
332
333static const struct kernel_param_ops vmentry_l1d_flush_ops = {
334 .set = vmentry_l1d_flush_set,
335 .get = vmentry_l1d_flush_get,
336};
895ae47f 337module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
a399477e 338
d99e4152
GN		 339static bool guest_state_valid(struct kvm_vcpu *vcpu);
340static u32 vmx_segment_access_rights(struct kvm_segment *var);
1e4329ee 341static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
15d45071 342 u32 msr, int type);
75880a01 343
453eafbe
SC		 344void vmx_vmexit(void);
345
6aa8b732 346static DEFINE_PER_CPU(struct vmcs *, vmxarea);
75edce8a 347DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 348/*
349 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
350 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
351 */
352static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 353
bf9f6ac8
FW		 354/*
355 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
356 * can find which vCPU should be waken up.
357 */
358static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
359static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
360
2384d2b3
SY		 361static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
362static DEFINE_SPINLOCK(vmx_vpid_lock);
363
3077c191
SC		 364struct vmcs_config vmcs_config;
365struct vmx_capability vmx_capability;
d56f546d 366
6aa8b732
AK		 367#define VMX_SEGMENT_FIELD(seg) \
368 [VCPU_SREG_##seg] = { \
369 .selector = GUEST_##seg##_SELECTOR, \
370 .base = GUEST_##seg##_BASE, \
371 .limit = GUEST_##seg##_LIMIT, \
372 .ar_bytes = GUEST_##seg##_AR_BYTES, \
373 }
374
772e0318 375static const struct kvm_vmx_segment_field {
6aa8b732
AK		 376 unsigned selector;
377 unsigned base;
378 unsigned limit;
379 unsigned ar_bytes;
380} kvm_vmx_segment_fields[] = {
381 VMX_SEGMENT_FIELD(CS),
382 VMX_SEGMENT_FIELD(DS),
383 VMX_SEGMENT_FIELD(ES),
384 VMX_SEGMENT_FIELD(FS),
385 VMX_SEGMENT_FIELD(GS),
386 VMX_SEGMENT_FIELD(SS),
387 VMX_SEGMENT_FIELD(TR),
388 VMX_SEGMENT_FIELD(LDTR),
389};
390
cf3646eb 391u64 host_efer;
2342080c 392static unsigned long host_idt_base;
26bb0981 393
4d56c8a7 394/*
898a811f
JM		 395 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
396 * will emulate SYSCALL in legacy mode if the vendor string in guest
397 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
398 * support this emulation, IA32_STAR must always be included in
399 * vmx_msr_index[], even in i386 builds.
4d56c8a7 400 */
cf3646eb 401const u32 vmx_msr_index[] = {
05b3e0c2 402#ifdef CONFIG_X86_64
44ea2b17 403 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 404#endif
8c06585d 405 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 406};
6aa8b732 407
773e8a04
VK		 408#if IS_ENABLED(CONFIG_HYPERV)
409static bool __read_mostly enlightened_vmcs = true;
410module_param(enlightened_vmcs, bool, 0444);
411
877ad952
TL		 412/* check_ept_pointer() should be under protection of ept_pointer_lock. */
413static void check_ept_pointer_match(struct kvm *kvm)
414{
415 struct kvm_vcpu *vcpu;
416 u64 tmp_eptp = INVALID_PAGE;
417 int i;
418
419 kvm_for_each_vcpu(i, vcpu, kvm) {
420 if (!VALID_PAGE(tmp_eptp)) {
421 tmp_eptp = to_vmx(vcpu)->ept_pointer;
422 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
423 to_kvm_vmx(kvm)->ept_pointers_match
424 = EPT_POINTERS_MISMATCH;
425 return;
426 }
427 }
428
429 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
430}
431
8997f657 432static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
1f3a3e46
LT		 433 void *data)
434{
435 struct kvm_tlb_range *range = data;
436
437 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
438 range->pages);
439}
440
441static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
442 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
443{
444 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
445
446 /*
447 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
448 * of the base of EPT PML4 table, strip off EPT configuration
449 * information.
450 */
451 if (range)
452 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
453 kvm_fill_hv_flush_list_func, (void *)range);
454 else
455 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
456}
457
458static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
459 struct kvm_tlb_range *range)
877ad952 460{
a5c214da 461 struct kvm_vcpu *vcpu;
b7c1c226 462 int ret = 0, i;
877ad952
TL		 463
464 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
465
466 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
467 check_ept_pointer_match(kvm);
468
469 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
53963a70 470 kvm_for_each_vcpu(i, vcpu, kvm) {
1f3a3e46
LT		 471 /* If ept_pointer is invalid pointer, bypass flush request. */
472 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
473 ret |= __hv_remote_flush_tlb_with_range(
474 kvm, vcpu, range);
53963a70 475 }
a5c214da 476 } else {
1f3a3e46
LT		 477 ret = __hv_remote_flush_tlb_with_range(kvm,
478 kvm_get_vcpu(kvm, 0), range);
877ad952 479 }
877ad952 480
877ad952
TL		 481 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
482 return ret;
483}
1f3a3e46
LT		 484static int hv_remote_flush_tlb(struct kvm *kvm)
485{
486 return hv_remote_flush_tlb_with_range(kvm, NULL);
487}
488
773e8a04
VK		 489#endif /* IS_ENABLED(CONFIG_HYPERV) */
490
64672c95
YJ		 491/*
492 * Comment's format: document - errata name - stepping - processor name.
493 * Refer from
494 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
495 */
496static u32 vmx_preemption_cpu_tfms[] = {
497/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
4980x000206E6,
499/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
500/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
501/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
5020x00020652,
503/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
5040x00020655,
505/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
506/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
507/*
508 * 320767.pdf - AAP86 - B1 -
509 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
510 */
5110x000106E5,
512/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
5130x000106A0,
514/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
5150x000106A1,
516/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
5170x000106A4,
518 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
519 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
520 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
5210x000106A5,
3d82c565
WH		 522 /* Xeon E3-1220 V2 */
5230x000306A8,
64672c95
YJ		 524};
525
526static inline bool cpu_has_broken_vmx_preemption_timer(void)
527{
528 u32 eax = cpuid_eax(0x00000001), i;
529
530 /* Clear the reserved bits */
531 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 532 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 533 if (eax == vmx_preemption_cpu_tfms[i])
534 return true;
535
536 return false;
537}
538
35754c98 539static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 540{
35754c98 541 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 542}
543
04547156
SY		 544static inline bool report_flexpriority(void)
545{
546 return flexpriority_enabled;
547}
548
97b7ead3 549static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 550{
551 int i;
552
a2fa3e9f 553 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 554 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 555 return i;
556 return -1;
557}
558
97b7ead3 559struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 560{
561 int i;
562
8b9cf98c 563 i = __find_msr_index(vmx, msr);
a75beee6 564 if (i >= 0)
a2fa3e9f 565 return &vmx->guest_msrs[i];
8b6d44c7 566 return NULL;
7725f0ba
AK		 567}
568
7c97fcb3
SC		 569void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
570{
571 vmcs_clear(loaded_vmcs->vmcs);
572 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
573 vmcs_clear(loaded_vmcs->shadow_vmcs);
574 loaded_vmcs->cpu = -1;
575 loaded_vmcs->launched = 0;
576}
577
2965faa5 578#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 579/*
580 * This bitmap is used to indicate whether the vmclear
581 * operation is enabled on all cpus. All disabled by
582 * default.
583 */
584static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
585
586static inline void crash_enable_local_vmclear(int cpu)
587{
588 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
589}
590
591static inline void crash_disable_local_vmclear(int cpu)
592{
593 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
594}
595
596static inline int crash_local_vmclear_enabled(int cpu)
597{
598 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
599}
600
601static void crash_vmclear_local_loaded_vmcss(void)
602{
603 int cpu = raw_smp_processor_id();
604 struct loaded_vmcs *v;
605
606 if (!crash_local_vmclear_enabled(cpu))
607 return;
608
609 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
610 loaded_vmcss_on_cpu_link)
611 vmcs_clear(v->vmcs);
612}
613#else
614static inline void crash_enable_local_vmclear(int cpu) { }
615static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 616#endif /* CONFIG_KEXEC_CORE */
8f536b76 617
d462b819 618static void __loaded_vmcs_clear(void *arg)
6aa8b732 619{
d462b819 620 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 621 int cpu = raw_smp_processor_id();
6aa8b732 622
d462b819
NHE		 623 if (loaded_vmcs->cpu != cpu)
624 return; /* vcpu migration can race with cpu offline */
625 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 626 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 627 crash_disable_local_vmclear(cpu);
d462b819 628 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 629
630 /*
631 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
632 * is before setting loaded_vmcs->vcpu to -1 which is done in
633 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
634 * then adds the vmcs into percpu list before it is deleted.
635 */
636 smp_wmb();
637
d462b819 638 loaded_vmcs_init(loaded_vmcs);
8f536b76 639 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 640}
641
89b0c9f5 642void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 643{
e6c7d321
XG		 644 int cpu = loaded_vmcs->cpu;
645
646 if (cpu != -1)
647 smp_call_function_single(cpu,
648 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 649}
650
2fb92db1
AK		 651static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
652 unsigned field)
653{
654 bool ret;
655 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
656
657 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
658 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
659 vmx->segment_cache.bitmask = 0;
660 }
661 ret = vmx->segment_cache.bitmask & mask;
662 vmx->segment_cache.bitmask |= mask;
663 return ret;
664}
665
666static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
667{
668 u16 *p = &vmx->segment_cache.seg[seg].selector;
669
670 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
671 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
672 return *p;
673}
674
675static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
676{
677 ulong *p = &vmx->segment_cache.seg[seg].base;
678
679 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
680 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
681 return *p;
682}
683
684static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
685{
686 u32 *p = &vmx->segment_cache.seg[seg].limit;
687
688 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
689 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
690 return *p;
691}
692
693static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
694{
695 u32 *p = &vmx->segment_cache.seg[seg].ar;
696
697 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
698 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
699 return *p;
700}
701
97b7ead3 702void update_exception_bitmap(struct kvm_vcpu *vcpu)
abd3f2d6
AK		 703{
704 u32 eb;
705
fd7373cc 706 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 707 (1u << DB_VECTOR) | (1u << AC_VECTOR);
9e869480
LA		 708 /*
709 * Guest access to VMware backdoor ports could legitimately
710 * trigger #GP because of TSS I/O permission bitmap.
711 * We intercept those #GP and allow access to them anyway
712 * as VMware does.
713 */
714 if (enable_vmware_backdoor)
715 eb |= (1u << GP_VECTOR);
fd7373cc
JK		 716 if ((vcpu->guest_debug &
717 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
718 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
719 eb |= 1u << BP_VECTOR;
7ffd92c5 720 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 721 eb = ~0;
089d034e 722 if (enable_ept)
1439442c 723 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE		 724
725 /* When we are running a nested L2 guest and L1 specified for it a
726 * certain exception bitmap, we must trap the same exceptions and pass
727 * them to L1. When running L2, we will only handle the exceptions
728 * specified above if L1 did not want them.
729 */
730 if (is_guest_mode(vcpu))
731 eb |= get_vmcs12(vcpu)->exception_bitmap;
732
abd3f2d6
AK		 733 vmcs_write32(EXCEPTION_BITMAP, eb);
734}
735
d28b387f
KA		 736/*
737 * Check if MSR is intercepted for currently loaded MSR bitmap.
738 */
739static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
740{
741 unsigned long *msr_bitmap;
742 int f = sizeof(unsigned long);
743
744 if (!cpu_has_vmx_msr_bitmap())
745 return true;
746
747 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
748
749 if (msr <= 0x1fff) {
750 return !!test_bit(msr, msr_bitmap + 0x800 / f);
751 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
752 msr &= 0x1fff;
753 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
754 }
755
756 return true;
757}
758
2961e876
GN		 759static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
760 unsigned long entry, unsigned long exit)
8bf00a52 761{
2961e876
GN		 762 vm_entry_controls_clearbit(vmx, entry);
763 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 764}
765
ca83b4a7
KRW		 766static int find_msr(struct vmx_msrs *m, unsigned int msr)
767{
768 unsigned int i;
769
770 for (i = 0; i < m->nr; ++i) {
771 if (m->val[i].index == msr)
772 return i;
773 }
774 return -ENOENT;
775}
776
61d2ef2c
AK		 777static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
778{
ca83b4a7 779 int i;
61d2ef2c
AK		 780 struct msr_autoload *m = &vmx->msr_autoload;
781
8bf00a52
GN		 782 switch (msr) {
783 case MSR_EFER:
c73da3fc 784 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 785 clear_atomic_switch_msr_special(vmx,
786 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 787 VM_EXIT_LOAD_IA32_EFER);
788 return;
789 }
790 break;
791 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 792 if (cpu_has_load_perf_global_ctrl()) {
2961e876 793 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 794 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
795 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
796 return;
797 }
798 break;
110312c8 799 }
ca83b4a7
KRW		 800 i = find_msr(&m->guest, msr);
801 if (i < 0)
31907093 802 goto skip_guest;
33966dd6 803 --m->guest.nr;
33966dd6 804 m->guest.val[i] = m->guest.val[m->guest.nr];
33966dd6 805 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
110312c8 806
31907093
KRW		 807skip_guest:
808 i = find_msr(&m->host, msr);
809 if (i < 0)
61d2ef2c 810 return;
31907093
KRW		 811
812 --m->host.nr;
813 m->host.val[i] = m->host.val[m->host.nr];
33966dd6 814 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c
AK		 815}
816
2961e876
GN		 817static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
818 unsigned long entry, unsigned long exit,
819 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
820 u64 guest_val, u64 host_val)
8bf00a52
GN		 821{
822 vmcs_write64(guest_val_vmcs, guest_val);
5a5e8a15
SC		 823 if (host_val_vmcs != HOST_IA32_EFER)
824 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 825 vm_entry_controls_setbit(vmx, entry);
826 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 827}
828
61d2ef2c 829static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
989e3992 830 u64 guest_val, u64 host_val, bool entry_only)
61d2ef2c 831{
989e3992 832 int i, j = 0;
61d2ef2c
AK		 833 struct msr_autoload *m = &vmx->msr_autoload;
834
8bf00a52
GN		 835 switch (msr) {
836 case MSR_EFER:
c73da3fc 837 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 838 add_atomic_switch_msr_special(vmx,
839 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 840 VM_EXIT_LOAD_IA32_EFER,
841 GUEST_IA32_EFER,
842 HOST_IA32_EFER,
843 guest_val, host_val);
844 return;
845 }
846 break;
847 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 848 if (cpu_has_load_perf_global_ctrl()) {
2961e876 849 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 850 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
851 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
852 GUEST_IA32_PERF_GLOBAL_CTRL,
853 HOST_IA32_PERF_GLOBAL_CTRL,
854 guest_val, host_val);
855 return;
856 }
857 break;
7099e2e1
RK		 858 case MSR_IA32_PEBS_ENABLE:
859 /* PEBS needs a quiescent period after being disabled (to write
860 * a record). Disabling PEBS through VMX MSR swapping doesn't
861 * provide that period, so a CPU could write host's record into
862 * guest's memory.
863 */
864 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 865 }
866
ca83b4a7 867 i = find_msr(&m->guest, msr);
989e3992
KRW		 868 if (!entry_only)
869 j = find_msr(&m->host, msr);
61d2ef2c 870
98ae70cc
XL		 871 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
872 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
60266204 873 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 874 "Can't add msr %x\n", msr);
875 return;
61d2ef2c 876 }
31907093 877 if (i < 0) {
ca83b4a7 878 i = m->guest.nr++;
33966dd6 879 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
31907093 880 }
989e3992
KRW		 881 m->guest.val[i].index = msr;
882 m->guest.val[i].value = guest_val;
883
884 if (entry_only)
885 return;
61d2ef2c 886
31907093
KRW		 887 if (j < 0) {
888 j = m->host.nr++;
33966dd6 889 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c 890 }
31907093
KRW		 891 m->host.val[j].index = msr;
892 m->host.val[j].value = host_val;
61d2ef2c
AK		 893}
894
92c0d900 895static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 896{
844a5fe2
PB		 897 u64 guest_efer = vmx->vcpu.arch.efer;
898 u64 ignore_bits = 0;
899
900 if (!enable_ept) {
901 /*
902 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
903 * host CPUID is more efficient than testing guest CPUID
904 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
905 */
906 if (boot_cpu_has(X86_FEATURE_SMEP))
907 guest_efer |= EFER_NX;
908 else if (!(guest_efer & EFER_NX))
909 ignore_bits |= EFER_NX;
910 }
3a34a881 911
51c6cf66 912 /*
844a5fe2 913 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 914 */
844a5fe2 915 ignore_bits |= EFER_SCE;
51c6cf66
AK		 916#ifdef CONFIG_X86_64
917 ignore_bits |= EFER_LMA | EFER_LME;
918 /* SCE is meaningful only in long mode on Intel */
919 if (guest_efer & EFER_LMA)
920 ignore_bits &= ~(u64)EFER_SCE;
921#endif
84ad33ef 922
f6577a5f
AL		 923 /*
924 * On EPT, we can't emulate NX, so we must switch EFER atomically.
925 * On CPUs that support "load IA32_EFER", always switch EFER
926 * atomically, since it's faster than switching it manually.
927 */
c73da3fc 928 if (cpu_has_load_ia32_efer() ||
f6577a5f 929 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 930 if (!(guest_efer & EFER_LMA))
931 guest_efer &= ~EFER_LME;
54b98bff
AL		 932 if (guest_efer != host_efer)
933 add_atomic_switch_msr(vmx, MSR_EFER,
989e3992 934 guest_efer, host_efer, false);
02343cf2
SC		 935 else
936 clear_atomic_switch_msr(vmx, MSR_EFER);
84ad33ef 937 return false;
844a5fe2 938 } else {
02343cf2
SC		 939 clear_atomic_switch_msr(vmx, MSR_EFER);
940
844a5fe2
PB		 941 guest_efer &= ~ignore_bits;
942 guest_efer |= host_efer & ignore_bits;
943
944 vmx->guest_msrs[efer_offset].data = guest_efer;
945 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 946
844a5fe2
PB		 947 return true;
948 }
51c6cf66
AK		 949}
950
e28baead
AL		 951#ifdef CONFIG_X86_32
952/*
953 * On 32-bit kernels, VM exits still load the FS and GS bases from the
954 * VMCS rather than the segment table. KVM uses this helper to figure
955 * out the current bases to poke them into the VMCS before entry.
956 */
2d49ec72
GN		 957static unsigned long segment_base(u16 selector)
958{
8c2e41f7 959 struct desc_struct *table;
2d49ec72
GN		 960 unsigned long v;
961
8c2e41f7 962 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 963 return 0;
964
45fc8757 965 table = get_current_gdt_ro();
2d49ec72 966
8c2e41f7 967 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN		 968 u16 ldt_selector = kvm_read_ldt();
969
8c2e41f7 970 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 971 return 0;
972
8c2e41f7 973 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 974 }
8c2e41f7 975 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN		 976 return v;
977}
e28baead 978#endif
2d49ec72 979
2ef444f1
CP		 980static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
981{
982 u32 i;
983
984 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
985 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
986 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
987 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
988 for (i = 0; i < addr_range; i++) {
989 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
990 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
991 }
992}
993
994static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
995{
996 u32 i;
997
998 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
999 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1000 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1001 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1002 for (i = 0; i < addr_range; i++) {
1003 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1004 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1005 }
1006}
1007
1008static void pt_guest_enter(struct vcpu_vmx *vmx)
1009{
1010 if (pt_mode == PT_MODE_SYSTEM)
1011 return;
1012
2ef444f1 1013 /*
b08c2896
CP		 1014 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1015 * Save host state before VM entry.
2ef444f1 1016 */
b08c2896 1017 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
2ef444f1
CP		 1018 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1019 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1020 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1021 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1022 }
1023}
1024
1025static void pt_guest_exit(struct vcpu_vmx *vmx)
1026{
1027 if (pt_mode == PT_MODE_SYSTEM)
1028 return;
1029
1030 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1031 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1032 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1033 }
1034
1035 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1036 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1037}
1038
13b964a2
SC		 1039void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1040 unsigned long fs_base, unsigned long gs_base)
1041{
1042 if (unlikely(fs_sel != host->fs_sel)) {
1043 if (!(fs_sel & 7))
1044 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1045 else
1046 vmcs_write16(HOST_FS_SELECTOR, 0);
1047 host->fs_sel = fs_sel;
1048 }
1049 if (unlikely(gs_sel != host->gs_sel)) {
1050 if (!(gs_sel & 7))
1051 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1052 else
1053 vmcs_write16(HOST_GS_SELECTOR, 0);
1054 host->gs_sel = gs_sel;
1055 }
1056 if (unlikely(fs_base != host->fs_base)) {
1057 vmcs_writel(HOST_FS_BASE, fs_base);
1058 host->fs_base = fs_base;
1059 }
1060 if (unlikely(gs_base != host->gs_base)) {
1061 vmcs_writel(HOST_GS_BASE, gs_base);
1062 host->gs_base = gs_base;
1063 }
1064}
1065
97b7ead3 1066void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
33ed6329 1067{
04d2cc77 1068 struct vcpu_vmx *vmx = to_vmx(vcpu);
d7ee039e 1069 struct vmcs_host_state *host_state;
51e8a8cc 1070#ifdef CONFIG_X86_64
35060ed6 1071 int cpu = raw_smp_processor_id();
51e8a8cc 1072#endif
e368b875
SC		 1073 unsigned long fs_base, gs_base;
1074 u16 fs_sel, gs_sel;
26bb0981 1075 int i;
04d2cc77 1076
d264ee0c
SC		 1077 vmx->req_immediate_exit = false;
1078
f48b4711
LA		 1079 /*
1080 * Note that guest MSRs to be saved/restored can also be changed
1081 * when guest state is loaded. This happens when guest transitions
1082 * to/from long-mode by setting MSR_EFER.LMA.
1083 */
b464f57e
PB		 1084 if (!vmx->guest_msrs_ready) {
1085 vmx->guest_msrs_ready = true;
f48b4711
LA		 1086 for (i = 0; i < vmx->save_nmsrs; ++i)
1087 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1088 vmx->guest_msrs[i].data,
1089 vmx->guest_msrs[i].mask);
1090
1091 }
b464f57e 1092 if (vmx->guest_state_loaded)
33ed6329
AK		 1093 return;
1094
b464f57e 1095 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1096
33ed6329
AK		 1097 /*
1098 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1099 * allow segment selectors with cpl > 0 or ti == 1.
1100 */
d7ee039e 1101 host_state->ldt_sel = kvm_read_ldt();
42b933b5
VK		 1102
1103#ifdef CONFIG_X86_64
d7ee039e
SC		 1104 savesegment(ds, host_state->ds_sel);
1105 savesegment(es, host_state->es_sel);
e368b875
SC		 1106
1107 gs_base = cpu_kernelmode_gs_base(cpu);
b062b794
VK		 1108 if (likely(is_64bit_mm(current->mm))) {
1109 save_fsgs_for_kvm();
e368b875
SC		 1110 fs_sel = current->thread.fsindex;
1111 gs_sel = current->thread.gsindex;
b062b794 1112 fs_base = current->thread.fsbase;
e368b875 1113 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
b062b794 1114 } else {
e368b875
SC		 1115 savesegment(fs, fs_sel);
1116 savesegment(gs, gs_sel);
b062b794 1117 fs_base = read_msr(MSR_FS_BASE);
e368b875 1118 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
33ed6329 1119 }
b2da15ac 1120
4679b61f 1121 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
4fde8d57 1122#else
e368b875
SC		 1123 savesegment(fs, fs_sel);
1124 savesegment(gs, gs_sel);
1125 fs_base = segment_base(fs_sel);
1126 gs_base = segment_base(gs_sel);
707c0874 1127#endif
e368b875 1128
13b964a2 1129 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
b464f57e 1130 vmx->guest_state_loaded = true;
33ed6329
AK		 1131}
1132
6d6095bd 1133static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
33ed6329 1134{
d7ee039e
SC		 1135 struct vmcs_host_state *host_state;
1136
b464f57e 1137 if (!vmx->guest_state_loaded)
33ed6329
AK		 1138 return;
1139
b464f57e 1140 host_state = &vmx->loaded_vmcs->host_state;
bd9966de 1141
e1beb1d3 1142 ++vmx->vcpu.stat.host_state_reload;
bd9966de 1143
c8770e7b 1144#ifdef CONFIG_X86_64
4679b61f 1145 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
c8770e7b 1146#endif
d7ee039e
SC		 1147 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1148 kvm_load_ldt(host_state->ldt_sel);
33ed6329 1149#ifdef CONFIG_X86_64
d7ee039e 1150 load_gs_index(host_state->gs_sel);
9581d442 1151#else
d7ee039e 1152 loadsegment(gs, host_state->gs_sel);
33ed6329 1153#endif
33ed6329 1154 }
d7ee039e
SC		 1155 if (host_state->fs_sel & 7)
1156 loadsegment(fs, host_state->fs_sel);
b2da15ac 1157#ifdef CONFIG_X86_64
d7ee039e
SC		 1158 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1159 loadsegment(ds, host_state->ds_sel);
1160 loadsegment(es, host_state->es_sel);
b2da15ac 1161 }
b2da15ac 1162#endif
b7ffc44d 1163 invalidate_tss_limit();
44ea2b17 1164#ifdef CONFIG_X86_64
c8770e7b 1165 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1166#endif
45fc8757 1167 load_fixmap_gdt(raw_smp_processor_id());
b464f57e
PB		 1168 vmx->guest_state_loaded = false;
1169 vmx->guest_msrs_ready = false;
33ed6329
AK		 1170}
1171
678e315e
SC		 1172#ifdef CONFIG_X86_64
1173static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
a9b21b62 1174{
4679b61f 1175 preempt_disable();
b464f57e 1176 if (vmx->guest_state_loaded)
4679b61f
PB		 1177 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1178 preempt_enable();
678e315e 1179 return vmx->msr_guest_kernel_gs_base;
a9b21b62
AK		 1180}
1181
678e315e
SC		 1182static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1183{
4679b61f 1184 preempt_disable();
b464f57e 1185 if (vmx->guest_state_loaded)
4679b61f
PB		 1186 wrmsrl(MSR_KERNEL_GS_BASE, data);
1187 preempt_enable();
678e315e
SC		 1188 vmx->msr_guest_kernel_gs_base = data;
1189}
1190#endif
1191
28b835d6
FW		 1192static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1193{
1194 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1195 struct pi_desc old, new;
1196 unsigned int dest;
1197
31afb2ea
PB		 1198 /*
1199 * In case of hot-plug or hot-unplug, we may have to undo
1200 * vmx_vcpu_pi_put even if there is no assigned device. And we
1201 * always keep PI.NDST up to date for simplicity: it makes the
1202 * code easier, and CPU migration is not a fast path.
1203 */
1204 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
28b835d6
FW		 1205 return;
1206
31afb2ea 1207 /* The full case. */
28b835d6
FW		 1208 do {
1209 old.control = new.control = pi_desc->control;
1210
31afb2ea 1211 dest = cpu_physical_id(cpu);
28b835d6 1212
31afb2ea
PB		 1213 if (x2apic_enabled())
1214 new.ndst = dest;
1215 else
1216 new.ndst = (dest << 8) & 0xFF00;
28b835d6 1217
28b835d6 1218 new.sn = 0;
c0a1666b
PB		 1219 } while (cmpxchg64(&pi_desc->control, old.control,
1220 new.control) != old.control);
c112b5f5
LK		 1221
1222 /*
1223 * Clear SN before reading the bitmap. The VT-d firmware
1224 * writes the bitmap and reads SN atomically (5.2.3 in the
1225 * spec), so it doesn't really have a memory barrier that
1226 * pairs with this, but we cannot do that and we need one.
1227 */
1228 smp_mb__after_atomic();
1229
1230 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1231 pi_set_on(pi_desc);
28b835d6 1232}
1be0e61c 1233
8ef863e6 1234void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1235{
a2fa3e9f 1236 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 1237 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 1238
b80c76ec 1239 if (!already_loaded) {
fe0e80be 1240 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 1241 local_irq_disable();
8f536b76 1242 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1243
1244 /*
1245 * Read loaded_vmcs->cpu should be before fetching
1246 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1247 * See the comments in __loaded_vmcs_clear().
1248 */
1249 smp_rmb();
1250
d462b819
NHE		 1251 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1252 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1253 crash_enable_local_vmclear(cpu);
92fe13be 1254 local_irq_enable();
b80c76ec
JM		 1255 }
1256
1257 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1258 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1259 vmcs_load(vmx->loaded_vmcs->vmcs);
15d45071 1260 indirect_branch_prediction_barrier();
b80c76ec
JM		 1261 }
1262
1263 if (!already_loaded) {
59c58ceb 1264 void *gdt = get_current_gdt_ro();
b80c76ec
JM		 1265 unsigned long sysenter_esp;
1266
1267 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1268
6aa8b732
AK		 1269 /*
1270 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 1271 * processors. See 22.2.4.
6aa8b732 1272 */
e0c23063 1273 vmcs_writel(HOST_TR_BASE,
72f5e08d 1274 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
59c58ceb 1275 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 1276
b7ffc44d
AL		 1277 /*
1278 * VM exits change the host TR limit to 0x67 after a VM
1279 * exit. This is okay, since 0x67 covers everything except
1280 * the IO bitmap and have have code to handle the IO bitmap
1281 * being lost after a VM exit.
1282 */
1283 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1284
6aa8b732
AK		 1285 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1286 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 1287
d462b819 1288 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1289 }
28b835d6 1290
2680d6da
OH		 1291 /* Setup TSC multiplier */
1292 if (kvm_has_tsc_control &&
c95ba92a
PF		 1293 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1294 decache_tsc_multiplier(vmx);
8ef863e6
SC		 1295}
1296
1297/*
1298 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1299 * vcpu mutex is already taken.
1300 */
1301void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1302{
1303 struct vcpu_vmx *vmx = to_vmx(vcpu);
1304
1305 vmx_vcpu_load_vmcs(vcpu, cpu);
2680d6da 1306
28b835d6 1307 vmx_vcpu_pi_load(vcpu, cpu);
8ef863e6 1308
1be0e61c 1309 vmx->host_pkru = read_pkru();
74c55931 1310 vmx->host_debugctlmsr = get_debugctlmsr();
28b835d6
FW		 1311}
1312
1313static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1314{
1315 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1316
1317 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 1318 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1319 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 1320 return;
1321
1322 /* Set SN when the vCPU is preempted */
1323 if (vcpu->preempted)
1324 pi_set_sn(pi_desc);
6aa8b732
AK		 1325}
1326
13b964a2 1327static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
6aa8b732 1328{
28b835d6
FW		 1329 vmx_vcpu_pi_put(vcpu);
1330
6d6095bd 1331 vmx_prepare_switch_to_host(to_vmx(vcpu));
6aa8b732
AK		 1332}
1333
f244deed
WL		 1334static bool emulation_required(struct kvm_vcpu *vcpu)
1335{
1336 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1337}
1338
edcafe3c
AK		 1339static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1340
97b7ead3 1341unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
6aa8b732 1342{
78ac8b47 1343 unsigned long rflags, save_rflags;
345dcaa8 1344
6de12732
AK		 1345 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1346 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1347 rflags = vmcs_readl(GUEST_RFLAGS);
1348 if (to_vmx(vcpu)->rmode.vm86_active) {
1349 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1350 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1351 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1352 }
1353 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1354 }
6de12732 1355 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1356}
1357
97b7ead3 1358void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6aa8b732 1359{
f244deed
WL		 1360 unsigned long old_rflags = vmx_get_rflags(vcpu);
1361
6de12732
AK		 1362 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1363 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1364 if (to_vmx(vcpu)->rmode.vm86_active) {
1365 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1366 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1367 }
6aa8b732 1368 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed
WL		 1369
1370 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1371 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 1372}
1373
97b7ead3 1374u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1375{
1376 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1377 int ret = 0;
1378
1379 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1380 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1381 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1382 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1383
37ccdcbe 1384 return ret;
2809f5d2
GC		 1385}
1386
97b7ead3 1387void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2809f5d2
GC		 1388{
1389 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1390 u32 interruptibility = interruptibility_old;
1391
1392 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1393
48005f64 1394 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1395 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1396 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1397 interruptibility |= GUEST_INTR_STATE_STI;
1398
1399 if ((interruptibility != interruptibility_old))
1400 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1401}
1402
bf8c55d8
CP		 1403static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1404{
1405 struct vcpu_vmx *vmx = to_vmx(vcpu);
1406 unsigned long value;
1407
1408 /*
1409 * Any MSR write that attempts to change bits marked reserved will
1410 * case a #GP fault.
1411 */
1412 if (data & vmx->pt_desc.ctl_bitmask)
1413 return 1;
1414
1415 /*
1416 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1417 * result in a #GP unless the same write also clears TraceEn.
1418 */
1419 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1420 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1421 return 1;
1422
1423 /*
1424 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1425 * and FabricEn would cause #GP, if
1426 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1427 */
1428 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1429 !(data & RTIT_CTL_FABRIC_EN) &&
1430 !intel_pt_validate_cap(vmx->pt_desc.caps,
1431 PT_CAP_single_range_output))
1432 return 1;
1433
1434 /*
1435 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1436 * utilize encodings marked reserved will casue a #GP fault.
1437 */
1438 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1439 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1440 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1441 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1442 return 1;
1443 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1444 PT_CAP_cycle_thresholds);
1445 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1446 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1447 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1448 return 1;
1449 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1450 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1451 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1452 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1453 return 1;
1454
1455 /*
1456 * If ADDRx_CFG is reserved or the encodings is >2 will
1457 * cause a #GP fault.
1458 */
1459 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1460 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1461 return 1;
1462 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1463 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1464 return 1;
1465 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1466 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1467 return 1;
1468 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1469 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1470 return 1;
1471
1472 return 0;
1473}
1474
1475
6aa8b732
AK		 1476static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1477{
1478 unsigned long rip;
6aa8b732 1479
5fdbf976 1480 rip = kvm_rip_read(vcpu);
6aa8b732 1481 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1482 kvm_rip_write(vcpu, rip);
6aa8b732 1483
2809f5d2
GC		 1484 /* skipping an emulated instruction also counts */
1485 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1486}
1487
caa057a2
WL		 1488static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1489{
1490 /*
1491 * Ensure that we clear the HLT state in the VMCS. We don't need to
1492 * explicitly skip the instruction because if the HLT state is set,
1493 * then the instruction is already executing and RIP has already been
1494 * advanced.
1495 */
1496 if (kvm_hlt_in_guest(vcpu->kvm) &&
1497 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1498 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1499}
1500
cfcd20e5 1501static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 1502{
77ab6db0 1503 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL		 1504 unsigned nr = vcpu->arch.exception.nr;
1505 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 1506 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 1507 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1508
da998b46
JM		 1509 kvm_deliver_exception_payload(vcpu);
1510
8ab2d2e2 1511 if (has_error_code) {
77ab6db0 1512 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1513 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1514 }
77ab6db0 1515
7ffd92c5 1516 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1517 int inc_eip = 0;
1518 if (kvm_exception_is_soft(nr))
1519 inc_eip = vcpu->arch.event_exit_inst_len;
1520 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1521 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1522 return;
1523 }
1524
add5ff7a
SC		 1525 WARN_ON_ONCE(vmx->emulation_required);
1526
66fd3f7f
GN		 1527 if (kvm_exception_is_soft(nr)) {
1528 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1529 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1530 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1531 } else
1532 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1533
1534 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
caa057a2
WL		 1535
1536 vmx_clear_hlt(vcpu);
298101da
AK		 1537}
1538
4e47c7a6
SY		 1539static bool vmx_rdtscp_supported(void)
1540{
1541 return cpu_has_vmx_rdtscp();
1542}
1543
ad756a16
MJ		 1544static bool vmx_invpcid_supported(void)
1545{
eb4b248e 1546 return cpu_has_vmx_invpcid();
ad756a16
MJ		 1547}
1548
a75beee6
ED		 1549/*
1550 * Swap MSR entry in host/guest MSR entry array.
1551 */
8b9cf98c 1552static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1553{
26bb0981 1554 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1555
1556 tmp = vmx->guest_msrs[to];
1557 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1558 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1559}
1560
e38aea3e
AK		 1561/*
1562 * Set up the vmcs to automatically save and restore system
1563 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1564 * mode, as fiddling with msrs is very expensive.
1565 */
8b9cf98c 1566static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1567{
26bb0981 1568 int save_nmsrs, index;
e38aea3e 1569
a75beee6
ED		 1570 save_nmsrs = 0;
1571#ifdef CONFIG_X86_64
84c8c5b8
JM		 1572 /*
1573 * The SYSCALL MSRs are only needed on long mode guests, and only
1574 * when EFER.SCE is set.
1575 */
1576 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1577 index = __find_msr_index(vmx, MSR_STAR);
a75beee6 1578 if (index >= 0)
8b9cf98c
RR		 1579 move_msr_up(vmx, index, save_nmsrs++);
1580 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1581 if (index >= 0)
8b9cf98c 1582 move_msr_up(vmx, index, save_nmsrs++);
84c8c5b8
JM		 1583 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1584 if (index >= 0)
8b9cf98c 1585 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1586 }
1587#endif
92c0d900
AK		 1588 index = __find_msr_index(vmx, MSR_EFER);
1589 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1590 move_msr_up(vmx, index, save_nmsrs++);
0023ef39
JM		 1591 index = __find_msr_index(vmx, MSR_TSC_AUX);
1592 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1593 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1594
26bb0981 1595 vmx->save_nmsrs = save_nmsrs;
b464f57e 1596 vmx->guest_msrs_ready = false;
5897297b 1597
8d14695f 1598 if (cpu_has_vmx_msr_bitmap())
904e14fb 1599 vmx_update_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1600}
1601
e79f245d 1602static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
6aa8b732 1603{
e79f245d 1604 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6aa8b732 1605
e79f245d
KA		 1606 if (is_guest_mode(vcpu) &&
1607 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1608 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1609
1610 return vcpu->arch.tsc_offset;
6aa8b732
AK		 1611}
1612
326e7425 1613static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1614{
45c3af97
PB		 1615 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1616 u64 g_tsc_offset = 0;
1617
1618 /*
1619 * We're here if L1 chose not to trap WRMSR to TSC. According
1620 * to the spec, this should set L1's TSC; The offset that L1
1621 * set for L2 remains unchanged, and still needs to be added
1622 * to the newly set TSC to get L2's TSC.
1623 */
1624 if (is_guest_mode(vcpu) &&
1625 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1626 g_tsc_offset = vmcs12->tsc_offset;
326e7425 1627
45c3af97
PB		 1628 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1629 vcpu->arch.tsc_offset - g_tsc_offset,
1630 offset);
1631 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1632 return offset + g_tsc_offset;
6aa8b732
AK		 1633}
1634
801d3424
NHE		 1635/*
1636 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1637 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1638 * all guests if the "nested" module option is off, and can also be disabled
1639 * for a single guest by disabling its VMX cpuid bit.
1640 */
7c97fcb3 1641bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
801d3424 1642{
d6321d49 1643 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
801d3424
NHE		 1644}
1645
55d2375e
SC		 1646static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1647 uint64_t val)
62cc6b9d 1648{
55d2375e 1649 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
62cc6b9d 1650
55d2375e 1651 return !(val & ~valid_bits);
62cc6b9d
DM		 1652}
1653
55d2375e 1654static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
62cc6b9d 1655{
55d2375e
SC		 1656 switch (msr->index) {
1657 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1658 if (!nested)
1659 return 1;
1660 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1661 default:
1662 return 1;
1663 }
62cc6b9d 1664
62cc6b9d
DM		 1665 return 0;
1666}
1667
55d2375e
SC		 1668/*
1669 * Reads an msr value (of 'msr_index') into 'pdata'.
1670 * Returns 0 on success, non-0 otherwise.
1671 * Assumes vcpu_load() was already called.
1672 */
1673static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
62cc6b9d 1674{
55d2375e
SC		 1675 struct vcpu_vmx *vmx = to_vmx(vcpu);
1676 struct shared_msr_entry *msr;
bf8c55d8 1677 u32 index;
62cc6b9d 1678
55d2375e
SC		 1679 switch (msr_info->index) {
1680#ifdef CONFIG_X86_64
1681 case MSR_FS_BASE:
1682 msr_info->data = vmcs_readl(GUEST_FS_BASE);
62cc6b9d 1683 break;
55d2375e
SC		 1684 case MSR_GS_BASE:
1685 msr_info->data = vmcs_readl(GUEST_GS_BASE);
62cc6b9d 1686 break;
55d2375e
SC		 1687 case MSR_KERNEL_GS_BASE:
1688 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
62cc6b9d 1689 break;
55d2375e
SC		 1690#endif
1691 case MSR_EFER:
1692 return kvm_get_msr_common(vcpu, msr_info);
1693 case MSR_IA32_SPEC_CTRL:
1694 if (!msr_info->host_initiated &&
1695 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1696 return 1;
1697
1698 msr_info->data = to_vmx(vcpu)->spec_ctrl;
62cc6b9d 1699 break;
6aa8b732 1700 case MSR_IA32_SYSENTER_CS:
609e36d3 1701 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 1702 break;
1703 case MSR_IA32_SYSENTER_EIP:
609e36d3 1704 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1705 break;
1706 case MSR_IA32_SYSENTER_ESP:
609e36d3 1707 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1708 break;
0dd376e7 1709 case MSR_IA32_BNDCFGS:
691bd434 1710 if (!kvm_mpx_supported() ||
d6321d49
RK		 1711 (!msr_info->host_initiated &&
1712 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1713 return 1;
609e36d3 1714 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 1715 break;
c45dcc71
AR		 1716 case MSR_IA32_MCG_EXT_CTL:
1717 if (!msr_info->host_initiated &&
a6cb099a 1718 !(vmx->msr_ia32_feature_control &
c45dcc71 1719 FEATURE_CONTROL_LMCE))
cae50139 1720 return 1;
c45dcc71
AR		 1721 msr_info->data = vcpu->arch.mcg_ext_ctl;
1722 break;
cae50139 1723 case MSR_IA32_FEATURE_CONTROL:
a6cb099a 1724 msr_info->data = vmx->msr_ia32_feature_control;
cae50139
JK		 1725 break;
1726 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1727 if (!nested_vmx_allowed(vcpu))
1728 return 1;
6677f3da
PB		 1729 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1730 &msr_info->data);
20300099 1731 case MSR_IA32_XSS:
4d763b16
WL		 1732 if (!vmx_xsaves_supported() ||
1733 (!msr_info->host_initiated &&
1734 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1735 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
20300099 1736 return 1;
609e36d3 1737 msr_info->data = vcpu->arch.ia32_xss;
20300099 1738 break;
bf8c55d8
CP		 1739 case MSR_IA32_RTIT_CTL:
1740 if (pt_mode != PT_MODE_HOST_GUEST)
1741 return 1;
1742 msr_info->data = vmx->pt_desc.guest.ctl;
1743 break;
1744 case MSR_IA32_RTIT_STATUS:
1745 if (pt_mode != PT_MODE_HOST_GUEST)
1746 return 1;
1747 msr_info->data = vmx->pt_desc.guest.status;
1748 break;
1749 case MSR_IA32_RTIT_CR3_MATCH:
1750 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1751 !intel_pt_validate_cap(vmx->pt_desc.caps,
1752 PT_CAP_cr3_filtering))
1753 return 1;
1754 msr_info->data = vmx->pt_desc.guest.cr3_match;
1755 break;
1756 case MSR_IA32_RTIT_OUTPUT_BASE:
1757 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1758 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1759 PT_CAP_topa_output) &&
1760 !intel_pt_validate_cap(vmx->pt_desc.caps,
1761 PT_CAP_single_range_output)))
1762 return 1;
1763 msr_info->data = vmx->pt_desc.guest.output_base;
1764 break;
1765 case MSR_IA32_RTIT_OUTPUT_MASK:
1766 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1767 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1768 PT_CAP_topa_output) &&
1769 !intel_pt_validate_cap(vmx->pt_desc.caps,
1770 PT_CAP_single_range_output)))
1771 return 1;
1772 msr_info->data = vmx->pt_desc.guest.output_mask;
1773 break;
1774 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1775 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1776 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1777 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1778 PT_CAP_num_address_ranges)))
1779 return 1;
1780 if (index % 2)
1781 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1782 else
1783 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1784 break;
4e47c7a6 1785 case MSR_TSC_AUX:
d6321d49
RK		 1786 if (!msr_info->host_initiated &&
1787 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6 1788 return 1;
b2869f28 1789 /* Else, falls through */
6aa8b732 1790 default:
a6cb099a 1791 msr = find_msr_entry(vmx, msr_info->index);
3bab1f5d 1792 if (msr) {
609e36d3 1793 msr_info->data = msr->data;
3bab1f5d 1794 break;
6aa8b732 1795 }
609e36d3 1796 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 1797 }
1798
6aa8b732
AK		 1799 return 0;
1800}
1801
1802/*
1803 * Writes msr value into into the appropriate "register".
1804 * Returns 0 on success, non-0 otherwise.
1805 * Assumes vcpu_load() was already called.
1806 */
8fe8ab46 1807static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 1808{
a2fa3e9f 1809 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1810 struct shared_msr_entry *msr;
2cc51560 1811 int ret = 0;
8fe8ab46
WA		 1812 u32 msr_index = msr_info->index;
1813 u64 data = msr_info->data;
bf8c55d8 1814 u32 index;
2cc51560 1815
6aa8b732 1816 switch (msr_index) {
3bab1f5d 1817 case MSR_EFER:
8fe8ab46 1818 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 1819 break;
16175a79 1820#ifdef CONFIG_X86_64
6aa8b732 1821 case MSR_FS_BASE:
2fb92db1 1822 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1823 vmcs_writel(GUEST_FS_BASE, data);
1824 break;
1825 case MSR_GS_BASE:
2fb92db1 1826 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1827 vmcs_writel(GUEST_GS_BASE, data);
1828 break;
44ea2b17 1829 case MSR_KERNEL_GS_BASE:
678e315e 1830 vmx_write_guest_kernel_gs_base(vmx, data);
44ea2b17 1831 break;
6aa8b732
AK		 1832#endif
1833 case MSR_IA32_SYSENTER_CS:
de70d279
SC		 1834 if (is_guest_mode(vcpu))
1835 get_vmcs12(vcpu)->guest_sysenter_cs = data;
6aa8b732
AK		 1836 vmcs_write32(GUEST_SYSENTER_CS, data);
1837 break;
1838 case MSR_IA32_SYSENTER_EIP:
de70d279
SC		 1839 if (is_guest_mode(vcpu))
1840 get_vmcs12(vcpu)->guest_sysenter_eip = data;
f5b42c33 1841 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1842 break;
1843 case MSR_IA32_SYSENTER_ESP:
de70d279
SC		 1844 if (is_guest_mode(vcpu))
1845 get_vmcs12(vcpu)->guest_sysenter_esp = data;
f5b42c33 1846 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1847 break;
699a1ac2
SC		 1848 case MSR_IA32_DEBUGCTLMSR:
1849 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1850 VM_EXIT_SAVE_DEBUG_CONTROLS)
1851 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1852
1853 ret = kvm_set_msr_common(vcpu, msr_info);
1854 break;
1855
0dd376e7 1856 case MSR_IA32_BNDCFGS:
691bd434 1857 if (!kvm_mpx_supported() ||
d6321d49
RK		 1858 (!msr_info->host_initiated &&
1859 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1860 return 1;
fd8cb433 1861 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4531662d 1862 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 1863 return 1;
0dd376e7
LJ		 1864 vmcs_write64(GUEST_BNDCFGS, data);
1865 break;
d28b387f
KA		 1866 case MSR_IA32_SPEC_CTRL:
1867 if (!msr_info->host_initiated &&
d28b387f
KA		 1868 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1869 return 1;
1870
1871 /* The STIBP bit doesn't fault even if it's not advertised */
9f65fb29 1872 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
d28b387f
KA		 1873 return 1;
1874
1875 vmx->spec_ctrl = data;
1876
1877 if (!data)
1878 break;
1879
1880 /*
1881 * For non-nested:
1882 * When it's written (to non-zero) for the first time, pass
1883 * it through.
1884 *
1885 * For nested:
1886 * The handling of the MSR bitmap for L2 guests is done in
1887 * nested_vmx_merge_msr_bitmap. We should not touch the
1888 * vmcs02.msr_bitmap here since it gets completely overwritten
1889 * in the merging. We update the vmcs01 here for L1 as well
1890 * since it will end up touching the MSR anyway now.
1891 */
1892 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1893 MSR_IA32_SPEC_CTRL,
1894 MSR_TYPE_RW);
1895 break;
15d45071
AR		 1896 case MSR_IA32_PRED_CMD:
1897 if (!msr_info->host_initiated &&
15d45071
AR		 1898 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1899 return 1;
1900
1901 if (data & ~PRED_CMD_IBPB)
1902 return 1;
1903
1904 if (!data)
1905 break;
1906
1907 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1908
1909 /*
1910 * For non-nested:
1911 * When it's written (to non-zero) for the first time, pass
1912 * it through.
1913 *
1914 * For nested:
1915 * The handling of the MSR bitmap for L2 guests is done in
1916 * nested_vmx_merge_msr_bitmap. We should not touch the
1917 * vmcs02.msr_bitmap here since it gets completely overwritten
1918 * in the merging.
1919 */
1920 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1921 MSR_TYPE_W);
1922 break;
468d472f 1923 case MSR_IA32_CR_PAT:
d28f4290
SC		 1924 if (!kvm_pat_valid(data))
1925 return 1;
1926
142e4be7
SC		 1927 if (is_guest_mode(vcpu) &&
1928 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
1929 get_vmcs12(vcpu)->guest_ia32_pat = data;
1930
468d472f
SY		 1931 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1932 vmcs_write64(GUEST_IA32_PAT, data);
1933 vcpu->arch.pat = data;
1934 break;
1935 }
8fe8ab46 1936 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 1937 break;
ba904635
WA		 1938 case MSR_IA32_TSC_ADJUST:
1939 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 1940 break;
c45dcc71
AR		 1941 case MSR_IA32_MCG_EXT_CTL:
1942 if ((!msr_info->host_initiated &&
1943 !(to_vmx(vcpu)->msr_ia32_feature_control &
1944 FEATURE_CONTROL_LMCE)) ||
1945 (data & ~MCG_EXT_CTL_LMCE_EN))
1946 return 1;
1947 vcpu->arch.mcg_ext_ctl = data;
1948 break;
cae50139 1949 case MSR_IA32_FEATURE_CONTROL:
37e4c997 1950 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 1951 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK		 1952 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
1953 return 1;
3b84080b 1954 vmx->msr_ia32_feature_control = data;
cae50139
JK		 1955 if (msr_info->host_initiated && data == 0)
1956 vmx_leave_nested(vcpu);
1957 break;
1958 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 1959 if (!msr_info->host_initiated)
1960 return 1; /* they are read-only */
1961 if (!nested_vmx_allowed(vcpu))
1962 return 1;
1963 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099 1964 case MSR_IA32_XSS:
4d763b16
WL		 1965 if (!vmx_xsaves_supported() ||
1966 (!msr_info->host_initiated &&
1967 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1968 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
20300099
WL		 1969 return 1;
1970 /*
1971 * The only supported bit as of Skylake is bit 8, but
1972 * it is not supported on KVM.
1973 */
1974 if (data != 0)
1975 return 1;
1976 vcpu->arch.ia32_xss = data;
1977 if (vcpu->arch.ia32_xss != host_xss)
1978 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
989e3992 1979 vcpu->arch.ia32_xss, host_xss, false);
20300099
WL		 1980 else
1981 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
1982 break;
bf8c55d8
CP		 1983 case MSR_IA32_RTIT_CTL:
1984 if ((pt_mode != PT_MODE_HOST_GUEST) ||
ee85dec2
LK		 1985 vmx_rtit_ctl_check(vcpu, data) ||
1986 vmx->nested.vmxon)
bf8c55d8
CP		 1987 return 1;
1988 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
1989 vmx->pt_desc.guest.ctl = data;
b08c2896 1990 pt_update_intercept_for_msr(vmx);
bf8c55d8
CP		 1991 break;
1992 case MSR_IA32_RTIT_STATUS:
1993 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1994 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1995 (data & MSR_IA32_RTIT_STATUS_MASK))
1996 return 1;
1997 vmx->pt_desc.guest.status = data;
1998 break;
1999 case MSR_IA32_RTIT_CR3_MATCH:
2000 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2001 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2002 !intel_pt_validate_cap(vmx->pt_desc.caps,
2003 PT_CAP_cr3_filtering))
2004 return 1;
2005 vmx->pt_desc.guest.cr3_match = data;
2006 break;
2007 case MSR_IA32_RTIT_OUTPUT_BASE:
2008 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2009 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2010 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2011 PT_CAP_topa_output) &&
2012 !intel_pt_validate_cap(vmx->pt_desc.caps,
2013 PT_CAP_single_range_output)) ||
2014 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2015 return 1;
2016 vmx->pt_desc.guest.output_base = data;
2017 break;
2018 case MSR_IA32_RTIT_OUTPUT_MASK:
2019 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2020 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2021 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2022 PT_CAP_topa_output) &&
2023 !intel_pt_validate_cap(vmx->pt_desc.caps,
2024 PT_CAP_single_range_output)))
2025 return 1;
2026 vmx->pt_desc.guest.output_mask = data;
2027 break;
2028 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2029 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2030 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2031 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2032 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2033 PT_CAP_num_address_ranges)))
2034 return 1;
2035 if (index % 2)
2036 vmx->pt_desc.guest.addr_b[index / 2] = data;
2037 else
2038 vmx->pt_desc.guest.addr_a[index / 2] = data;
2039 break;
4e47c7a6 2040 case MSR_TSC_AUX:
d6321d49
RK		 2041 if (!msr_info->host_initiated &&
2042 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 2043 return 1;
2044 /* Check reserved bit, higher 32 bits should be zero */
2045 if ((data >> 32) != 0)
2046 return 1;
b2869f28 2047 /* Else, falls through */
6aa8b732 2048 default:
8b9cf98c 2049 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2050 if (msr) {
8b3c3104 2051 u64 old_msr_data = msr->data;
3bab1f5d 2052 msr->data = data;
2225fd56
AK		 2053 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2054 preempt_disable();
8b3c3104
AH		 2055 ret = kvm_set_shared_msr(msr->index, msr->data,
2056 msr->mask);
2225fd56 2057 preempt_enable();
8b3c3104
AH		 2058 if (ret)
2059 msr->data = old_msr_data;
2225fd56 2060 }
3bab1f5d 2061 break;
6aa8b732 2062 }
8fe8ab46 2063 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2064 }
2065
2cc51560 2066 return ret;
6aa8b732
AK		 2067}
2068
5fdbf976 2069static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2070{
5fdbf976
MT		 2071 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2072 switch (reg) {
2073 case VCPU_REGS_RSP:
2074 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2075 break;
2076 case VCPU_REGS_RIP:
2077 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2078 break;
6de4f3ad
AK		 2079 case VCPU_EXREG_PDPTR:
2080 if (enable_ept)
2081 ept_save_pdptrs(vcpu);
2082 break;
5fdbf976
MT		 2083 default:
2084 break;
2085 }
6aa8b732
AK		 2086}
2087
6aa8b732
AK		 2088static __init int cpu_has_kvm_support(void)
2089{
6210e37b 2090 return cpu_has_vmx();
6aa8b732
AK		 2091}
2092
2093static __init int vmx_disabled_by_bios(void)
2094{
2095 u64 msr;
2096
2097 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2098 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2099 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2100 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2101 && tboot_enabled())
2102 return 1;
23f3e991 2103 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2104 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2105 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2106 && !tboot_enabled()) {
2107 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2108 "activate TXT before enabling KVM\n");
cafd6659 2109 return 1;
f9335afe 2110 }
23f3e991
JC		 2111 /* launched w/o TXT and VMX disabled */
2112 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2113 && !tboot_enabled())
2114 return 1;
cafd6659
SW		 2115 }
2116
2117 return 0;
6aa8b732
AK		 2118}
2119
7725b894
DX		 2120static void kvm_cpu_vmxon(u64 addr)
2121{
fe0e80be 2122 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS		 2123 intel_pt_handle_vmx(1);
2124
4b1e5478 2125 asm volatile ("vmxon %0" : : "m"(addr));
7725b894
DX		 2126}
2127
13a34e06 2128static int hardware_enable(void)
6aa8b732
AK		 2129{
2130 int cpu = raw_smp_processor_id();
2131 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2132 u64 old, test_bits;
6aa8b732 2133
1e02ce4c 2134 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2135 return -EBUSY;
2136
773e8a04
VK		 2137 /*
2138 * This can happen if we hot-added a CPU but failed to allocate
2139 * VP assist page for it.
2140 */
2141 if (static_branch_unlikely(&enable_evmcs) &&
2142 !hv_get_vp_assist_page(cpu))
2143 return -EFAULT;
2144
d462b819 2145 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 2146 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2147 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 2148
2149 /*
2150 * Now we can enable the vmclear operation in kdump
2151 * since the loaded_vmcss_on_cpu list on this cpu
2152 * has been initialized.
2153 *
2154 * Though the cpu is not in VMX operation now, there
2155 * is no problem to enable the vmclear operation
2156 * for the loaded_vmcss_on_cpu list is empty!
2157 */
2158 crash_enable_local_vmclear(cpu);
2159
6aa8b732 2160 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2161
2162 test_bits = FEATURE_CONTROL_LOCKED;
2163 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2164 if (tboot_enabled())
2165 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2166
2167 if ((old & test_bits) != test_bits) {
6aa8b732 2168 /* enable and lock */
cafd6659
SW		 2169 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2170 }
fe0e80be 2171 kvm_cpu_vmxon(phys_addr);
fdf288bf
DH		 2172 if (enable_ept)
2173 ept_sync_global();
10474ae8
AG		 2174
2175 return 0;
6aa8b732
AK		 2176}
2177
d462b819 2178static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2179{
2180 int cpu = raw_smp_processor_id();
d462b819 2181 struct loaded_vmcs *v, *n;
543e4243 2182
d462b819
NHE		 2183 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2184 loaded_vmcss_on_cpu_link)
2185 __loaded_vmcs_clear(v);
543e4243
AK		 2186}
2187
710ff4a8
EH		 2188
2189/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2190 * tricks.
2191 */
2192static void kvm_cpu_vmxoff(void)
6aa8b732 2193{
4b1e5478 2194 asm volatile (__ex("vmxoff"));
1c5ac21a
AS		 2195
2196 intel_pt_handle_vmx(0);
fe0e80be 2197 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK		 2198}
2199
13a34e06 2200static void hardware_disable(void)
710ff4a8 2201{
fe0e80be
DH		 2202 vmclear_local_loaded_vmcss();
2203 kvm_cpu_vmxoff();
710ff4a8
EH		 2204}
2205
1c3d14fe 2206static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2207 u32 msr, u32 *result)
1c3d14fe
YS		 2208{
2209 u32 vmx_msr_low, vmx_msr_high;
2210 u32 ctl = ctl_min | ctl_opt;
2211
2212 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2213
2214 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2215 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2216
2217 /* Ensure minimum (required) set of control bits are supported. */
2218 if (ctl_min & ~ctl)
002c7f7c 2219 return -EIO;
1c3d14fe
YS		 2220
2221 *result = ctl;
2222 return 0;
2223}
2224
7caaa711
SC		 2225static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2226 struct vmx_capability *vmx_cap)
6aa8b732
AK		 2227{
2228 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2229 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2230 u32 _pin_based_exec_control = 0;
2231 u32 _cpu_based_exec_control = 0;
f78e0e2e 2232 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2233 u32 _vmexit_control = 0;
2234 u32 _vmentry_control = 0;
2235
1389309c 2236 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
10166744 2237 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2238#ifdef CONFIG_X86_64
2239 CPU_BASED_CR8_LOAD_EXITING |
2240 CPU_BASED_CR8_STORE_EXITING |
2241#endif
d56f546d
SY		 2242 CPU_BASED_CR3_LOAD_EXITING |
2243 CPU_BASED_CR3_STORE_EXITING |
8eb73e2d 2244 CPU_BASED_UNCOND_IO_EXITING |
1c3d14fe 2245 CPU_BASED_MOV_DR_EXITING |
a7052897 2246 CPU_BASED_USE_TSC_OFFSETING |
4d5422ce
WL		 2247 CPU_BASED_MWAIT_EXITING |
2248 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2249 CPU_BASED_INVLPG_EXITING |
2250 CPU_BASED_RDPMC_EXITING;
443381a8 2251
f78e0e2e 2252 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2253 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2254 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2255 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2256 &_cpu_based_exec_control) < 0)
002c7f7c 2257 return -EIO;
6e5d865c
YS		 2258#ifdef CONFIG_X86_64
2259 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2260 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2261 ~CPU_BASED_CR8_STORE_EXITING;
2262#endif
f78e0e2e 2263 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2264 min2 = 0;
2265 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2266 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2267 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2268 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2269 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2270 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2271 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
0367f205 2272 SECONDARY_EXEC_DESC |
ad756a16 2273 SECONDARY_EXEC_RDTSCP |
83d4c286 2274 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2275 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2276 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2277 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 2278 SECONDARY_EXEC_XSAVES |
736fdf72
DH		 2279 SECONDARY_EXEC_RDSEED_EXITING |
2280 SECONDARY_EXEC_RDRAND_EXITING |
8b3e34e4 2281 SECONDARY_EXEC_ENABLE_PML |
2a499e49 2282 SECONDARY_EXEC_TSC_SCALING |
f99e3daf
CP		 2283 SECONDARY_EXEC_PT_USE_GPA |
2284 SECONDARY_EXEC_PT_CONCEAL_VMX |
0b665d30
SC		 2285 SECONDARY_EXEC_ENABLE_VMFUNC |
2286 SECONDARY_EXEC_ENCLS_EXITING;
d56f546d
SY		 2287 if (adjust_vmx_controls(min2, opt2,
2288 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2289 &_cpu_based_2nd_exec_control) < 0)
2290 return -EIO;
2291 }
2292#ifndef CONFIG_X86_64
2293 if (!(_cpu_based_2nd_exec_control &
2294 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2295 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2296#endif
83d4c286
YZ		 2297
2298 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2299 _cpu_based_2nd_exec_control &= ~(
8d14695f 2300 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2301 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2302 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2303
61f1dd90 2304 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
7caaa711 2305 &vmx_cap->ept, &vmx_cap->vpid);
61f1dd90 2306
d56f546d 2307 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2308 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2309 enabled */
5fff7d27
GN		 2310 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2311 CPU_BASED_CR3_STORE_EXITING |
2312 CPU_BASED_INVLPG_EXITING);
7caaa711
SC		 2313 } else if (vmx_cap->ept) {
2314 vmx_cap->ept = 0;
61f1dd90
WL		 2315 pr_warn_once("EPT CAP should not exist if not support "
2316 "1-setting enable EPT VM-execution control\n");
2317 }
2318 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
7caaa711
SC		 2319 vmx_cap->vpid) {
2320 vmx_cap->vpid = 0;
61f1dd90
WL		 2321 pr_warn_once("VPID CAP should not exist if not support "
2322 "1-setting enable VPID VM-execution control\n");
d56f546d 2323 }
1c3d14fe 2324
91fa0f8e 2325 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2326#ifdef CONFIG_X86_64
2327 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2328#endif
c73da3fc 2329 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
c73da3fc
SC		 2330 VM_EXIT_LOAD_IA32_PAT |
2331 VM_EXIT_LOAD_IA32_EFER |
f99e3daf
CP		 2332 VM_EXIT_CLEAR_BNDCFGS |
2333 VM_EXIT_PT_CONCEAL_PIP |
2334 VM_EXIT_CLEAR_IA32_RTIT_CTL;
1c3d14fe
YS		 2335 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2336 &_vmexit_control) < 0)
002c7f7c 2337 return -EIO;
1c3d14fe 2338
8a1b4392
PB		 2339 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2340 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2341 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 2342 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2343 &_pin_based_exec_control) < 0)
2344 return -EIO;
2345
1c17c3e6
PB		 2346 if (cpu_has_broken_vmx_preemption_timer())
2347 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 2348 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 2349 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 2350 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2351
c845f9c6 2352 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
c73da3fc
SC		 2353 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2354 VM_ENTRY_LOAD_IA32_PAT |
2355 VM_ENTRY_LOAD_IA32_EFER |
f99e3daf
CP		 2356 VM_ENTRY_LOAD_BNDCFGS |
2357 VM_ENTRY_PT_CONCEAL_PIP |
2358 VM_ENTRY_LOAD_IA32_RTIT_CTL;
1c3d14fe
YS		 2359 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2360 &_vmentry_control) < 0)
002c7f7c 2361 return -EIO;
6aa8b732 2362
c73da3fc
SC		 2363 /*
2364 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2365 * can't be used due to an errata where VM Exit may incorrectly clear
2366 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2367 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2368 */
2369 if (boot_cpu_data.x86 == 0x6) {
2370 switch (boot_cpu_data.x86_model) {
2371 case 26: /* AAK155 */
2372 case 30: /* AAP115 */
2373 case 37: /* AAT100 */
2374 case 44: /* BC86,AAY89,BD102 */
2375 case 46: /* BA97 */
85ba2b16 2376 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
c73da3fc
SC		 2377 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2378 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2379 "does not work properly. Using workaround\n");
2380 break;
2381 default:
2382 break;
2383 }
2384 }
2385
2386
c68876fd 2387 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2388
2389 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2390 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2391 return -EIO;
1c3d14fe
YS		 2392
2393#ifdef CONFIG_X86_64
2394 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2395 if (vmx_msr_high & (1u<<16))
002c7f7c 2396 return -EIO;
1c3d14fe
YS		 2397#endif
2398
2399 /* Require Write-Back (WB) memory type for VMCS accesses. */
2400 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2401 return -EIO;
1c3d14fe 2402
002c7f7c 2403 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 2404 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 2405 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
773e8a04 2406
2307af1c 2407 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2408
002c7f7c
YS		 2409 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2410 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2411 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2412 vmcs_conf->vmexit_ctrl = _vmexit_control;
2413 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2414
773e8a04
VK		 2415 if (static_branch_unlikely(&enable_evmcs))
2416 evmcs_sanitize_exec_ctrls(vmcs_conf);
2417
1c3d14fe 2418 return 0;
c68876fd 2419}
6aa8b732 2420
41836839 2421struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
6aa8b732
AK		 2422{
2423 int node = cpu_to_node(cpu);
2424 struct page *pages;
2425 struct vmcs *vmcs;
2426
41836839 2427 pages = __alloc_pages_node(node, flags, vmcs_config.order);
6aa8b732
AK		 2428 if (!pages)
2429 return NULL;
2430 vmcs = page_address(pages);
1c3d14fe 2431 memset(vmcs, 0, vmcs_config.size);
2307af1c
LA		 2432
2433 /* KVM supports Enlightened VMCS v1 only */
2434 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2435 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2307af1c 2436 else
392b2f25 2437 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2438
491a6038
LA		 2439 if (shadow)
2440 vmcs->hdr.shadow_vmcs = 1;
6aa8b732
AK		 2441 return vmcs;
2442}
2443
89b0c9f5 2444void free_vmcs(struct vmcs *vmcs)
6aa8b732 2445{
1c3d14fe 2446 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2447}
2448
d462b819
NHE		 2449/*
2450 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2451 */
89b0c9f5 2452void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
d462b819
NHE		 2453{
2454 if (!loaded_vmcs->vmcs)
2455 return;
2456 loaded_vmcs_clear(loaded_vmcs);
2457 free_vmcs(loaded_vmcs->vmcs);
2458 loaded_vmcs->vmcs = NULL;
904e14fb
PB		 2459 if (loaded_vmcs->msr_bitmap)
2460 free_page((unsigned long)loaded_vmcs->msr_bitmap);
355f4fb1 2461 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 2462}
2463
89b0c9f5 2464int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
f21f165e 2465{
491a6038 2466 loaded_vmcs->vmcs = alloc_vmcs(false);
f21f165e
PB		 2467 if (!loaded_vmcs->vmcs)
2468 return -ENOMEM;
2469
2470 loaded_vmcs->shadow_vmcs = NULL;
804939ea 2471 loaded_vmcs->hv_timer_soft_disabled = false;
f21f165e 2472 loaded_vmcs_init(loaded_vmcs);
904e14fb
PB		 2473
2474 if (cpu_has_vmx_msr_bitmap()) {
41836839
BG		 2475 loaded_vmcs->msr_bitmap = (unsigned long *)
2476 __get_free_page(GFP_KERNEL_ACCOUNT);
904e14fb
PB		 2477 if (!loaded_vmcs->msr_bitmap)
2478 goto out_vmcs;
2479 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
ceef7d10 2480
1f008e11
AB		 2481 if (IS_ENABLED(CONFIG_HYPERV) &&
2482 static_branch_unlikely(&enable_evmcs) &&
ceef7d10
VK		 2483 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2484 struct hv_enlightened_vmcs *evmcs =
2485 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2486
2487 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2488 }
904e14fb 2489 }
d7ee039e
SC		 2490
2491 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
3af80fec
SC		 2492 memset(&loaded_vmcs->controls_shadow, 0,
2493 sizeof(struct vmcs_controls_shadow));
d7ee039e 2494
f21f165e 2495 return 0;
904e14fb
PB		 2496
2497out_vmcs:
2498 free_loaded_vmcs(loaded_vmcs);
2499 return -ENOMEM;
f21f165e
PB		 2500}
2501
39959588 2502static void free_kvm_area(void)
6aa8b732
AK		 2503{
2504 int cpu;
2505
3230bb47 2506 for_each_possible_cpu(cpu) {
6aa8b732 2507 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2508 per_cpu(vmxarea, cpu) = NULL;
2509 }
6aa8b732
AK		 2510}
2511
6aa8b732
AK		 2512static __init int alloc_kvm_area(void)
2513{
2514 int cpu;
2515
3230bb47 2516 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2517 struct vmcs *vmcs;
2518
41836839 2519 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
6aa8b732
AK		 2520 if (!vmcs) {
2521 free_kvm_area();
2522 return -ENOMEM;
2523 }
2524
2307af1c
LA		 2525 /*
2526 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2527 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2528 * revision_id reported by MSR_IA32_VMX_BASIC.
2529 *
312a4661 2530 * However, even though not explicitly documented by
2307af1c
LA		 2531 * TLFS, VMXArea passed as VMXON argument should
2532 * still be marked with revision_id reported by
2533 * physical CPU.
2534 */
2535 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2536 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2537
6aa8b732
AK		 2538 per_cpu(vmxarea, cpu) = vmcs;
2539 }
2540 return 0;
2541}
2542
91b0aa2c 2543static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2544 struct kvm_segment *save)
6aa8b732 2545{
d99e4152
GN		 2546 if (!emulate_invalid_guest_state) {
2547 /*
2548 * CS and SS RPL should be equal during guest entry according
2549 * to VMX spec, but in reality it is not always so. Since vcpu
2550 * is in the middle of the transition from real mode to
2551 * protected mode it is safe to assume that RPL 0 is a good
2552 * default value.
2553 */
2554 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 2555 save->selector &= ~SEGMENT_RPL_MASK;
2556 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 2557 save->s = 1;
6aa8b732 2558 }
d99e4152 2559 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2560}
2561
2562static void enter_pmode(struct kvm_vcpu *vcpu)
2563{
2564 unsigned long flags;
a89a8fb9 2565 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2566
d99e4152
GN		 2567 /*
2568 * Update real mode segment cache. It may be not up-to-date if sement
2569 * register was written while vcpu was in a guest mode.
2570 */
2571 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2572 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2573 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2574 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2575 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2576 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2577
7ffd92c5 2578 vmx->rmode.vm86_active = 0;
6aa8b732 2579
2fb92db1
AK		 2580 vmx_segment_cache_clear(vmx);
2581
f5f7b2fe 2582 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2583
2584 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2585 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2586 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2587 vmcs_writel(GUEST_RFLAGS, flags);
2588
66aee91a
RR		 2589 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2590 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2591
2592 update_exception_bitmap(vcpu);
2593
91b0aa2c
GN		 2594 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2595 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2596 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2597 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2598 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2599 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2600}
2601
f5f7b2fe 2602static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2603{
772e0318 2604 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2605 struct kvm_segment var = *save;
2606
2607 var.dpl = 0x3;
2608 if (seg == VCPU_SREG_CS)
2609 var.type = 0x3;
2610
2611 if (!emulate_invalid_guest_state) {
2612 var.selector = var.base >> 4;
2613 var.base = var.base & 0xffff0;
2614 var.limit = 0xffff;
2615 var.g = 0;
2616 var.db = 0;
2617 var.present = 1;
2618 var.s = 1;
2619 var.l = 0;
2620 var.unusable = 0;
2621 var.type = 0x3;
2622 var.avl = 0;
2623 if (save->base & 0xf)
2624 printk_once(KERN_WARNING "kvm: segment base is not "
2625 "paragraph aligned when entering "
2626 "protected mode (seg=%d)", seg);
2627 }
6aa8b732 2628
d99e4152 2629 vmcs_write16(sf->selector, var.selector);
96794e4e 2630 vmcs_writel(sf->base, var.base);
d99e4152
GN		 2631 vmcs_write32(sf->limit, var.limit);
2632 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2633}
2634
2635static void enter_rmode(struct kvm_vcpu *vcpu)
2636{
2637 unsigned long flags;
a89a8fb9 2638 struct vcpu_vmx *vmx = to_vmx(vcpu);
40bbb9d0 2639 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
6aa8b732 2640
f5f7b2fe
AK		 2641 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2642 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2643 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2644 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2645 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2646 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2647 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2648
7ffd92c5 2649 vmx->rmode.vm86_active = 1;
6aa8b732 2650
776e58ea
GN		 2651 /*
2652 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2653 * vcpu. Warn the user that an update is overdue.
776e58ea 2654 */
40bbb9d0 2655 if (!kvm_vmx->tss_addr)
776e58ea
GN		 2656 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2657 "called before entering vcpu\n");
776e58ea 2658
2fb92db1
AK		 2659 vmx_segment_cache_clear(vmx);
2660
40bbb9d0 2661 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
6aa8b732 2662 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2663 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2664
2665 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2666 vmx->rmode.save_rflags = flags;
6aa8b732 2667
053de044 2668 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2669
2670 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2671 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2672 update_exception_bitmap(vcpu);
2673
d99e4152
GN		 2674 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2675 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2676 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2677 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2678 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2679 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2680
8668a3c4 2681 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2682}
2683
97b7ead3 2684void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
401d10de
AS		 2685{
2686 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2687 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2688
2689 if (!msr)
2690 return;
401d10de 2691
f6801dff 2692 vcpu->arch.efer = efer;
401d10de 2693 if (efer & EFER_LMA) {
2961e876 2694 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2695 msr->data = efer;
2696 } else {
2961e876 2697 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2698
2699 msr->data = efer & ~EFER_LME;
2700 }
2701 setup_msrs(vmx);
2702}
2703
05b3e0c2 2704#ifdef CONFIG_X86_64
6aa8b732
AK		 2705
2706static void enter_lmode(struct kvm_vcpu *vcpu)
2707{
2708 u32 guest_tr_ar;
2709
2fb92db1
AK		 2710 vmx_segment_cache_clear(to_vmx(vcpu));
2711
6aa8b732 2712 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 2713 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2714 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2715 __func__);
6aa8b732 2716 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 2717 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2718 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 2719 }
da38f438 2720 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2721}
2722
2723static void exit_lmode(struct kvm_vcpu *vcpu)
2724{
2961e876 2725 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 2726 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2727}
2728
2729#endif
2730
faff8758
JS		 2731static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2732{
2733 int vpid = to_vmx(vcpu)->vpid;
2734
2735 if (!vpid_sync_vcpu_addr(vpid, addr))
2736 vpid_sync_context(vpid);
2737
2738 /*
2739 * If VPIDs are not supported or enabled, then the above is a no-op.
2740 * But we don't really need a TLB flush in that case anyway, because
2741 * each VM entry/exit includes an implicit flush when VPID is 0.
2742 */
2743}
2744
e8467fda
AK		 2745static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2746{
2747 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2748
2749 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2750 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2751}
2752
aff48baa
AK		 2753static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2754{
b4d18517 2755 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
aff48baa
AK		 2756 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2757 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2758}
2759
25c4c276 2760static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2761{
fc78f519
AK		 2762 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2763
2764 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2765 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2766}
2767
1439442c
SY		 2768static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2769{
d0d538b9
GN		 2770 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2771
6de4f3ad
AK		 2772 if (!test_bit(VCPU_EXREG_PDPTR,
2773 (unsigned long *)&vcpu->arch.regs_dirty))
2774 return;
2775
bf03d4f9 2776 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2777 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2778 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2779 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2780 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 2781 }
2782}
2783
97b7ead3 2784void ept_save_pdptrs(struct kvm_vcpu *vcpu)
8f5d549f 2785{
d0d538b9
GN		 2786 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2787
bf03d4f9 2788 if (is_pae_paging(vcpu)) {
d0d538b9
GN		 2789 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2790 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2791 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2792 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2793 }
6de4f3ad
AK		 2794
2795 __set_bit(VCPU_EXREG_PDPTR,
2796 (unsigned long *)&vcpu->arch.regs_avail);
2797 __set_bit(VCPU_EXREG_PDPTR,
2798 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2799}
2800
1439442c
SY		 2801static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2802 unsigned long cr0,
2803 struct kvm_vcpu *vcpu)
2804{
2183f564
SC		 2805 struct vcpu_vmx *vmx = to_vmx(vcpu);
2806
5233dd51
MT		 2807 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2808 vmx_decache_cr3(vcpu);
1439442c
SY		 2809 if (!(cr0 & X86_CR0_PG)) {
2810 /* From paging/starting to nonpaging */
2183f564
SC		 2811 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2812 CPU_BASED_CR3_STORE_EXITING);
1439442c 2813 vcpu->arch.cr0 = cr0;
fc78f519 2814 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2815 } else if (!is_paging(vcpu)) {
2816 /* From nonpaging to paging */
2183f564
SC		 2817 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2818 CPU_BASED_CR3_STORE_EXITING);
1439442c 2819 vcpu->arch.cr0 = cr0;
fc78f519 2820 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2821 }
95eb84a7
SY		 2822
2823 if (!(cr0 & X86_CR0_WP))
2824 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2825}
2826
97b7ead3 2827void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 2828{
7ffd92c5 2829 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2830 unsigned long hw_cr0;
2831
3de6347b 2832 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3a624e29 2833 if (enable_unrestricted_guest)
5037878e 2834 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 2835 else {
5037878e 2836 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 2837
218e763f
GN		 2838 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2839 enter_pmode(vcpu);
6aa8b732 2840
218e763f
GN		 2841 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2842 enter_rmode(vcpu);
2843 }
6aa8b732 2844
05b3e0c2 2845#ifdef CONFIG_X86_64
f6801dff 2846 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2847 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2848 enter_lmode(vcpu);
707d92fa 2849 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2850 exit_lmode(vcpu);
2851 }
2852#endif
2853
b4d18517 2854 if (enable_ept && !enable_unrestricted_guest)
1439442c
SY		 2855 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2856
6aa8b732 2857 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2858 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2859 vcpu->arch.cr0 = cr0;
14168786
GN		 2860
2861 /* depends on vcpu->arch.cr0 to be set to a new value */
2862 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2863}
2864
855feb67
YZ		 2865static int get_ept_level(struct kvm_vcpu *vcpu)
2866{
2867 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2868 return 5;
2869 return 4;
2870}
2871
89b0c9f5 2872u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c 2873{
855feb67
YZ		 2874 u64 eptp = VMX_EPTP_MT_WB;
2875
2876 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
1439442c 2877
995f00a6
PF		 2878 if (enable_ept_ad_bits &&
2879 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
bb97a016 2880 eptp |= VMX_EPTP_AD_ENABLE_BIT;
1439442c
SY		 2881 eptp |= (root_hpa & PAGE_MASK);
2882
2883 return eptp;
2884}
2885
97b7ead3 2886void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
6aa8b732 2887{
877ad952 2888 struct kvm *kvm = vcpu->kvm;
1439442c
SY		 2889 unsigned long guest_cr3;
2890 u64 eptp;
2891
2892 guest_cr3 = cr3;
089d034e 2893 if (enable_ept) {
995f00a6 2894 eptp = construct_eptp(vcpu, cr3);
1439442c 2895 vmcs_write64(EPT_POINTER, eptp);
877ad952
TL		 2896
2897 if (kvm_x86_ops->tlb_remote_flush) {
2898 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2899 to_vmx(vcpu)->ept_pointer = eptp;
2900 to_kvm_vmx(kvm)->ept_pointers_match
2901 = EPT_POINTERS_CHECK;
2902 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2903 }
2904
e90008df
SC		 2905 if (enable_unrestricted_guest || is_paging(vcpu) ||
2906 is_guest_mode(vcpu))
59ab5a8f
JK		 2907 guest_cr3 = kvm_read_cr3(vcpu);
2908 else
877ad952 2909 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
7c93be44 2910 ept_load_pdptrs(vcpu);
1439442c
SY		 2911 }
2912
1439442c 2913 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2914}
2915
97b7ead3 2916int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2917{
fe7f895d 2918 struct vcpu_vmx *vmx = to_vmx(vcpu);
085e68ee
BS		 2919 /*
2920 * Pass through host's Machine Check Enable value to hw_cr4, which
2921 * is in force while we are in guest mode. Do not let guests control
2922 * this bit, even if host CR4.MCE == 0.
2923 */
5dc1f044
SC		 2924 unsigned long hw_cr4;
2925
2926 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2927 if (enable_unrestricted_guest)
2928 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
fe7f895d 2929 else if (vmx->rmode.vm86_active)
5dc1f044
SC		 2930 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2931 else
2932 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
1439442c 2933
64f7a115
SC		 2934 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2935 if (cr4 & X86_CR4_UMIP) {
fe7f895d 2936 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
64f7a115
SC		 2937 hw_cr4 &= ~X86_CR4_UMIP;
2938 } else if (!is_guest_mode(vcpu) ||
fe7f895d
SC		 2939 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
2940 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
2941 }
64f7a115 2942 }
0367f205 2943
5e1746d6
NHE		 2944 if (cr4 & X86_CR4_VMXE) {
2945 /*
2946 * To use VMXON (and later other VMX instructions), a guest
2947 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2948 * So basically the check on whether to allow nested VMX
5bea5123
PB		 2949 * is here. We operate under the default treatment of SMM,
2950 * so VMX cannot be enabled under SMM.
5e1746d6 2951 */
5bea5123 2952 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5e1746d6 2953 return 1;
1a0d74e6 2954 }
3899152c 2955
fe7f895d 2956 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 2957 return 1;
2958
ad312c7c 2959 vcpu->arch.cr4 = cr4;
5dc1f044
SC		 2960
2961 if (!enable_unrestricted_guest) {
2962 if (enable_ept) {
2963 if (!is_paging(vcpu)) {
2964 hw_cr4 &= ~X86_CR4_PAE;
2965 hw_cr4 |= X86_CR4_PSE;
2966 } else if (!(cr4 & X86_CR4_PAE)) {
2967 hw_cr4 &= ~X86_CR4_PAE;
2968 }
bc23008b 2969 }
1439442c 2970
656ec4a4 2971 /*
ddba2628
HH		 2972 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
2973 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
2974 * to be manually disabled when guest switches to non-paging
2975 * mode.
2976 *
2977 * If !enable_unrestricted_guest, the CPU is always running
2978 * with CR0.PG=1 and CR4 needs to be modified.
2979 * If enable_unrestricted_guest, the CPU automatically
2980 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 2981 */
5dc1f044
SC		 2982 if (!is_paging(vcpu))
2983 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
2984 }
656ec4a4 2985
1439442c
SY		 2986 vmcs_writel(CR4_READ_SHADOW, cr4);
2987 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2988 return 0;
6aa8b732
AK		 2989}
2990
97b7ead3 2991void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
6aa8b732 2992{
a9179499 2993 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2994 u32 ar;
2995
c6ad1153 2996 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 2997 *var = vmx->rmode.segs[seg];
a9179499 2998 if (seg == VCPU_SREG_TR
2fb92db1 2999 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3000 return;
1390a28b
AK		 3001 var->base = vmx_read_guest_seg_base(vmx, seg);
3002 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3003 return;
a9179499 3004 }
2fb92db1
AK		 3005 var->base = vmx_read_guest_seg_base(vmx, seg);
3006 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3007 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3008 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3009 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3010 var->type = ar & 15;
3011 var->s = (ar >> 4) & 1;
3012 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3013 /*
3014 * Some userspaces do not preserve unusable property. Since usable
3015 * segment has to be present according to VMX spec we can use present
3016 * property to amend userspace bug by making unusable segment always
3017 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3018 * segment as unusable.
3019 */
3020 var->present = !var->unusable;
6aa8b732
AK		 3021 var->avl = (ar >> 12) & 1;
3022 var->l = (ar >> 13) & 1;
3023 var->db = (ar >> 14) & 1;
3024 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3025}
3026
a9179499
AK		 3027static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3028{
a9179499
AK		 3029 struct kvm_segment s;
3030
3031 if (to_vmx(vcpu)->rmode.vm86_active) {
3032 vmx_get_segment(vcpu, &s, seg);
3033 return s.base;
3034 }
2fb92db1 3035 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3036}
3037
97b7ead3 3038int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3039{
b09408d0
MT		 3040 struct vcpu_vmx *vmx = to_vmx(vcpu);
3041
ae9fedc7 3042 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3043 return 0;
ae9fedc7
PB		 3044 else {
3045 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3046 return VMX_AR_DPL(ar);
69c73028 3047 }
69c73028
AK		 3048}
3049
653e3108 3050static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3051{
6aa8b732
AK		 3052 u32 ar;
3053
f0495f9b 3054 if (var->unusable || !var->present)
6aa8b732
AK		 3055 ar = 1 << 16;
3056 else {
3057 ar = var->type & 15;
3058 ar |= (var->s & 1) << 4;
3059 ar |= (var->dpl & 3) << 5;
3060 ar |= (var->present & 1) << 7;
3061 ar |= (var->avl & 1) << 12;
3062 ar |= (var->l & 1) << 13;
3063 ar |= (var->db & 1) << 14;
3064 ar |= (var->g & 1) << 15;
3065 }
653e3108
AK		 3066
3067 return ar;
3068}
3069
97b7ead3 3070void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
653e3108 3071{
7ffd92c5 3072 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3073 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3074
2fb92db1
AK		 3075 vmx_segment_cache_clear(vmx);
3076
1ecd50a9
GN		 3077 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3078 vmx->rmode.segs[seg] = *var;
3079 if (seg == VCPU_SREG_TR)
3080 vmcs_write16(sf->selector, var->selector);
3081 else if (var->s)
3082 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3083 goto out;
653e3108 3084 }
1ecd50a9 3085
653e3108
AK		 3086 vmcs_writel(sf->base, var->base);
3087 vmcs_write32(sf->limit, var->limit);
3088 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3089
3090 /*
3091 * Fix the "Accessed" bit in AR field of segment registers for older
3092 * qemu binaries.
3093 * IA32 arch specifies that at the time of processor reset the
3094 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3095 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3096 * state vmexit when "unrestricted guest" mode is turned on.
3097 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3098 * tree. Newer qemu binaries with that qemu fix would not need this
3099 * kvm hack.
3100 */
3101 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3102 var->type |= 0x1; /* Accessed */
3a624e29 3103
f924d66d 3104 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3105
3106out:
98eb2f8b 3107 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3108}
3109
6aa8b732
AK		 3110static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3111{
2fb92db1 3112 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3113
3114 *db = (ar >> 14) & 1;
3115 *l = (ar >> 13) & 1;
3116}
3117
89a27f4d 3118static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3119{
89a27f4d
GN		 3120 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3121 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3122}
3123
89a27f4d 3124static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3125{
89a27f4d
GN		 3126 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3127 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3128}
3129
89a27f4d 3130static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3131{
89a27f4d
GN		 3132 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3133 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3134}
3135
89a27f4d 3136static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3137{
89a27f4d
GN		 3138 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3139 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3140}
3141
648dfaa7
MG		 3142static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3143{
3144 struct kvm_segment var;
3145 u32 ar;
3146
3147 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3148 var.dpl = 0x3;
0647f4aa
GN		 3149 if (seg == VCPU_SREG_CS)
3150 var.type = 0x3;
648dfaa7
MG		 3151 ar = vmx_segment_access_rights(&var);
3152
3153 if (var.base != (var.selector << 4))
3154 return false;
89efbed0 3155 if (var.limit != 0xffff)
648dfaa7 3156 return false;
07f42f5f 3157 if (ar != 0xf3)
648dfaa7
MG		 3158 return false;
3159
3160 return true;
3161}
3162
3163static bool code_segment_valid(struct kvm_vcpu *vcpu)
3164{
3165 struct kvm_segment cs;
3166 unsigned int cs_rpl;
3167
3168 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3169 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3170
1872a3f4
AK		 3171 if (cs.unusable)
3172 return false;
4d283ec9 3173 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3174 return false;
3175 if (!cs.s)
3176 return false;
4d283ec9 3177 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3178 if (cs.dpl > cs_rpl)
3179 return false;
1872a3f4 3180 } else {
648dfaa7
MG		 3181 if (cs.dpl != cs_rpl)
3182 return false;
3183 }
3184 if (!cs.present)
3185 return false;
3186
3187 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3188 return true;
3189}
3190
3191static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3192{
3193 struct kvm_segment ss;
3194 unsigned int ss_rpl;
3195
3196 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3197 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3198
1872a3f4
AK		 3199 if (ss.unusable)
3200 return true;
3201 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3202 return false;
3203 if (!ss.s)
3204 return false;
3205 if (ss.dpl != ss_rpl) /* DPL != RPL */
3206 return false;
3207 if (!ss.present)
3208 return false;
3209
3210 return true;
3211}
3212
3213static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3214{
3215 struct kvm_segment var;
3216 unsigned int rpl;
3217
3218 vmx_get_segment(vcpu, &var, seg);
b32a9918 3219 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3220
1872a3f4
AK		 3221 if (var.unusable)
3222 return true;
648dfaa7
MG		 3223 if (!var.s)
3224 return false;
3225 if (!var.present)
3226 return false;
4d283ec9 3227 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3228 if (var.dpl < rpl) /* DPL < RPL */
3229 return false;
3230 }
3231
3232 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3233 * rights flags
3234 */
3235 return true;
3236}
3237
3238static bool tr_valid(struct kvm_vcpu *vcpu)
3239{
3240 struct kvm_segment tr;
3241
3242 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3243
1872a3f4
AK		 3244 if (tr.unusable)
3245 return false;
b32a9918 3246 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3247 return false;
1872a3f4 3248 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3249 return false;
3250 if (!tr.present)
3251 return false;
3252
3253 return true;
3254}
3255
3256static bool ldtr_valid(struct kvm_vcpu *vcpu)
3257{
3258 struct kvm_segment ldtr;
3259
3260 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3261
1872a3f4
AK		 3262 if (ldtr.unusable)
3263 return true;
b32a9918 3264 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3265 return false;
3266 if (ldtr.type != 2)
3267 return false;
3268 if (!ldtr.present)
3269 return false;
3270
3271 return true;
3272}
3273
3274static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3275{
3276 struct kvm_segment cs, ss;
3277
3278 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3279 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3280
b32a9918
NA		 3281 return ((cs.selector & SEGMENT_RPL_MASK) ==
3282 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3283}
3284
3285/*
3286 * Check if guest state is valid. Returns true if valid, false if
3287 * not.
3288 * We assume that registers are always usable
3289 */
3290static bool guest_state_valid(struct kvm_vcpu *vcpu)
3291{
c5e97c80
GN		 3292 if (enable_unrestricted_guest)
3293 return true;
3294
648dfaa7 3295 /* real mode guest state checks */
f13882d8 3296 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3297 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3298 return false;
3299 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3300 return false;
3301 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3302 return false;
3303 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3304 return false;
3305 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3306 return false;
3307 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3308 return false;
3309 } else {
3310 /* protected mode guest state checks */
3311 if (!cs_ss_rpl_check(vcpu))
3312 return false;
3313 if (!code_segment_valid(vcpu))
3314 return false;
3315 if (!stack_segment_valid(vcpu))
3316 return false;
3317 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3318 return false;
3319 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3320 return false;
3321 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3322 return false;
3323 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3324 return false;
3325 if (!tr_valid(vcpu))
3326 return false;
3327 if (!ldtr_valid(vcpu))
3328 return false;
3329 }
3330 /* TODO:
3331 * - Add checks on RIP
3332 * - Add checks on RFLAGS
3333 */
3334
3335 return true;
3336}
3337
d77c26fc 3338static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3339{
40dcaa9f 3340 gfn_t fn;
195aefde 3341 u16 data = 0;
1f755a82 3342 int idx, r;
6aa8b732 3343
40dcaa9f 3344 idx = srcu_read_lock(&kvm->srcu);
40bbb9d0 3345 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
195aefde
IE		 3346 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3347 if (r < 0)
10589a46 3348 goto out;
195aefde 3349 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3350 r = kvm_write_guest_page(kvm, fn++, &data,
3351 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3352 if (r < 0)
10589a46 3353 goto out;
195aefde
IE		 3354 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3355 if (r < 0)
10589a46 3356 goto out;
195aefde
IE		 3357 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3358 if (r < 0)
10589a46 3359 goto out;
195aefde 3360 data = ~0;
10589a46
MT		 3361 r = kvm_write_guest_page(kvm, fn, &data,
3362 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3363 sizeof(u8));
10589a46 3364out:
40dcaa9f 3365 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3366 return r;
6aa8b732
AK		 3367}
3368
b7ebfb05
SY		 3369static int init_rmode_identity_map(struct kvm *kvm)
3370{
40bbb9d0 3371 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
f51770ed 3372 int i, idx, r = 0;
ba049e93 3373 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 3374 u32 tmp;
3375
40bbb9d0 3376 /* Protect kvm_vmx->ept_identity_pagetable_done. */
a255d479
TC		 3377 mutex_lock(&kvm->slots_lock);
3378
40bbb9d0 3379 if (likely(kvm_vmx->ept_identity_pagetable_done))
a255d479 3380 goto out2;
a255d479 3381
40bbb9d0
SC		 3382 if (!kvm_vmx->ept_identity_map_addr)
3383 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3384 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
a255d479 3385
d8a6e365 3386 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
40bbb9d0 3387 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
f51770ed 3388 if (r < 0)
a255d479
TC		 3389 goto out2;
3390
40dcaa9f 3391 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3392 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3393 if (r < 0)
3394 goto out;
3395 /* Set up identity-mapping pagetable for EPT in real mode */
3396 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3397 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3398 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3399 r = kvm_write_guest_page(kvm, identity_map_pfn,
3400 &tmp, i * sizeof(tmp), sizeof(tmp));
3401 if (r < 0)
3402 goto out;
3403 }
40bbb9d0 3404 kvm_vmx->ept_identity_pagetable_done = true;
f51770ed 3405
b7ebfb05 3406out:
40dcaa9f 3407 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3408
3409out2:
3410 mutex_unlock(&kvm->slots_lock);
f51770ed 3411 return r;
b7ebfb05
SY		 3412}
3413
6aa8b732
AK		 3414static void seg_setup(int seg)
3415{
772e0318 3416 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3417 unsigned int ar;
6aa8b732
AK		 3418
3419 vmcs_write16(sf->selector, 0);
3420 vmcs_writel(sf->base, 0);
3421 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3422 ar = 0x93;
3423 if (seg == VCPU_SREG_CS)
3424 ar |= 0x08; /* code segment */
3a624e29
NK		 3425
3426 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3427}
3428
f78e0e2e
SY		 3429static int alloc_apic_access_page(struct kvm *kvm)
3430{
4484141a 3431 struct page *page;
f78e0e2e
SY		 3432 int r = 0;
3433
79fac95e 3434 mutex_lock(&kvm->slots_lock);
c24ae0dc 3435 if (kvm->arch.apic_access_page_done)
f78e0e2e 3436 goto out;
1d8007bd
PB		 3437 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3438 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 3439 if (r)
3440 goto out;
72dc67a6 3441
73a6d941 3442 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3443 if (is_error_page(page)) {
3444 r = -EFAULT;
3445 goto out;
3446 }
3447
c24ae0dc
TC		 3448 /*
3449 * Do not pin the page in memory, so that memory hot-unplug
3450 * is able to migrate it.
3451 */
3452 put_page(page);
3453 kvm->arch.apic_access_page_done = true;
f78e0e2e 3454out:
79fac95e 3455 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3456 return r;
3457}
3458
97b7ead3 3459int allocate_vpid(void)
2384d2b3
SY		 3460{
3461 int vpid;
3462
919818ab 3463 if (!enable_vpid)
991e7a0e 3464 return 0;
2384d2b3
SY		 3465 spin_lock(&vmx_vpid_lock);
3466 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 3467 if (vpid < VMX_NR_VPIDS)
2384d2b3 3468 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 3469 else
3470 vpid = 0;
2384d2b3 3471 spin_unlock(&vmx_vpid_lock);
991e7a0e 3472 return vpid;
2384d2b3
SY		 3473}
3474
97b7ead3 3475void free_vpid(int vpid)
cdbecfc3 3476{
991e7a0e 3477 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 3478 return;
3479 spin_lock(&vmx_vpid_lock);
991e7a0e 3480 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 3481 spin_unlock(&vmx_vpid_lock);
3482}
3483
1e4329ee 3484static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb 3485 u32 msr, int type)
25c5f225 3486{
3e7c73e9 3487 int f = sizeof(unsigned long);
25c5f225
SY		 3488
3489 if (!cpu_has_vmx_msr_bitmap())
3490 return;
3491
ceef7d10
VK		 3492 if (static_branch_unlikely(&enable_evmcs))
3493 evmcs_touch_msr_bitmap();
3494
25c5f225
SY		 3495 /*
3496 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3497 * have the write-low and read-high bitmap offsets the wrong way round.
3498 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3499 */
25c5f225 3500 if (msr <= 0x1fff) {
8d14695f
YZ		 3501 if (type & MSR_TYPE_R)
3502 /* read-low */
3503 __clear_bit(msr, msr_bitmap + 0x000 / f);
3504
3505 if (type & MSR_TYPE_W)
3506 /* write-low */
3507 __clear_bit(msr, msr_bitmap + 0x800 / f);
3508
25c5f225
SY		 3509 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3510 msr &= 0x1fff;
8d14695f
YZ		 3511 if (type & MSR_TYPE_R)
3512 /* read-high */
3513 __clear_bit(msr, msr_bitmap + 0x400 / f);
3514
3515 if (type & MSR_TYPE_W)
3516 /* write-high */
3517 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3518
3519 }
3520}
3521
1e4329ee 3522static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3523 u32 msr, int type)
3524{
3525 int f = sizeof(unsigned long);
3526
3527 if (!cpu_has_vmx_msr_bitmap())
3528 return;
3529
ceef7d10
VK		 3530 if (static_branch_unlikely(&enable_evmcs))
3531 evmcs_touch_msr_bitmap();
3532
904e14fb
PB		 3533 /*
3534 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3535 * have the write-low and read-high bitmap offsets the wrong way round.
3536 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3537 */
3538 if (msr <= 0x1fff) {
3539 if (type & MSR_TYPE_R)
3540 /* read-low */
3541 __set_bit(msr, msr_bitmap + 0x000 / f);
3542
3543 if (type & MSR_TYPE_W)
3544 /* write-low */
3545 __set_bit(msr, msr_bitmap + 0x800 / f);
3546
3547 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3548 msr &= 0x1fff;
3549 if (type & MSR_TYPE_R)
3550 /* read-high */
3551 __set_bit(msr, msr_bitmap + 0x400 / f);
3552
3553 if (type & MSR_TYPE_W)
3554 /* write-high */
3555 __set_bit(msr, msr_bitmap + 0xc00 / f);
3556
3557 }
3558}
3559
1e4329ee 3560static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3561 u32 msr, int type, bool value)
3562{
3563 if (value)
3564 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3565 else
3566 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3567}
3568
904e14fb 3569static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5897297b 3570{
904e14fb
PB		 3571 u8 mode = 0;
3572
3573 if (cpu_has_secondary_exec_ctrls() &&
fe7f895d 3574 (secondary_exec_controls_get(to_vmx(vcpu)) &
904e14fb
PB		 3575 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3576 mode |= MSR_BITMAP_MODE_X2APIC;
3577 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3578 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3579 }
3580
904e14fb 3581 return mode;
8d14695f
YZ		 3582}
3583
904e14fb
PB		 3584static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3585 u8 mode)
8d14695f 3586{
904e14fb
PB		 3587 int msr;
3588
3589 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3590 unsigned word = msr / BITS_PER_LONG;
3591 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3592 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3593 }
3594
3595 if (mode & MSR_BITMAP_MODE_X2APIC) {
3596 /*
3597 * TPR reads and writes can be virtualized even if virtual interrupt
3598 * delivery is not in use.
3599 */
3600 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3601 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3602 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3603 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3604 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3605 }
f6e90f9e 3606 }
5897297b
AK		 3607}
3608
97b7ead3 3609void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
904e14fb
PB		 3610{
3611 struct vcpu_vmx *vmx = to_vmx(vcpu);
3612 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3613 u8 mode = vmx_msr_bitmap_mode(vcpu);
3614 u8 changed = mode ^ vmx->msr_bitmap_mode;
3615
3616 if (!changed)
3617 return;
3618
904e14fb
PB		 3619 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3620 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3621
3622 vmx->msr_bitmap_mode = mode;
3623}
3624
b08c2896
CP		 3625void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3626{
3627 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3628 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3629 u32 i;
3630
3631 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3632 MSR_TYPE_RW, flag);
3633 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3634 MSR_TYPE_RW, flag);
3635 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3636 MSR_TYPE_RW, flag);
3637 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3638 MSR_TYPE_RW, flag);
3639 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3640 vmx_set_intercept_for_msr(msr_bitmap,
3641 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3642 vmx_set_intercept_for_msr(msr_bitmap,
3643 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3644 }
3645}
3646
b2a05fef 3647static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
d50ab6c1 3648{
d62caabb 3649 return enable_apicv;
d50ab6c1
PB		 3650}
3651
e6c67d8c
LA		 3652static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3653{
3654 struct vcpu_vmx *vmx = to_vmx(vcpu);
3655 void *vapic_page;
3656 u32 vppr;
3657 int rvi;
3658
3659 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3660 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
96c66e87 3661 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
e6c67d8c
LA		 3662 return false;
3663
7e712684 3664 rvi = vmx_get_rvi();
e6c67d8c 3665
96c66e87 3666 vapic_page = vmx->nested.virtual_apic_map.hva;
e6c67d8c 3667 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
e6c67d8c
LA		 3668
3669 return ((rvi & 0xf0) > (vppr & 0xf0));
3670}
3671
06a5524f
WV		 3672static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3673 bool nested)
21bc8dc5
RK		 3674{
3675#ifdef CONFIG_SMP
06a5524f
WV		 3676 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3677
21bc8dc5 3678 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6 3679 /*
5753743f
HZ		 3680 * The vector of interrupt to be delivered to vcpu had
3681 * been set in PIR before this function.
3682 *
3683 * Following cases will be reached in this block, and
3684 * we always send a notification event in all cases as
3685 * explained below.
3686 *
3687 * Case 1: vcpu keeps in non-root mode. Sending a
3688 * notification event posts the interrupt to vcpu.
3689 *
3690 * Case 2: vcpu exits to root mode and is still
3691 * runnable. PIR will be synced to vIRR before the
3692 * next vcpu entry. Sending a notification event in
3693 * this case has no effect, as vcpu is not in root
3694 * mode.
28b835d6 3695 *
5753743f
HZ		 3696 * Case 3: vcpu exits to root mode and is blocked.
3697 * vcpu_block() has already synced PIR to vIRR and
3698 * never blocks vcpu if vIRR is not cleared. Therefore,
3699 * a blocked vcpu here does not wait for any requested
3700 * interrupts in PIR, and sending a notification event
3701 * which has no effect is safe here.
28b835d6 3702 */
28b835d6 3703
06a5524f 3704 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK		 3705 return true;
3706 }
3707#endif
3708 return false;
3709}
3710
705699a1
WV		 3711static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3712 int vector)
3713{
3714 struct vcpu_vmx *vmx = to_vmx(vcpu);
3715
3716 if (is_guest_mode(vcpu) &&
3717 vector == vmx->nested.posted_intr_nv) {
705699a1
WV		 3718 /*
3719 * If a posted intr is not recognized by hardware,
3720 * we will accomplish it in the next vmentry.
3721 */
3722 vmx->nested.pi_pending = true;
3723 kvm_make_request(KVM_REQ_EVENT, vcpu);
6b697711
LA		 3724 /* the PIR and ON have been set by L1. */
3725 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3726 kvm_vcpu_kick(vcpu);
705699a1
WV		 3727 return 0;
3728 }
3729 return -1;
3730}
a20ed54d
YZ		 3731/*
3732 * Send interrupt to vcpu via posted interrupt way.
3733 * 1. If target vcpu is running(non-root mode), send posted interrupt
3734 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3735 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3736 * interrupt from PIR in next vmentry.
3737 */
3738static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3739{
3740 struct vcpu_vmx *vmx = to_vmx(vcpu);
3741 int r;
3742
705699a1
WV		 3743 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3744 if (!r)
3745 return;
3746
a20ed54d
YZ		 3747 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3748 return;
3749
b95234c8
PB		 3750 /* If a previous notification has sent the IPI, nothing to do. */
3751 if (pi_test_and_set_on(&vmx->pi_desc))
3752 return;
3753
06a5524f 3754 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d
YZ		 3755 kvm_vcpu_kick(vcpu);
3756}
3757
a3a8ff8e
NHE		 3758/*
3759 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3760 * will not change in the lifetime of the guest.
3761 * Note that host-state that does change is set elsewhere. E.g., host-state
3762 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3763 */
97b7ead3 3764void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3765{
3766 u32 low32, high32;
3767 unsigned long tmpl;
d6e41f11 3768 unsigned long cr0, cr3, cr4;
a3a8ff8e 3769
04ac88ab
AL		 3770 cr0 = read_cr0();
3771 WARN_ON(cr0 & X86_CR0_TS);
3772 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL		 3773
3774 /*
3775 * Save the most likely value for this task's CR3 in the VMCS.
3776 * We can't use __get_current_cr3_fast() because we're not atomic.
3777 */
6c690ee1 3778 cr3 = __read_cr3();
d6e41f11 3779 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
d7ee039e 3780 vmx->loaded_vmcs->host_state.cr3 = cr3;
a3a8ff8e 3781
d974baa3 3782 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 3783 cr4 = cr4_read_shadow();
d974baa3 3784 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
d7ee039e 3785 vmx->loaded_vmcs->host_state.cr4 = cr4;
d974baa3 3786
a3a8ff8e 3787 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3788#ifdef CONFIG_X86_64
3789 /*
3790 * Load null selectors, so we can avoid reloading them in
6d6095bd
SC		 3791 * vmx_prepare_switch_to_host(), in case userspace uses
3792 * the null selectors too (the expected case).
b2da15ac
AK		 3793 */
3794 vmcs_write16(HOST_DS_SELECTOR, 0);
3795 vmcs_write16(HOST_ES_SELECTOR, 0);
3796#else
a3a8ff8e
NHE		 3797 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3798 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3799#endif
a3a8ff8e
NHE		 3800 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3801 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3802
2342080c 3803 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
a3a8ff8e 3804
453eafbe 3805 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
a3a8ff8e
NHE		 3806
3807 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3808 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3809 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3810 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3811
3812 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3813 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3814 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3815 }
5a5e8a15 3816
c73da3fc 3817 if (cpu_has_load_ia32_efer())
5a5e8a15 3818 vmcs_write64(HOST_IA32_EFER, host_efer);
a3a8ff8e
NHE		 3819}
3820
97b7ead3 3821void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
bf8179a0
NHE		 3822{
3823 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3824 if (enable_ept)
3825 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3826 if (is_guest_mode(&vmx->vcpu))
3827 vmx->vcpu.arch.cr4_guest_owned_bits &=
3828 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3829 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3830}
3831
c075c3e4 3832u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
01e439be
YZ		 3833{
3834 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3835
d62caabb 3836 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 3837 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
d02fcf50
PB		 3838
3839 if (!enable_vnmi)
3840 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3841
804939ea
SC		 3842 if (!enable_preemption_timer)
3843 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3844
01e439be
YZ		 3845 return pin_based_exec_ctrl;
3846}
3847
d62caabb
AS		 3848static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3849{
3850 struct vcpu_vmx *vmx = to_vmx(vcpu);
3851
c5f2c766 3852 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 3853 if (cpu_has_secondary_exec_ctrls()) {
3854 if (kvm_vcpu_apicv_active(vcpu))
fe7f895d 3855 secondary_exec_controls_setbit(vmx,
3ce424e4
RK		 3856 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3857 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3858 else
fe7f895d 3859 secondary_exec_controls_clearbit(vmx,
3ce424e4
RK		 3860 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3861 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3862 }
3863
3864 if (cpu_has_vmx_msr_bitmap())
904e14fb 3865 vmx_update_msr_bitmap(vcpu);
d62caabb
AS		 3866}
3867
89b0c9f5
SC		 3868u32 vmx_exec_control(struct vcpu_vmx *vmx)
3869{
3870 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3871
3872 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3873 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3874
3875 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3876 exec_control &= ~CPU_BASED_TPR_SHADOW;
3877#ifdef CONFIG_X86_64
3878 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3879 CPU_BASED_CR8_LOAD_EXITING;
3880#endif
3881 }
3882 if (!enable_ept)
3883 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3884 CPU_BASED_CR3_LOAD_EXITING |
3885 CPU_BASED_INVLPG_EXITING;
3886 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3887 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3888 CPU_BASED_MONITOR_EXITING);
3889 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3890 exec_control &= ~CPU_BASED_HLT_EXITING;
3891 return exec_control;
3892}
3893
3894
80154d77 3895static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
bf8179a0 3896{
80154d77
PB		 3897 struct kvm_vcpu *vcpu = &vmx->vcpu;
3898
bf8179a0 3899 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
0367f205 3900
f99e3daf
CP		 3901 if (pt_mode == PT_MODE_SYSTEM)
3902 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
80154d77 3903 if (!cpu_need_virtualize_apic_accesses(vcpu))
bf8179a0
NHE		 3904 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3905 if (vmx->vpid == 0)
3906 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3907 if (!enable_ept) {
3908 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3909 enable_unrestricted_guest = 0;
3910 }
3911 if (!enable_unrestricted_guest)
3912 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
b31c114b 3913 if (kvm_pause_in_guest(vmx->vcpu.kvm))
bf8179a0 3914 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
80154d77 3915 if (!kvm_vcpu_apicv_active(vcpu))
c7c9c56c
YZ		 3916 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3917 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 3918 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
0367f205
PB		 3919
3920 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3921 * in vmx_set_cr4. */
3922 exec_control &= ~SECONDARY_EXEC_DESC;
3923
abc4fc58
AG		 3924 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3925 (handle_vmptrld).
3926 We can NOT enable shadow_vmcs here because we don't have yet
3927 a current VMCS12
3928 */
3929 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 3930
3931 if (!enable_pml)
3932 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 3933
3db13480
PB		 3934 if (vmx_xsaves_supported()) {
3935 /* Exposing XSAVES only when XSAVE is exposed */
3936 bool xsaves_enabled =
3937 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3938 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
3939
3940 if (!xsaves_enabled)
3941 exec_control &= ~SECONDARY_EXEC_XSAVES;
3942
3943 if (nested) {
3944 if (xsaves_enabled)
6677f3da 3945 vmx->nested.msrs.secondary_ctls_high |=
3db13480
PB		 3946 SECONDARY_EXEC_XSAVES;
3947 else
6677f3da 3948 vmx->nested.msrs.secondary_ctls_high &=
3db13480
PB		 3949 ~SECONDARY_EXEC_XSAVES;
3950 }
3951 }
3952
80154d77
PB		 3953 if (vmx_rdtscp_supported()) {
3954 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
3955 if (!rdtscp_enabled)
3956 exec_control &= ~SECONDARY_EXEC_RDTSCP;
3957
3958 if (nested) {
3959 if (rdtscp_enabled)
6677f3da 3960 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 3961 SECONDARY_EXEC_RDTSCP;
3962 else
6677f3da 3963 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 3964 ~SECONDARY_EXEC_RDTSCP;
3965 }
3966 }
3967
3968 if (vmx_invpcid_supported()) {
3969 /* Exposing INVPCID only when PCID is exposed */
3970 bool invpcid_enabled =
3971 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
3972 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
3973
3974 if (!invpcid_enabled) {
3975 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3976 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
3977 }
3978
3979 if (nested) {
3980 if (invpcid_enabled)
6677f3da 3981 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 3982 SECONDARY_EXEC_ENABLE_INVPCID;
3983 else
6677f3da 3984 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 3985 ~SECONDARY_EXEC_ENABLE_INVPCID;
3986 }
3987 }
3988
45ec368c
JM		 3989 if (vmx_rdrand_supported()) {
3990 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
3991 if (rdrand_enabled)
736fdf72 3992 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 3993
3994 if (nested) {
3995 if (rdrand_enabled)
6677f3da 3996 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 3997 SECONDARY_EXEC_RDRAND_EXITING;
45ec368c 3998 else
6677f3da 3999 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4000 ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 4001 }
4002 }
4003
75f4fc8d
JM		 4004 if (vmx_rdseed_supported()) {
4005 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4006 if (rdseed_enabled)
736fdf72 4007 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4008
4009 if (nested) {
4010 if (rdseed_enabled)
6677f3da 4011 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 4012 SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d 4013 else
6677f3da 4014 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 4015 ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 4016 }
4017 }
4018
80154d77 4019 vmx->secondary_exec_control = exec_control;
bf8179a0
NHE		 4020}
4021
ce88decf
XG		 4022static void ept_set_mmio_spte_mask(void)
4023{
4024 /*
4025 * EPT Misconfigurations can be generated if the value of bits 2:0
4026 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 4027 */
dcdca5fe
PF		 4028 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4029 VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG		 4030}
4031
f53cd63c 4032#define VMX_XSS_EXIT_BITMAP 0
6aa8b732 4033
944c3464
SC		 4034/*
4035 * Sets up the vmcs for emulated real mode.
4036 */
4037static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4038{
4039 int i;
4040
4041 if (nested)
4042 nested_vmx_vcpu_setup();
4043
25c5f225 4044 if (cpu_has_vmx_msr_bitmap())
904e14fb 4045 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
25c5f225 4046
6aa8b732
AK		 4047 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4048
6aa8b732 4049 /* Control */
3af80fec 4050 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
64672c95 4051 vmx->hv_deadline_tsc = -1;
6e5d865c 4052
3af80fec 4053 exec_controls_set(vmx, vmx_exec_control(vmx));
6aa8b732 4054
dfa169bb 4055 if (cpu_has_secondary_exec_ctrls()) {
80154d77 4056 vmx_compute_secondary_exec_control(vmx);
3af80fec 4057 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
dfa169bb 4058 }
f78e0e2e 4059
d62caabb 4060 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 4061 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4062 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4063 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4064 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4065
4066 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 4067
0bcf261c 4068 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 4069 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4070 }
4071
b31c114b 4072 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4b8d54f9 4073 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4074 vmx->ple_window = ple_window;
4075 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4076 }
4077
c3707958
XG		 4078 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4079 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4080 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4081
9581d442
AK		 4082 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4083 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4084 vmx_set_constant_host_state(vmx);
6aa8b732
AK		 4085 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4086 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6aa8b732 4087
2a499e49
BD		 4088 if (cpu_has_vmx_vmfunc())
4089 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4090
2cc51560
ED		 4091 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4092 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
33966dd6 4093 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2cc51560 4094 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
33966dd6 4095 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6aa8b732 4096
74545705
RK		 4097 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4098 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4099
03916db9 4100 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4101 u32 index = vmx_msr_index[i];
4102 u32 data_low, data_high;
a2fa3e9f 4103 int j = vmx->nmsrs;
6aa8b732
AK		 4104
4105 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4106 continue;
432bd6cb
AK		 4107 if (wrmsr_safe(index, data_low, data_high) < 0)
4108 continue;
26bb0981
AK		 4109 vmx->guest_msrs[j].index = i;
4110 vmx->guest_msrs[j].data = 0;
d5696725 4111 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4112 ++vmx->nmsrs;
6aa8b732 4113 }
6aa8b732 4114
3af80fec 4115 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
6aa8b732
AK		 4116
4117 /* 22.2.1, 20.8.1 */
3af80fec 4118 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
1c3d14fe 4119
bd7e5b08
PB		 4120 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4121 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4122
bf8179a0 4123 set_cr4_guest_host_mask(vmx);
e00c8cf2 4124
f53cd63c
WL		 4125 if (vmx_xsaves_supported())
4126 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4127
4e59516a 4128 if (enable_pml) {
4e59516a
PF		 4129 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4130 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4131 }
0b665d30
SC		 4132
4133 if (cpu_has_vmx_encls_vmexit())
4134 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2ef444f1
CP		 4135
4136 if (pt_mode == PT_MODE_HOST_GUEST) {
4137 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4138 /* Bit[6~0] are forced to 1, writes are ignored. */
4139 vmx->pt_desc.guest.output_mask = 0x7F;
4140 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4141 }
e00c8cf2
AK		 4142}
4143
d28bc9dd 4144static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4145{
4146 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4147 struct msr_data apic_base_msr;
d28bc9dd 4148 u64 cr0;
e00c8cf2 4149
7ffd92c5 4150 vmx->rmode.vm86_active = 0;
d28b387f 4151 vmx->spec_ctrl = 0;
e00c8cf2 4152
518e7b94 4153 vcpu->arch.microcode_version = 0x100000000ULL;
ad312c7c 4154 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4155 kvm_set_cr8(vcpu, 0);
4156
4157 if (!init_event) {
4158 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4159 MSR_IA32_APICBASE_ENABLE;
4160 if (kvm_vcpu_is_reset_bsp(vcpu))
4161 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4162 apic_base_msr.host_initiated = true;
4163 kvm_set_apic_base(vcpu, &apic_base_msr);
4164 }
e00c8cf2 4165
2fb92db1
AK		 4166 vmx_segment_cache_clear(vmx);
4167
5706be0d 4168 seg_setup(VCPU_SREG_CS);
66450a21 4169 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 4170 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 4171
4172 seg_setup(VCPU_SREG_DS);
4173 seg_setup(VCPU_SREG_ES);
4174 seg_setup(VCPU_SREG_FS);
4175 seg_setup(VCPU_SREG_GS);
4176 seg_setup(VCPU_SREG_SS);
4177
4178 vmcs_write16(GUEST_TR_SELECTOR, 0);
4179 vmcs_writel(GUEST_TR_BASE, 0);
4180 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4181 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4182
4183 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4184 vmcs_writel(GUEST_LDTR_BASE, 0);
4185 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4186 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4187
d28bc9dd
NA		 4188 if (!init_event) {
4189 vmcs_write32(GUEST_SYSENTER_CS, 0);
4190 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4191 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4192 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4193 }
e00c8cf2 4194
c37c2873 4195 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
66450a21 4196 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4197
e00c8cf2
AK		 4198 vmcs_writel(GUEST_GDTR_BASE, 0);
4199 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4200
4201 vmcs_writel(GUEST_IDTR_BASE, 0);
4202 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4203
443381a8 4204 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 4205 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 4206 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
a554d207
WL		 4207 if (kvm_mpx_supported())
4208 vmcs_write64(GUEST_BNDCFGS, 0);
e00c8cf2 4209
e00c8cf2
AK		 4210 setup_msrs(vmx);
4211
6aa8b732
AK		 4212 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4213
d28bc9dd 4214 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4215 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4216 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4217 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4218 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4219 vmcs_write32(TPR_THRESHOLD, 0);
4220 }
4221
a73896cb 4222 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4223
2384d2b3
SY		 4224 if (vmx->vpid != 0)
4225 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4226
d28bc9dd 4227 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 4228 vmx->vcpu.arch.cr0 = cr0;
f2463247 4229 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 4230 vmx_set_cr4(vcpu, 0);
5690891b 4231 vmx_set_efer(vcpu, 0);
bd7e5b08 4232
d28bc9dd 4233 update_exception_bitmap(vcpu);
6aa8b732 4234
dd5f5341 4235 vpid_sync_context(vmx->vpid);
caa057a2
WL		 4236 if (init_event)
4237 vmx_clear_hlt(vcpu);
6aa8b732
AK		 4238}
4239
55d2375e 4240static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 4241{
2183f564 4242 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK		 4243}
4244
c9a7953f 4245static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 4246{
d02fcf50 4247 if (!enable_vnmi ||
8a1b4392 4248 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK		 4249 enable_irq_window(vcpu);
4250 return;
4251 }
3b86cd99 4252
2183f564 4253 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK		 4254}
4255
66fd3f7f 4256static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4257{
9c8cba37 4258 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4259 uint32_t intr;
4260 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4261
229456fc 4262 trace_kvm_inj_virq(irq);
2714d1d3 4263
fa89a817 4264 ++vcpu->stat.irq_injections;
7ffd92c5 4265 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4266 int inc_eip = 0;
4267 if (vcpu->arch.interrupt.soft)
4268 inc_eip = vcpu->arch.event_exit_inst_len;
4269 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4270 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4271 return;
4272 }
66fd3f7f
GN		 4273 intr = irq | INTR_INFO_VALID_MASK;
4274 if (vcpu->arch.interrupt.soft) {
4275 intr |= INTR_TYPE_SOFT_INTR;
4276 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4277 vmx->vcpu.arch.event_exit_inst_len);
4278 } else
4279 intr |= INTR_TYPE_EXT_INTR;
4280 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
caa057a2
WL		 4281
4282 vmx_clear_hlt(vcpu);
85f455f7
ED		 4283}
4284
f08864b4
SY		 4285static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4286{
66a5a347
JK		 4287 struct vcpu_vmx *vmx = to_vmx(vcpu);
4288
d02fcf50 4289 if (!enable_vnmi) {
8a1b4392
PB		 4290 /*
4291 * Tracking the NMI-blocked state in software is built upon
4292 * finding the next open IRQ window. This, in turn, depends on
4293 * well-behaving guests: They have to keep IRQs disabled at
4294 * least as long as the NMI handler runs. Otherwise we may
4295 * cause NMI nesting, maybe breaking the guest. But as this is
4296 * highly unlikely, we can live with the residual risk.
4297 */
4298 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4299 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4300 }
4301
4c4a6f79
PB		 4302 ++vcpu->stat.nmi_injections;
4303 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 4304
7ffd92c5 4305 if (vmx->rmode.vm86_active) {
71f9833b 4306 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4307 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4308 return;
4309 }
c5a6d5f7 4310
f08864b4
SY		 4311 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4312 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
caa057a2
WL		 4313
4314 vmx_clear_hlt(vcpu);
f08864b4
SY		 4315}
4316
97b7ead3 4317bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3cfc3092 4318{
4c4a6f79
PB		 4319 struct vcpu_vmx *vmx = to_vmx(vcpu);
4320 bool masked;
4321
d02fcf50 4322 if (!enable_vnmi)
8a1b4392 4323 return vmx->loaded_vmcs->soft_vnmi_blocked;
4c4a6f79 4324 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 4325 return false;
4c4a6f79
PB		 4326 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4327 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4328 return masked;
3cfc3092
JK		 4329}
4330
97b7ead3 4331void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3cfc3092
JK		 4332{
4333 struct vcpu_vmx *vmx = to_vmx(vcpu);
4334
d02fcf50 4335 if (!enable_vnmi) {
8a1b4392
PB		 4336 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4337 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4338 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4339 }
4340 } else {
4341 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4342 if (masked)
4343 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4344 GUEST_INTR_STATE_NMI);
4345 else
4346 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4347 GUEST_INTR_STATE_NMI);
4348 }
3cfc3092
JK		 4349}
4350
2505dc9f
JK		 4351static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4352{
b6b8a145
JK		 4353 if (to_vmx(vcpu)->nested.nested_run_pending)
4354 return 0;
ea8ceb83 4355
d02fcf50 4356 if (!enable_vnmi &&
8a1b4392
PB		 4357 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4358 return 0;
4359
2505dc9f
JK		 4360 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4361 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4362 | GUEST_INTR_STATE_NMI));
4363}
4364
78646121
GN		 4365static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4366{
b6b8a145
JK		 4367 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4368 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4369 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4370 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4371}
4372
cbc94022
IE		 4373static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4374{
4375 int ret;
cbc94022 4376
f7eaeb0a
SC		 4377 if (enable_unrestricted_guest)
4378 return 0;
4379
1d8007bd
PB		 4380 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4381 PAGE_SIZE * 3);
cbc94022
IE		 4382 if (ret)
4383 return ret;
40bbb9d0 4384 to_kvm_vmx(kvm)->tss_addr = addr;
1f755a82 4385 return init_rmode_tss(kvm);
cbc94022
IE		 4386}
4387
2ac52ab8
SC		 4388static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4389{
40bbb9d0 4390 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
2ac52ab8
SC		 4391 return 0;
4392}
4393
0ca1b4f4 4394static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4395{
77ab6db0 4396 switch (vec) {
77ab6db0 4397 case BP_VECTOR:
c573cd22
JK		 4398 /*
4399 * Update instruction length as we may reinject the exception
4400 * from user space while in guest debugging mode.
4401 */
4402 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4403 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4404 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4405 return false;
4406 /* fall through */
4407 case DB_VECTOR:
4408 if (vcpu->guest_debug &
4409 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4410 return false;
d0bfb940
JK		 4411 /* fall through */
4412 case DE_VECTOR:
77ab6db0
JK		 4413 case OF_VECTOR:
4414 case BR_VECTOR:
4415 case UD_VECTOR:
4416 case DF_VECTOR:
4417 case SS_VECTOR:
4418 case GP_VECTOR:
4419 case MF_VECTOR:
0ca1b4f4
GN		 4420 return true;
4421 break;
77ab6db0 4422 }
0ca1b4f4
GN		 4423 return false;
4424}
4425
4426static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4427 int vec, u32 err_code)
4428{
4429 /*
4430 * Instruction with address size override prefix opcode 0x67
4431 * Cause the #SS fault with 0 error code in VM86 mode.
4432 */
4433 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
0ce97a2b 4434 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
0ca1b4f4
GN		 4435 if (vcpu->arch.halt_request) {
4436 vcpu->arch.halt_request = 0;
5cb56059 4437 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 4438 }
4439 return 1;
4440 }
4441 return 0;
4442 }
4443
4444 /*
4445 * Forward all other exceptions that are valid in real mode.
4446 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4447 * the required debugging infrastructure rework.
4448 */
4449 kvm_queue_exception(vcpu, vec);
4450 return 1;
6aa8b732
AK		 4451}
4452
a0861c02
AK		 4453/*
4454 * Trigger machine check on the host. We assume all the MSRs are already set up
4455 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4456 * We pass a fake environment to the machine check handler because we want
4457 * the guest to be always treated like user space, no matter what context
4458 * it used internally.
4459 */
4460static void kvm_machine_check(void)
4461{
4462#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4463 struct pt_regs regs = {
4464 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4465 .flags = X86_EFLAGS_IF,
4466 };
4467
4468 do_machine_check(&regs, 0);
4469#endif
4470}
4471
851ba692 4472static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02 4473{
95b5a48c 4474 /* handled by vmx_vcpu_run() */
a0861c02
AK		 4475 return 1;
4476}
4477
95b5a48c 4478static int handle_exception_nmi(struct kvm_vcpu *vcpu)
6aa8b732 4479{
1155f76a 4480 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4481 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4482 u32 intr_info, ex_no, error_code;
42dbaa5a 4483 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4484 u32 vect_info;
4485 enum emulation_result er;
4486
1155f76a 4487 vect_info = vmx->idt_vectoring_info;
88786475 4488 intr_info = vmx->exit_intr_info;
6aa8b732 4489
2ea72039 4490 if (is_machine_check(intr_info) || is_nmi(intr_info))
95b5a48c 4491 return 1; /* handled by handle_exception_nmi_irqoff() */
2ab455cc 4492
082d06ed
WL		 4493 if (is_invalid_opcode(intr_info))
4494 return handle_ud(vcpu);
7aa81cc0 4495
6aa8b732 4496 error_code = 0;
2e11384c 4497 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4498 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e 4499
9e869480
LA		 4500 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4501 WARN_ON_ONCE(!enable_vmware_backdoor);
0ce97a2b 4502 er = kvm_emulate_instruction(vcpu,
9e869480
LA		 4503 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
4504 if (er == EMULATE_USER_EXIT)
4505 return 0;
4506 else if (er != EMULATE_DONE)
4507 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4508 return 1;
4509 }
4510
bf4ca23e
XG		 4511 /*
4512 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4513 * MMIO, it is better to report an internal error.
4514 * See the comments in vmx_handle_exit.
4515 */
4516 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4517 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4518 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4519 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 4520 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 4521 vcpu->run->internal.data[0] = vect_info;
4522 vcpu->run->internal.data[1] = intr_info;
80f0e95d 4523 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 4524 return 0;
4525 }
4526
6aa8b732
AK		 4527 if (is_page_fault(intr_info)) {
4528 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL		 4529 /* EPT won't cause page fault directly */
4530 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
d0006530 4531 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6aa8b732
AK		 4532 }
4533
d0bfb940 4534 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4535
4536 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4537 return handle_rmode_exception(vcpu, ex_no, error_code);
4538
42dbaa5a 4539 switch (ex_no) {
54a20552
EN		 4540 case AC_VECTOR:
4541 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4542 return 1;
42dbaa5a
JK		 4543 case DB_VECTOR:
4544 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4545 if (!(vcpu->guest_debug &
4546 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1fc5d194 4547 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4548 vcpu->arch.dr6 |= dr6 | DR6_RTM;
32d43cd3 4549 if (is_icebp(intr_info))
fd2a445a
HD		 4550 skip_emulated_instruction(vcpu);
4551
42dbaa5a
JK		 4552 kvm_queue_exception(vcpu, DB_VECTOR);
4553 return 1;
4554 }
4555 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4556 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4557 /* fall through */
4558 case BP_VECTOR:
c573cd22
JK		 4559 /*
4560 * Update instruction length as we may reinject #BP from
4561 * user space while in guest debugging mode. Reading it for
4562 * #DB as well causes no harm, it is not used in that case.
4563 */
4564 vmx->vcpu.arch.event_exit_inst_len =
4565 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4566 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4567 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4568 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4569 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4570 break;
4571 default:
d0bfb940
JK		 4572 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4573 kvm_run->ex.exception = ex_no;
4574 kvm_run->ex.error_code = error_code;
42dbaa5a 4575 break;
6aa8b732 4576 }
6aa8b732
AK		 4577 return 0;
4578}
4579
851ba692 4580static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4581{
1165f5fe 4582 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4583 return 1;
4584}
4585
851ba692 4586static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4587{
851ba692 4588 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 4589 vcpu->mmio_needed = 0;
988ad74f
AK		 4590 return 0;
4591}
6aa8b732 4592
851ba692 4593static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4594{
bfdaab09 4595 unsigned long exit_qualification;
dca7f128 4596 int size, in, string;
039576c0 4597 unsigned port;
6aa8b732 4598
bfdaab09 4599 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4600 string = (exit_qualification & 16) != 0;
e70669ab 4601
cf8f70bf 4602 ++vcpu->stat.io_exits;
e70669ab 4603
432baf60 4604 if (string)
0ce97a2b 4605 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4606
cf8f70bf
GN		 4607 port = exit_qualification >> 16;
4608 size = (exit_qualification & 7) + 1;
432baf60 4609 in = (exit_qualification & 8) != 0;
cf8f70bf 4610
dca7f128 4611 return kvm_fast_pio(vcpu, size, port, in);
6aa8b732
AK		 4612}
4613
102d8325
IM		 4614static void
4615vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4616{
4617 /*
4618 * Patch in the VMCALL instruction:
4619 */
4620 hypercall[0] = 0x0f;
4621 hypercall[1] = 0x01;
4622 hypercall[2] = 0xc1;
102d8325
IM		 4623}
4624
0fa06071 4625/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4626static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4627{
eeadf9e7 4628 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4629 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4630 unsigned long orig_val = val;
4631
eeadf9e7
NHE		 4632 /*
4633 * We get here when L2 changed cr0 in a way that did not change
4634 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4635 * but did change L0 shadowed bits. So we first calculate the
4636 * effective cr0 value that L1 would like to write into the
4637 * hardware. It consists of the L2-owned bits from the new
4638 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4639 */
1a0d74e6
JK		 4640 val = (val & ~vmcs12->cr0_guest_host_mask) |
4641 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4642
3899152c 4643 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 4644 return 1;
1a0d74e6
JK		 4645
4646 if (kvm_set_cr0(vcpu, val))
4647 return 1;
4648 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4649 return 0;
1a0d74e6
JK		 4650 } else {
4651 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 4652 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 4653 return 1;
3899152c 4654
eeadf9e7 4655 return kvm_set_cr0(vcpu, val);
1a0d74e6 4656 }
eeadf9e7
NHE		 4657}
4658
4659static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4660{
4661 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4662 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4663 unsigned long orig_val = val;
4664
4665 /* analogously to handle_set_cr0 */
4666 val = (val & ~vmcs12->cr4_guest_host_mask) |
4667 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4668 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4669 return 1;
1a0d74e6 4670 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4671 return 0;
4672 } else
4673 return kvm_set_cr4(vcpu, val);
4674}
4675
0367f205
PB		 4676static int handle_desc(struct kvm_vcpu *vcpu)
4677{
4678 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
0ce97a2b 4679 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
0367f205
PB		 4680}
4681
851ba692 4682static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4683{
229456fc 4684 unsigned long exit_qualification, val;
6aa8b732
AK		 4685 int cr;
4686 int reg;
49a9b07e 4687 int err;
6affcbed 4688 int ret;
6aa8b732 4689
bfdaab09 4690 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4691 cr = exit_qualification & 15;
4692 reg = (exit_qualification >> 8) & 15;
4693 switch ((exit_qualification >> 4) & 3) {
4694 case 0: /* mov to cr */
1e32c079 4695 val = kvm_register_readl(vcpu, reg);
229456fc 4696 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4697 switch (cr) {
4698 case 0:
eeadf9e7 4699 err = handle_set_cr0(vcpu, val);
6affcbed 4700 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4701 case 3:
e1de91cc 4702 WARN_ON_ONCE(enable_unrestricted_guest);
2390218b 4703 err = kvm_set_cr3(vcpu, val);
6affcbed 4704 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4705 case 4:
eeadf9e7 4706 err = handle_set_cr4(vcpu, val);
6affcbed 4707 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4708 case 8: {
4709 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 4710 u8 cr8 = (u8)val;
eea1cff9 4711 err = kvm_set_cr8(vcpu, cr8);
6affcbed 4712 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 4713 if (lapic_in_kernel(vcpu))
6affcbed 4714 return ret;
0a5fff19 4715 if (cr8_prev <= cr8)
6affcbed
KH		 4716 return ret;
4717 /*
4718 * TODO: we might be squashing a
4719 * KVM_GUESTDBG_SINGLESTEP-triggered
4720 * KVM_EXIT_DEBUG here.
4721 */
851ba692 4722 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4723 return 0;
4724 }
4b8073e4 4725 }
6aa8b732 4726 break;
25c4c276 4727 case 2: /* clts */
bd7e5b08
PB		 4728 WARN_ONCE(1, "Guest should always own CR0.TS");
4729 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4730 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 4731 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4732 case 1: /*mov from cr*/
4733 switch (cr) {
4734 case 3:
e1de91cc 4735 WARN_ON_ONCE(enable_unrestricted_guest);
9f8fe504
AK		 4736 val = kvm_read_cr3(vcpu);
4737 kvm_register_write(vcpu, reg, val);
4738 trace_kvm_cr_read(cr, val);
6affcbed 4739 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 4740 case 8:
229456fc
MT		 4741 val = kvm_get_cr8(vcpu);
4742 kvm_register_write(vcpu, reg, val);
4743 trace_kvm_cr_read(cr, val);
6affcbed 4744 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4745 }
4746 break;
4747 case 3: /* lmsw */
a1f83a74 4748 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4749 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4750 kvm_lmsw(vcpu, val);
6aa8b732 4751
6affcbed 4752 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4753 default:
4754 break;
4755 }
851ba692 4756 vcpu->run->exit_reason = 0;
a737f256 4757 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4758 (int)(exit_qualification >> 4) & 3, cr);
4759 return 0;
4760}
4761
851ba692 4762static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4763{
bfdaab09 4764 unsigned long exit_qualification;
16f8a6f9
NA		 4765 int dr, dr7, reg;
4766
4767 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4768 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4769
4770 /* First, if DR does not exist, trigger UD */
4771 if (!kvm_require_dr(vcpu, dr))
4772 return 1;
6aa8b732 4773
f2483415 4774 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4775 if (!kvm_require_cpl(vcpu, 0))
4776 return 1;
16f8a6f9
NA		 4777 dr7 = vmcs_readl(GUEST_DR7);
4778 if (dr7 & DR7_GD) {
42dbaa5a
JK		 4779 /*
4780 * As the vm-exit takes precedence over the debug trap, we
4781 * need to emulate the latter, either for the host or the
4782 * guest debugging itself.
4783 */
4784 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 4785 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 4786 vcpu->run->debug.arch.dr7 = dr7;
82b32774 4787 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 4788 vcpu->run->debug.arch.exception = DB_VECTOR;
4789 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4790 return 0;
4791 } else {
1fc5d194 4792 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 4793 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 4794 kvm_queue_exception(vcpu, DB_VECTOR);
4795 return 1;
4796 }
4797 }
4798
81908bf4 4799 if (vcpu->guest_debug == 0) {
2183f564 4800 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4801
4802 /*
4803 * No more DR vmexits; force a reload of the debug registers
4804 * and reenter on this instruction. The next vmexit will
4805 * retrieve the full state of the debug registers.
4806 */
4807 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4808 return 1;
4809 }
4810
42dbaa5a
JK		 4811 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4812 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 4813 unsigned long val;
4c4d563b
JK		 4814
4815 if (kvm_get_dr(vcpu, dr, &val))
4816 return 1;
4817 kvm_register_write(vcpu, reg, val);
020df079 4818 } else
5777392e 4819 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 4820 return 1;
4821
6affcbed 4822 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4823}
4824
73aaf249
JK		 4825static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4826{
4827 return vcpu->arch.dr6;
4828}
4829
4830static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4831{
4832}
4833
81908bf4
PB		 4834static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4835{
81908bf4
PB		 4836 get_debugreg(vcpu->arch.db[0], 0);
4837 get_debugreg(vcpu->arch.db[1], 1);
4838 get_debugreg(vcpu->arch.db[2], 2);
4839 get_debugreg(vcpu->arch.db[3], 3);
4840 get_debugreg(vcpu->arch.dr6, 6);
4841 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4842
4843 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2183f564 4844 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4845}
4846
020df079
GN		 4847static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4848{
4849 vmcs_writel(GUEST_DR7, val);
4850}
4851
851ba692 4852static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4853{
6a908b62 4854 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK		 4855}
4856
851ba692 4857static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4858{
2b3eaf81 4859 u32 ecx = kvm_rcx_read(vcpu);
609e36d3 4860 struct msr_data msr_info;
6aa8b732 4861
609e36d3
PB		 4862 msr_info.index = ecx;
4863 msr_info.host_initiated = false;
4864 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 4865 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4866 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4867 return 1;
4868 }
4869
609e36d3 4870 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 4871
2b3eaf81
SC		 4872 kvm_rax_write(vcpu, msr_info.data & -1u);
4873 kvm_rdx_write(vcpu, (msr_info.data >> 32) & -1u);
6affcbed 4874 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4875}
4876
851ba692 4877static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4878{
8fe8ab46 4879 struct msr_data msr;
2b3eaf81
SC		 4880 u32 ecx = kvm_rcx_read(vcpu);
4881 u64 data = kvm_read_edx_eax(vcpu);
6aa8b732 4882
8fe8ab46
WA		 4883 msr.data = data;
4884 msr.index = ecx;
4885 msr.host_initiated = false;
854e8bb1 4886 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 4887 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4888 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4889 return 1;
4890 }
4891
59200273 4892 trace_kvm_msr_write(ecx, data);
6affcbed 4893 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4894}
4895
851ba692 4896static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4897{
eb90f341 4898 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 4899 return 1;
4900}
4901
851ba692 4902static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4903{
2183f564 4904 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 4905
3842d135
AK		 4906 kvm_make_request(KVM_REQ_EVENT, vcpu);
4907
a26bf12a 4908 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 4909 return 1;
4910}
4911
851ba692 4912static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 4913{
d3bef15f 4914 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4915}
4916
851ba692 4917static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4918{
0d9c055e 4919 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 4920}
4921
ec25d5e6
GN		 4922static int handle_invd(struct kvm_vcpu *vcpu)
4923{
0ce97a2b 4924 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4925}
4926
851ba692 4927static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4928{
f9c617f6 4929 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4930
4931 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 4932 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 4933}
4934
fee84b07
AK		 4935static int handle_rdpmc(struct kvm_vcpu *vcpu)
4936{
4937 int err;
4938
4939 err = kvm_rdpmc(vcpu);
6affcbed 4940 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 4941}
4942
851ba692 4943static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 4944{
6affcbed 4945 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4946}
4947
2acf923e
DC		 4948static int handle_xsetbv(struct kvm_vcpu *vcpu)
4949{
4950 u64 new_bv = kvm_read_edx_eax(vcpu);
de3cd117 4951 u32 index = kvm_rcx_read(vcpu);
2acf923e
DC		 4952
4953 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 4954 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 4955 return 1;
4956}
4957
f53cd63c
WL		 4958static int handle_xsaves(struct kvm_vcpu *vcpu)
4959{
6affcbed 4960 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 4961 WARN(1, "this should never happen\n");
4962 return 1;
4963}
4964
4965static int handle_xrstors(struct kvm_vcpu *vcpu)
4966{
6affcbed 4967 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 4968 WARN(1, "this should never happen\n");
4969 return 1;
4970}
4971
851ba692 4972static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4973{
58fbbf26
KT		 4974 if (likely(fasteoi)) {
4975 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4976 int access_type, offset;
4977
4978 access_type = exit_qualification & APIC_ACCESS_TYPE;
4979 offset = exit_qualification & APIC_ACCESS_OFFSET;
4980 /*
4981 * Sane guest uses MOV to write EOI, with written value
4982 * not cared. So make a short-circuit here by avoiding
4983 * heavy instruction emulation.
4984 */
4985 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4986 (offset == APIC_EOI)) {
4987 kvm_lapic_set_eoi(vcpu);
6affcbed 4988 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 4989 }
4990 }
0ce97a2b 4991 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4992}
4993
c7c9c56c
YZ		 4994static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4995{
4996 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4997 int vector = exit_qualification & 0xff;
4998
4999 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5000 kvm_apic_set_eoi_accelerated(vcpu, vector);
5001 return 1;
5002}
5003
83d4c286
YZ		 5004static int handle_apic_write(struct kvm_vcpu *vcpu)
5005{
5006 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5007 u32 offset = exit_qualification & 0xfff;
5008
5009 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5010 kvm_apic_write_nodecode(vcpu, offset);
5011 return 1;
5012}
5013
851ba692 5014static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5015{
60637aac 5016 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5017 unsigned long exit_qualification;
e269fb21
JK		 5018 bool has_error_code = false;
5019 u32 error_code = 0;
37817f29 5020 u16 tss_selector;
7f3d35fd 5021 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5022
5023 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5024 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5025 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5026
5027 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5028
5029 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5030 if (reason == TASK_SWITCH_GATE && idt_v) {
5031 switch (type) {
5032 case INTR_TYPE_NMI_INTR:
5033 vcpu->arch.nmi_injected = false;
654f06fc 5034 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5035 break;
5036 case INTR_TYPE_EXT_INTR:
66fd3f7f 5037 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5038 kvm_clear_interrupt_queue(vcpu);
5039 break;
5040 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5041 if (vmx->idt_vectoring_info &
5042 VECTORING_INFO_DELIVER_CODE_MASK) {
5043 has_error_code = true;
5044 error_code =
5045 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5046 }
5047 /* fall through */
64a7ec06
GN		 5048 case INTR_TYPE_SOFT_EXCEPTION:
5049 kvm_clear_exception_queue(vcpu);
5050 break;
5051 default:
5052 break;
5053 }
60637aac 5054 }
37817f29
IE		 5055 tss_selector = exit_qualification;
5056
64a7ec06
GN		 5057 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5058 type != INTR_TYPE_EXT_INTR &&
5059 type != INTR_TYPE_NMI_INTR))
5060 skip_emulated_instruction(vcpu);
5061
7f3d35fd
KW		 5062 if (kvm_task_switch(vcpu, tss_selector,
5063 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5064 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5065 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5066 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5067 vcpu->run->internal.ndata = 0;
42dbaa5a 5068 return 0;
acb54517 5069 }
42dbaa5a 5070
42dbaa5a
JK		 5071 /*
5072 * TODO: What about debug traps on tss switch?
5073 * Are we supposed to inject them and update dr6?
5074 */
5075
5076 return 1;
37817f29
IE		 5077}
5078
851ba692 5079static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5080{
f9c617f6 5081 unsigned long exit_qualification;
1439442c 5082 gpa_t gpa;
eebed243 5083 u64 error_code;
1439442c 5084
f9c617f6 5085 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5086
0be9c7a8
GN		 5087 /*
5088 * EPT violation happened while executing iret from NMI,
5089 * "blocked by NMI" bit has to be set before next VM entry.
5090 * There are errata that may cause this bit to not be set:
5091 * AAK134, BY25.
5092 */
bcd1c294 5093 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
d02fcf50 5094 enable_vnmi &&
bcd1c294 5095 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5096 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5097
1439442c 5098 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5099 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 5100
27959a44 5101 /* Is it a read fault? */
ab22a473 5102 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 5103 ? PFERR_USER_MASK : 0;
5104 /* Is it a write fault? */
ab22a473 5105 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 5106 ? PFERR_WRITE_MASK : 0;
5107 /* Is it a fetch fault? */
ab22a473 5108 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 5109 ? PFERR_FETCH_MASK : 0;
5110 /* ept page table entry is present? */
5111 error_code |= (exit_qualification &
5112 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5113 EPT_VIOLATION_EXECUTABLE))
5114 ? PFERR_PRESENT_MASK : 0;
4f5982a5 5115
eebed243
PB		 5116 error_code |= (exit_qualification & 0x100) != 0 ?
5117 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
25d92081 5118
25d92081 5119 vcpu->arch.exit_qualification = exit_qualification;
4f5982a5 5120 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5121}
5122
851ba692 5123static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5124{
68f89400
MT		 5125 gpa_t gpa;
5126
9034e6e8
PB		 5127 /*
5128 * A nested guest cannot optimize MMIO vmexits, because we have an
5129 * nGPA here instead of the required GPA.
5130 */
68f89400 5131 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9034e6e8
PB		 5132 if (!is_guest_mode(vcpu) &&
5133 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 5134 trace_kvm_fast_mmio(gpa);
d391f120
VK		 5135 /*
5136 * Doing kvm_skip_emulated_instruction() depends on undefined
5137 * behavior: Intel's manual doesn't mandate
5138 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
5139 * occurs and while on real hardware it was observed to be set,
5140 * other hypervisors (namely Hyper-V) don't set it, we end up
5141 * advancing IP with some random value. Disable fast mmio when
5142 * running nested and keep it for real hardware in hope that
5143 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
5144 */
5145 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
5146 return kvm_skip_emulated_instruction(vcpu);
5147 else
0ce97a2b 5148 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
c4409905 5149 EMULATE_DONE;
68c3b4d1 5150 }
68f89400 5151
c75d0edc 5152 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
68f89400
MT		 5153}
5154
851ba692 5155static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 5156{
d02fcf50 5157 WARN_ON_ONCE(!enable_vnmi);
2183f564 5158 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 5159 ++vcpu->stat.nmi_window_exits;
3842d135 5160 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5161
5162 return 1;
5163}
5164
80ced186 5165static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5166{
8b3079a5
AK		 5167 struct vcpu_vmx *vmx = to_vmx(vcpu);
5168 enum emulation_result err = EMULATE_DONE;
80ced186 5169 int ret = 1;
49e9d557 5170 bool intr_window_requested;
b8405c18 5171 unsigned count = 130;
49e9d557 5172
2bb8cafe
SC		 5173 /*
5174 * We should never reach the point where we are emulating L2
5175 * due to invalid guest state as that means we incorrectly
5176 * allowed a nested VMEntry with an invalid vmcs12.
5177 */
5178 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5179
2183f564
SC		 5180 intr_window_requested = exec_controls_get(vmx) &
5181 CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5182
98eb2f8b 5183 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5184 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5185 return handle_interrupt_window(&vmx->vcpu);
5186
72875d8a 5187 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK		 5188 return 1;
5189
0ce97a2b 5190 err = kvm_emulate_instruction(vcpu, 0);
ea953ef0 5191
ac0a48c3 5192 if (err == EMULATE_USER_EXIT) {
94452b9e 5193 ++vcpu->stat.mmio_exits;
80ced186
MG		 5194 ret = 0;
5195 goto out;
5196 }
1d5a4d9b 5197
add5ff7a
SC		 5198 if (err != EMULATE_DONE)
5199 goto emulation_error;
5200
5201 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5202 vcpu->arch.exception.pending)
5203 goto emulation_error;
ea953ef0 5204
8d76c49e
GN		 5205 if (vcpu->arch.halt_request) {
5206 vcpu->arch.halt_request = 0;
5cb56059 5207 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5208 goto out;
5209 }
5210
ea953ef0 5211 if (signal_pending(current))
80ced186 5212 goto out;
ea953ef0
MG		 5213 if (need_resched())
5214 schedule();
5215 }
5216
80ced186
MG		 5217out:
5218 return ret;
b4a2d31d 5219
add5ff7a
SC		 5220emulation_error:
5221 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5222 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5223 vcpu->run->internal.ndata = 0;
5224 return 0;
b4a2d31d
RK		 5225}
5226
5227static void grow_ple_window(struct kvm_vcpu *vcpu)
5228{
5229 struct vcpu_vmx *vmx = to_vmx(vcpu);
5230 int old = vmx->ple_window;
5231
c8e88717
BM		 5232 vmx->ple_window = __grow_ple_window(old, ple_window,
5233 ple_window_grow,
5234 ple_window_max);
b4a2d31d
RK		 5235
5236 if (vmx->ple_window != old)
5237 vmx->ple_window_dirty = true;
7b46268d
RK		 5238
5239 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5240}
5241
5242static void shrink_ple_window(struct kvm_vcpu *vcpu)
5243{
5244 struct vcpu_vmx *vmx = to_vmx(vcpu);
5245 int old = vmx->ple_window;
5246
c8e88717
BM		 5247 vmx->ple_window = __shrink_ple_window(old, ple_window,
5248 ple_window_shrink,
5249 ple_window);
b4a2d31d
RK		 5250
5251 if (vmx->ple_window != old)
5252 vmx->ple_window_dirty = true;
7b46268d
RK		 5253
5254 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5255}
5256
bf9f6ac8
FW		 5257/*
5258 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5259 */
5260static void wakeup_handler(void)
5261{
5262 struct kvm_vcpu *vcpu;
5263 int cpu = smp_processor_id();
5264
5265 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5266 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5267 blocked_vcpu_list) {
5268 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5269
5270 if (pi_test_on(pi_desc) == 1)
5271 kvm_vcpu_kick(vcpu);
5272 }
5273 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5274}
5275
e01bca2f 5276static void vmx_enable_tdp(void)
f160c7b7
JS		 5277{
5278 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5279 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5280 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5281 0ull, VMX_EPT_EXECUTABLE_MASK,
5282 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
d0ec49d4 5283 VMX_EPT_RWX_MASK, 0ull);
f160c7b7
JS		 5284
5285 ept_set_mmio_spte_mask();
5286 kvm_enable_tdp();
5287}
5288
4b8d54f9
ZE		 5289/*
5290 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5291 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5292 */
9fb41ba8 5293static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5294{
b31c114b 5295 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d
RK		 5296 grow_ple_window(vcpu);
5297
de63ad4c
LM		 5298 /*
5299 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5300 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5301 * never set PAUSE_EXITING and just set PLE if supported,
5302 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5303 */
5304 kvm_vcpu_on_spin(vcpu, true);
6affcbed 5305 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 5306}
5307
87c00572 5308static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5309{
6affcbed 5310 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 5311}
5312
87c00572
GS		 5313static int handle_mwait(struct kvm_vcpu *vcpu)
5314{
5315 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5316 return handle_nop(vcpu);
5317}
5318
45ec368c
JM		 5319static int handle_invalid_op(struct kvm_vcpu *vcpu)
5320{
5321 kvm_queue_exception(vcpu, UD_VECTOR);
5322 return 1;
5323}
5324
5f3d45e7
MD		 5325static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5326{
5327 return 1;
5328}
5329
87c00572
GS		 5330static int handle_monitor(struct kvm_vcpu *vcpu)
5331{
5332 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5333 return handle_nop(vcpu);
5334}
5335
55d2375e 5336static int handle_invpcid(struct kvm_vcpu *vcpu)
19677e32 5337{
55d2375e
SC		 5338 u32 vmx_instruction_info;
5339 unsigned long type;
5340 bool pcid_enabled;
5341 gva_t gva;
5342 struct x86_exception e;
5343 unsigned i;
5344 unsigned long roots_to_free = 0;
5345 struct {
5346 u64 pcid;
5347 u64 gla;
5348 } operand;
f9eb4af6 5349
55d2375e 5350 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
19677e32
BD		 5351 kvm_queue_exception(vcpu, UD_VECTOR);
5352 return 1;
5353 }
5354
55d2375e
SC		 5355 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5356 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5357
5358 if (type > 3) {
5359 kvm_inject_gp(vcpu, 0);
f9eb4af6
EK		 5360 return 1;
5361 }
5362
55d2375e
SC		 5363 /* According to the Intel instruction reference, the memory operand
5364 * is read even if it isn't needed (e.g., for type==all)
5365 */
3573e22c 5366 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
fdb28619
EK		 5367 vmx_instruction_info, false,
5368 sizeof(operand), &gva))
3573e22c
BD		 5369 return 1;
5370
55d2375e 5371 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
3573e22c
BD		 5372 kvm_inject_page_fault(vcpu, &e);
5373 return 1;
5374 }
5375
55d2375e
SC		 5376 if (operand.pcid >> 12 != 0) {
5377 kvm_inject_gp(vcpu, 0);
5378 return 1;
abfc52c6 5379 }
e29acc55 5380
55d2375e 5381 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
e29acc55 5382
55d2375e
SC		 5383 switch (type) {
5384 case INVPCID_TYPE_INDIV_ADDR:
5385 if ((!pcid_enabled && (operand.pcid != 0)) ||
5386 is_noncanonical_address(operand.gla, vcpu)) {
5387 kvm_inject_gp(vcpu, 0);
5388 return 1;
5389 }
5390 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5391 return kvm_skip_emulated_instruction(vcpu);
61ada748 5392
55d2375e
SC		 5393 case INVPCID_TYPE_SINGLE_CTXT:
5394 if (!pcid_enabled && (operand.pcid != 0)) {
5395 kvm_inject_gp(vcpu, 0);
5396 return 1;
5397 }
e29acc55 5398
55d2375e
SC		 5399 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5400 kvm_mmu_sync_roots(vcpu);
5401 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5402 }
e29acc55 5403
55d2375e
SC		 5404 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5405 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5406 == operand.pcid)
5407 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
63aff655 5408
55d2375e
SC		 5409 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5410 /*
5411 * If neither the current cr3 nor any of the prev_roots use the
5412 * given PCID, then nothing needs to be done here because a
5413 * resync will happen anyway before switching to any other CR3.
5414 */
e29acc55 5415
55d2375e 5416 return kvm_skip_emulated_instruction(vcpu);
61ada748 5417
55d2375e
SC		 5418 case INVPCID_TYPE_ALL_NON_GLOBAL:
5419 /*
5420 * Currently, KVM doesn't mark global entries in the shadow
5421 * page tables, so a non-global flush just degenerates to a
5422 * global flush. If needed, we could optimize this later by
5423 * keeping track of global entries in shadow page tables.
5424 */
e29acc55 5425
55d2375e
SC		 5426 /* fall-through */
5427 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5428 kvm_mmu_unload(vcpu);
5429 return kvm_skip_emulated_instruction(vcpu);
e29acc55 5430
55d2375e
SC		 5431 default:
5432 BUG(); /* We have already checked above that type <= 3 */
5433 }
e29acc55
JM		 5434}
5435
55d2375e 5436static int handle_pml_full(struct kvm_vcpu *vcpu)
ec378aee 5437{
55d2375e 5438 unsigned long exit_qualification;
b3897a49 5439
55d2375e 5440 trace_kvm_pml_full(vcpu->vcpu_id);
b3897a49 5441
55d2375e 5442 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
cbf71279
RK		 5443
5444 /*
55d2375e
SC		 5445 * PML buffer FULL happened while executing iret from NMI,
5446 * "blocked by NMI" bit has to be set before next VM entry.
cbf71279 5447 */
55d2375e
SC		 5448 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5449 enable_vnmi &&
5450 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5451 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5452 GUEST_INTR_STATE_NMI);
e49fcb8b 5453
55d2375e
SC		 5454 /*
5455 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5456 * here.., and there's no userspace involvement needed for PML.
5457 */
ec378aee
NHE		 5458 return 1;
5459}
5460
55d2375e 5461static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8ca44e88 5462{
804939ea
SC		 5463 struct vcpu_vmx *vmx = to_vmx(vcpu);
5464
5465 if (!vmx->req_immediate_exit &&
5466 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
55d2375e 5467 kvm_lapic_expired_hv_timer(vcpu);
804939ea 5468
55d2375e 5469 return 1;
8ca44e88
DM		 5470}
5471
55d2375e
SC		 5472/*
5473 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5474 * are overwritten by nested_vmx_setup() when nested=1.
5475 */
5476static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
b8bbab92 5477{
55d2375e
SC		 5478 kvm_queue_exception(vcpu, UD_VECTOR);
5479 return 1;
b8bbab92
VK		 5480}
5481
55d2375e 5482static int handle_encls(struct kvm_vcpu *vcpu)
e7953d7f 5483{
55d2375e
SC		 5484 /*
5485 * SGX virtualization is not yet supported. There is no software
5486 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5487 * to prevent the guest from executing ENCLS.
5488 */
5489 kvm_queue_exception(vcpu, UD_VECTOR);
5490 return 1;
e7953d7f
AG		 5491}
5492
ec378aee 5493/*
55d2375e
SC		 5494 * The exit handlers return 1 if the exit was handled fully and guest execution
5495 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5496 * to be done to userspace and return 0.
ec378aee 5497 */
55d2375e 5498static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
95b5a48c 5499 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
55d2375e
SC		 5500 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5501 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5502 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5503 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5504 [EXIT_REASON_CR_ACCESS] = handle_cr,
5505 [EXIT_REASON_DR_ACCESS] = handle_dr,
5506 [EXIT_REASON_CPUID] = handle_cpuid,
5507 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5508 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5509 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5510 [EXIT_REASON_HLT] = handle_halt,
5511 [EXIT_REASON_INVD] = handle_invd,
5512 [EXIT_REASON_INVLPG] = handle_invlpg,
5513 [EXIT_REASON_RDPMC] = handle_rdpmc,
5514 [EXIT_REASON_VMCALL] = handle_vmcall,
5515 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5516 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5517 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5518 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5519 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5520 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5521 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5522 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5523 [EXIT_REASON_VMON] = handle_vmx_instruction,
5524 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5525 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5526 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5527 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5528 [EXIT_REASON_WBINVD] = handle_wbinvd,
5529 [EXIT_REASON_XSETBV] = handle_xsetbv,
5530 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5531 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5532 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5533 [EXIT_REASON_LDTR_TR] = handle_desc,
5534 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5535 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5536 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5537 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5538 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5539 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5540 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5541 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5542 [EXIT_REASON_RDRAND] = handle_invalid_op,
5543 [EXIT_REASON_RDSEED] = handle_invalid_op,
5544 [EXIT_REASON_XSAVES] = handle_xsaves,
5545 [EXIT_REASON_XRSTORS] = handle_xrstors,
5546 [EXIT_REASON_PML_FULL] = handle_pml_full,
5547 [EXIT_REASON_INVPCID] = handle_invpcid,
5548 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5549 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5550 [EXIT_REASON_ENCLS] = handle_encls,
5551};
b8bbab92 5552
55d2375e
SC		 5553static const int kvm_vmx_max_exit_handlers =
5554 ARRAY_SIZE(kvm_vmx_exit_handlers);
ec378aee 5555
55d2375e 5556static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
ec378aee 5557{
55d2375e
SC		 5558 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5559 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
ec378aee
NHE		 5560}
5561
55d2375e 5562static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
27d6c865 5563{
55d2375e
SC		 5564 if (vmx->pml_pg) {
5565 __free_page(vmx->pml_pg);
5566 vmx->pml_pg = NULL;
b8bbab92 5567 }
27d6c865
NHE		 5568}
5569
55d2375e 5570static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
cd232ad0 5571{
55d2375e
SC		 5572 struct vcpu_vmx *vmx = to_vmx(vcpu);
5573 u64 *pml_buf;
5574 u16 pml_idx;
cd232ad0 5575
55d2375e 5576 pml_idx = vmcs_read16(GUEST_PML_INDEX);
cd232ad0 5577
55d2375e
SC		 5578 /* Do nothing if PML buffer is empty */
5579 if (pml_idx == (PML_ENTITY_NUM - 1))
5580 return;
cd232ad0 5581
55d2375e
SC		 5582 /* PML index always points to next available PML buffer entity */
5583 if (pml_idx >= PML_ENTITY_NUM)
5584 pml_idx = 0;
5585 else
5586 pml_idx++;
945679e3 5587
55d2375e
SC		 5588 pml_buf = page_address(vmx->pml_pg);
5589 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5590 u64 gpa;
945679e3 5591
55d2375e
SC		 5592 gpa = pml_buf[pml_idx];
5593 WARN_ON(gpa & (PAGE_SIZE - 1));
5594 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
945679e3
VK		 5595 }
5596
55d2375e
SC		 5597 /* reset PML index */
5598 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
945679e3
VK		 5599}
5600
f4160e45 5601/*
55d2375e
SC		 5602 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5603 * Called before reporting dirty_bitmap to userspace.
f4160e45 5604 */
55d2375e 5605static void kvm_flush_pml_buffers(struct kvm *kvm)
49f705c5 5606{
55d2375e
SC		 5607 int i;
5608 struct kvm_vcpu *vcpu;
49f705c5 5609 /*
55d2375e
SC		 5610 * We only need to kick vcpu out of guest mode here, as PML buffer
5611 * is flushed at beginning of all VMEXITs, and it's obvious that only
5612 * vcpus running in guest are possible to have unflushed GPAs in PML
5613 * buffer.
49f705c5 5614 */
55d2375e
SC		 5615 kvm_for_each_vcpu(i, vcpu, kvm)
5616 kvm_vcpu_kick(vcpu);
49f705c5
NHE		 5617}
5618
55d2375e 5619static void vmx_dump_sel(char *name, uint32_t sel)
49f705c5 5620{
55d2375e
SC		 5621 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5622 name, vmcs_read16(sel),
5623 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5624 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5625 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
49f705c5
NHE		 5626}
5627
55d2375e 5628static void vmx_dump_dtsel(char *name, uint32_t limit)
a8bc284e 5629{
55d2375e
SC		 5630 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5631 name, vmcs_read32(limit),
5632 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
a8bc284e
JM		 5633}
5634
69090810 5635void dump_vmcs(void)
63846663 5636{
6f2f8453
PB		 5637 u32 vmentry_ctl, vmexit_ctl;
5638 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5639 unsigned long cr4;
5640 u64 efer;
55d2375e 5641 int i, n;
63846663 5642
6f2f8453
PB		 5643 if (!dump_invalid_vmcs) {
5644 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5645 return;
5646 }
5647
5648 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5649 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5650 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5651 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5652 cr4 = vmcs_readl(GUEST_CR4);
5653 efer = vmcs_read64(GUEST_IA32_EFER);
5654 secondary_exec_control = 0;
55d2375e
SC		 5655 if (cpu_has_secondary_exec_ctrls())
5656 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
14c07ad8 5657
55d2375e
SC		 5658 pr_err("*** Guest State ***\n");
5659 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5660 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5661 vmcs_readl(CR0_GUEST_HOST_MASK));
5662 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5663 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5664 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5665 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5666 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5667 {
5668 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5669 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5670 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5671 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
e9ac033e 5672 }
55d2375e
SC		 5673 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5674 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5675 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5676 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5677 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5678 vmcs_readl(GUEST_SYSENTER_ESP),
5679 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5680 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5681 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5682 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5683 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5684 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5685 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5686 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5687 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5688 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5689 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5690 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5691 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5692 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5693 efer, vmcs_read64(GUEST_IA32_PAT));
5694 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5695 vmcs_read64(GUEST_IA32_DEBUGCTL),
5696 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5697 if (cpu_has_load_perf_global_ctrl() &&
5698 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5699 pr_err("PerfGlobCtl = 0x%016llx\n",
5700 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5701 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5702 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5703 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5704 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5705 vmcs_read32(GUEST_ACTIVITY_STATE));
5706 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5707 pr_err("InterruptStatus = %04x\n",
5708 vmcs_read16(GUEST_INTR_STATUS));
ff651cb6 5709
55d2375e
SC		 5710 pr_err("*** Host State ***\n");
5711 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5712 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5713 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5714 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5715 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5716 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5717 vmcs_read16(HOST_TR_SELECTOR));
5718 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5719 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5720 vmcs_readl(HOST_TR_BASE));
5721 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5722 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5723 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5724 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5725 vmcs_readl(HOST_CR4));
5726 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5727 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5728 vmcs_read32(HOST_IA32_SYSENTER_CS),
5729 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5730 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5731 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5732 vmcs_read64(HOST_IA32_EFER),
5733 vmcs_read64(HOST_IA32_PAT));
5734 if (cpu_has_load_perf_global_ctrl() &&
5735 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5736 pr_err("PerfGlobCtl = 0x%016llx\n",
5737 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
ff651cb6 5738
55d2375e
SC		 5739 pr_err("*** Control State ***\n");
5740 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5741 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5742 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5743 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5744 vmcs_read32(EXCEPTION_BITMAP),
5745 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5746 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5747 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5748 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5749 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5750 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5751 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5752 vmcs_read32(VM_EXIT_INTR_INFO),
5753 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5754 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5755 pr_err(" reason=%08x qualification=%016lx\n",
5756 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5757 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5758 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5759 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5760 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5761 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5762 pr_err("TSC Multiplier = 0x%016llx\n",
5763 vmcs_read64(TSC_MULTIPLIER));
9d609649
PB		 5764 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5765 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5766 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5767 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5768 }
d6a85c32 5769 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9d609649
PB		 5770 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5771 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
d6a85c32 5772 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
9d609649 5773 }
55d2375e
SC		 5774 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5775 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5776 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5777 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5778 n = vmcs_read32(CR3_TARGET_COUNT);
5779 for (i = 0; i + 1 < n; i += 4)
5780 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5781 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5782 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5783 if (i < n)
5784 pr_err("CR3 target%u=%016lx\n",
5785 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5786 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5787 pr_err("PLE Gap=%08x Window=%08x\n",
5788 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5789 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5790 pr_err("Virtual processor ID = 0x%04x\n",
5791 vmcs_read16(VIRTUAL_PROCESSOR_ID));
ff651cb6
WV		 5792}
5793
55d2375e
SC		 5794/*
5795 * The guest has exited. See if we can fix it or if we need userspace
5796 * assistance.
5797 */
5798static int vmx_handle_exit(struct kvm_vcpu *vcpu)
ff651cb6 5799{
55d2375e
SC		 5800 struct vcpu_vmx *vmx = to_vmx(vcpu);
5801 u32 exit_reason = vmx->exit_reason;
5802 u32 vectoring_info = vmx->idt_vectoring_info;
ff651cb6 5803
55d2375e 5804 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
ff651cb6 5805
55d2375e
SC		 5806 /*
5807 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5808 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5809 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5810 * mode as if vcpus is in root mode, the PML buffer must has been
5811 * flushed already.
5812 */
5813 if (enable_pml)
5814 vmx_flush_pml_buffer(vcpu);
1dc35dac 5815
55d2375e
SC		 5816 /* If guest state is invalid, start emulating */
5817 if (vmx->emulation_required)
5818 return handle_invalid_guest_state(vcpu);
1dc35dac 5819
55d2375e
SC		 5820 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5821 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9ed38ffa 5822
55d2375e
SC		 5823 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5824 dump_vmcs();
5825 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5826 vcpu->run->fail_entry.hardware_entry_failure_reason
5827 = exit_reason;
5828 return 0;
9ed38ffa
LP		 5829 }
5830
55d2375e
SC		 5831 if (unlikely(vmx->fail)) {
5832 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5833 vcpu->run->fail_entry.hardware_entry_failure_reason
5834 = vmcs_read32(VM_INSTRUCTION_ERROR);
5835 return 0;
5836 }
50c28f21 5837
55d2375e
SC		 5838 /*
5839 * Note:
5840 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5841 * delivery event since it indicates guest is accessing MMIO.
5842 * The vm-exit can be triggered again after return to guest that
5843 * will cause infinite loop.
5844 */
5845 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5846 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5847 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5848 exit_reason != EXIT_REASON_PML_FULL &&
5849 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5850 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5851 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5852 vcpu->run->internal.ndata = 3;
5853 vcpu->run->internal.data[0] = vectoring_info;
5854 vcpu->run->internal.data[1] = exit_reason;
5855 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5856 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5857 vcpu->run->internal.ndata++;
5858 vcpu->run->internal.data[3] =
5859 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5860 }
5861 return 0;
5862 }
50c28f21 5863
55d2375e
SC		 5864 if (unlikely(!enable_vnmi &&
5865 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5866 if (vmx_interrupt_allowed(vcpu)) {
5867 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5868 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5869 vcpu->arch.nmi_pending) {
5870 /*
5871 * This CPU don't support us in finding the end of an
5872 * NMI-blocked window if the guest runs with IRQs
5873 * disabled. So we pull the trigger after 1 s of
5874 * futile waiting, but inform the user about this.
5875 */
5876 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5877 "state on VCPU %d after 1 s timeout\n",
5878 __func__, vcpu->vcpu_id);
5879 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5880 }
5881 }
50c28f21 5882
55d2375e
SC		 5883 if (exit_reason < kvm_vmx_max_exit_handlers
5884 && kvm_vmx_exit_handlers[exit_reason])
5885 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5886 else {
5887 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5888 exit_reason);
5889 kvm_queue_exception(vcpu, UD_VECTOR);
5890 return 1;
5891 }
9ed38ffa
LP		 5892}
5893
efebf0aa 5894/*
55d2375e
SC		 5895 * Software based L1D cache flush which is used when microcode providing
5896 * the cache control MSR is not loaded.
efebf0aa 5897 *
55d2375e
SC		 5898 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5899 * flush it is required to read in 64 KiB because the replacement algorithm
5900 * is not exactly LRU. This could be sized at runtime via topology
5901 * information but as all relevant affected CPUs have 32KiB L1D cache size
5902 * there is no point in doing so.
efebf0aa 5903 */
55d2375e 5904static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
fe3ef05c 5905{
55d2375e 5906 int size = PAGE_SIZE << L1D_CACHE_ORDER;
25a2e4fe
PB		 5907
5908 /*
55d2375e
SC		 5909 * This code is only executed when the the flush mode is 'cond' or
5910 * 'always'
25a2e4fe 5911 */
55d2375e
SC		 5912 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5913 bool flush_l1d;
25a2e4fe 5914
55d2375e
SC		 5915 /*
5916 * Clear the per-vcpu flush bit, it gets set again
5917 * either from vcpu_run() or from one of the unsafe
5918 * VMEXIT handlers.
5919 */
5920 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5921 vcpu->arch.l1tf_flush_l1d = false;
25a2e4fe 5922
55d2375e
SC		 5923 /*
5924 * Clear the per-cpu flush bit, it gets set again from
5925 * the interrupt handlers.
5926 */
5927 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5928 kvm_clear_cpu_l1tf_flush_l1d();
25a2e4fe 5929
55d2375e
SC		 5930 if (!flush_l1d)
5931 return;
5932 }
09abe320 5933
55d2375e 5934 vcpu->stat.l1d_flush++;
25a2e4fe 5935
55d2375e
SC		 5936 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5937 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5938 return;
5939 }
25a2e4fe 5940
55d2375e
SC		 5941 asm volatile(
5942 /* First ensure the pages are in the TLB */
5943 "xorl %%eax, %%eax\n"
5944 ".Lpopulate_tlb:\n\t"
5945 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5946 "addl $4096, %%eax\n\t"
5947 "cmpl %%eax, %[size]\n\t"
5948 "jne .Lpopulate_tlb\n\t"
5949 "xorl %%eax, %%eax\n\t"
5950 "cpuid\n\t"
5951 /* Now fill the cache */
5952 "xorl %%eax, %%eax\n"
5953 ".Lfill_cache:\n"
5954 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5955 "addl $64, %%eax\n\t"
5956 "cmpl %%eax, %[size]\n\t"
5957 "jne .Lfill_cache\n\t"
5958 "lfence\n"
5959 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5960 [size] "r" (size)
5961 : "eax", "ebx", "ecx", "edx");
09abe320 5962}
25a2e4fe 5963
55d2375e 5964static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
09abe320 5965{
55d2375e 5966 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
09abe320 5967
55d2375e
SC		 5968 if (is_guest_mode(vcpu) &&
5969 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5970 return;
25a2e4fe 5971
55d2375e
SC		 5972 if (irr == -1 || tpr < irr) {
5973 vmcs_write32(TPR_THRESHOLD, 0);
5974 return;
25a2e4fe 5975 }
55d2375e
SC		 5976
5977 vmcs_write32(TPR_THRESHOLD, irr);
8665c3f9
PB		 5978}
5979
55d2375e 5980void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
8665c3f9 5981{
fe7f895d 5982 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 5983 u32 sec_exec_control;
8665c3f9 5984
55d2375e
SC		 5985 if (!lapic_in_kernel(vcpu))
5986 return;
9314006d 5987
55d2375e
SC		 5988 if (!flexpriority_enabled &&
5989 !cpu_has_vmx_virtualize_x2apic_mode())
5990 return;
705699a1 5991
55d2375e
SC		 5992 /* Postpone execution until vmcs01 is the current VMCS. */
5993 if (is_guest_mode(vcpu)) {
fe7f895d 5994 vmx->nested.change_vmcs01_virtual_apic_mode = true;
55d2375e 5995 return;
6beb7bd5 5996 }
fe3ef05c 5997
fe7f895d 5998 sec_exec_control = secondary_exec_controls_get(vmx);
55d2375e
SC		 5999 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6000 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
09abe320 6001
55d2375e
SC		 6002 switch (kvm_get_apic_mode(vcpu)) {
6003 case LAPIC_MODE_INVALID:
6004 WARN_ONCE(true, "Invalid local APIC state");
6005 case LAPIC_MODE_DISABLED:
6006 break;
6007 case LAPIC_MODE_XAPIC:
6008 if (flexpriority_enabled) {
6009 sec_exec_control |=
6010 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6011 vmx_flush_tlb(vcpu, true);
6012 }
6013 break;
6014 case LAPIC_MODE_X2APIC:
6015 if (cpu_has_vmx_virtualize_x2apic_mode())
6016 sec_exec_control |=
6017 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6018 break;
09abe320 6019 }
fe7f895d 6020 secondary_exec_controls_set(vmx, sec_exec_control);
09abe320 6021
55d2375e
SC		 6022 vmx_update_msr_bitmap(vcpu);
6023}
0238ea91 6024
55d2375e
SC		 6025static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6026{
6027 if (!is_guest_mode(vcpu)) {
6028 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6029 vmx_flush_tlb(vcpu, true);
6030 }
6031}
fe3ef05c 6032
55d2375e
SC		 6033static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6034{
6035 u16 status;
6036 u8 old;
32c7acf0 6037
55d2375e
SC		 6038 if (max_isr == -1)
6039 max_isr = 0;
608406e2 6040
55d2375e
SC		 6041 status = vmcs_read16(GUEST_INTR_STATUS);
6042 old = status >> 8;
6043 if (max_isr != old) {
6044 status &= 0xff;
6045 status |= max_isr << 8;
6046 vmcs_write16(GUEST_INTR_STATUS, status);
6047 }
6048}
6beb7bd5 6049
55d2375e
SC		 6050static void vmx_set_rvi(int vector)
6051{
6052 u16 status;
6053 u8 old;
0b665d30 6054
55d2375e
SC		 6055 if (vector == -1)
6056 vector = 0;
fe3ef05c 6057
55d2375e
SC		 6058 status = vmcs_read16(GUEST_INTR_STATUS);
6059 old = (u8)status & 0xff;
6060 if ((u8)vector != old) {
6061 status &= ~0xff;
6062 status |= (u8)vector;
6063 vmcs_write16(GUEST_INTR_STATUS, status);
09abe320 6064 }
55d2375e 6065}
09abe320 6066
55d2375e
SC		 6067static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6068{
09abe320 6069 /*
55d2375e
SC		 6070 * When running L2, updating RVI is only relevant when
6071 * vmcs12 virtual-interrupt-delivery enabled.
6072 * However, it can be enabled only when L1 also
6073 * intercepts external-interrupts and in that case
6074 * we should not update vmcs02 RVI but instead intercept
6075 * interrupt. Therefore, do nothing when running L2.
fe3ef05c 6076 */
55d2375e
SC		 6077 if (!is_guest_mode(vcpu))
6078 vmx_set_rvi(max_irr);
6079}
fe3ef05c 6080
55d2375e
SC		 6081static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6082{
6083 struct vcpu_vmx *vmx = to_vmx(vcpu);
6084 int max_irr;
6085 bool max_irr_updated;
a7c0b07d 6086
55d2375e
SC		 6087 WARN_ON(!vcpu->arch.apicv_active);
6088 if (pi_test_on(&vmx->pi_desc)) {
6089 pi_clear_on(&vmx->pi_desc);
6090 /*
6091 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6092 * But on x86 this is just a compiler barrier anyway.
6093 */
6094 smp_mb__after_atomic();
6095 max_irr_updated =
6096 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
c4ebd629
VK		 6097
6098 /*
55d2375e
SC		 6099 * If we are running L2 and L1 has a new pending interrupt
6100 * which can be injected, we should re-evaluate
6101 * what should be done with this new L1 interrupt.
6102 * If L1 intercepts external-interrupts, we should
6103 * exit from L2 to L1. Otherwise, interrupt should be
6104 * delivered directly to L2.
c4ebd629 6105 */
55d2375e
SC		 6106 if (is_guest_mode(vcpu) && max_irr_updated) {
6107 if (nested_exit_on_intr(vcpu))
6108 kvm_vcpu_exiting_guest_mode(vcpu);
6109 else
6110 kvm_make_request(KVM_REQ_EVENT, vcpu);
c4ebd629 6111 }
55d2375e
SC		 6112 } else {
6113 max_irr = kvm_lapic_find_highest_irr(vcpu);
a7c0b07d 6114 }
55d2375e
SC		 6115 vmx_hwapic_irr_update(vcpu, max_irr);
6116 return max_irr;
6117}
a7c0b07d 6118
55d2375e
SC		 6119static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6120{
6121 if (!kvm_vcpu_apicv_active(vcpu))
6122 return;
25a2e4fe 6123
55d2375e
SC		 6124 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6125 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6126 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6127 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8665c3f9
PB		 6128}
6129
55d2375e 6130static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8665c3f9
PB		 6131{
6132 struct vcpu_vmx *vmx = to_vmx(vcpu);
9d1887ef 6133
55d2375e
SC		 6134 pi_clear_on(&vmx->pi_desc);
6135 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6136}
8665c3f9 6137
95b5a48c 6138static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
55d2375e 6139{
beb8d93b 6140 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
fe3ef05c 6141
55d2375e 6142 /* if exit due to PF check for async PF */
beb8d93b 6143 if (is_page_fault(vmx->exit_intr_info))
55d2375e 6144 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
e79f245d 6145
55d2375e 6146 /* Handle machine checks before interrupts are enabled */
beb8d93b 6147 if (is_machine_check(vmx->exit_intr_info))
55d2375e 6148 kvm_machine_check();
fe3ef05c 6149
55d2375e 6150 /* We need to handle NMIs before interrupts are enabled */
beb8d93b 6151 if (is_nmi(vmx->exit_intr_info)) {
55d2375e
SC		 6152 kvm_before_interrupt(&vmx->vcpu);
6153 asm("int $2");
6154 kvm_after_interrupt(&vmx->vcpu);
fe3ef05c 6155 }
55d2375e 6156}
fe3ef05c 6157
95b5a48c 6158static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
55d2375e 6159{
49def500
SC		 6160 unsigned int vector;
6161 unsigned long entry;
55d2375e 6162#ifdef CONFIG_X86_64
49def500 6163 unsigned long tmp;
55d2375e 6164#endif
49def500
SC		 6165 gate_desc *desc;
6166 u32 intr_info;
fe3ef05c 6167
49def500
SC		 6168 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6169 if (WARN_ONCE(!is_external_intr(intr_info),
6170 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6171 return;
6172
6173 vector = intr_info & INTR_INFO_VECTOR_MASK;
2342080c 6174 desc = (gate_desc *)host_idt_base + vector;
49def500
SC		 6175 entry = gate_offset(desc);
6176
165072b0
SC		 6177 kvm_before_interrupt(vcpu);
6178
49def500 6179 asm volatile(
55d2375e 6180#ifdef CONFIG_X86_64
49def500
SC		 6181 "mov %%" _ASM_SP ", %[sp]\n\t"
6182 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6183 "push $%c[ss]\n\t"
6184 "push %[sp]\n\t"
55d2375e 6185#endif
49def500
SC		 6186 "pushf\n\t"
6187 __ASM_SIZE(push) " $%c[cs]\n\t"
6188 CALL_NOSPEC
6189 :
55d2375e 6190#ifdef CONFIG_X86_64
49def500 6191 [sp]"=&r"(tmp),
55d2375e 6192#endif
49def500
SC		 6193 ASM_CALL_CONSTRAINT
6194 :
6195 THUNK_TARGET(entry),
6196 [ss]"i"(__KERNEL_DS),
6197 [cs]"i"(__KERNEL_CS)
6198 );
165072b0
SC		 6199
6200 kvm_after_interrupt(vcpu);
55d2375e 6201}
95b5a48c
SC		 6202STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6203
6204static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6205{
6206 struct vcpu_vmx *vmx = to_vmx(vcpu);
6207
6208 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6209 handle_external_interrupt_irqoff(vcpu);
6210 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6211 handle_exception_nmi_irqoff(vmx);
6212}
5a6a9748 6213
55d2375e
SC		 6214static bool vmx_has_emulated_msr(int index)
6215{
6216 switch (index) {
6217 case MSR_IA32_SMBASE:
6218 /*
6219 * We cannot do SMM unless we can run the guest in big
6220 * real mode.
6221 */
6222 return enable_unrestricted_guest || emulate_invalid_guest_state;
95c5c7c7
PB		 6223 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6224 return nested;
55d2375e
SC		 6225 case MSR_AMD64_VIRT_SPEC_CTRL:
6226 /* This is AMD only. */
6227 return false;
6228 default:
6229 return true;
3184a995 6230 }
55d2375e 6231}
2bb8cafe 6232
86f5201d
CP		 6233static bool vmx_pt_supported(void)
6234{
6235 return pt_mode == PT_MODE_HOST_GUEST;
6236}
6237
55d2375e
SC		 6238static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6239{
6240 u32 exit_intr_info;
6241 bool unblock_nmi;
6242 u8 vector;
6243 bool idtv_info_valid;
7ca29de2 6244
55d2375e 6245 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
feaf0c7d 6246
55d2375e
SC		 6247 if (enable_vnmi) {
6248 if (vmx->loaded_vmcs->nmi_known_unmasked)
6249 return;
6250 /*
6251 * Can't use vmx->exit_intr_info since we're not sure what
6252 * the exit reason is.
6253 */
6254 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6255 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6256 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6257 /*
6258 * SDM 3: 27.7.1.2 (September 2008)
6259 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6260 * a guest IRET fault.
6261 * SDM 3: 23.2.2 (September 2008)
6262 * Bit 12 is undefined in any of the following cases:
6263 * If the VM exit sets the valid bit in the IDT-vectoring
6264 * information field.
6265 * If the VM exit is due to a double fault.
6266 */
6267 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6268 vector != DF_VECTOR && !idtv_info_valid)
6269 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6270 GUEST_INTR_STATE_NMI);
6271 else
6272 vmx->loaded_vmcs->nmi_known_unmasked =
6273 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6274 & GUEST_INTR_STATE_NMI);
6275 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6276 vmx->loaded_vmcs->vnmi_blocked_time +=
6277 ktime_to_ns(ktime_sub(ktime_get(),
6278 vmx->loaded_vmcs->entry_time));
fe3ef05c
NHE		 6279}
6280
55d2375e
SC		 6281static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6282 u32 idt_vectoring_info,
6283 int instr_len_field,
6284 int error_code_field)
0c7f650e 6285{
55d2375e
SC		 6286 u8 vector;
6287 int type;
6288 bool idtv_info_valid;
0c7f650e 6289
55d2375e 6290 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
0c7f650e 6291
55d2375e
SC		 6292 vcpu->arch.nmi_injected = false;
6293 kvm_clear_exception_queue(vcpu);
6294 kvm_clear_interrupt_queue(vcpu);
27c42a1b 6295
55d2375e
SC		 6296 if (!idtv_info_valid)
6297 return;
c7c2c709 6298
55d2375e 6299 kvm_make_request(KVM_REQ_EVENT, vcpu);
ca0bde28 6300
55d2375e
SC		 6301 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6302 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
64a919f7 6303
55d2375e
SC		 6304 switch (type) {
6305 case INTR_TYPE_NMI_INTR:
6306 vcpu->arch.nmi_injected = true;
6307 /*
6308 * SDM 3: 27.7.1.2 (September 2008)
6309 * Clear bit "block by NMI" before VM entry if a NMI
6310 * delivery faulted.
6311 */
6312 vmx_set_nmi_mask(vcpu, false);
6313 break;
6314 case INTR_TYPE_SOFT_EXCEPTION:
6315 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6316 /* fall through */
6317 case INTR_TYPE_HARD_EXCEPTION:
6318 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6319 u32 err = vmcs_read32(error_code_field);
6320 kvm_requeue_exception_e(vcpu, vector, err);
6321 } else
6322 kvm_requeue_exception(vcpu, vector);
6323 break;
6324 case INTR_TYPE_SOFT_INTR:
6325 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6326 /* fall through */
6327 case INTR_TYPE_EXT_INTR:
6328 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6329 break;
6330 default:
6331 break;
0447378a 6332 }
ca0bde28
JM		 6333}
6334
55d2375e 6335static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
f145d90d 6336{
55d2375e
SC		 6337 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6338 VM_EXIT_INSTRUCTION_LEN,
6339 IDT_VECTORING_ERROR_CODE);
f145d90d
LA		 6340}
6341
55d2375e 6342static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
ca0bde28 6343{
55d2375e
SC		 6344 __vmx_complete_interrupts(vcpu,
6345 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6346 VM_ENTRY_INSTRUCTION_LEN,
6347 VM_ENTRY_EXCEPTION_ERROR_CODE);
f1b026a3 6348
55d2375e 6349 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
ca0bde28
JM		 6350}
6351
55d2375e 6352static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
52017608 6353{
55d2375e
SC		 6354 int i, nr_msrs;
6355 struct perf_guest_switch_msr *msrs;
7c177938 6356
55d2375e 6357 msrs = perf_guest_get_msrs(&nr_msrs);
384bb783 6358
55d2375e
SC		 6359 if (!msrs)
6360 return;
f1b026a3 6361
55d2375e
SC		 6362 for (i = 0; i < nr_msrs; i++)
6363 if (msrs[i].host == msrs[i].guest)
6364 clear_atomic_switch_msr(vmx, msrs[i].msr);
6365 else
6366 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6367 msrs[i].host, false);
ca0bde28 6368}
52017608 6369
55d2375e 6370static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
858e25c0
JM		 6371{
6372 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e
SC		 6373 u64 tscl;
6374 u32 delta_tsc;
52017608 6375
55d2375e 6376 if (vmx->req_immediate_exit) {
804939ea
SC		 6377 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6378 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6379 } else if (vmx->hv_deadline_tsc != -1) {
55d2375e
SC		 6380 tscl = rdtsc();
6381 if (vmx->hv_deadline_tsc > tscl)
6382 /* set_hv_timer ensures the delta fits in 32-bits */
6383 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6384 cpu_preemption_timer_multi);
6385 else
6386 delta_tsc = 0;
858e25c0 6387
804939ea
SC		 6388 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6389 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6390 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6391 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6392 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
7f7f1ba3 6393 }
858e25c0
JM		 6394}
6395
c09b03eb 6396void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
ca0bde28 6397{
c09b03eb
SC		 6398 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6399 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6400 vmcs_writel(HOST_RSP, host_rsp);
6401 }
5ad6ece8 6402}
5f3d5799 6403
fc2ba5a2 6404bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
5ad6ece8
SC		 6405
6406static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6407{
6408 struct vcpu_vmx *vmx = to_vmx(vcpu);
6409 unsigned long cr3, cr4;
6410
6411 /* Record the guest's net vcpu time for enforced NMI injections. */
6412 if (unlikely(!enable_vnmi &&
6413 vmx->loaded_vmcs->soft_vnmi_blocked))
6414 vmx->loaded_vmcs->entry_time = ktime_get();
6415
6416 /* Don't enter VMX if guest state is invalid, let the exit handler
6417 start emulation until we arrive back to a valid state */
6418 if (vmx->emulation_required)
6419 return;
6420
6421 if (vmx->ple_window_dirty) {
6422 vmx->ple_window_dirty = false;
6423 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6424 }
6425
3731905e
SC		 6426 if (vmx->nested.need_vmcs12_to_shadow_sync)
6427 nested_sync_vmcs12_to_shadow(vcpu);
5ad6ece8
SC		 6428
6429 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6430 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6431 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6432 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6433
6434 cr3 = __get_current_cr3_fast();
6435 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6436 vmcs_writel(HOST_CR3, cr3);
6437 vmx->loaded_vmcs->host_state.cr3 = cr3;
6438 }
6439
6440 cr4 = cr4_read_shadow();
6441 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6442 vmcs_writel(HOST_CR4, cr4);
6443 vmx->loaded_vmcs->host_state.cr4 = cr4;
6444 }
6445
6446 /* When single-stepping over STI and MOV SS, we must clear the
6447 * corresponding interruptibility bits in the guest state. Otherwise
6448 * vmentry fails as it then expects bit 14 (BS) in pending debug
6449 * exceptions being set, but that's not correct for the guest debugging
6450 * case. */
6451 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6452 vmx_set_interrupt_shadow(vcpu, 0);
6453
1811d979
WC		 6454 kvm_load_guest_xcr0(vcpu);
6455
5ad6ece8
SC		 6456 if (static_cpu_has(X86_FEATURE_PKU) &&
6457 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6458 vcpu->arch.pkru != vmx->host_pkru)
6459 __write_pkru(vcpu->arch.pkru);
6460
6461 pt_guest_enter(vmx);
6462
6463 atomic_switch_perf_msrs(vmx);
6464
804939ea
SC		 6465 if (enable_preemption_timer)
6466 vmx_update_hv_timer(vcpu);
5ad6ece8 6467
b6c4bc65
WL		 6468 if (lapic_in_kernel(vcpu) &&
6469 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6470 kvm_wait_lapic_expire(vcpu);
6471
5ad6ece8
SC		 6472 /*
6473 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6474 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6475 * is no need to worry about the conditional branch over the wrmsr
6476 * being speculatively taken.
6477 */
6478 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6479
fa4bff16 6480 /* L1D Flush includes CPU buffer clear to mitigate MDS */
c823dd5c
SC		 6481 if (static_branch_unlikely(&vmx_l1d_should_flush))
6482 vmx_l1d_flush(vcpu);
fa4bff16
LT		 6483 else if (static_branch_unlikely(&mds_user_clear))
6484 mds_clear_cpu_buffers();
c823dd5c
SC		 6485
6486 if (vcpu->arch.cr2 != read_cr2())
6487 write_cr2(vcpu->arch.cr2);
6488
fc2ba5a2
SC		 6489 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6490 vmx->loaded_vmcs->launched);
c823dd5c
SC		 6491
6492 vcpu->arch.cr2 = read_cr2();
b6b8a145 6493
55d2375e
SC		 6494 /*
6495 * We do not use IBRS in the kernel. If this vCPU has used the
6496 * SPEC_CTRL MSR it may have left it on; save the value and
6497 * turn it off. This is much more efficient than blindly adding
6498 * it to the atomic save/restore list. Especially as the former
6499 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6500 *
6501 * For non-nested case:
6502 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6503 * save it.
6504 *
6505 * For nested case:
6506 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6507 * save it.
6508 */
6509 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6510 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b6b8a145 6511
55d2375e 6512 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
d264ee0c 6513
55d2375e
SC		 6514 /* All fields are clean at this point */
6515 if (static_branch_unlikely(&enable_evmcs))
6516 current_evmcs->hv_clean_fields |=
6517 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
f4124500 6518
55d2375e
SC		 6519 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6520 if (vmx->host_debugctlmsr)
6521 update_debugctlmsr(vmx->host_debugctlmsr);
f4124500 6522
55d2375e
SC		 6523#ifndef CONFIG_X86_64
6524 /*
6525 * The sysexit path does not restore ds/es, so we must set them to
6526 * a reasonable value ourselves.
6527 *
6528 * We can't defer this to vmx_prepare_switch_to_host() since that
6529 * function may be executed in interrupt context, which saves and
6530 * restore segments around it, nullifying its effect.
6531 */
6532 loadsegment(ds, __USER_DS);
6533 loadsegment(es, __USER_DS);
6534#endif
4704d0be 6535
55d2375e
SC		 6536 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6537 | (1 << VCPU_EXREG_RFLAGS)
6538 | (1 << VCPU_EXREG_PDPTR)
6539 | (1 << VCPU_EXREG_SEGMENTS)
6540 | (1 << VCPU_EXREG_CR3));
6541 vcpu->arch.regs_dirty = 0;
7854cbca 6542
2ef444f1
CP		 6543 pt_guest_exit(vmx);
6544
3633cfc3 6545 /*
55d2375e
SC		 6546 * eager fpu is enabled if PKEY is supported and CR4 is switched
6547 * back on host, so it is safe to read guest PKRU from current
6548 * XSAVE.
3633cfc3 6549 */
55d2375e
SC		 6550 if (static_cpu_has(X86_FEATURE_PKU) &&
6551 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
c806e887 6552 vcpu->arch.pkru = rdpkru();
55d2375e
SC		 6553 if (vcpu->arch.pkru != vmx->host_pkru)
6554 __write_pkru(vmx->host_pkru);
3633cfc3
NHE		 6555 }
6556
1811d979
WC		 6557 kvm_put_guest_xcr0(vcpu);
6558
55d2375e
SC		 6559 vmx->nested.nested_run_pending = 0;
6560 vmx->idt_vectoring_info = 0;
119a9c01 6561
55d2375e 6562 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
beb8d93b
SC		 6563 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6564 kvm_machine_check();
6565
55d2375e
SC		 6566 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6567 return;
608406e2 6568
55d2375e
SC		 6569 vmx->loaded_vmcs->launched = 1;
6570 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
c18911a2 6571
55d2375e
SC		 6572 vmx_recover_nmi_blocking(vmx);
6573 vmx_complete_interrupts(vmx);
6574}
2996fca0 6575
55d2375e
SC		 6576static struct kvm *vmx_vm_alloc(void)
6577{
41836839
BG		 6578 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6579 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6580 PAGE_KERNEL);
55d2375e 6581 return &kvm_vmx->kvm;
cf8b84f4
JM		 6582}
6583
55d2375e
SC		 6584static void vmx_vm_free(struct kvm *kvm)
6585{
6586 vfree(to_kvm_vmx(kvm));
6587}
6588
6589static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
cf8b84f4 6590{
55d2375e 6591 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6592
55d2375e
SC		 6593 if (enable_pml)
6594 vmx_destroy_pml_buffer(vmx);
6595 free_vpid(vmx->vpid);
55d2375e
SC		 6596 nested_vmx_free_vcpu(vcpu);
6597 free_loaded_vmcs(vmx->loaded_vmcs);
6598 kfree(vmx->guest_msrs);
6599 kvm_vcpu_uninit(vcpu);
b666a4b6 6600 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
55d2375e
SC		 6601 kmem_cache_free(kvm_vcpu_cache, vmx);
6602}
4704d0be 6603
55d2375e
SC		 6604static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6605{
6606 int err;
41836839 6607 struct vcpu_vmx *vmx;
55d2375e
SC		 6608 unsigned long *msr_bitmap;
6609 int cpu;
7313c698 6610
41836839 6611 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6612 if (!vmx)
6613 return ERR_PTR(-ENOMEM);
4704d0be 6614
41836839
BG		 6615 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6616 GFP_KERNEL_ACCOUNT);
b666a4b6
MO		 6617 if (!vmx->vcpu.arch.guest_fpu) {
6618 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6619 err = -ENOMEM;
6620 goto free_partial_vcpu;
6621 }
6622
55d2375e 6623 vmx->vpid = allocate_vpid();
7cdc2d62 6624
55d2375e
SC		 6625 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6626 if (err)
6627 goto free_vcpu;
5f3d5799 6628
55d2375e 6629 err = -ENOMEM;
5f3d5799
JK		 6630
6631 /*
55d2375e
SC		 6632 * If PML is turned on, failure on enabling PML just results in failure
6633 * of creating the vcpu, therefore we can simplify PML logic (by
6634 * avoiding dealing with cases, such as enabling PML partially on vcpus
6635 * for the guest, etc.
5f3d5799 6636 */
55d2375e 6637 if (enable_pml) {
41836839 6638 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
55d2375e
SC		 6639 if (!vmx->pml_pg)
6640 goto uninit_vcpu;
6641 }
4704d0be 6642
41836839 6643 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
55d2375e
SC		 6644 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6645 > PAGE_SIZE);
21feb4eb 6646
55d2375e
SC		 6647 if (!vmx->guest_msrs)
6648 goto free_pml;
4704d0be 6649
55d2375e
SC		 6650 err = alloc_loaded_vmcs(&vmx->vmcs01);
6651 if (err < 0)
6652 goto free_msrs;
cb61de2f 6653
55d2375e 6654 msr_bitmap = vmx->vmcs01.msr_bitmap;
788fc1e9 6655 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
55d2375e
SC		 6656 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6657 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6658 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6659 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6660 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6661 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
b5170063
WL		 6662 if (kvm_cstate_in_guest(kvm)) {
6663 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6664 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6665 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6666 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6667 }
55d2375e 6668 vmx->msr_bitmap_mode = 0;
4704d0be 6669
55d2375e
SC		 6670 vmx->loaded_vmcs = &vmx->vmcs01;
6671 cpu = get_cpu();
6672 vmx_vcpu_load(&vmx->vcpu, cpu);
6673 vmx->vcpu.cpu = cpu;
6674 vmx_vcpu_setup(vmx);
6675 vmx_vcpu_put(&vmx->vcpu);
6676 put_cpu();
6677 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6678 err = alloc_apic_access_page(kvm);
6679 if (err)
6680 goto free_vmcs;
6681 }
6682
6683 if (enable_ept && !enable_unrestricted_guest) {
6684 err = init_rmode_identity_map(kvm);
6685 if (err)
6686 goto free_vmcs;
6687 }
4704d0be 6688
55d2375e
SC		 6689 if (nested)
6690 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6691 vmx_capability.ept,
6692 kvm_vcpu_apicv_active(&vmx->vcpu));
6693 else
6694 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
bd18bffc 6695
55d2375e
SC		 6696 vmx->nested.posted_intr_nv = -1;
6697 vmx->nested.current_vmptr = -1ull;
bd18bffc 6698
55d2375e 6699 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
feaf0c7d 6700
6f1e03bc 6701 /*
55d2375e
SC		 6702 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6703 * or POSTED_INTR_WAKEUP_VECTOR.
6f1e03bc 6704 */
55d2375e
SC		 6705 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6706 vmx->pi_desc.sn = 1;
4704d0be 6707
53963a70
LT		 6708 vmx->ept_pointer = INVALID_PAGE;
6709
55d2375e 6710 return &vmx->vcpu;
4704d0be 6711
55d2375e
SC		 6712free_vmcs:
6713 free_loaded_vmcs(vmx->loaded_vmcs);
6714free_msrs:
6715 kfree(vmx->guest_msrs);
6716free_pml:
6717 vmx_destroy_pml_buffer(vmx);
6718uninit_vcpu:
6719 kvm_vcpu_uninit(&vmx->vcpu);
6720free_vcpu:
6721 free_vpid(vmx->vpid);
b666a4b6
MO		 6722 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6723free_partial_vcpu:
55d2375e
SC		 6724 kmem_cache_free(kvm_vcpu_cache, vmx);
6725 return ERR_PTR(err);
6726}
36be0b9d 6727
65fd4cb6
TG		 6728#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6729#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
21feb4eb 6730
55d2375e
SC		 6731static int vmx_vm_init(struct kvm *kvm)
6732{
6733 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
ff651cb6 6734
55d2375e
SC		 6735 if (!ple_gap)
6736 kvm->arch.pause_in_guest = true;
3af18d9c 6737
55d2375e
SC		 6738 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6739 switch (l1tf_mitigation) {
6740 case L1TF_MITIGATION_OFF:
6741 case L1TF_MITIGATION_FLUSH_NOWARN:
6742 /* 'I explicitly don't care' is set */
6743 break;
6744 case L1TF_MITIGATION_FLUSH:
6745 case L1TF_MITIGATION_FLUSH_NOSMT:
6746 case L1TF_MITIGATION_FULL:
6747 /*
6748 * Warn upon starting the first VM in a potentially
6749 * insecure environment.
6750 */
b284909a 6751 if (sched_smt_active())
55d2375e
SC		 6752 pr_warn_once(L1TF_MSG_SMT);
6753 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6754 pr_warn_once(L1TF_MSG_L1D);
6755 break;
6756 case L1TF_MITIGATION_FULL_FORCE:
6757 /* Flush is enforced */
6758 break;
6759 }
6760 }
6761 return 0;
4704d0be
NHE		 6762}
6763
f257d6dc 6764static int __init vmx_check_processor_compat(void)
bd18bffc 6765{
55d2375e
SC		 6766 struct vmcs_config vmcs_conf;
6767 struct vmx_capability vmx_cap;
bd18bffc 6768
55d2375e 6769 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
f257d6dc 6770 return -EIO;
55d2375e
SC		 6771 if (nested)
6772 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6773 enable_apicv);
6774 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6775 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6776 smp_processor_id());
f257d6dc 6777 return -EIO;
bd18bffc 6778 }
f257d6dc 6779 return 0;
bd18bffc
SC		 6780}
6781
55d2375e 6782static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
bd18bffc 6783{
55d2375e
SC		 6784 u8 cache;
6785 u64 ipat = 0;
bd18bffc 6786
55d2375e
SC		 6787 /* For VT-d and EPT combination
6788 * 1. MMIO: always map as UC
6789 * 2. EPT with VT-d:
6790 * a. VT-d without snooping control feature: can't guarantee the
6791 * result, try to trust guest.
6792 * b. VT-d with snooping control feature: snooping control feature of
6793 * VT-d engine can guarantee the cache correctness. Just set it
6794 * to WB to keep consistent with host. So the same as item 3.
6795 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6796 * consistent with host MTRR
bd18bffc 6797 */
55d2375e
SC		 6798 if (is_mmio) {
6799 cache = MTRR_TYPE_UNCACHABLE;
6800 goto exit;
6801 }
bd18bffc 6802
55d2375e
SC		 6803 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6804 ipat = VMX_EPT_IPAT_BIT;
6805 cache = MTRR_TYPE_WRBACK;
6806 goto exit;
6807 }
bd18bffc 6808
55d2375e
SC		 6809 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6810 ipat = VMX_EPT_IPAT_BIT;
6811 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6812 cache = MTRR_TYPE_WRBACK;
6813 else
6814 cache = MTRR_TYPE_UNCACHABLE;
6815 goto exit;
6816 }
bd18bffc 6817
55d2375e 6818 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
bd18bffc 6819
55d2375e
SC		 6820exit:
6821 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6822}
bd18bffc 6823
55d2375e
SC		 6824static int vmx_get_lpage_level(void)
6825{
6826 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6827 return PT_DIRECTORY_LEVEL;
6828 else
6829 /* For shadow and EPT supported 1GB page */
6830 return PT_PDPE_LEVEL;
6831}
bd18bffc 6832
fe7f895d 6833static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
55d2375e 6834{
bd18bffc 6835 /*
55d2375e
SC		 6836 * These bits in the secondary execution controls field
6837 * are dynamic, the others are mostly based on the hypervisor
6838 * architecture and the guest's CPUID. Do not touch the
6839 * dynamic bits.
bd18bffc 6840 */
55d2375e
SC		 6841 u32 mask =
6842 SECONDARY_EXEC_SHADOW_VMCS |
6843 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6844 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6845 SECONDARY_EXEC_DESC;
bd18bffc 6846
fe7f895d
SC		 6847 u32 new_ctl = vmx->secondary_exec_control;
6848 u32 cur_ctl = secondary_exec_controls_get(vmx);
bd18bffc 6849
fe7f895d 6850 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
bd18bffc
SC		 6851}
6852
4704d0be 6853/*
55d2375e
SC		 6854 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6855 * (indicating "allowed-1") if they are supported in the guest's CPUID.
4704d0be 6856 */
55d2375e 6857static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
4704d0be
NHE		 6858{
6859 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6860 struct kvm_cpuid_entry2 *entry;
4704d0be 6861
55d2375e
SC		 6862 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6863 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
e79f245d 6864
55d2375e
SC		 6865#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6866 if (entry && (entry->_reg & (_cpuid_mask))) \
6867 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6868} while (0)
ff651cb6 6869
55d2375e
SC		 6870 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6871 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6872 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6873 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6874 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6875 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6876 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6877 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6878 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6879 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6880 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6881 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6882 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6883 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6884 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
61ada748 6885
55d2375e
SC		 6886 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6887 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6888 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6889 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6890 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6891 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
cf3215d9 6892
55d2375e
SC		 6893#undef cr4_fixed1_update
6894}
36c3cc42 6895
55d2375e
SC		 6896static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6897{
6898 struct vcpu_vmx *vmx = to_vmx(vcpu);
f459a707 6899
55d2375e
SC		 6900 if (kvm_mpx_supported()) {
6901 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
4704d0be 6902
55d2375e
SC		 6903 if (mpx_enabled) {
6904 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6905 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6906 } else {
6907 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6908 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6909 }
dccbfcf5 6910 }
55d2375e 6911}
4704d0be 6912
6c0f0bba
LK		 6913static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6914{
6915 struct vcpu_vmx *vmx = to_vmx(vcpu);
6916 struct kvm_cpuid_entry2 *best = NULL;
6917 int i;
6918
6919 for (i = 0; i < PT_CPUID_LEAVES; i++) {
6920 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6921 if (!best)
6922 return;
6923 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6924 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6925 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6926 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
6927 }
6928
6929 /* Get the number of configurable Address Ranges for filtering */
6930 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
6931 PT_CAP_num_address_ranges);
6932
6933 /* Initialize and clear the no dependency bits */
6934 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
6935 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
6936
6937 /*
6938 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
6939 * will inject an #GP
6940 */
6941 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
6942 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
6943
6944 /*
6945 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
6946 * PSBFreq can be set
6947 */
6948 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
6949 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
6950 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
6951
6952 /*
6953 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
6954 * MTCFreq can be set
6955 */
6956 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
6957 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
6958 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
6959
6960 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
6961 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
6962 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
6963 RTIT_CTL_PTW_EN);
6964
6965 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
6966 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
6967 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
6968
6969 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
6970 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
6971 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
6972
6973 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
6974 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
6975 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
6976
6977 /* unmask address range configure area */
6978 for (i = 0; i < vmx->pt_desc.addr_range; i++)
d14eff1b 6979 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6c0f0bba
LK		 6980}
6981
55d2375e
SC		 6982static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6983{
6984 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6985
55d2375e
SC		 6986 if (cpu_has_secondary_exec_ctrls()) {
6987 vmx_compute_secondary_exec_control(vmx);
fe7f895d 6988 vmcs_set_secondary_exec_control(vmx);
705699a1 6989 }
4704d0be 6990
55d2375e
SC		 6991 if (nested_vmx_allowed(vcpu))
6992 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
6993 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6994 else
6995 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
6996 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4f350c6d 6997
55d2375e
SC		 6998 if (nested_vmx_allowed(vcpu)) {
6999 nested_vmx_cr_fixed1_bits_update(vcpu);
7000 nested_vmx_entry_exit_ctls_update(vcpu);
4f350c6d 7001 }
6c0f0bba
LK		 7002
7003 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7004 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7005 update_intel_pt_cfg(vcpu);
55d2375e 7006}
09abb5e3 7007
55d2375e
SC		 7008static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7009{
7010 if (func == 1 && nested)
7011 entry->ecx |= bit(X86_FEATURE_VMX);
4704d0be
NHE		 7012}
7013
55d2375e 7014static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
42124925 7015{
55d2375e 7016 to_vmx(vcpu)->req_immediate_exit = true;
7c177938
NHE		 7017}
7018
8a76d7f2
JR		 7019static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7020 struct x86_instruction_info *info,
7021 enum x86_intercept_stage stage)
7022{
fb6d4d34
PB		 7023 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7024 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7025
7026 /*
7027 * RDPID causes #UD if disabled through secondary execution controls.
7028 * Because it is marked as EmulateOnUD, we need to intercept it here.
7029 */
7030 if (info->intercept == x86_intercept_rdtscp &&
7031 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7032 ctxt->exception.vector = UD_VECTOR;
7033 ctxt->exception.error_code_valid = false;
7034 return X86EMUL_PROPAGATE_FAULT;
7035 }
7036
7037 /* TODO: check more intercepts... */
8a76d7f2
JR		 7038 return X86EMUL_CONTINUE;
7039}
7040
64672c95
YJ		 7041#ifdef CONFIG_X86_64
7042/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7043static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7044 u64 divisor, u64 *result)
7045{
7046 u64 low = a << shift, high = a >> (64 - shift);
7047
7048 /* To avoid the overflow on divq */
7049 if (high >= divisor)
7050 return 1;
7051
7052 /* Low hold the result, high hold rem which is discarded */
7053 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7054 "rm" (divisor), "0" (low), "1" (high));
7055 *result = low;
7056
7057 return 0;
7058}
7059
f9927982
SC		 7060static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7061 bool *expired)
64672c95 7062{
386c6ddb 7063 struct vcpu_vmx *vmx;
c5ce8235 7064 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
39497d76 7065 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
386c6ddb 7066
0c5f81da
WL		 7067 if (kvm_mwait_in_guest(vcpu->kvm) ||
7068 kvm_can_post_timer_interrupt(vcpu))
386c6ddb
KA		 7069 return -EOPNOTSUPP;
7070
7071 vmx = to_vmx(vcpu);
7072 tscl = rdtsc();
7073 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7074 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
39497d76
SC		 7075 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7076 ktimer->timer_advance_ns);
c5ce8235
WL		 7077
7078 if (delta_tsc > lapic_timer_advance_cycles)
7079 delta_tsc -= lapic_timer_advance_cycles;
7080 else
7081 delta_tsc = 0;
64672c95
YJ		 7082
7083 /* Convert to host delta tsc if tsc scaling is enabled */
7084 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
0967fa1c 7085 delta_tsc && u64_shl_div_u64(delta_tsc,
64672c95 7086 kvm_tsc_scaling_ratio_frac_bits,
0967fa1c 7087 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
64672c95
YJ		 7088 return -ERANGE;
7089
7090 /*
7091 * If the delta tsc can't fit in the 32 bit after the multi shift,
7092 * we can't use the preemption timer.
7093 * It's possible that it fits on later vmentries, but checking
7094 * on every vmentry is costly so we just use an hrtimer.
7095 */
7096 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7097 return -ERANGE;
7098
7099 vmx->hv_deadline_tsc = tscl + delta_tsc;
f9927982
SC		 7100 *expired = !delta_tsc;
7101 return 0;
64672c95
YJ		 7102}
7103
7104static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7105{
f459a707 7106 to_vmx(vcpu)->hv_deadline_tsc = -1;
64672c95
YJ		 7107}
7108#endif
7109
48d89b92 7110static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 7111{
b31c114b 7112 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d 7113 shrink_ple_window(vcpu);
ae97a3b8
RK		 7114}
7115
843e4330
KH		 7116static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7117 struct kvm_memory_slot *slot)
7118{
7119 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7120 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7121}
7122
7123static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7124 struct kvm_memory_slot *slot)
7125{
7126 kvm_mmu_slot_set_dirty(kvm, slot);
7127}
7128
7129static void vmx_flush_log_dirty(struct kvm *kvm)
7130{
7131 kvm_flush_pml_buffers(kvm);
7132}
7133
c5f983f6
BD		 7134static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7135{
7136 struct vmcs12 *vmcs12;
7137 struct vcpu_vmx *vmx = to_vmx(vcpu);
3d5f6beb 7138 gpa_t gpa, dst;
c5f983f6
BD		 7139
7140 if (is_guest_mode(vcpu)) {
7141 WARN_ON_ONCE(vmx->nested.pml_full);
7142
7143 /*
7144 * Check if PML is enabled for the nested guest.
7145 * Whether eptp bit 6 is set is already checked
7146 * as part of A/D emulation.
7147 */
7148 vmcs12 = get_vmcs12(vcpu);
7149 if (!nested_cpu_has_pml(vmcs12))
7150 return 0;
7151
4769886b 7152 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD		 7153 vmx->nested.pml_full = true;
7154 return 1;
7155 }
7156
7157 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
3d5f6beb 7158 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
c5f983f6 7159
3d5f6beb
KA		 7160 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7161 offset_in_page(dst), sizeof(gpa)))
c5f983f6
BD		 7162 return 0;
7163
3d5f6beb 7164 vmcs12->guest_pml_index--;
c5f983f6
BD		 7165 }
7166
7167 return 0;
7168}
7169
843e4330
KH		 7170static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7171 struct kvm_memory_slot *memslot,
7172 gfn_t offset, unsigned long mask)
7173{
7174 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7175}
7176
cd39e117
PB		 7177static void __pi_post_block(struct kvm_vcpu *vcpu)
7178{
7179 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7180 struct pi_desc old, new;
7181 unsigned int dest;
cd39e117
PB		 7182
7183 do {
7184 old.control = new.control = pi_desc->control;
8b306e2f
PB		 7185 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7186 "Wakeup handler not enabled while the VCPU is blocked\n");
cd39e117
PB		 7187
7188 dest = cpu_physical_id(vcpu->cpu);
7189
7190 if (x2apic_enabled())
7191 new.ndst = dest;
7192 else
7193 new.ndst = (dest << 8) & 0xFF00;
7194
cd39e117
PB		 7195 /* set 'NV' to 'notification vector' */
7196 new.nv = POSTED_INTR_VECTOR;
c0a1666b
PB		 7197 } while (cmpxchg64(&pi_desc->control, old.control,
7198 new.control) != old.control);
cd39e117 7199
8b306e2f
PB		 7200 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7201 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117 7202 list_del(&vcpu->blocked_vcpu_list);
8b306e2f 7203 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117
PB		 7204 vcpu->pre_pcpu = -1;
7205 }
7206}
7207
bf9f6ac8
FW		 7208/*
7209 * This routine does the following things for vCPU which is going
7210 * to be blocked if VT-d PI is enabled.
7211 * - Store the vCPU to the wakeup list, so when interrupts happen
7212 * we can find the right vCPU to wake up.
7213 * - Change the Posted-interrupt descriptor as below:
7214 * 'NDST' <-- vcpu->pre_pcpu
7215 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7216 * - If 'ON' is set during this process, which means at least one
7217 * interrupt is posted for this vCPU, we cannot block it, in
7218 * this case, return 1, otherwise, return 0.
7219 *
7220 */
bc22512b 7221static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7222{
bf9f6ac8
FW		 7223 unsigned int dest;
7224 struct pi_desc old, new;
7225 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7226
7227 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 7228 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7229 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 7230 return 0;
7231
8b306e2f
PB		 7232 WARN_ON(irqs_disabled());
7233 local_irq_disable();
7234 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7235 vcpu->pre_pcpu = vcpu->cpu;
7236 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7237 list_add_tail(&vcpu->blocked_vcpu_list,
7238 &per_cpu(blocked_vcpu_on_cpu,
7239 vcpu->pre_pcpu));
7240 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7241 }
bf9f6ac8
FW		 7242
7243 do {
7244 old.control = new.control = pi_desc->control;
7245
bf9f6ac8
FW		 7246 WARN((pi_desc->sn == 1),
7247 "Warning: SN field of posted-interrupts "
7248 "is set before blocking\n");
7249
7250 /*
7251 * Since vCPU can be preempted during this process,
7252 * vcpu->cpu could be different with pre_pcpu, we
7253 * need to set pre_pcpu as the destination of wakeup
7254 * notification event, then we can find the right vCPU
7255 * to wakeup in wakeup handler if interrupts happen
7256 * when the vCPU is in blocked state.
7257 */
7258 dest = cpu_physical_id(vcpu->pre_pcpu);
7259
7260 if (x2apic_enabled())
7261 new.ndst = dest;
7262 else
7263 new.ndst = (dest << 8) & 0xFF00;
7264
7265 /* set 'NV' to 'wakeup vector' */
7266 new.nv = POSTED_INTR_WAKEUP_VECTOR;
c0a1666b
PB		 7267 } while (cmpxchg64(&pi_desc->control, old.control,
7268 new.control) != old.control);
bf9f6ac8 7269
8b306e2f
PB		 7270 /* We should not block the vCPU if an interrupt is posted for it. */
7271 if (pi_test_on(pi_desc) == 1)
7272 __pi_post_block(vcpu);
7273
7274 local_irq_enable();
7275 return (vcpu->pre_pcpu == -1);
bf9f6ac8
FW		 7276}
7277
bc22512b
YJ		 7278static int vmx_pre_block(struct kvm_vcpu *vcpu)
7279{
7280 if (pi_pre_block(vcpu))
7281 return 1;
7282
64672c95
YJ		 7283 if (kvm_lapic_hv_timer_in_use(vcpu))
7284 kvm_lapic_switch_to_sw_timer(vcpu);
7285
bc22512b
YJ		 7286 return 0;
7287}
7288
7289static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8 7290{
8b306e2f 7291 if (vcpu->pre_pcpu == -1)
bf9f6ac8
FW		 7292 return;
7293
8b306e2f
PB		 7294 WARN_ON(irqs_disabled());
7295 local_irq_disable();
cd39e117 7296 __pi_post_block(vcpu);
8b306e2f 7297 local_irq_enable();
bf9f6ac8
FW		 7298}
7299
bc22512b
YJ		 7300static void vmx_post_block(struct kvm_vcpu *vcpu)
7301{
64672c95
YJ		 7302 if (kvm_x86_ops->set_hv_timer)
7303 kvm_lapic_switch_to_hv_timer(vcpu);
7304
bc22512b
YJ		 7305 pi_post_block(vcpu);
7306}
7307
efc64404
FW		 7308/*
7309 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7310 *
7311 * @kvm: kvm
7312 * @host_irq: host irq of the interrupt
7313 * @guest_irq: gsi of the interrupt
7314 * @set: set or unset PI
7315 * returns 0 on success, < 0 on failure
7316 */
7317static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7318 uint32_t guest_irq, bool set)
7319{
7320 struct kvm_kernel_irq_routing_entry *e;
7321 struct kvm_irq_routing_table *irq_rt;
7322 struct kvm_lapic_irq irq;
7323 struct kvm_vcpu *vcpu;
7324 struct vcpu_data vcpu_info;
3a8b0677 7325 int idx, ret = 0;
efc64404
FW		 7326
7327 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 7328 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7329 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 7330 return 0;
7331
7332 idx = srcu_read_lock(&kvm->irq_srcu);
7333 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
3a8b0677
JS		 7334 if (guest_irq >= irq_rt->nr_rt_entries ||
7335 hlist_empty(&irq_rt->map[guest_irq])) {
7336 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7337 guest_irq, irq_rt->nr_rt_entries);
7338 goto out;
7339 }
efc64404
FW		 7340
7341 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7342 if (e->type != KVM_IRQ_ROUTING_MSI)
7343 continue;
7344 /*
7345 * VT-d PI cannot support posting multicast/broadcast
7346 * interrupts to a vCPU, we still use interrupt remapping
7347 * for these kind of interrupts.
7348 *
7349 * For lowest-priority interrupts, we only support
7350 * those with single CPU as the destination, e.g. user
7351 * configures the interrupts via /proc/irq or uses
7352 * irqbalance to make the interrupts single-CPU.
7353 *
7354 * We will support full lowest-priority interrupt later.
7355 */
7356
37131313 7357 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW		 7358 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
7359 /*
7360 * Make sure the IRTE is in remapped mode if
7361 * we don't handle it in posted mode.
7362 */
7363 ret = irq_set_vcpu_affinity(host_irq, NULL);
7364 if (ret < 0) {
7365 printk(KERN_INFO
7366 "failed to back to remapped mode, irq: %u\n",
7367 host_irq);
7368 goto out;
7369 }
7370
efc64404 7371 continue;
23a1c257 7372 }
efc64404
FW		 7373
7374 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7375 vcpu_info.vector = irq.vector;
7376
2698d82e 7377 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
efc64404
FW		 7378 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7379
7380 if (set)
7381 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
dc91f2eb 7382 else
efc64404 7383 ret = irq_set_vcpu_affinity(host_irq, NULL);
efc64404
FW		 7384
7385 if (ret < 0) {
7386 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7387 __func__);
7388 goto out;
7389 }
7390 }
7391
7392 ret = 0;
7393out:
7394 srcu_read_unlock(&kvm->irq_srcu, idx);
7395 return ret;
7396}
7397
c45dcc71
AR		 7398static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7399{
7400 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7401 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7402 FEATURE_CONTROL_LMCE;
7403 else
7404 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7405 ~FEATURE_CONTROL_LMCE;
7406}
7407
72d7b374
LP		 7408static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7409{
72e9cbdb
LP		 7410 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7411 if (to_vmx(vcpu)->nested.nested_run_pending)
7412 return 0;
72d7b374
LP		 7413 return 1;
7414}
7415
0234bf88
LP		 7416static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7417{
72e9cbdb
LP		 7418 struct vcpu_vmx *vmx = to_vmx(vcpu);
7419
7420 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7421 if (vmx->nested.smm.guest_mode)
7422 nested_vmx_vmexit(vcpu, -1, 0, 0);
7423
7424 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7425 vmx->nested.vmxon = false;
caa057a2 7426 vmx_clear_hlt(vcpu);
0234bf88
LP		 7427 return 0;
7428}
7429
ed19321f 7430static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 7431{
72e9cbdb
LP		 7432 struct vcpu_vmx *vmx = to_vmx(vcpu);
7433 int ret;
7434
7435 if (vmx->nested.smm.vmxon) {
7436 vmx->nested.vmxon = true;
7437 vmx->nested.smm.vmxon = false;
7438 }
7439
7440 if (vmx->nested.smm.guest_mode) {
a633e41e 7441 ret = nested_vmx_enter_non_root_mode(vcpu, false);
72e9cbdb
LP		 7442 if (ret)
7443 return ret;
7444
7445 vmx->nested.smm.guest_mode = false;
7446 }
0234bf88
LP		 7447 return 0;
7448}
7449
cc3d967f
LP		 7450static int enable_smi_window(struct kvm_vcpu *vcpu)
7451{
7452 return 0;
7453}
7454
05d5a486
SB		 7455static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7456{
9481b7f1 7457 return false;
05d5a486
SB		 7458}
7459
a3203381
SC		 7460static __init int hardware_setup(void)
7461{
7462 unsigned long host_bndcfgs;
2342080c 7463 struct desc_ptr dt;
a3203381
SC		 7464 int r, i;
7465
7466 rdmsrl_safe(MSR_EFER, &host_efer);
7467
2342080c
SC		 7468 store_idt(&dt);
7469 host_idt_base = dt.address;
7470
a3203381
SC		 7471 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7472 kvm_define_shared_msr(i, vmx_msr_index[i]);
7473
7474 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7475 return -EIO;
7476
7477 if (boot_cpu_has(X86_FEATURE_NX))
7478 kvm_enable_efer_bits(EFER_NX);
7479
7480 if (boot_cpu_has(X86_FEATURE_MPX)) {
7481 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7482 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7483 }
7484
7485 if (boot_cpu_has(X86_FEATURE_XSAVES))
7486 rdmsrl(MSR_IA32_XSS, host_xss);
7487
7488 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7489 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7490 enable_vpid = 0;
7491
7492 if (!cpu_has_vmx_ept() ||
7493 !cpu_has_vmx_ept_4levels() ||
7494 !cpu_has_vmx_ept_mt_wb() ||
7495 !cpu_has_vmx_invept_global())
7496 enable_ept = 0;
7497
7498 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7499 enable_ept_ad_bits = 0;
7500
7501 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7502 enable_unrestricted_guest = 0;
7503
7504 if (!cpu_has_vmx_flexpriority())
7505 flexpriority_enabled = 0;
7506
7507 if (!cpu_has_virtual_nmis())
7508 enable_vnmi = 0;
7509
7510 /*
7511 * set_apic_access_page_addr() is used to reload apic access
7512 * page upon invalidation. No need to do anything if not
7513 * using the APIC_ACCESS_ADDR VMCS field.
7514 */
7515 if (!flexpriority_enabled)
7516 kvm_x86_ops->set_apic_access_page_addr = NULL;
7517
7518 if (!cpu_has_vmx_tpr_shadow())
7519 kvm_x86_ops->update_cr8_intercept = NULL;
7520
7521 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7522 kvm_disable_largepages();
7523
7524#if IS_ENABLED(CONFIG_HYPERV)
7525 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
1f3a3e46
LT		 7526 && enable_ept) {
7527 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7528 kvm_x86_ops->tlb_remote_flush_with_range =
7529 hv_remote_flush_tlb_with_range;
7530 }
a3203381
SC		 7531#endif
7532
7533 if (!cpu_has_vmx_ple()) {
7534 ple_gap = 0;
7535 ple_window = 0;
7536 ple_window_grow = 0;
7537 ple_window_max = 0;
7538 ple_window_shrink = 0;
7539 }
7540
7541 if (!cpu_has_vmx_apicv()) {
7542 enable_apicv = 0;
7543 kvm_x86_ops->sync_pir_to_irr = NULL;
7544 }
7545
7546 if (cpu_has_vmx_tsc_scaling()) {
7547 kvm_has_tsc_control = true;
7548 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7549 kvm_tsc_scaling_ratio_frac_bits = 48;
7550 }
7551
7552 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7553
7554 if (enable_ept)
7555 vmx_enable_tdp();
7556 else
7557 kvm_disable_tdp();
7558
a3203381
SC		 7559 /*
7560 * Only enable PML when hardware supports PML feature, and both EPT
7561 * and EPT A/D bit features are enabled -- PML depends on them to work.
7562 */
7563 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7564 enable_pml = 0;
7565
7566 if (!enable_pml) {
7567 kvm_x86_ops->slot_enable_log_dirty = NULL;
7568 kvm_x86_ops->slot_disable_log_dirty = NULL;
7569 kvm_x86_ops->flush_log_dirty = NULL;
7570 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7571 }
7572
7573 if (!cpu_has_vmx_preemption_timer())
804939ea 7574 enable_preemption_timer = false;
a3203381 7575
804939ea
SC		 7576 if (enable_preemption_timer) {
7577 u64 use_timer_freq = 5000ULL * 1000 * 1000;
a3203381
SC		 7578 u64 vmx_msr;
7579
7580 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7581 cpu_preemption_timer_multi =
7582 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
804939ea
SC		 7583
7584 if (tsc_khz)
7585 use_timer_freq = (u64)tsc_khz * 1000;
7586 use_timer_freq >>= cpu_preemption_timer_multi;
7587
7588 /*
7589 * KVM "disables" the preemption timer by setting it to its max
7590 * value. Don't use the timer if it might cause spurious exits
7591 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7592 */
7593 if (use_timer_freq > 0xffffffffu / 10)
7594 enable_preemption_timer = false;
7595 }
7596
7597 if (!enable_preemption_timer) {
a3203381
SC		 7598 kvm_x86_ops->set_hv_timer = NULL;
7599 kvm_x86_ops->cancel_hv_timer = NULL;
804939ea 7600 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
a3203381
SC		 7601 }
7602
a3203381 7603 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
a3203381
SC		 7604
7605 kvm_mce_cap_supported |= MCG_LMCE_P;
7606
f99e3daf
CP		 7607 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7608 return -EINVAL;
7609 if (!enable_ept || !cpu_has_vmx_intel_pt())
7610 pt_mode = PT_MODE_SYSTEM;
7611
a3203381 7612 if (nested) {
3e8eaccc
SC		 7613 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7614 vmx_capability.ept, enable_apicv);
7615
e4027cfa 7616 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
a3203381
SC		 7617 if (r)
7618 return r;
7619 }
7620
7621 r = alloc_kvm_area();
7622 if (r)
7623 nested_vmx_hardware_unsetup();
7624 return r;
7625}
7626
7627static __exit void hardware_unsetup(void)
7628{
7629 if (nested)
7630 nested_vmx_hardware_unsetup();
7631
7632 free_kvm_area();
7633}
7634
404f6aac 7635static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 7636 .cpu_has_kvm_support = cpu_has_kvm_support,
7637 .disabled_by_bios = vmx_disabled_by_bios,
7638 .hardware_setup = hardware_setup,
7639 .hardware_unsetup = hardware_unsetup,
002c7f7c 7640 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7641 .hardware_enable = hardware_enable,
7642 .hardware_disable = hardware_disable,
04547156 7643 .cpu_has_accelerated_tpr = report_flexpriority,
bc226f07 7644 .has_emulated_msr = vmx_has_emulated_msr,
6aa8b732 7645
b31c114b 7646 .vm_init = vmx_vm_init,
434a1e94
SC		 7647 .vm_alloc = vmx_vm_alloc,
7648 .vm_free = vmx_vm_free,
b31c114b 7649
6aa8b732
AK		 7650 .vcpu_create = vmx_create_vcpu,
7651 .vcpu_free = vmx_free_vcpu,
04d2cc77 7652 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7653
6d6095bd 7654 .prepare_guest_switch = vmx_prepare_switch_to_guest,
6aa8b732
AK		 7655 .vcpu_load = vmx_vcpu_load,
7656 .vcpu_put = vmx_vcpu_put,
7657
a96036b8 7658 .update_bp_intercept = update_exception_bitmap,
801e459a 7659 .get_msr_feature = vmx_get_msr_feature,
6aa8b732
AK		 7660 .get_msr = vmx_get_msr,
7661 .set_msr = vmx_set_msr,
7662 .get_segment_base = vmx_get_segment_base,
7663 .get_segment = vmx_get_segment,
7664 .set_segment = vmx_set_segment,
2e4d2653 7665 .get_cpl = vmx_get_cpl,
6aa8b732 7666 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7667 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7668 .decache_cr3 = vmx_decache_cr3,
25c4c276 7669 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7670 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7671 .set_cr3 = vmx_set_cr3,
7672 .set_cr4 = vmx_set_cr4,
6aa8b732 7673 .set_efer = vmx_set_efer,
6aa8b732
AK		 7674 .get_idt = vmx_get_idt,
7675 .set_idt = vmx_set_idt,
7676 .get_gdt = vmx_get_gdt,
7677 .set_gdt = vmx_set_gdt,
73aaf249
JK		 7678 .get_dr6 = vmx_get_dr6,
7679 .set_dr6 = vmx_set_dr6,
020df079 7680 .set_dr7 = vmx_set_dr7,
81908bf4 7681 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 7682 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7683 .get_rflags = vmx_get_rflags,
7684 .set_rflags = vmx_set_rflags,
be94f6b7 7685
6aa8b732 7686 .tlb_flush = vmx_flush_tlb,
faff8758 7687 .tlb_flush_gva = vmx_flush_tlb_gva,
6aa8b732 7688
6aa8b732 7689 .run = vmx_vcpu_run,
6062d012 7690 .handle_exit = vmx_handle_exit,
6aa8b732 7691 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7692 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7693 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7694 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7695 .set_irq = vmx_inject_irq,
95ba8273 7696 .set_nmi = vmx_inject_nmi,
298101da 7697 .queue_exception = vmx_queue_exception,
b463a6f7 7698 .cancel_injection = vmx_cancel_injection,
78646121 7699 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7700 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7701 .get_nmi_mask = vmx_get_nmi_mask,
7702 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7703 .enable_nmi_window = enable_nmi_window,
7704 .enable_irq_window = enable_irq_window,
7705 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 7706 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
38b99173 7707 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS		 7708 .get_enable_apicv = vmx_get_enable_apicv,
7709 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 7710 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 7711 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ		 7712 .hwapic_irr_update = vmx_hwapic_irr_update,
7713 .hwapic_isr_update = vmx_hwapic_isr_update,
e6c67d8c 7714 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
a20ed54d
YZ		 7715 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7716 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 7717
cbc94022 7718 .set_tss_addr = vmx_set_tss_addr,
2ac52ab8 7719 .set_identity_map_addr = vmx_set_identity_map_addr,
67253af5 7720 .get_tdp_level = get_ept_level,
4b12f0de 7721 .get_mt_mask = vmx_get_mt_mask,
229456fc 7722
586f9607 7723 .get_exit_info = vmx_get_exit_info,
586f9607 7724
17cc3935 7725 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7726
7727 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7728
7729 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7730 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7731
7732 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7733
7734 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7735
e79f245d 7736 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
326e7425 7737 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
1c97f0a0
JR		 7738
7739 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7740
7741 .check_intercept = vmx_check_intercept,
95b5a48c 7742 .handle_exit_irqoff = vmx_handle_exit_irqoff,
da8999d3 7743 .mpx_supported = vmx_mpx_supported,
55412b2e 7744 .xsaves_supported = vmx_xsaves_supported,
66336cab 7745 .umip_emulated = vmx_umip_emulated,
86f5201d 7746 .pt_supported = vmx_pt_supported,
b6b8a145 7747
d264ee0c 7748 .request_immediate_exit = vmx_request_immediate_exit,
ae97a3b8
RK		 7749
7750 .sched_in = vmx_sched_in,
843e4330
KH		 7751
7752 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7753 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7754 .flush_log_dirty = vmx_flush_log_dirty,
7755 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 7756 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 7757
bf9f6ac8
FW		 7758 .pre_block = vmx_pre_block,
7759 .post_block = vmx_post_block,
7760
25462f7f 7761 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 7762
7763 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 7764
7765#ifdef CONFIG_X86_64
7766 .set_hv_timer = vmx_set_hv_timer,
7767 .cancel_hv_timer = vmx_cancel_hv_timer,
7768#endif
c45dcc71
AR		 7769
7770 .setup_mce = vmx_setup_mce,
0234bf88 7771
72d7b374 7772 .smi_allowed = vmx_smi_allowed,
0234bf88
LP		 7773 .pre_enter_smm = vmx_pre_enter_smm,
7774 .pre_leave_smm = vmx_pre_leave_smm,
cc3d967f 7775 .enable_smi_window = enable_smi_window,
57b119da 7776
e4027cfa
SC		 7777 .check_nested_events = NULL,
7778 .get_nested_state = NULL,
7779 .set_nested_state = NULL,
7780 .get_vmcs12_pages = NULL,
7781 .nested_enable_evmcs = NULL,
05d5a486 7782 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
6aa8b732
AK		 7783};
7784
72c6d2db 7785static void vmx_cleanup_l1d_flush(void)
a47dd5f0
PB		 7786{
7787 if (vmx_l1d_flush_pages) {
7788 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7789 vmx_l1d_flush_pages = NULL;
7790 }
72c6d2db
TG		 7791 /* Restore state so sysfs ignores VMX */
7792 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 7793}
7794
a7b9020b
TG		 7795static void vmx_exit(void)
7796{
7797#ifdef CONFIG_KEXEC_CORE
7798 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7799 synchronize_rcu();
7800#endif
7801
7802 kvm_exit();
7803
7804#if IS_ENABLED(CONFIG_HYPERV)
7805 if (static_branch_unlikely(&enable_evmcs)) {
7806 int cpu;
7807 struct hv_vp_assist_page *vp_ap;
7808 /*
7809 * Reset everything to support using non-enlightened VMCS
7810 * access later (e.g. when we reload the module with
7811 * enlightened_vmcs=0)
7812 */
7813 for_each_online_cpu(cpu) {
7814 vp_ap = hv_get_vp_assist_page(cpu);
7815
7816 if (!vp_ap)
7817 continue;
7818
7819 vp_ap->current_nested_vmcs = 0;
7820 vp_ap->enlighten_vmentry = 0;
7821 }
7822
7823 static_branch_disable(&enable_evmcs);
7824 }
7825#endif
7826 vmx_cleanup_l1d_flush();
7827}
7828module_exit(vmx_exit);
7829
6aa8b732
AK		 7830static int __init vmx_init(void)
7831{
773e8a04
VK		 7832 int r;
7833
7834#if IS_ENABLED(CONFIG_HYPERV)
7835 /*
7836 * Enlightened VMCS usage should be recommended and the host needs
7837 * to support eVMCS v1 or above. We can also disable eVMCS support
7838 * with module parameter.
7839 */
7840 if (enlightened_vmcs &&
7841 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7842 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7843 KVM_EVMCS_VERSION) {
7844 int cpu;
7845
7846 /* Check that we have assist pages on all online CPUs */
7847 for_each_online_cpu(cpu) {
7848 if (!hv_get_vp_assist_page(cpu)) {
7849 enlightened_vmcs = false;
7850 break;
7851 }
7852 }
7853
7854 if (enlightened_vmcs) {
7855 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7856 static_branch_enable(&enable_evmcs);
7857 }
7858 } else {
7859 enlightened_vmcs = false;
7860 }
7861#endif
7862
7863 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
a7b9020b 7864 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7865 if (r)
34a1cd60 7866 return r;
25c5f225 7867
a7b9020b 7868 /*
7db92e16
TG		 7869 * Must be called after kvm_init() so enable_ept is properly set
7870 * up. Hand the parameter mitigation value in which was stored in
7871 * the pre module init parser. If no parameter was given, it will
7872 * contain 'auto' which will be turned into the default 'cond'
7873 * mitigation mode.
7874 */
7875 if (boot_cpu_has(X86_BUG_L1TF)) {
7876 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7877 if (r) {
7878 vmx_exit();
7879 return r;
7880 }
a47dd5f0 7881 }
25c5f225 7882
2965faa5 7883#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 7884 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7885 crash_vmclear_local_loaded_vmcss);
7886#endif
21ebf53b 7887 vmx_check_vmcs12_offsets();
8f536b76 7888
fdef3ad1 7889 return 0;
6aa8b732 7890}
a7b9020b 7891module_init(vmx_init);
Linux 6.x block layer and io_uring tree(s)