[linux-2.6-block.git] / arch / x86 / kvm / pmu_amd.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * KVM PMU support for AMD
 *
 * Copyright 2015, Red Hat, Inc. and/or its affiliates.
 *
 * Author:
 *   Wei Huang <wei@redhat.com>
 *
 * Implementation is based on pmu_intel.c file
 */
#include <linux/types.h>
#include <linux/kvm_host.h>
#include <linux/perf_event.h>
#include "x86.h"
#include "cpuid.h"
#include "lapic.h"
#include "pmu.h"

enum pmu_type {
	PMU_TYPE_COUNTER = 0,
	PMU_TYPE_EVNTSEL,
};

enum index {
	INDEX_ZERO = 0,
	INDEX_ONE,
	INDEX_TWO,
	INDEX_THREE,
	INDEX_FOUR,
	INDEX_FIVE,
	INDEX_ERROR,
};

/* duplicated from amd_perfmon_event_map, K7 and above should work. */
static struct kvm_event_hw_type_mapping amd_event_mapping[] = {
	[0] = { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES },
	[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
	[2] = { 0x7d, 0x07, PERF_COUNT_HW_CACHE_REFERENCES },
	[3] = { 0x7e, 0x07, PERF_COUNT_HW_CACHE_MISSES },
	[4] = { 0xc2, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
	[5] = { 0xc3, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
	[6] = { 0xd0, 0x00, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND },
	[7] = { 0xd1, 0x00, PERF_COUNT_HW_STALLED_CYCLES_BACKEND },
};

static unsigned int get_msr_base(struct kvm_pmu *pmu, enum pmu_type type)
{
	struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);

	if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) {
		if (type == PMU_TYPE_COUNTER)
			return MSR_F15H_PERF_CTR;
		else
			return MSR_F15H_PERF_CTL;
	} else {
		if (type == PMU_TYPE_COUNTER)
			return MSR_K7_PERFCTR0;
		else
			return MSR_K7_EVNTSEL0;
	}
}

static enum index msr_to_index(u32 msr)
{
	switch (msr) {
	case MSR_F15H_PERF_CTL0:
	case MSR_F15H_PERF_CTR0:
	case MSR_K7_EVNTSEL0:
	case MSR_K7_PERFCTR0:
		return INDEX_ZERO;
	case MSR_F15H_PERF_CTL1:
	case MSR_F15H_PERF_CTR1:
	case MSR_K7_EVNTSEL1:
	case MSR_K7_PERFCTR1:
		return INDEX_ONE;
	case MSR_F15H_PERF_CTL2:
	case MSR_F15H_PERF_CTR2:
	case MSR_K7_EVNTSEL2:
	case MSR_K7_PERFCTR2:
		return INDEX_TWO;
	case MSR_F15H_PERF_CTL3:
	case MSR_F15H_PERF_CTR3:
	case MSR_K7_EVNTSEL3:
	case MSR_K7_PERFCTR3:
		return INDEX_THREE;
	case MSR_F15H_PERF_CTL4:
	case MSR_F15H_PERF_CTR4:
		return INDEX_FOUR;
	case MSR_F15H_PERF_CTL5:
	case MSR_F15H_PERF_CTR5:
		return INDEX_FIVE;
	default:
		return INDEX_ERROR;
	}
}

static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr,
					     enum pmu_type type)
{
	switch (msr) {
	case MSR_F15H_PERF_CTL0:
	case MSR_F15H_PERF_CTL1:
	case MSR_F15H_PERF_CTL2:
	case MSR_F15H_PERF_CTL3:
	case MSR_F15H_PERF_CTL4:
	case MSR_F15H_PERF_CTL5:
	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
		if (type != PMU_TYPE_EVNTSEL)
			return NULL;
		break;
	case MSR_F15H_PERF_CTR0:
	case MSR_F15H_PERF_CTR1:
	case MSR_F15H_PERF_CTR2:
	case MSR_F15H_PERF_CTR3:
	case MSR_F15H_PERF_CTR4:
	case MSR_F15H_PERF_CTR5:
	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
		if (type != PMU_TYPE_COUNTER)
			return NULL;
		break;
	default:
		return NULL;
	}

	return &pmu->gp_counters[msr_to_index(msr)];
}

static unsigned amd_find_arch_event(struct kvm_pmu *pmu,
				    u8 event_select,
				    u8 unit_mask)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(amd_event_mapping); i++)
		if (amd_event_mapping[i].eventsel == event_select
		    && amd_event_mapping[i].unit_mask == unit_mask)
			break;

	if (i == ARRAY_SIZE(amd_event_mapping))
		return PERF_COUNT_HW_MAX;

	return amd_event_mapping[i].event_type;
}

/* return PERF_COUNT_HW_MAX as AMD doesn't have fixed events */
static unsigned amd_find_fixed_event(int idx)
{
	return PERF_COUNT_HW_MAX;
}

/* check if a PMC is enabled by comparing it against global_ctrl bits. Because
 * AMD CPU doesn't have global_ctrl MSR, all PMCs are enabled (return TRUE).
 */
static bool amd_pmc_is_enabled(struct kvm_pmc *pmc)
{
	return true;
}

static struct kvm_pmc *amd_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
{
	unsigned int base = get_msr_base(pmu, PMU_TYPE_COUNTER);
	struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);

	if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) {
		/*
		 * The idx is contiguous. The MSRs are not. The counter MSRs
		 * are interleaved with the event select MSRs.
		 */
		pmc_idx *= 2;
	}

	return get_gp_pmc_amd(pmu, base + pmc_idx, PMU_TYPE_COUNTER);
}

/* returns 0 if idx's corresponding MSR exists; otherwise returns 1. */
static int amd_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);

	idx &= ~(3u << 30);

	return (idx >= pmu->nr_arch_gp_counters);
}

/* idx is the ECX register of RDPMC instruction */
static struct kvm_pmc *amd_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu,
	unsigned int idx, u64 *mask)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	struct kvm_pmc *counters;

	idx &= ~(3u << 30);
	if (idx >= pmu->nr_arch_gp_counters)
		return NULL;
	counters = pmu->gp_counters;

	return &counters[idx];
}

static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
{
	/* All MSRs refer to exactly one PMC, so msr_idx_to_pmc is enough.  */
	return false;
}

static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	struct kvm_pmc *pmc;

	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
	pmc = pmc ? pmc : get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);

	return pmc;
}

static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	struct kvm_pmc *pmc;

	/* MSR_PERFCTRn */
	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
	if (pmc) {
		*data = pmc_read_counter(pmc);
		return 0;
	}
	/* MSR_EVNTSELn */
	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
	if (pmc) {
		*data = pmc->eventsel;
		return 0;
	}

	return 1;
}

static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	struct kvm_pmc *pmc;
	u32 msr = msr_info->index;
	u64 data = msr_info->data;

	/* MSR_PERFCTRn */
	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
	if (pmc) {
		pmc->counter += data - pmc_read_counter(pmc);
		return 0;
	}
	/* MSR_EVNTSELn */
	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
	if (pmc) {
		if (data == pmc->eventsel)
			return 0;
		if (!(data & pmu->reserved_bits)) {
			reprogram_gp_counter(pmc, data);
			return 0;
		}
	}

	return 1;
}

static void amd_pmu_refresh(struct kvm_vcpu *vcpu)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);

	if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE))
		pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS_CORE;
	else
		pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS;

	pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;
	pmu->reserved_bits = 0xffffffff00200000ull;
	pmu->version = 1;
	/* not applicable to AMD; but clean them to prevent any fall out */
	pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
	pmu->nr_arch_fixed_counters = 0;
	pmu->global_status = 0;
	bitmap_set(pmu->all_valid_pmc_idx, 0, pmu->nr_arch_gp_counters);
}

static void amd_pmu_init(struct kvm_vcpu *vcpu)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	int i;

	BUILD_BUG_ON(AMD64_NUM_COUNTERS_CORE > INTEL_PMC_MAX_GENERIC);

	for (i = 0; i < AMD64_NUM_COUNTERS_CORE ; i++) {
		pmu->gp_counters[i].type = KVM_PMC_GP;
		pmu->gp_counters[i].vcpu = vcpu;
		pmu->gp_counters[i].idx = i;
		pmu->gp_counters[i].current_config = 0;
	}
}

static void amd_pmu_reset(struct kvm_vcpu *vcpu)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	int i;

	for (i = 0; i < AMD64_NUM_COUNTERS_CORE; i++) {
		struct kvm_pmc *pmc = &pmu->gp_counters[i];

		pmc_stop_counter(pmc);
		pmc->counter = pmc->eventsel = 0;
	}
}

struct kvm_pmu_ops amd_pmu_ops = {
	.find_arch_event = amd_find_arch_event,
	.find_fixed_event = amd_find_fixed_event,
	.pmc_is_enabled = amd_pmc_is_enabled,
	.pmc_idx_to_pmc = amd_pmc_idx_to_pmc,
	.rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc,
	.msr_idx_to_pmc = amd_msr_idx_to_pmc,
	.is_valid_rdpmc_ecx = amd_is_valid_rdpmc_ecx,
	.is_valid_msr = amd_is_valid_msr,
	.get_msr = amd_pmu_get_msr,
	.set_msr = amd_pmu_set_msr,
	.refresh = amd_pmu_refresh,
	.init = amd_pmu_init,
	.reset = amd_pmu_reset,
};
Commit	Line	Data
20c8ccb1	1	// SPDX-License-Identifier: GPL-2.0-only
25462f7f WH	2	/*
	3	* KVM PMU support for AMD
	4	*
	5	* Copyright 2015, Red Hat, Inc. and/or its affiliates.
	6	*
	7	* Author:
	8	* Wei Huang <wei@redhat.com>
	9	*
25462f7f WH	10	* Implementation is based on pmu_intel.c file
	11	*/
	12	#include <linux/types.h>
	13	#include <linux/kvm_host.h>
	14	#include <linux/perf_event.h>
	15	#include "x86.h"
	16	#include "cpuid.h"
	17	#include "lapic.h"
	18	#include "pmu.h"
	19
c51eb52b JN	20	enum pmu_type {
	21	PMU_TYPE_COUNTER = 0,
	22	PMU_TYPE_EVNTSEL,
	23	};
	24
	25	enum index {
	26	INDEX_ZERO = 0,
	27	INDEX_ONE,
	28	INDEX_TWO,
	29	INDEX_THREE,
	30	INDEX_FOUR,
	31	INDEX_FIVE,
	32	INDEX_ERROR,
	33	};
	34
ca724305 WH	35	/* duplicated from amd_perfmon_event_map, K7 and above should work. */
	36	static struct kvm_event_hw_type_mapping amd_event_mapping[] = {
	37	[0] = { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES },
	38	[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
080fe0b7 MF	39	[2] = { 0x7d, 0x07, PERF_COUNT_HW_CACHE_REFERENCES },
080fe0b7 MF	40	[3] = { 0x7e, 0x07, PERF_COUNT_HW_CACHE_MISSES },
ca724305 WH	41	[4] = { 0xc2, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
	42	[5] = { 0xc3, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
	43	[6] = { 0xd0, 0x00, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND },
	44	[7] = { 0xd1, 0x00, PERF_COUNT_HW_STALLED_CYCLES_BACKEND },
	45	};
	46
c51eb52b JN	47	static unsigned int get_msr_base(struct kvm_pmu *pmu, enum pmu_type type)
	48	{
	49	struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
	50
	51	if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) {
	52	if (type == PMU_TYPE_COUNTER)
	53	return MSR_F15H_PERF_CTR;
	54	else
	55	return MSR_F15H_PERF_CTL;
	56	} else {
	57	if (type == PMU_TYPE_COUNTER)
	58	return MSR_K7_PERFCTR0;
	59	else
	60	return MSR_K7_EVNTSEL0;
	61	}
	62	}
	63
	64	static enum index msr_to_index(u32 msr)
	65	{
	66	switch (msr) {
	67	case MSR_F15H_PERF_CTL0:
	68	case MSR_F15H_PERF_CTR0:
	69	case MSR_K7_EVNTSEL0:
	70	case MSR_K7_PERFCTR0:
	71	return INDEX_ZERO;
	72	case MSR_F15H_PERF_CTL1:
	73	case MSR_F15H_PERF_CTR1:
	74	case MSR_K7_EVNTSEL1:
	75	case MSR_K7_PERFCTR1:
	76	return INDEX_ONE;
	77	case MSR_F15H_PERF_CTL2:
	78	case MSR_F15H_PERF_CTR2:
	79	case MSR_K7_EVNTSEL2:
	80	case MSR_K7_PERFCTR2:
	81	return INDEX_TWO;
	82	case MSR_F15H_PERF_CTL3:
	83	case MSR_F15H_PERF_CTR3:
	84	case MSR_K7_EVNTSEL3:
	85	case MSR_K7_PERFCTR3:
	86	return INDEX_THREE;
	87	case MSR_F15H_PERF_CTL4:
	88	case MSR_F15H_PERF_CTR4:
	89	return INDEX_FOUR;
	90	case MSR_F15H_PERF_CTL5:
	91	case MSR_F15H_PERF_CTR5:
	92	return INDEX_FIVE;
	93	default:
	94	return INDEX_ERROR;
	95	}
	96	}
	97
	98	static inline struct kvm_pmc get_gp_pmc_amd(struct kvm_pmu pmu, u32 msr,
	99	enum pmu_type type)
	100	{
	101	switch (msr) {
	102	case MSR_F15H_PERF_CTL0:
	103	case MSR_F15H_PERF_CTL1:
	104	case MSR_F15H_PERF_CTL2:
	105	case MSR_F15H_PERF_CTL3:
	106	case MSR_F15H_PERF_CTL4:
	107	case MSR_F15H_PERF_CTL5:
	108	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
	109	if (type != PMU_TYPE_EVNTSEL)
	110	return NULL;
111	break;
112	case MSR_F15H_PERF_CTR0:
113	case MSR_F15H_PERF_CTR1:
114	case MSR_F15H_PERF_CTR2:
115	case MSR_F15H_PERF_CTR3:
116	case MSR_F15H_PERF_CTR4:
117	case MSR_F15H_PERF_CTR5:
118	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
119	if (type != PMU_TYPE_COUNTER)
120	return NULL;
121	break;
122	default:
123	return NULL;
124	}
125
126	return &pmu->gp_counters[msr_to_index(msr)];
127	}
128
25462f7f WH	129	static unsigned amd_find_arch_event(struct kvm_pmu *pmu,
	130	u8 event_select,
	131	u8 unit_mask)
	132	{
ca724305 WH	133	int i;
	134
	135	for (i = 0; i < ARRAY_SIZE(amd_event_mapping); i++)
	136	if (amd_event_mapping[i].eventsel == event_select
	137	&& amd_event_mapping[i].unit_mask == unit_mask)
	138	break;
	139
	140	if (i == ARRAY_SIZE(amd_event_mapping))
	141	return PERF_COUNT_HW_MAX;
	142
	143	return amd_event_mapping[i].event_type;
25462f7f WH	144	}
	145
	146	/* return PERF_COUNT_HW_MAX as AMD doesn't have fixed events */
	147	static unsigned amd_find_fixed_event(int idx)
	148	{
	149	return PERF_COUNT_HW_MAX;
	150	}
	151
ca724305 WH	152	/* check if a PMC is enabled by comparing it against global_ctrl bits. Because
	153	* AMD CPU doesn't have global_ctrl MSR, all PMCs are enabled (return TRUE).
	154	*/
25462f7f WH	155	static bool amd_pmc_is_enabled(struct kvm_pmc *pmc)
25462f7f WH	156	{
ca724305	157	return true;
25462f7f WH	158	}
	159
	160	static struct kvm_pmc amd_pmc_idx_to_pmc(struct kvm_pmu pmu, int pmc_idx)
	161	{
c51eb52b JN	162	unsigned int base = get_msr_base(pmu, PMU_TYPE_COUNTER);
	163	struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
	164
	165	if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) {
	166	/*
	167	* The idx is contiguous. The MSRs are not. The counter MSRs
	168	* are interleaved with the event select MSRs.
	169	*/
	170	pmc_idx *= 2;
	171	}
	172
	173	return get_gp_pmc_amd(pmu, base + pmc_idx, PMU_TYPE_COUNTER);
25462f7f WH	174	}
	175
	176	/* returns 0 if idx's corresponding MSR exists; otherwise returns 1. */
98ff80f5	177	static int amd_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
25462f7f	178	{
ca724305 WH	179	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	180
	181	idx &= ~(3u << 30);
	182
	183	return (idx >= pmu->nr_arch_gp_counters);
25462f7f WH	184	}
	185
	186	/* idx is the ECX register of RDPMC instruction */
98ff80f5 LX	187	static struct kvm_pmc amd_rdpmc_ecx_to_pmc(struct kvm_vcpu vcpu,
98ff80f5 LX	188	unsigned int idx, u64 *mask)
25462f7f	189	{
ca724305 WH	190	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	191	struct kvm_pmc *counters;
	192
	193	idx &= ~(3u << 30);
	194	if (idx >= pmu->nr_arch_gp_counters)
	195	return NULL;
	196	counters = pmu->gp_counters;
	197
	198	return &counters[idx];
25462f7f WH	199	}
	200
	201	static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
c900c156 LX	202	{
	203	/* All MSRs refer to exactly one PMC, so msr_idx_to_pmc is enough. */
	204	return false;
	205	}
	206
	207	static struct kvm_pmc amd_msr_idx_to_pmc(struct kvm_vcpu vcpu, u32 msr)
25462f7f	208	{
ca724305	209	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
c900c156	210	struct kvm_pmc *pmc;
ca724305	211
c900c156 LX	212	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
c900c156 LX	213	pmc = pmc ? pmc : get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
ca724305	214
c900c156	215	return pmc;
25462f7f WH	216	}
	217
	218	static int amd_pmu_get_msr(struct kvm_vcpu vcpu, u32 msr, u64 data)
	219	{
ca724305 WH	220	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	221	struct kvm_pmc *pmc;
	222
c51eb52b JN	223	/* MSR_PERFCTRn */
c51eb52b JN	224	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
ca724305 WH	225	if (pmc) {
	226	*data = pmc_read_counter(pmc);
	227	return 0;
	228	}
c51eb52b JN	229	/* MSR_EVNTSELn */
c51eb52b JN	230	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
ca724305 WH	231	if (pmc) {
	232	*data = pmc->eventsel;
	233	return 0;
	234	}
	235
25462f7f WH	236	return 1;
	237	}
	238
	239	static int amd_pmu_set_msr(struct kvm_vcpu vcpu, struct msr_data msr_info)
	240	{
ca724305 WH	241	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	242	struct kvm_pmc *pmc;
	243	u32 msr = msr_info->index;
	244	u64 data = msr_info->data;
	245
c51eb52b JN	246	/* MSR_PERFCTRn */
c51eb52b JN	247	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
ca724305	248	if (pmc) {
ca724305 WH	249	pmc->counter += data - pmc_read_counter(pmc);
	250	return 0;
	251	}
c51eb52b JN	252	/* MSR_EVNTSELn */
c51eb52b JN	253	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
ca724305 WH	254	if (pmc) {
	255	if (data == pmc->eventsel)
	256	return 0;
	257	if (!(data & pmu->reserved_bits)) {
	258	reprogram_gp_counter(pmc, data);
	259	return 0;
	260	}
	261	}
	262
25462f7f WH	263	return 1;
	264	}
	265
	266	static void amd_pmu_refresh(struct kvm_vcpu *vcpu)
	267	{
ca724305 WH	268	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
ca724305 WH	269
c51eb52b JN	270	if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE))
	271	pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS_CORE;
	272	else
	273	pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS;
	274
ca724305 WH	275	pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;
ca724305 WH	276	pmu->reserved_bits = 0xffffffff00200000ull;
a80c4ec1	277	pmu->version = 1;
ca724305 WH	278	/* not applicable to AMD; but clean them to prevent any fall out */
	279	pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
	280	pmu->nr_arch_fixed_counters = 0;
ca724305	281	pmu->global_status = 0;
b35e5548	282	bitmap_set(pmu->all_valid_pmc_idx, 0, pmu->nr_arch_gp_counters);
25462f7f WH	283	}
	284
	285	static void amd_pmu_init(struct kvm_vcpu *vcpu)
	286	{
ca724305 WH	287	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	288	int i;
	289
c51eb52b JN	290	BUILD_BUG_ON(AMD64_NUM_COUNTERS_CORE > INTEL_PMC_MAX_GENERIC);
	291
	292	for (i = 0; i < AMD64_NUM_COUNTERS_CORE ; i++) {
ca724305 WH	293	pmu->gp_counters[i].type = KVM_PMC_GP;
	294	pmu->gp_counters[i].vcpu = vcpu;
	295	pmu->gp_counters[i].idx = i;
a6da0d77	296	pmu->gp_counters[i].current_config = 0;
ca724305	297	}
25462f7f WH	298	}
	299
	300	static void amd_pmu_reset(struct kvm_vcpu *vcpu)
	301	{
ca724305 WH	302	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	303	int i;
	304
c51eb52b	305	for (i = 0; i < AMD64_NUM_COUNTERS_CORE; i++) {
ca724305 WH	306	struct kvm_pmc *pmc = &pmu->gp_counters[i];
	307
	308	pmc_stop_counter(pmc);
	309	pmc->counter = pmc->eventsel = 0;
	310	}
25462f7f WH	311	}
	312
	313	struct kvm_pmu_ops amd_pmu_ops = {
	314	.find_arch_event = amd_find_arch_event,
	315	.find_fixed_event = amd_find_fixed_event,
	316	.pmc_is_enabled = amd_pmc_is_enabled,
	317	.pmc_idx_to_pmc = amd_pmc_idx_to_pmc,
98ff80f5	318	.rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc,
c900c156	319	.msr_idx_to_pmc = amd_msr_idx_to_pmc,
98ff80f5	320	.is_valid_rdpmc_ecx = amd_is_valid_rdpmc_ecx,
25462f7f WH	321	.is_valid_msr = amd_is_valid_msr,
	322	.get_msr = amd_pmu_get_msr,
	323	.set_msr = amd_pmu_set_msr,
	324	.refresh = amd_pmu_refresh,
	325	.init = amd_pmu_init,
	326	.reset = amd_pmu_reset,
	327	};