Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
35 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
36 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 37 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
cea0f0e7 AK |
38 | #ifdef CONFIG_X86_64 |
39 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 40 | #define CMPXCHG cmpxchg |
cea0f0e7 | 41 | #else |
b3e4e63f | 42 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
43 | #define PT_MAX_FULL_LEVELS 2 |
44 | #endif | |
6aa8b732 AK |
45 | #elif PTTYPE == 32 |
46 | #define pt_element_t u32 | |
47 | #define guest_walker guest_walker32 | |
48 | #define FNAME(name) paging##32_##name | |
49 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
50 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
51 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 52 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 53 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 54 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
55 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT |
56 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
86407bcb | 57 | #define PT_HAVE_ACCESSED_DIRTY(mmu) true |
b3e4e63f | 58 | #define CMPXCHG cmpxchg |
37406aaa NHE |
59 | #elif PTTYPE == PTTYPE_EPT |
60 | #define pt_element_t u64 | |
61 | #define guest_walker guest_walkerEPT | |
62 | #define FNAME(name) ept_##name | |
63 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
64 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
65 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
66 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
67 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
ae1e2d10 PB |
68 | #define PT_GUEST_DIRTY_SHIFT 9 |
69 | #define PT_GUEST_ACCESSED_SHIFT 8 | |
70 | #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad) | |
37406aaa NHE |
71 | #define CMPXCHG cmpxchg64 |
72 | #define PT_MAX_FULL_LEVELS 4 | |
6aa8b732 AK |
73 | #else |
74 | #error Invalid PTTYPE value | |
75 | #endif | |
76 | ||
ae1e2d10 PB |
77 | #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT) |
78 | #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT) | |
79 | ||
e04da980 JR |
80 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
81 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 82 | |
6aa8b732 AK |
83 | /* |
84 | * The guest_walker structure emulates the behavior of the hardware page | |
85 | * table walker. | |
86 | */ | |
87 | struct guest_walker { | |
88 | int level; | |
8cbc7069 | 89 | unsigned max_level; |
cea0f0e7 | 90 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 91 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 92 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 93 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 94 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
ba6a3541 | 95 | bool pte_writable[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
96 | unsigned pt_access; |
97 | unsigned pte_access; | |
815af8d4 | 98 | gfn_t gfn; |
8c28d031 | 99 | struct x86_exception fault; |
6aa8b732 AK |
100 | }; |
101 | ||
e04da980 | 102 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 103 | { |
e04da980 | 104 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
105 | } |
106 | ||
86407bcb PB |
107 | static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access, |
108 | unsigned gpte) | |
0ad805a0 NHE |
109 | { |
110 | unsigned mask; | |
111 | ||
61719a8f | 112 | /* dirty bit is not supported, so no need to track it */ |
86407bcb | 113 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
114 | return; |
115 | ||
0ad805a0 NHE |
116 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
117 | ||
118 | mask = (unsigned)~ACC_WRITE_MASK; | |
119 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
120 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
121 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
122 | *access &= mask; |
123 | } | |
124 | ||
0ad805a0 NHE |
125 | static inline int FNAME(is_present_gpte)(unsigned long pte) |
126 | { | |
37406aaa | 127 | #if PTTYPE != PTTYPE_EPT |
812f30b2 | 128 | return pte & PT_PRESENT_MASK; |
37406aaa NHE |
129 | #else |
130 | return pte & 7; | |
131 | #endif | |
0ad805a0 NHE |
132 | } |
133 | ||
a78484c6 | 134 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
135 | pt_element_t __user *ptep_user, unsigned index, |
136 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 137 | { |
c8cfbb55 | 138 | int npages; |
b3e4e63f MT |
139 | pt_element_t ret; |
140 | pt_element_t *table; | |
141 | struct page *page; | |
142 | ||
73b0140b | 143 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, FOLL_WRITE, &page); |
c8cfbb55 TY |
144 | /* Check if the user is doing something meaningless. */ |
145 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
146 | return -EFAULT; |
147 | ||
8fd75e12 | 148 | table = kmap_atomic(page); |
b3e4e63f | 149 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 150 | kunmap_atomic(table); |
b3e4e63f MT |
151 | |
152 | kvm_release_page_dirty(page); | |
153 | ||
154 | return (ret != orig_pte); | |
155 | } | |
156 | ||
0ad805a0 NHE |
157 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
158 | struct kvm_mmu_page *sp, u64 *spte, | |
159 | u64 gpte) | |
160 | { | |
44dd3ffa | 161 | if (is_rsvd_bits_set(vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) |
0ad805a0 NHE |
162 | goto no_present; |
163 | ||
164 | if (!FNAME(is_present_gpte)(gpte)) | |
165 | goto no_present; | |
166 | ||
61719a8f | 167 | /* if accessed bit is not supported prefetch non accessed gpte */ |
44dd3ffa VK |
168 | if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) && |
169 | !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
170 | goto no_present; |
171 | ||
172 | return false; | |
173 | ||
174 | no_present: | |
175 | drop_spte(vcpu->kvm, spte); | |
176 | return true; | |
177 | } | |
178 | ||
d95c5568 BD |
179 | /* |
180 | * For PTTYPE_EPT, a page table can be executable but not readable | |
181 | * on supported processors. Therefore, set_spte does not automatically | |
182 | * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK | |
183 | * to signify readability since it isn't used in the EPT case | |
184 | */ | |
42522d08 | 185 | static inline unsigned FNAME(gpte_access)(u64 gpte) |
0ad805a0 NHE |
186 | { |
187 | unsigned access; | |
37406aaa NHE |
188 | #if PTTYPE == PTTYPE_EPT |
189 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
190 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
d95c5568 | 191 | ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0); |
37406aaa | 192 | #else |
bb9eadf0 PB |
193 | BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK); |
194 | BUILD_BUG_ON(ACC_EXEC_MASK != 1); | |
195 | access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK); | |
196 | /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */ | |
197 | access ^= (gpte >> PT64_NX_SHIFT); | |
37406aaa | 198 | #endif |
0ad805a0 NHE |
199 | |
200 | return access; | |
201 | } | |
202 | ||
8cbc7069 AK |
203 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
204 | struct kvm_mmu *mmu, | |
205 | struct guest_walker *walker, | |
206 | int write_fault) | |
207 | { | |
208 | unsigned level, index; | |
209 | pt_element_t pte, orig_pte; | |
210 | pt_element_t __user *ptep_user; | |
211 | gfn_t table_gfn; | |
212 | int ret; | |
213 | ||
61719a8f | 214 | /* dirty/accessed bits are not supported, so no need to update them */ |
86407bcb | 215 | if (!PT_HAVE_ACCESSED_DIRTY(mmu)) |
61719a8f GN |
216 | return 0; |
217 | ||
8cbc7069 AK |
218 | for (level = walker->max_level; level >= walker->level; --level) { |
219 | pte = orig_pte = walker->ptes[level - 1]; | |
220 | table_gfn = walker->table_gfn[level - 1]; | |
221 | ptep_user = walker->ptep_user[level - 1]; | |
222 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 223 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 224 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 225 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 226 | } |
0ad805a0 | 227 | if (level == walker->level && write_fault && |
d8089bac | 228 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 229 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
bab4165e BD |
230 | #if PTTYPE == PTTYPE_EPT |
231 | if (kvm_arch_write_log_dirty(vcpu)) | |
232 | return -EINVAL; | |
233 | #endif | |
d8089bac | 234 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
235 | } |
236 | if (pte == orig_pte) | |
237 | continue; | |
238 | ||
ba6a3541 PB |
239 | /* |
240 | * If the slot is read-only, simply do not process the accessed | |
241 | * and dirty bits. This is the correct thing to do if the slot | |
242 | * is ROM, and page tables in read-as-ROM/write-as-MMIO slots | |
243 | * are only supported if the accessed and dirty bits are already | |
244 | * set in the ROM (so that MMIO writes are never needed). | |
245 | * | |
246 | * Note that NPT does not allow this at all and faults, since | |
247 | * it always wants nested page table entries for the guest | |
248 | * page tables to be writable. And EPT works but will simply | |
249 | * overwrite the read-only memory to set the accessed and dirty | |
250 | * bits. | |
251 | */ | |
252 | if (unlikely(!walker->pte_writable[level - 1])) | |
253 | continue; | |
254 | ||
8cbc7069 AK |
255 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); |
256 | if (ret) | |
257 | return ret; | |
258 | ||
54bf36aa | 259 | kvm_vcpu_mark_page_dirty(vcpu, table_gfn); |
17e4bce0 | 260 | walker->ptes[level - 1] = pte; |
8cbc7069 AK |
261 | } |
262 | return 0; | |
263 | } | |
264 | ||
be94f6b7 HH |
265 | static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte) |
266 | { | |
267 | unsigned pkeys = 0; | |
268 | #if PTTYPE == 64 | |
269 | pte_t pte = {.pte = gpte}; | |
270 | ||
271 | pkeys = pte_flags_pkey(pte_flags(pte)); | |
272 | #endif | |
273 | return pkeys; | |
274 | } | |
275 | ||
ac79c978 AK |
276 | /* |
277 | * Fetch a guest pte for a guest virtual address | |
278 | */ | |
1e301feb JR |
279 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
280 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 281 | gva_t addr, u32 access) |
6aa8b732 | 282 | { |
8cbc7069 | 283 | int ret; |
42bf3f0a | 284 | pt_element_t pte; |
b7233635 | 285 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 286 | gfn_t table_gfn; |
0780516a PB |
287 | u64 pt_access, pte_access; |
288 | unsigned index, accessed_dirty, pte_pkey; | |
ae1e2d10 | 289 | unsigned nested_access; |
42bf3f0a | 290 | gpa_t pte_gpa; |
86407bcb | 291 | bool have_ad; |
134291bf | 292 | int offset; |
0780516a | 293 | u64 walk_nx_mask = 0; |
134291bf TY |
294 | const int write_fault = access & PFERR_WRITE_MASK; |
295 | const int user_fault = access & PFERR_USER_MASK; | |
296 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
297 | u16 errcode = 0; | |
13d22b6a AK |
298 | gpa_t real_gpa; |
299 | gfn_t gfn; | |
6aa8b732 | 300 | |
6fbc2770 | 301 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 302 | retry_walk: |
1e301feb JR |
303 | walker->level = mmu->root_level; |
304 | pte = mmu->get_cr3(vcpu); | |
86407bcb | 305 | have_ad = PT_HAVE_ACCESSED_DIRTY(mmu); |
1e301feb | 306 | |
1b0973bd | 307 | #if PTTYPE == 64 |
0780516a | 308 | walk_nx_mask = 1ULL << PT64_NX_SHIFT; |
1e301feb | 309 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 310 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 311 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 312 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 313 | goto error; |
1b0973bd AK |
314 | --walker->level; |
315 | } | |
316 | #endif | |
8cbc7069 | 317 | walker->max_level = walker->level; |
1715d0dc | 318 | ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu))); |
6aa8b732 | 319 | |
ae1e2d10 PB |
320 | /* |
321 | * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging | |
322 | * by the MOV to CR instruction are treated as reads and do not cause the | |
323 | * processor to set the dirty flag in any EPT paging-structure entry. | |
324 | */ | |
325 | nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK; | |
326 | ||
0780516a | 327 | pte_access = ~0; |
13d22b6a | 328 | ++walker->level; |
ac79c978 | 329 | |
13d22b6a | 330 | do { |
6e2ca7d1 TY |
331 | gfn_t real_gfn; |
332 | unsigned long host_addr; | |
333 | ||
0780516a | 334 | pt_access = pte_access; |
13d22b6a AK |
335 | --walker->level; |
336 | ||
42bf3f0a | 337 | index = PT_INDEX(addr, walker->level); |
5fb07ddb | 338 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
339 | offset = index * sizeof(pt_element_t); |
340 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
829ee279 LP |
341 | |
342 | BUG_ON(walker->level < 1); | |
42bf3f0a | 343 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 344 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 345 | |
6e2ca7d1 | 346 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
ae1e2d10 | 347 | nested_access, |
54987b7a | 348 | &walker->fault); |
5e352519 PB |
349 | |
350 | /* | |
351 | * FIXME: This can happen if emulation (for of an INS/OUTS | |
352 | * instruction) triggers a nested page fault. The exit | |
353 | * qualification / exit info field will incorrectly have | |
354 | * "guest page access" as the nested page fault's cause, | |
355 | * instead of "guest page structure access". To fix this, | |
356 | * the x86_exception struct should be augmented with enough | |
357 | * information to fix the exit_qualification or exit_info_1 | |
358 | * fields. | |
359 | */ | |
134291bf | 360 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
54987b7a | 361 | return 0; |
5e352519 | 362 | |
6e2ca7d1 TY |
363 | real_gfn = gpa_to_gfn(real_gfn); |
364 | ||
54bf36aa | 365 | host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn, |
ba6a3541 | 366 | &walker->pte_writable[walker->level - 1]); |
134291bf TY |
367 | if (unlikely(kvm_is_error_hva(host_addr))) |
368 | goto error; | |
6e2ca7d1 TY |
369 | |
370 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
371 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
372 | goto error; | |
8cbc7069 | 373 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 374 | |
07420171 | 375 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 376 | |
0780516a PB |
377 | /* |
378 | * Inverting the NX it lets us AND it like other | |
379 | * permission bits. | |
380 | */ | |
381 | pte_access = pt_access & (pte ^ walk_nx_mask); | |
382 | ||
0ad805a0 | 383 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 384 | goto error; |
7993ba43 | 385 | |
d2b0f981 | 386 | if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) { |
7a98205d | 387 | errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
134291bf | 388 | goto error; |
f59c1d2d | 389 | } |
82725b20 | 390 | |
7819026e | 391 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 392 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 393 | |
be94f6b7 | 394 | pte_pkey = FNAME(gpte_pkeys)(vcpu, pte); |
0780516a PB |
395 | accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0; |
396 | ||
397 | /* Convert to ACC_*_MASK flags for struct guest_walker. */ | |
42522d08 PX |
398 | walker->pt_access = FNAME(gpte_access)(pt_access ^ walk_nx_mask); |
399 | walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask); | |
0780516a | 400 | errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access); |
f13577e8 | 401 | if (unlikely(errcode)) |
f59c1d2d AK |
402 | goto error; |
403 | ||
13d22b6a AK |
404 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
405 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
406 | ||
407 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
408 | gfn += pse36_gfn_delta(pte); | |
409 | ||
54987b7a | 410 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault); |
13d22b6a AK |
411 | if (real_gpa == UNMAPPED_GVA) |
412 | return 0; | |
413 | ||
414 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
415 | ||
8ea667f2 | 416 | if (!write_fault) |
0780516a | 417 | FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte); |
908e7d79 GN |
418 | else |
419 | /* | |
61719a8f GN |
420 | * On a write fault, fold the dirty bit into accessed_dirty. |
421 | * For modes without A/D bits support accessed_dirty will be | |
422 | * always clear. | |
908e7d79 | 423 | */ |
d8089bac GN |
424 | accessed_dirty &= pte >> |
425 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
426 | |
427 | if (unlikely(!accessed_dirty)) { | |
428 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
429 | if (unlikely(ret < 0)) | |
430 | goto error; | |
431 | else if (ret) | |
432 | goto retry_walk; | |
433 | } | |
42bf3f0a | 434 | |
fe135d2c | 435 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", |
0780516a | 436 | __func__, (u64)pte, walker->pte_access, walker->pt_access); |
7993ba43 AK |
437 | return 1; |
438 | ||
f59c1d2d | 439 | error: |
134291bf | 440 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
441 | if (fetch_fault && (mmu->nx || |
442 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 443 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 444 | |
134291bf TY |
445 | walker->fault.vector = PF_VECTOR; |
446 | walker->fault.error_code_valid = true; | |
447 | walker->fault.error_code = errcode; | |
25d92081 YZ |
448 | |
449 | #if PTTYPE == PTTYPE_EPT | |
450 | /* | |
451 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
452 | * misconfiguration requires to be injected. The detection is | |
453 | * done by is_rsvd_bits_set() above. | |
454 | * | |
455 | * We set up the value of exit_qualification to inject: | |
ddd6f0e9 KA |
456 | * [2:0] - Derive from the access bits. The exit_qualification might be |
457 | * out of date if it is serving an EPT misconfiguration. | |
25d92081 YZ |
458 | * [5:3] - Calculated by the page walk of the guest EPT page tables |
459 | * [7:8] - Derived from [7:8] of real exit_qualification | |
460 | * | |
461 | * The other bits are set to 0. | |
462 | */ | |
463 | if (!(errcode & PFERR_RSVD_MASK)) { | |
ddd6f0e9 KA |
464 | vcpu->arch.exit_qualification &= 0x180; |
465 | if (write_fault) | |
466 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE; | |
467 | if (user_fault) | |
468 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ; | |
469 | if (fetch_fault) | |
470 | vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR; | |
0780516a | 471 | vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3; |
25d92081 YZ |
472 | } |
473 | #endif | |
6389ee94 AK |
474 | walker->fault.address = addr; |
475 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 476 | |
8c28d031 | 477 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 478 | return 0; |
6aa8b732 AK |
479 | } |
480 | ||
1e301feb | 481 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 482 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb | 483 | { |
44dd3ffa | 484 | return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr, |
33770780 | 485 | access); |
1e301feb JR |
486 | } |
487 | ||
37406aaa | 488 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
489 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
490 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 491 | u32 access) |
6539e738 JR |
492 | { |
493 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 494 | addr, access); |
6539e738 | 495 | } |
37406aaa | 496 | #endif |
6539e738 | 497 | |
bd6360cc XG |
498 | static bool |
499 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
500 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 501 | { |
41074d07 | 502 | unsigned pte_access; |
bd6360cc | 503 | gfn_t gfn; |
ba049e93 | 504 | kvm_pfn_t pfn; |
0028425f | 505 | |
0ad805a0 | 506 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 507 | return false; |
407c61c6 | 508 | |
b8688d51 | 509 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
510 | |
511 | gfn = gpte_to_gfn(gpte); | |
42522d08 | 512 | pte_access = sp->role.access & FNAME(gpte_access)(gpte); |
44dd3ffa | 513 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
bd6360cc XG |
514 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
515 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 516 | if (is_error_pfn(pfn)) |
bd6360cc | 517 | return false; |
0f53b5b1 | 518 | |
1403283a | 519 | /* |
bd6360cc XG |
520 | * we call mmu_set_spte() with host_writable = true because |
521 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 522 | */ |
029499b4 TY |
523 | mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn, |
524 | true, true); | |
bd6360cc XG |
525 | |
526 | return true; | |
527 | } | |
528 | ||
529 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
530 | u64 *spte, const void *pte) | |
531 | { | |
532 | pt_element_t gpte = *(const pt_element_t *)pte; | |
533 | ||
534 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
535 | } |
536 | ||
39c8c672 AK |
537 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
538 | struct guest_walker *gw, int level) | |
539 | { | |
39c8c672 | 540 | pt_element_t curr_pte; |
189be38d XG |
541 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
542 | u64 mask; | |
543 | int r, index; | |
544 | ||
545 | if (level == PT_PAGE_TABLE_LEVEL) { | |
546 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
547 | base_gpa = pte_gpa & ~mask; | |
548 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
549 | ||
54bf36aa | 550 | r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa, |
189be38d XG |
551 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); |
552 | curr_pte = gw->prefetch_ptes[index]; | |
553 | } else | |
54bf36aa | 554 | r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, |
39c8c672 | 555 | &curr_pte, sizeof(curr_pte)); |
189be38d | 556 | |
39c8c672 AK |
557 | return r || curr_pte != gw->ptes[level - 1]; |
558 | } | |
559 | ||
189be38d XG |
560 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
561 | u64 *sptep) | |
957ed9ef XG |
562 | { |
563 | struct kvm_mmu_page *sp; | |
189be38d | 564 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 565 | u64 *spte; |
189be38d | 566 | int i; |
957ed9ef XG |
567 | |
568 | sp = page_header(__pa(sptep)); | |
569 | ||
570 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
571 | return; | |
572 | ||
573 | if (sp->role.direct) | |
574 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
575 | ||
576 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
577 | spte = sp->spt + i; |
578 | ||
579 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
580 | if (spte == sptep) |
581 | continue; | |
582 | ||
c3707958 | 583 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
584 | continue; |
585 | ||
bd6360cc | 586 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 587 | break; |
957ed9ef XG |
588 | } |
589 | } | |
590 | ||
6aa8b732 AK |
591 | /* |
592 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
593 | * If the guest tries to write a write-protected page, we need to |
594 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 595 | */ |
d4878f24 | 596 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 597 | struct guest_walker *gw, |
c2288505 | 598 | int write_fault, int hlevel, |
ba049e93 | 599 | kvm_pfn_t pfn, bool map_writable, bool prefault) |
6aa8b732 | 600 | { |
5991b332 | 601 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 602 | struct kvm_shadow_walk_iterator it; |
d4878f24 | 603 | unsigned direct_access, access = gw->pt_access; |
9b8ebbdb | 604 | int top_level, ret; |
abb9e0b8 | 605 | |
b36c7a7c | 606 | direct_access = gw->pte_access; |
84754cd8 | 607 | |
44dd3ffa | 608 | top_level = vcpu->arch.mmu->root_level; |
5991b332 AK |
609 | if (top_level == PT32E_ROOT_LEVEL) |
610 | top_level = PT32_ROOT_LEVEL; | |
611 | /* | |
612 | * Verify that the top-level gpte is still there. Since the page | |
613 | * is a root page, it is either write protected (and cannot be | |
614 | * changed from now on) or it is invalid (in which case, we don't | |
615 | * really care if it changes underneath us after this point). | |
616 | */ | |
617 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
618 | goto out_gpte_changed; | |
619 | ||
44dd3ffa | 620 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
37f6a4e2 MT |
621 | goto out_gpte_changed; |
622 | ||
24157aaf AK |
623 | for (shadow_walk_init(&it, vcpu, addr); |
624 | shadow_walk_okay(&it) && it.level > gw->level; | |
625 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
626 | gfn_t table_gfn; |
627 | ||
a30f47cb | 628 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 629 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 630 | |
5991b332 | 631 | sp = NULL; |
24157aaf AK |
632 | if (!is_shadow_present_pte(*it.sptep)) { |
633 | table_gfn = gw->table_gfn[it.level - 2]; | |
634 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
bb11c6c9 | 635 | false, access); |
5991b332 | 636 | } |
0b3c9333 AK |
637 | |
638 | /* | |
639 | * Verify that the gpte in the page we've just write | |
640 | * protected is still there. | |
641 | */ | |
24157aaf | 642 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 643 | goto out_gpte_changed; |
abb9e0b8 | 644 | |
5991b332 | 645 | if (sp) |
98bba238 | 646 | link_shadow_page(vcpu, it.sptep, sp); |
e7a04c99 | 647 | } |
050e6499 | 648 | |
0b3c9333 | 649 | for (; |
24157aaf AK |
650 | shadow_walk_okay(&it) && it.level > hlevel; |
651 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
652 | gfn_t direct_gfn; |
653 | ||
a30f47cb | 654 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 655 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 656 | |
24157aaf | 657 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 658 | |
24157aaf | 659 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
660 | continue; |
661 | ||
24157aaf | 662 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 663 | |
24157aaf | 664 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
bb11c6c9 | 665 | true, direct_access); |
98bba238 | 666 | link_shadow_page(vcpu, it.sptep, sp); |
0b3c9333 AK |
667 | } |
668 | ||
a30f47cb | 669 | clear_sp_write_flooding_count(it.sptep); |
9b8ebbdb PB |
670 | ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, |
671 | it.level, gw->gfn, pfn, prefault, map_writable); | |
189be38d | 672 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 673 | |
9b8ebbdb | 674 | return ret; |
0b3c9333 AK |
675 | |
676 | out_gpte_changed: | |
0b3c9333 | 677 | kvm_release_pfn_clean(pfn); |
9b8ebbdb | 678 | return RET_PF_RETRY; |
6aa8b732 AK |
679 | } |
680 | ||
7751babd XG |
681 | /* |
682 | * To see whether the mapped gfn can write its page table in the current | |
683 | * mapping. | |
684 | * | |
685 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
686 | * size to map the writable gfn which is used as current page table, we should | |
687 | * force kvm to use small page size to map it because new shadow page will be | |
688 | * created when kvm establishes shadow page table that stop kvm using large | |
689 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
690 | * | |
93c05d3e XG |
691 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
692 | * currently used as its page table. | |
693 | * | |
7751babd XG |
694 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
695 | * since the PDPT is always shadowed, that means, we can not use large page | |
696 | * size to map the gfn which is used as PDPT. | |
697 | */ | |
698 | static bool | |
699 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
700 | struct guest_walker *walker, int user_fault, |
701 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
702 | { |
703 | int level; | |
704 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 705 | bool self_changed = false; |
7751babd XG |
706 | |
707 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
708 | (!is_write_protection(vcpu) && !user_fault))) | |
709 | return false; | |
710 | ||
93c05d3e XG |
711 | for (level = walker->level; level <= walker->max_level; level++) { |
712 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
713 | ||
714 | self_changed |= !(gfn & mask); | |
715 | *write_fault_to_shadow_pgtable |= !gfn; | |
716 | } | |
7751babd | 717 | |
93c05d3e | 718 | return self_changed; |
7751babd XG |
719 | } |
720 | ||
6aa8b732 AK |
721 | /* |
722 | * Page fault handler. There are several causes for a page fault: | |
723 | * - there is no shadow pte for the guest pte | |
724 | * - write access through a shadow pte marked read only so that we can set | |
725 | * the dirty bit | |
726 | * - write access to a shadow pte marked read only so we can update the page | |
727 | * dirty bitmap, when userspace requests it | |
728 | * - mmio access; in this case we will never install a present shadow pte | |
729 | * - normal guest page fault due to the guest pte marked not present, not | |
730 | * writable, or not executable | |
731 | * | |
e2dec939 AK |
732 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
733 | * a negative value on error. | |
6aa8b732 | 734 | */ |
56028d08 | 735 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 736 | bool prefault) |
6aa8b732 AK |
737 | { |
738 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
739 | int user_fault = error_code & PFERR_USER_MASK; |
740 | struct guest_walker walker; | |
e2dec939 | 741 | int r; |
ba049e93 | 742 | kvm_pfn_t pfn; |
7e4e4056 | 743 | int level = PT_PAGE_TABLE_LEVEL; |
8c85ac1c | 744 | bool force_pt_level = false; |
e930bffe | 745 | unsigned long mmu_seq; |
93c05d3e | 746 | bool map_writable, is_self_change_mapping; |
6aa8b732 | 747 | |
b8688d51 | 748 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 749 | |
e2dec939 AK |
750 | r = mmu_topup_memory_caches(vcpu); |
751 | if (r) | |
752 | return r; | |
714b93da | 753 | |
e9ee956e TY |
754 | /* |
755 | * If PFEC.RSVD is set, this is a shadow page fault. | |
756 | * The bit needs to be cleared before walking guest page tables. | |
757 | */ | |
758 | error_code &= ~PFERR_RSVD_MASK; | |
759 | ||
6aa8b732 | 760 | /* |
a8b876b1 | 761 | * Look up the guest pte for the faulting address. |
6aa8b732 | 762 | */ |
33770780 | 763 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
764 | |
765 | /* | |
766 | * The page is not mapped by the guest. Let the guest handle it. | |
767 | */ | |
7993ba43 | 768 | if (!r) { |
b8688d51 | 769 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 770 | if (!prefault) |
fb67e14f | 771 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 772 | |
9b8ebbdb | 773 | return RET_PF_RETRY; |
6aa8b732 AK |
774 | } |
775 | ||
e5691a81 XG |
776 | if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) { |
777 | shadow_page_table_clear_flood(vcpu, addr); | |
9b8ebbdb | 778 | return RET_PF_EMULATE; |
e5691a81 | 779 | } |
3d0c27ad | 780 | |
93c05d3e XG |
781 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
782 | ||
783 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
784 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
785 | ||
5ed5c5c8 | 786 | if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) { |
fd136902 TY |
787 | level = mapping_level(vcpu, walker.gfn, &force_pt_level); |
788 | if (likely(!force_pt_level)) { | |
789 | level = min(walker.level, level); | |
5ed5c5c8 TY |
790 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); |
791 | } | |
792 | } else | |
cd1872f0 | 793 | force_pt_level = true; |
7e4e4056 | 794 | |
e930bffe | 795 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 796 | smp_rmb(); |
af585b92 | 797 | |
78b2c54a | 798 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 799 | &map_writable)) |
9b8ebbdb | 800 | return RET_PF_RETRY; |
d7824fff | 801 | |
9034e6e8 | 802 | if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r)) |
d7c55201 XG |
803 | return r; |
804 | ||
c2288505 XG |
805 | /* |
806 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
807 | * we will cache the incorrect access into mmio spte. | |
808 | */ | |
809 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
810 | !is_write_protection(vcpu) && !user_fault && | |
811 | !is_noslot_pfn(pfn)) { | |
812 | walker.pte_access |= ACC_WRITE_MASK; | |
813 | walker.pte_access &= ~ACC_USER_MASK; | |
814 | ||
815 | /* | |
816 | * If we converted a user page to a kernel page, | |
817 | * so that the kernel can write to it when cr0.wp=0, | |
818 | * then we should prevent the kernel from executing it | |
819 | * if SMEP is enabled. | |
820 | */ | |
821 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
822 | walker.pte_access &= ~ACC_EXEC_MASK; | |
823 | } | |
824 | ||
aaee2c94 | 825 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 826 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 827 | goto out_unlock; |
bc32ce21 | 828 | |
0375f7fa | 829 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
26eeb53c WL |
830 | if (make_mmu_pages_available(vcpu) < 0) |
831 | goto out_unlock; | |
936a5fe6 AA |
832 | if (!force_pt_level) |
833 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
c2288505 | 834 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, |
d4878f24 | 835 | level, pfn, map_writable, prefault); |
1165f5fe | 836 | ++vcpu->stat.pf_fixed; |
0375f7fa | 837 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 838 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 839 | |
d4878f24 | 840 | return r; |
e930bffe AA |
841 | |
842 | out_unlock: | |
843 | spin_unlock(&vcpu->kvm->mmu_lock); | |
844 | kvm_release_pfn_clean(pfn); | |
9b8ebbdb | 845 | return RET_PF_RETRY; |
6aa8b732 AK |
846 | } |
847 | ||
505aef8f XG |
848 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
849 | { | |
850 | int offset = 0; | |
851 | ||
f71fa31f | 852 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
853 | |
854 | if (PTTYPE == 32) | |
855 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
856 | ||
857 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
858 | } | |
859 | ||
7eb77e9f | 860 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa) |
a7052897 | 861 | { |
a461930b | 862 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 863 | struct kvm_mmu_page *sp; |
a461930b AK |
864 | int level; |
865 | u64 *sptep; | |
866 | ||
bebb106a XG |
867 | vcpu_clear_mmio_info(vcpu, gva); |
868 | ||
f57f2ef5 XG |
869 | /* |
870 | * No need to check return value here, rmap_can_add() can | |
871 | * help us to skip pte prefetch later. | |
872 | */ | |
873 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 874 | |
7eb77e9f | 875 | if (!VALID_PAGE(root_hpa)) { |
37f6a4e2 MT |
876 | WARN_ON(1); |
877 | return; | |
878 | } | |
879 | ||
f57f2ef5 | 880 | spin_lock(&vcpu->kvm->mmu_lock); |
7eb77e9f | 881 | for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) { |
a461930b AK |
882 | level = iterator.level; |
883 | sptep = iterator.sptep; | |
ad218f85 | 884 | |
f78978aa | 885 | sp = page_header(__pa(sptep)); |
884a0ff0 | 886 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
887 | pt_element_t gpte; |
888 | gpa_t pte_gpa; | |
889 | ||
f78978aa XG |
890 | if (!sp->unsync) |
891 | break; | |
892 | ||
505aef8f | 893 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 894 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 895 | |
505aef8f | 896 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
c3134ce2 LT |
897 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, |
898 | sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level)); | |
f57f2ef5 XG |
899 | |
900 | if (!rmap_can_add(vcpu)) | |
901 | break; | |
902 | ||
54bf36aa PB |
903 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
904 | sizeof(pt_element_t))) | |
f57f2ef5 XG |
905 | break; |
906 | ||
907 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 908 | } |
a7052897 | 909 | |
f78978aa | 910 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
911 | break; |
912 | } | |
ad218f85 | 913 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
914 | } |
915 | ||
1871c602 | 916 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 917 | struct x86_exception *exception) |
6aa8b732 AK |
918 | { |
919 | struct guest_walker walker; | |
e119d117 AK |
920 | gpa_t gpa = UNMAPPED_GVA; |
921 | int r; | |
6aa8b732 | 922 | |
33770780 | 923 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 924 | |
e119d117 | 925 | if (r) { |
1755fbcc | 926 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 927 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
928 | } else if (exception) |
929 | *exception = walker.fault; | |
6aa8b732 AK |
930 | |
931 | return gpa; | |
932 | } | |
933 | ||
37406aaa | 934 | #if PTTYPE != PTTYPE_EPT |
6539e738 | 935 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
936 | u32 access, |
937 | struct x86_exception *exception) | |
6539e738 JR |
938 | { |
939 | struct guest_walker walker; | |
940 | gpa_t gpa = UNMAPPED_GVA; | |
941 | int r; | |
942 | ||
33770780 | 943 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
944 | |
945 | if (r) { | |
946 | gpa = gfn_to_gpa(walker.gfn); | |
947 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
948 | } else if (exception) |
949 | *exception = walker.fault; | |
6539e738 JR |
950 | |
951 | return gpa; | |
952 | } | |
37406aaa | 953 | #endif |
6539e738 | 954 | |
e8bc217a MT |
955 | /* |
956 | * Using the cached information from sp->gfns is safe because: | |
957 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
958 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
959 | * |
960 | * Note: | |
961 | * We should flush all tlbs if spte is dropped even though guest is | |
962 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
963 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
964 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
965 | * freed pages. | |
a086f6a1 | 966 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. |
e8bc217a | 967 | */ |
a4a8e6f7 | 968 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 969 | { |
505aef8f | 970 | int i, nr_present = 0; |
9bdbba13 | 971 | bool host_writable; |
51fb60d8 | 972 | gpa_t first_pte_gpa; |
5ce4786f | 973 | int set_spte_ret = 0; |
e8bc217a | 974 | |
2032a93d LJ |
975 | /* direct kvm_mmu_page can not be unsync. */ |
976 | BUG_ON(sp->role.direct); | |
977 | ||
505aef8f | 978 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 979 | |
e8bc217a MT |
980 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
981 | unsigned pte_access; | |
982 | pt_element_t gpte; | |
983 | gpa_t pte_gpa; | |
f55c3f41 | 984 | gfn_t gfn; |
e8bc217a | 985 | |
ce88decf | 986 | if (!sp->spt[i]) |
e8bc217a MT |
987 | continue; |
988 | ||
51fb60d8 | 989 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a | 990 | |
54bf36aa PB |
991 | if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte, |
992 | sizeof(pt_element_t))) | |
1f50f1b3 | 993 | return 0; |
e8bc217a | 994 | |
0ad805a0 | 995 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
7bfdf217 LT |
996 | /* |
997 | * Update spte before increasing tlbs_dirty to make | |
998 | * sure no tlb flush is lost after spte is zapped; see | |
999 | * the comments in kvm_flush_remote_tlbs(). | |
1000 | */ | |
1001 | smp_wmb(); | |
a086f6a1 | 1002 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
1003 | continue; |
1004 | } | |
1005 | ||
ce88decf XG |
1006 | gfn = gpte_to_gfn(gpte); |
1007 | pte_access = sp->role.access; | |
42522d08 | 1008 | pte_access &= FNAME(gpte_access)(gpte); |
44dd3ffa | 1009 | FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte); |
ce88decf | 1010 | |
54bf36aa | 1011 | if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access, |
f2fd125d | 1012 | &nr_present)) |
ce88decf XG |
1013 | continue; |
1014 | ||
407c61c6 | 1015 | if (gfn != sp->gfns[i]) { |
c3707958 | 1016 | drop_spte(vcpu->kvm, &sp->spt[i]); |
7bfdf217 LT |
1017 | /* |
1018 | * The same as above where we are doing | |
1019 | * prefetch_invalid_gpte(). | |
1020 | */ | |
1021 | smp_wmb(); | |
a086f6a1 | 1022 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
1023 | continue; |
1024 | } | |
1025 | ||
1026 | nr_present++; | |
ce88decf | 1027 | |
f8e453b0 XG |
1028 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
1029 | ||
5ce4786f JS |
1030 | set_spte_ret |= set_spte(vcpu, &sp->spt[i], |
1031 | pte_access, PT_PAGE_TABLE_LEVEL, | |
1032 | gfn, spte_to_pfn(sp->spt[i]), | |
1033 | true, false, host_writable); | |
e8bc217a MT |
1034 | } |
1035 | ||
5ce4786f JS |
1036 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH) |
1037 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1038 | ||
1f50f1b3 | 1039 | return nr_present; |
e8bc217a MT |
1040 | } |
1041 | ||
6aa8b732 AK |
1042 | #undef pt_element_t |
1043 | #undef guest_walker | |
1044 | #undef FNAME | |
1045 | #undef PT_BASE_ADDR_MASK | |
1046 | #undef PT_INDEX | |
e04da980 JR |
1047 | #undef PT_LVL_ADDR_MASK |
1048 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 1049 | #undef PT_LEVEL_BITS |
cea0f0e7 | 1050 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 1051 | #undef gpte_to_gfn |
e04da980 | 1052 | #undef gpte_to_gfn_lvl |
b3e4e63f | 1053 | #undef CMPXCHG |
d8089bac GN |
1054 | #undef PT_GUEST_ACCESSED_MASK |
1055 | #undef PT_GUEST_DIRTY_MASK | |
1056 | #undef PT_GUEST_DIRTY_SHIFT | |
1057 | #undef PT_GUEST_ACCESSED_SHIFT | |
86407bcb | 1058 | #undef PT_HAVE_ACCESSED_DIRTY |