[linux-2.6-block.git] / arch / x86 / kvm / lapic.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __KVM_X86_LAPIC_H
#define __KVM_X86_LAPIC_H

#include <kvm/iodev.h>

#include <linux/kvm_host.h>

#include "hyperv.h"
#include "smm.h"

#define KVM_APIC_INIT		0
#define KVM_APIC_SIPI		1

#define APIC_SHORT_MASK			0xc0000
#define APIC_DEST_NOSHORT		0x0
#define APIC_DEST_MASK			0x800

#define APIC_BUS_CYCLE_NS       1
#define APIC_BUS_FREQUENCY      (1000000000ULL / APIC_BUS_CYCLE_NS)

#define APIC_BROADCAST			0xFF
#define X2APIC_BROADCAST		0xFFFFFFFFul

enum lapic_mode {
	LAPIC_MODE_DISABLED = 0,
	LAPIC_MODE_INVALID = X2APIC_ENABLE,
	LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
	LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
};

enum lapic_lvt_entry {
	LVT_TIMER,
	LVT_THERMAL_MONITOR,
	LVT_PERFORMANCE_COUNTER,
	LVT_LINT0,
	LVT_LINT1,
	LVT_ERROR,
	LVT_CMCI,

	KVM_APIC_MAX_NR_LVT_ENTRIES,
};

#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))

struct kvm_timer {
	struct hrtimer timer;
	s64 period; 				/* unit: ns */
	ktime_t target_expiration;
	u32 timer_mode;
	u32 timer_mode_mask;
	u64 tscdeadline;
	u64 expired_tscdeadline;
	u32 timer_advance_ns;
	atomic_t pending;			/* accumulated triggered timers */
	bool hv_timer_in_use;
};

struct kvm_lapic {
	unsigned long base_address;
	struct kvm_io_device dev;
	struct kvm_timer lapic_timer;
	u32 divide_count;
	struct kvm_vcpu *vcpu;
	bool apicv_active;
	bool sw_enabled;
	bool irr_pending;
	bool lvt0_in_nmi_mode;
	/* Number of bits set in ISR. */
	s16 isr_count;
	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
	int highest_isr_cache;
	/**
	 * APIC register page.  The layout matches the register layout seen by
	 * the guest 1:1, because it is accessed by the vmx microcode.
	 * Note: Only one register, the TPR, is used by the microcode.
	 */
	void *regs;
	gpa_t vapic_addr;
	struct gfn_to_hva_cache vapic_cache;
	unsigned long pending_events;
	unsigned int sipi_vector;
	int nr_lvt_entries;
};

struct dest_map;

int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
void kvm_free_lapic(struct kvm_vcpu *vcpu);

int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
void kvm_recalculate_apic_map(struct kvm *kvm);
void kvm_apic_set_version(struct kvm_vcpu *vcpu);
void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
			   int shorthand, unsigned int dest, int dest_mode);
int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
		     struct dest_map *dest_map);
int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
int kvm_alloc_apic_access_page(struct kvm *kvm);
void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu);

bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
		struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);

u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);

u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);

void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);

int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);

int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);

int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);

int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
void kvm_lapic_exit(void);

u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);

#define VEC_POS(v) ((v) & (32 - 1))
#define REG_POS(v) (((v) >> 5) << 4)

static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
{
	clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline void kvm_lapic_set_vector(int vec, void *bitmap)
{
	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
{
	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
	/*
	 * irr_pending must be true if any interrupt is pending; set it after
	 * APIC_IRR to avoid race with apic_clear_irr
	 */
	apic->irr_pending = true;
}

static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off)
{
	return *((u32 *) (regs + reg_off));
}

static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
{
	return __kvm_lapic_get_reg(apic->regs, reg_off);
}

DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);

static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
{
	if (static_branch_unlikely(&kvm_has_noapic_vcpu))
		return vcpu->arch.apic;
	return true;
}

extern struct static_key_false_deferred apic_hw_disabled;

static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
{
	if (static_branch_unlikely(&apic_hw_disabled.key))
		return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
	return true;
}

extern struct static_key_false_deferred apic_sw_disabled;

static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
{
	if (static_branch_unlikely(&apic_sw_disabled.key))
		return apic->sw_enabled;
	return true;
}

static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
}

static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
{
	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
}

static inline int apic_x2apic_mode(struct kvm_lapic *apic)
{
	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
}

static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
}

static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
}

static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu)
{
	return !is_smm(vcpu) &&
	       !static_call(kvm_x86_apic_init_signal_blocked)(vcpu);
}

static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
{
	return (irq->delivery_mode == APIC_DM_LOWEST ||
			irq->msi_redir_hint);
}

static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
}

bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);

void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);

void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
			      unsigned long *vcpu_bitmap);

bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
			struct kvm_vcpu **dest_vcpu);
int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
			const unsigned long *bitmap, u32 bitmap_size);
void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);

static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
{
	return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
}

static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
{
	return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
}

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
82470196 ZX	2	#ifndef __KVM_X86_LAPIC_H
	3	#define __KVM_X86_LAPIC_H
	4
af669ac6	5	#include <kvm/iodev.h>
82470196 ZX	6
	7	#include <linux/kvm_host.h>
	8
9ff5e030	9	#include "hyperv.h"
b0b42197	10	#include "smm.h"
9ff5e030	11
66450a21 JK	12	#define KVM_APIC_INIT 0
	13	#define KVM_APIC_SIPI 1
	14
ac8ef992 PX	15	#define APIC_SHORT_MASK 0xc0000
	16	#define APIC_DEST_NOSHORT 0x0
	17	#define APIC_DEST_MASK 0x800
18f40c53	18
72c139ba LP	19	#define APIC_BUS_CYCLE_NS 1
	20	#define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
	21
4064a4c6 WL	22	#define APIC_BROADCAST 0xFF
	23	#define X2APIC_BROADCAST 0xFFFFFFFFul
	24
58871649 JM	25	enum lapic_mode {
	26	LAPIC_MODE_DISABLED = 0,
	27	LAPIC_MODE_INVALID = X2APIC_ENABLE,
	28	LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
	29	LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE \| X2APIC_ENABLE,
	30	};
	31
1d8c681f JW	32	enum lapic_lvt_entry {
	33	LVT_TIMER,
	34	LVT_THERMAL_MONITOR,
	35	LVT_PERFORMANCE_COUNTER,
	36	LVT_LINT0,
	37	LVT_LINT1,
	38	LVT_ERROR,
4b903561	39	LVT_CMCI,
1d8c681f JW	40
	41	KVM_APIC_MAX_NR_LVT_ENTRIES,
	42	};
	43
4b903561	44	#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))
987f625e	45
e9d90d47 AK	46	struct kvm_timer {
	47	struct hrtimer timer;
	48	s64 period; /* unit: ns */
8003c9ae	49	ktime_t target_expiration;
a323b409	50	u32 timer_mode;
e9d90d47 AK	51	u32 timer_mode_mask;
e9d90d47 AK	52	u64 tscdeadline;
d0659d94	53	u64 expired_tscdeadline;
39497d76	54	u32 timer_advance_ns;
e9d90d47	55	atomic_t pending; /* accumulated triggered timers */
ce7a058a	56	bool hv_timer_in_use;
e9d90d47 AK	57	};
e9d90d47 AK	58
82470196 ZX	59	struct kvm_lapic {
	60	unsigned long base_address;
	61	struct kvm_io_device dev;
d3c7b77d MT	62	struct kvm_timer lapic_timer;
d3c7b77d MT	63	u32 divide_count;
82470196	64	struct kvm_vcpu *vcpu;
ce0a58f4	65	bool apicv_active;
e462755c	66	bool sw_enabled;
33e4c686	67	bool irr_pending;
59fd1323	68	bool lvt0_in_nmi_mode;
8680b94b MT	69	/* Number of bits set in ISR. */
	70	s16 isr_count;
	71	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
	72	int highest_isr_cache;
5eadf916 MT	73	/**
	74	* APIC register page. The layout matches the register layout seen by
	75	* the guest 1:1, because it is accessed by the vmx microcode.
	76	* Note: Only one register, the TPR, is used by the microcode.
	77	*/
82470196	78	void *regs;
b93463aa	79	gpa_t vapic_addr;
fda4e2e8	80	struct gfn_to_hva_cache vapic_cache;
66450a21 JK	81	unsigned long pending_events;
66450a21 JK	82	unsigned int sipi_vector;
4b903561	83	int nr_lvt_entries;
82470196	84	};
9e4aabe2 JR	85
	86	struct dest_map;
	87
c3941d9e	88	int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
82470196 ZX	89	void kvm_free_lapic(struct kvm_vcpu *vcpu);
	90
	91	int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
	92	int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
	93	int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
4fe09bcf	94	int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
d28bc9dd	95	void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
82470196 ZX	96	u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
82470196 ZX	97	void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
58fbbf26	98	void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
82470196	99	void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
8b2cf73c	100	u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
4abaffce	101	void kvm_recalculate_apic_map(struct kvm *kvm);
fc61b800	102	void kvm_apic_set_version(struct kvm_vcpu *vcpu);
f83894b2	103	void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
1e6e2755	104	bool kvm_apic_match_dest(struct kvm_vcpu vcpu, struct kvm_lapic source,
5c69d5c1	105	int shorthand, unsigned int dest, int dest_mode);
59508b30	106	int kvm_apic_compare_prio(struct kvm_vcpu vcpu1, struct kvm_vcpu vcpu2);
25bb2cf9	107	void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
e7387b0e LA	108	bool __kvm_apic_update_irr(u32 pir, void regs, int *max_irr);
e7387b0e LA	109	bool kvm_apic_update_irr(struct kvm_vcpu vcpu, u32 pir, int *max_irr);
eb90f341	110	void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
b4f2225c	111	int kvm_apic_set_irq(struct kvm_vcpu vcpu, struct kvm_lapic_irq irq,
9e4aabe2	112	struct dest_map *dest_map);
89342082	113	int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
b26a695a	114	void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
c482f2ce	115	int kvm_alloc_apic_access_page(struct kvm *kvm);
2008fab3	116	void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu);
82470196	117
1e08ec4a	118	bool kvm_irq_delivery_to_apic_fast(struct kvm kvm, struct kvm_lapic src,
9e4aabe2	119	struct kvm_lapic_irq irq, int r, struct dest_map *dest_map);
d5361678	120	void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
1e08ec4a	121
82470196	122	u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
58cb628d	123	int kvm_set_apic_base(struct kvm_vcpu vcpu, struct msr_data msr_info);
a92e2543 RK	124	int kvm_apic_get_state(struct kvm_vcpu vcpu, struct kvm_lapic_state s);
a92e2543 RK	125	int kvm_apic_set_state(struct kvm_vcpu vcpu, struct kvm_lapic_state s);
58871649	126	enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
82470196	127	int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
82470196	128
a3e06bbe LJ	129	u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
	130	void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
	131
83d4c286	132	void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
c7c9c56c	133	void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
83d4c286	134
fda4e2e8	135	int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
b93463aa AK	136	void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
	137	void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
	138
b9964ee3	139	int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
0105d1a5 GN	140	int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
0105d1a5 GN	141	int kvm_x2apic_msr_read(struct kvm_vcpu vcpu, u32 msr, u64 data);
10388a07 GN	142
	143	int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
	144	int kvm_hv_vapic_msr_read(struct kvm_vcpu vcpu, u32 msr, u64 data);
	145
77c3323f	146	int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
cef84c30	147	void kvm_lapic_exit(void);
c48f1496	148
b5fcc59b SC	149	u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
b5fcc59b SC	150
1e6e2755 SS	151	#define VEC_POS(v) ((v) & (32 - 1))
	152	#define REG_POS(v) (((v) >> 5) << 4)
	153
ee171d2f WY	154	static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
	155	{
	156	clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
	157	}
	158
1e6e2755 SS	159	static inline void kvm_lapic_set_vector(int vec, void *bitmap)
	160	{
	161	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
	162	}
	163
	164	static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
	165	{
	166	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
	167	/*
	168	* irr_pending must be true if any interrupt is pending; set it after
	169	* APIC_IRR to avoid race with apic_clear_irr
	170	*/
	171	apic->irr_pending = true;
	172	}
	173
b9964ee3	174	static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off)
c48f1496	175	{
b9964ee3	176	return ((u32 ) (regs + reg_off));
c48f1496 GN	177	}
c48f1496 GN	178
b9964ee3	179	static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
1e6e2755	180	{
b9964ee3	181	return __kvm_lapic_get_reg(apic->regs, reg_off);
1e6e2755 SS	182	}
1e6e2755 SS	183
6e4e3b4d	184	DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
c48f1496	185
bce87cce	186	static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
c48f1496	187	{
6e4e3b4d	188	if (static_branch_unlikely(&kvm_has_noapic_vcpu))
c48f1496 GN	189	return vcpu->arch.apic;
	190	return true;
	191	}
	192
6e4e3b4d	193	extern struct static_key_false_deferred apic_hw_disabled;
c48f1496	194
3c649918	195	static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
c48f1496	196	{
6e4e3b4d	197	if (static_branch_unlikely(&apic_hw_disabled.key))
c48f1496	198	return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
3c649918	199	return true;
c48f1496 GN	200	}
c48f1496 GN	201
6e4e3b4d	202	extern struct static_key_false_deferred apic_sw_disabled;
c48f1496	203
f30ebc31	204	static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
c48f1496	205	{
6e4e3b4d	206	if (static_branch_unlikely(&apic_sw_disabled.key))
f30ebc31 RK	207	return apic->sw_enabled;
f30ebc31 RK	208	return true;
c48f1496 GN	209	}
	210
	211	static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
	212	{
bce87cce	213	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
c48f1496 GN	214	}
	215
	216	static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
	217	{
	218	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
	219	}
	220
8d14695f YZ	221	static inline int apic_x2apic_mode(struct kvm_lapic *apic)
	222	{
	223	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
	224	}
	225
d62caabb	226	static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
c7c9c56c	227	{
b8e1b962	228	return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
c7c9c56c YZ	229	}
c7c9c56c YZ	230
a61353ac	231	static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu)
66450a21	232	{
bce87cce	233	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
66450a21 JK	234	}
66450a21 JK	235
1b7a1b78 SC	236	static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu)
	237	{
	238	return !is_smm(vcpu) &&
	239	!static_call(kvm_x86_apic_init_signal_blocked)(vcpu);
	240	}
	241
d1ebdbf9 JS	242	static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
	243	{
	244	return (irq->delivery_mode == APIC_DM_LOWEST \|\|
	245	irq->msi_redir_hint);
	246	}
	247
f077825a PB	248	static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
f077825a PB	249	{
bce87cce	250	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
f077825a PB	251	}
f077825a PB	252
10606919 YZ	253	bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
10606919 YZ	254
b6c4bc65	255	void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
d0659d94	256
7ee30bc1 NNL	257	void kvm_bitmap_or_dest_vcpus(struct kvm kvm, struct kvm_lapic_irq irq,
	258	unsigned long *vcpu_bitmap);
	259
8feb4a04 FW	260	bool kvm_intr_is_single_vcpu_fast(struct kvm kvm, struct kvm_lapic_irq irq,
8feb4a04 FW	261	struct kvm_vcpu **dest_vcpu);
52004014 FW	262	int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
52004014 FW	263	const unsigned long *bitmap, u32 bitmap_size);
ce7a058a YJ	264	void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
	265	void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
	266	void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
	267	bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
a749e247	268	void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
199a8b84	269	bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
58871649 JM	270
	271	static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
	272	{
	273	return apic_base & (MSR_IA32_APICBASE_ENABLE \| X2APIC_ENABLE);
	274	}
	275
5c94ac5d ML	276	static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
	277	{
	278	return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
	279	}
	280
82470196	281	#endif