Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
bfc0f594 | 3 | #include <linux/kernel.h> |
0ef95533 | 4 | #include <linux/sched.h> |
e6017571 | 5 | #include <linux/sched/clock.h> |
0ef95533 | 6 | #include <linux/init.h> |
186f4360 | 7 | #include <linux/export.h> |
0ef95533 | 8 | #include <linux/timer.h> |
bfc0f594 | 9 | #include <linux/acpi_pmtmr.h> |
2dbe06fa | 10 | #include <linux/cpufreq.h> |
8fbbc4b4 AK |
11 | #include <linux/delay.h> |
12 | #include <linux/clocksource.h> | |
13 | #include <linux/percpu.h> | |
08604bd9 | 14 | #include <linux/timex.h> |
10b033d4 | 15 | #include <linux/static_key.h> |
bfc0f594 AK |
16 | |
17 | #include <asm/hpet.h> | |
8fbbc4b4 AK |
18 | #include <asm/timer.h> |
19 | #include <asm/vgtod.h> | |
20 | #include <asm/time.h> | |
21 | #include <asm/delay.h> | |
88b094fb | 22 | #include <asm/hypervisor.h> |
08047c4f | 23 | #include <asm/nmi.h> |
2d826404 | 24 | #include <asm/x86_init.h> |
03da3ff1 | 25 | #include <asm/geode.h> |
6731b0d6 | 26 | #include <asm/apic.h> |
655e52d2 | 27 | #include <asm/intel-family.h> |
30c7e5b1 | 28 | #include <asm/i8259.h> |
0ef95533 | 29 | |
f24ade3a | 30 | unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ |
0ef95533 | 31 | EXPORT_SYMBOL(cpu_khz); |
f24ade3a IM |
32 | |
33 | unsigned int __read_mostly tsc_khz; | |
0ef95533 AK |
34 | EXPORT_SYMBOL(tsc_khz); |
35 | ||
cf7a63ef PT |
36 | #define KHZ 1000 |
37 | ||
0ef95533 AK |
38 | /* |
39 | * TSC can be unstable due to cpufreq or due to unsynced TSCs | |
40 | */ | |
f24ade3a | 41 | static int __read_mostly tsc_unstable; |
0ef95533 | 42 | |
3bbfafb7 | 43 | static DEFINE_STATIC_KEY_FALSE(__use_tsc); |
10b033d4 | 44 | |
28a00184 | 45 | int tsc_clocksource_reliable; |
57c67da2 | 46 | |
f9677e0f CH |
47 | static u32 art_to_tsc_numerator; |
48 | static u32 art_to_tsc_denominator; | |
49 | static u64 art_to_tsc_offset; | |
50 | struct clocksource *art_related_clocksource; | |
51 | ||
20d1c86a | 52 | struct cyc2ns { |
59eaef78 PZ |
53 | struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */ |
54 | seqcount_t seq; /* 32 + 4 = 36 */ | |
20d1c86a | 55 | |
59eaef78 | 56 | }; /* fits one cacheline */ |
20d1c86a | 57 | |
59eaef78 | 58 | static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns); |
20d1c86a | 59 | |
59eaef78 | 60 | void cyc2ns_read_begin(struct cyc2ns_data *data) |
20d1c86a | 61 | { |
59eaef78 | 62 | int seq, idx; |
20d1c86a | 63 | |
59eaef78 | 64 | preempt_disable_notrace(); |
20d1c86a | 65 | |
59eaef78 PZ |
66 | do { |
67 | seq = this_cpu_read(cyc2ns.seq.sequence); | |
68 | idx = seq & 1; | |
20d1c86a | 69 | |
59eaef78 PZ |
70 | data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset); |
71 | data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul); | |
72 | data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift); | |
20d1c86a | 73 | |
59eaef78 | 74 | } while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence))); |
20d1c86a PZ |
75 | } |
76 | ||
59eaef78 | 77 | void cyc2ns_read_end(void) |
20d1c86a | 78 | { |
59eaef78 | 79 | preempt_enable_notrace(); |
20d1c86a PZ |
80 | } |
81 | ||
82 | /* | |
83 | * Accelerators for sched_clock() | |
57c67da2 PZ |
84 | * convert from cycles(64bits) => nanoseconds (64bits) |
85 | * basic equation: | |
86 | * ns = cycles / (freq / ns_per_sec) | |
87 | * ns = cycles * (ns_per_sec / freq) | |
88 | * ns = cycles * (10^9 / (cpu_khz * 10^3)) | |
89 | * ns = cycles * (10^6 / cpu_khz) | |
90 | * | |
91 | * Then we use scaling math (suggested by george@mvista.com) to get: | |
92 | * ns = cycles * (10^6 * SC / cpu_khz) / SC | |
93 | * ns = cycles * cyc2ns_scale / SC | |
94 | * | |
95 | * And since SC is a constant power of two, we can convert the div | |
b20112ed AH |
96 | * into a shift. The larger SC is, the more accurate the conversion, but |
97 | * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication | |
98 | * (64-bit result) can be used. | |
57c67da2 | 99 | * |
b20112ed | 100 | * We can use khz divisor instead of mhz to keep a better precision. |
57c67da2 PZ |
101 | * (mathieu.desnoyers@polymtl.ca) |
102 | * | |
103 | * -johnstul@us.ibm.com "math is hard, lets go shopping!" | |
104 | */ | |
105 | ||
20d1c86a PZ |
106 | static void cyc2ns_data_init(struct cyc2ns_data *data) |
107 | { | |
5e3c1afd | 108 | data->cyc2ns_mul = 0; |
b20112ed | 109 | data->cyc2ns_shift = 0; |
20d1c86a | 110 | data->cyc2ns_offset = 0; |
20d1c86a PZ |
111 | } |
112 | ||
120fc3fb | 113 | static void __init cyc2ns_init(int cpu) |
20d1c86a PZ |
114 | { |
115 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
116 | ||
117 | cyc2ns_data_init(&c2n->data[0]); | |
118 | cyc2ns_data_init(&c2n->data[1]); | |
119 | ||
59eaef78 | 120 | seqcount_init(&c2n->seq); |
20d1c86a PZ |
121 | } |
122 | ||
57c67da2 PZ |
123 | static inline unsigned long long cycles_2_ns(unsigned long long cyc) |
124 | { | |
59eaef78 | 125 | struct cyc2ns_data data; |
20d1c86a PZ |
126 | unsigned long long ns; |
127 | ||
59eaef78 | 128 | cyc2ns_read_begin(&data); |
20d1c86a | 129 | |
59eaef78 PZ |
130 | ns = data.cyc2ns_offset; |
131 | ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift); | |
20d1c86a | 132 | |
59eaef78 | 133 | cyc2ns_read_end(); |
20d1c86a | 134 | |
57c67da2 PZ |
135 | return ns; |
136 | } | |
137 | ||
5c3c2ea6 | 138 | static void set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now) |
57c67da2 | 139 | { |
615cd033 | 140 | unsigned long long ns_now; |
59eaef78 PZ |
141 | struct cyc2ns_data data; |
142 | struct cyc2ns *c2n; | |
20d1c86a | 143 | unsigned long flags; |
57c67da2 PZ |
144 | |
145 | local_irq_save(flags); | |
146 | sched_clock_idle_sleep_event(); | |
147 | ||
aa297292 | 148 | if (!khz) |
20d1c86a PZ |
149 | goto done; |
150 | ||
57c67da2 PZ |
151 | ns_now = cycles_2_ns(tsc_now); |
152 | ||
20d1c86a PZ |
153 | /* |
154 | * Compute a new multiplier as per the above comment and ensure our | |
155 | * time function is continuous; see the comment near struct | |
156 | * cyc2ns_data. | |
157 | */ | |
59eaef78 | 158 | clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz, |
b20112ed AH |
159 | NSEC_PER_MSEC, 0); |
160 | ||
b9511cd7 AH |
161 | /* |
162 | * cyc2ns_shift is exported via arch_perf_update_userpage() where it is | |
163 | * not expected to be greater than 31 due to the original published | |
164 | * conversion algorithm shifting a 32-bit value (now specifies a 64-bit | |
165 | * value) - refer perf_event_mmap_page documentation in perf_event.h. | |
166 | */ | |
59eaef78 PZ |
167 | if (data.cyc2ns_shift == 32) { |
168 | data.cyc2ns_shift = 31; | |
169 | data.cyc2ns_mul >>= 1; | |
b9511cd7 AH |
170 | } |
171 | ||
59eaef78 PZ |
172 | data.cyc2ns_offset = ns_now - |
173 | mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift); | |
174 | ||
175 | c2n = per_cpu_ptr(&cyc2ns, cpu); | |
20d1c86a | 176 | |
59eaef78 PZ |
177 | raw_write_seqcount_latch(&c2n->seq); |
178 | c2n->data[0] = data; | |
179 | raw_write_seqcount_latch(&c2n->seq); | |
180 | c2n->data[1] = data; | |
57c67da2 | 181 | |
20d1c86a | 182 | done: |
ac1e843f | 183 | sched_clock_idle_wakeup_event(); |
57c67da2 PZ |
184 | local_irq_restore(flags); |
185 | } | |
615cd033 | 186 | |
0ef95533 AK |
187 | /* |
188 | * Scheduler clock - returns current time in nanosec units. | |
189 | */ | |
190 | u64 native_sched_clock(void) | |
191 | { | |
3bbfafb7 PZ |
192 | if (static_branch_likely(&__use_tsc)) { |
193 | u64 tsc_now = rdtsc(); | |
194 | ||
195 | /* return the value in ns */ | |
196 | return cycles_2_ns(tsc_now); | |
197 | } | |
0ef95533 AK |
198 | |
199 | /* | |
200 | * Fall back to jiffies if there's no TSC available: | |
201 | * ( But note that we still use it if the TSC is marked | |
202 | * unstable. We do this because unlike Time Of Day, | |
203 | * the scheduler clock tolerates small errors and it's | |
204 | * very important for it to be as fast as the platform | |
3ad2f3fb | 205 | * can achieve it. ) |
0ef95533 | 206 | */ |
0ef95533 | 207 | |
3bbfafb7 PZ |
208 | /* No locking but a rare wrong value is not a big deal: */ |
209 | return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); | |
0ef95533 AK |
210 | } |
211 | ||
a94cab23 AK |
212 | /* |
213 | * Generate a sched_clock if you already have a TSC value. | |
214 | */ | |
215 | u64 native_sched_clock_from_tsc(u64 tsc) | |
216 | { | |
217 | return cycles_2_ns(tsc); | |
218 | } | |
219 | ||
0ef95533 AK |
220 | /* We need to define a real function for sched_clock, to override the |
221 | weak default version */ | |
222 | #ifdef CONFIG_PARAVIRT | |
223 | unsigned long long sched_clock(void) | |
224 | { | |
225 | return paravirt_sched_clock(); | |
226 | } | |
f94c8d11 | 227 | |
698eff63 | 228 | bool using_native_sched_clock(void) |
f94c8d11 PZ |
229 | { |
230 | return pv_time_ops.sched_clock == native_sched_clock; | |
231 | } | |
0ef95533 AK |
232 | #else |
233 | unsigned long long | |
234 | sched_clock(void) __attribute__((alias("native_sched_clock"))); | |
f94c8d11 | 235 | |
698eff63 | 236 | bool using_native_sched_clock(void) { return true; } |
0ef95533 AK |
237 | #endif |
238 | ||
239 | int check_tsc_unstable(void) | |
240 | { | |
241 | return tsc_unstable; | |
242 | } | |
243 | EXPORT_SYMBOL_GPL(check_tsc_unstable); | |
244 | ||
245 | #ifdef CONFIG_X86_TSC | |
246 | int __init notsc_setup(char *str) | |
247 | { | |
fe9af81e | 248 | mark_tsc_unstable("boot parameter notsc"); |
0ef95533 AK |
249 | return 1; |
250 | } | |
251 | #else | |
252 | /* | |
253 | * disable flag for tsc. Takes effect by clearing the TSC cpu flag | |
254 | * in cpu/common.c | |
255 | */ | |
256 | int __init notsc_setup(char *str) | |
257 | { | |
258 | setup_clear_cpu_cap(X86_FEATURE_TSC); | |
259 | return 1; | |
260 | } | |
261 | #endif | |
262 | ||
263 | __setup("notsc", notsc_setup); | |
bfc0f594 | 264 | |
e82b8e4e VP |
265 | static int no_sched_irq_time; |
266 | ||
395628ef AK |
267 | static int __init tsc_setup(char *str) |
268 | { | |
269 | if (!strcmp(str, "reliable")) | |
270 | tsc_clocksource_reliable = 1; | |
e82b8e4e VP |
271 | if (!strncmp(str, "noirqtime", 9)) |
272 | no_sched_irq_time = 1; | |
8309f86c PZ |
273 | if (!strcmp(str, "unstable")) |
274 | mark_tsc_unstable("boot parameter"); | |
395628ef AK |
275 | return 1; |
276 | } | |
277 | ||
278 | __setup("tsc=", tsc_setup); | |
279 | ||
bfc0f594 AK |
280 | #define MAX_RETRIES 5 |
281 | #define SMI_TRESHOLD 50000 | |
282 | ||
283 | /* | |
284 | * Read TSC and the reference counters. Take care of SMI disturbance | |
285 | */ | |
827014be | 286 | static u64 tsc_read_refs(u64 *p, int hpet) |
bfc0f594 AK |
287 | { |
288 | u64 t1, t2; | |
289 | int i; | |
290 | ||
291 | for (i = 0; i < MAX_RETRIES; i++) { | |
292 | t1 = get_cycles(); | |
293 | if (hpet) | |
827014be | 294 | *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; |
bfc0f594 | 295 | else |
827014be | 296 | *p = acpi_pm_read_early(); |
bfc0f594 AK |
297 | t2 = get_cycles(); |
298 | if ((t2 - t1) < SMI_TRESHOLD) | |
299 | return t2; | |
300 | } | |
301 | return ULLONG_MAX; | |
302 | } | |
303 | ||
d683ef7a TG |
304 | /* |
305 | * Calculate the TSC frequency from HPET reference | |
bfc0f594 | 306 | */ |
d683ef7a | 307 | static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) |
bfc0f594 | 308 | { |
d683ef7a | 309 | u64 tmp; |
bfc0f594 | 310 | |
d683ef7a TG |
311 | if (hpet2 < hpet1) |
312 | hpet2 += 0x100000000ULL; | |
313 | hpet2 -= hpet1; | |
314 | tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); | |
315 | do_div(tmp, 1000000); | |
d3878e16 | 316 | deltatsc = div64_u64(deltatsc, tmp); |
d683ef7a TG |
317 | |
318 | return (unsigned long) deltatsc; | |
319 | } | |
320 | ||
321 | /* | |
322 | * Calculate the TSC frequency from PMTimer reference | |
323 | */ | |
324 | static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) | |
325 | { | |
326 | u64 tmp; | |
bfc0f594 | 327 | |
d683ef7a TG |
328 | if (!pm1 && !pm2) |
329 | return ULONG_MAX; | |
330 | ||
331 | if (pm2 < pm1) | |
332 | pm2 += (u64)ACPI_PM_OVRRUN; | |
333 | pm2 -= pm1; | |
334 | tmp = pm2 * 1000000000LL; | |
335 | do_div(tmp, PMTMR_TICKS_PER_SEC); | |
336 | do_div(deltatsc, tmp); | |
337 | ||
338 | return (unsigned long) deltatsc; | |
339 | } | |
340 | ||
a977c400 | 341 | #define CAL_MS 10 |
b7743970 | 342 | #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS)) |
a977c400 TG |
343 | #define CAL_PIT_LOOPS 1000 |
344 | ||
345 | #define CAL2_MS 50 | |
b7743970 | 346 | #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS)) |
a977c400 TG |
347 | #define CAL2_PIT_LOOPS 5000 |
348 | ||
cce3e057 | 349 | |
ec0c15af LT |
350 | /* |
351 | * Try to calibrate the TSC against the Programmable | |
352 | * Interrupt Timer and return the frequency of the TSC | |
353 | * in kHz. | |
354 | * | |
355 | * Return ULONG_MAX on failure to calibrate. | |
356 | */ | |
a977c400 | 357 | static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) |
ec0c15af LT |
358 | { |
359 | u64 tsc, t1, t2, delta; | |
360 | unsigned long tscmin, tscmax; | |
361 | int pitcnt; | |
362 | ||
30c7e5b1 PZ |
363 | if (!has_legacy_pic()) { |
364 | /* | |
365 | * Relies on tsc_early_delay_calibrate() to have given us semi | |
366 | * usable udelay(), wait for the same 50ms we would have with | |
367 | * the PIT loop below. | |
368 | */ | |
369 | udelay(10 * USEC_PER_MSEC); | |
370 | udelay(10 * USEC_PER_MSEC); | |
371 | udelay(10 * USEC_PER_MSEC); | |
372 | udelay(10 * USEC_PER_MSEC); | |
373 | udelay(10 * USEC_PER_MSEC); | |
374 | return ULONG_MAX; | |
375 | } | |
376 | ||
ec0c15af LT |
377 | /* Set the Gate high, disable speaker */ |
378 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | |
379 | ||
380 | /* | |
381 | * Setup CTC channel 2* for mode 0, (interrupt on terminal | |
382 | * count mode), binary count. Set the latch register to 50ms | |
383 | * (LSB then MSB) to begin countdown. | |
384 | */ | |
385 | outb(0xb0, 0x43); | |
a977c400 TG |
386 | outb(latch & 0xff, 0x42); |
387 | outb(latch >> 8, 0x42); | |
ec0c15af LT |
388 | |
389 | tsc = t1 = t2 = get_cycles(); | |
390 | ||
391 | pitcnt = 0; | |
392 | tscmax = 0; | |
393 | tscmin = ULONG_MAX; | |
394 | while ((inb(0x61) & 0x20) == 0) { | |
395 | t2 = get_cycles(); | |
396 | delta = t2 - tsc; | |
397 | tsc = t2; | |
398 | if ((unsigned long) delta < tscmin) | |
399 | tscmin = (unsigned int) delta; | |
400 | if ((unsigned long) delta > tscmax) | |
401 | tscmax = (unsigned int) delta; | |
402 | pitcnt++; | |
403 | } | |
404 | ||
405 | /* | |
406 | * Sanity checks: | |
407 | * | |
a977c400 | 408 | * If we were not able to read the PIT more than loopmin |
ec0c15af LT |
409 | * times, then we have been hit by a massive SMI |
410 | * | |
411 | * If the maximum is 10 times larger than the minimum, | |
412 | * then we got hit by an SMI as well. | |
413 | */ | |
a977c400 | 414 | if (pitcnt < loopmin || tscmax > 10 * tscmin) |
ec0c15af LT |
415 | return ULONG_MAX; |
416 | ||
417 | /* Calculate the PIT value */ | |
418 | delta = t2 - t1; | |
a977c400 | 419 | do_div(delta, ms); |
ec0c15af LT |
420 | return delta; |
421 | } | |
422 | ||
6ac40ed0 LT |
423 | /* |
424 | * This reads the current MSB of the PIT counter, and | |
425 | * checks if we are running on sufficiently fast and | |
426 | * non-virtualized hardware. | |
427 | * | |
428 | * Our expectations are: | |
429 | * | |
430 | * - the PIT is running at roughly 1.19MHz | |
431 | * | |
432 | * - each IO is going to take about 1us on real hardware, | |
433 | * but we allow it to be much faster (by a factor of 10) or | |
434 | * _slightly_ slower (ie we allow up to a 2us read+counter | |
435 | * update - anything else implies a unacceptably slow CPU | |
436 | * or PIT for the fast calibration to work. | |
437 | * | |
438 | * - with 256 PIT ticks to read the value, we have 214us to | |
439 | * see the same MSB (and overhead like doing a single TSC | |
440 | * read per MSB value etc). | |
441 | * | |
442 | * - We're doing 2 reads per loop (LSB, MSB), and we expect | |
443 | * them each to take about a microsecond on real hardware. | |
444 | * So we expect a count value of around 100. But we'll be | |
445 | * generous, and accept anything over 50. | |
446 | * | |
447 | * - if the PIT is stuck, and we see *many* more reads, we | |
448 | * return early (and the next caller of pit_expect_msb() | |
449 | * then consider it a failure when they don't see the | |
450 | * next expected value). | |
451 | * | |
452 | * These expectations mean that we know that we have seen the | |
453 | * transition from one expected value to another with a fairly | |
454 | * high accuracy, and we didn't miss any events. We can thus | |
455 | * use the TSC value at the transitions to calculate a pretty | |
456 | * good value for the TSC frequencty. | |
457 | */ | |
b6e61eef LT |
458 | static inline int pit_verify_msb(unsigned char val) |
459 | { | |
460 | /* Ignore LSB */ | |
461 | inb(0x42); | |
462 | return inb(0x42) == val; | |
463 | } | |
464 | ||
9e8912e0 | 465 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
6ac40ed0 | 466 | { |
9e8912e0 | 467 | int count; |
68f30fbe | 468 | u64 tsc = 0, prev_tsc = 0; |
bfc0f594 | 469 | |
6ac40ed0 | 470 | for (count = 0; count < 50000; count++) { |
b6e61eef | 471 | if (!pit_verify_msb(val)) |
6ac40ed0 | 472 | break; |
68f30fbe | 473 | prev_tsc = tsc; |
9e8912e0 | 474 | tsc = get_cycles(); |
6ac40ed0 | 475 | } |
68f30fbe | 476 | *deltap = get_cycles() - prev_tsc; |
9e8912e0 LT |
477 | *tscp = tsc; |
478 | ||
479 | /* | |
480 | * We require _some_ success, but the quality control | |
481 | * will be based on the error terms on the TSC values. | |
482 | */ | |
483 | return count > 5; | |
6ac40ed0 LT |
484 | } |
485 | ||
486 | /* | |
9e8912e0 LT |
487 | * How many MSB values do we want to see? We aim for |
488 | * a maximum error rate of 500ppm (in practice the | |
489 | * real error is much smaller), but refuse to spend | |
68f30fbe | 490 | * more than 50ms on it. |
6ac40ed0 | 491 | */ |
68f30fbe | 492 | #define MAX_QUICK_PIT_MS 50 |
9e8912e0 | 493 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
bfc0f594 | 494 | |
6ac40ed0 LT |
495 | static unsigned long quick_pit_calibrate(void) |
496 | { | |
9e8912e0 LT |
497 | int i; |
498 | u64 tsc, delta; | |
499 | unsigned long d1, d2; | |
500 | ||
30c7e5b1 PZ |
501 | if (!has_legacy_pic()) |
502 | return 0; | |
503 | ||
6ac40ed0 | 504 | /* Set the Gate high, disable speaker */ |
bfc0f594 AK |
505 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
506 | ||
6ac40ed0 LT |
507 | /* |
508 | * Counter 2, mode 0 (one-shot), binary count | |
509 | * | |
510 | * NOTE! Mode 2 decrements by two (and then the | |
511 | * output is flipped each time, giving the same | |
512 | * final output frequency as a decrement-by-one), | |
513 | * so mode 0 is much better when looking at the | |
514 | * individual counts. | |
515 | */ | |
bfc0f594 | 516 | outb(0xb0, 0x43); |
bfc0f594 | 517 | |
6ac40ed0 LT |
518 | /* Start at 0xffff */ |
519 | outb(0xff, 0x42); | |
520 | outb(0xff, 0x42); | |
521 | ||
a6a80e1d LT |
522 | /* |
523 | * The PIT starts counting at the next edge, so we | |
524 | * need to delay for a microsecond. The easiest way | |
525 | * to do that is to just read back the 16-bit counter | |
526 | * once from the PIT. | |
527 | */ | |
b6e61eef | 528 | pit_verify_msb(0); |
a6a80e1d | 529 | |
9e8912e0 LT |
530 | if (pit_expect_msb(0xff, &tsc, &d1)) { |
531 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | |
532 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | |
533 | break; | |
534 | ||
5aac644a AH |
535 | delta -= tsc; |
536 | ||
537 | /* | |
538 | * Extrapolate the error and fail fast if the error will | |
539 | * never be below 500 ppm. | |
540 | */ | |
541 | if (i == 1 && | |
542 | d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11) | |
543 | return 0; | |
544 | ||
9e8912e0 LT |
545 | /* |
546 | * Iterate until the error is less than 500 ppm | |
547 | */ | |
b6e61eef LT |
548 | if (d1+d2 >= delta >> 11) |
549 | continue; | |
550 | ||
551 | /* | |
552 | * Check the PIT one more time to verify that | |
553 | * all TSC reads were stable wrt the PIT. | |
554 | * | |
555 | * This also guarantees serialization of the | |
556 | * last cycle read ('d2') in pit_expect_msb. | |
557 | */ | |
558 | if (!pit_verify_msb(0xfe - i)) | |
559 | break; | |
560 | goto success; | |
6ac40ed0 | 561 | } |
6ac40ed0 | 562 | } |
52045217 | 563 | pr_info("Fast TSC calibration failed\n"); |
6ac40ed0 | 564 | return 0; |
9e8912e0 LT |
565 | |
566 | success: | |
567 | /* | |
568 | * Ok, if we get here, then we've seen the | |
569 | * MSB of the PIT decrement 'i' times, and the | |
570 | * error has shrunk to less than 500 ppm. | |
571 | * | |
572 | * As a result, we can depend on there not being | |
573 | * any odd delays anywhere, and the TSC reads are | |
68f30fbe | 574 | * reliable (within the error). |
9e8912e0 LT |
575 | * |
576 | * kHz = ticks / time-in-seconds / 1000; | |
577 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | |
578 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | |
579 | */ | |
9e8912e0 LT |
580 | delta *= PIT_TICK_RATE; |
581 | do_div(delta, i*256*1000); | |
c767a54b | 582 | pr_info("Fast TSC calibration using PIT\n"); |
9e8912e0 | 583 | return delta; |
6ac40ed0 | 584 | } |
ec0c15af | 585 | |
bfc0f594 | 586 | /** |
aa297292 LB |
587 | * native_calibrate_tsc |
588 | * Determine TSC frequency via CPUID, else return 0. | |
bfc0f594 | 589 | */ |
e93ef949 | 590 | unsigned long native_calibrate_tsc(void) |
aa297292 LB |
591 | { |
592 | unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; | |
593 | unsigned int crystal_khz; | |
594 | ||
595 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
596 | return 0; | |
597 | ||
598 | if (boot_cpu_data.cpuid_level < 0x15) | |
599 | return 0; | |
600 | ||
601 | eax_denominator = ebx_numerator = ecx_hz = edx = 0; | |
602 | ||
603 | /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ | |
604 | cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); | |
605 | ||
606 | if (ebx_numerator == 0 || eax_denominator == 0) | |
607 | return 0; | |
608 | ||
609 | crystal_khz = ecx_hz / 1000; | |
610 | ||
611 | if (crystal_khz == 0) { | |
612 | switch (boot_cpu_data.x86_model) { | |
655e52d2 PB |
613 | case INTEL_FAM6_SKYLAKE_MOBILE: |
614 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
6baf3d61 PB |
615 | case INTEL_FAM6_KABYLAKE_MOBILE: |
616 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
ff4c8663 LB |
617 | crystal_khz = 24000; /* 24.0 MHz */ |
618 | break; | |
695085b4 | 619 | case INTEL_FAM6_ATOM_DENVERTON: |
6baf3d61 PB |
620 | crystal_khz = 25000; /* 25.0 MHz */ |
621 | break; | |
655e52d2 | 622 | case INTEL_FAM6_ATOM_GOLDMONT: |
ff4c8663 LB |
623 | crystal_khz = 19200; /* 19.2 MHz */ |
624 | break; | |
aa297292 LB |
625 | } |
626 | } | |
627 | ||
da4ae6c4 LB |
628 | if (crystal_khz == 0) |
629 | return 0; | |
4ca4df0b BG |
630 | /* |
631 | * TSC frequency determined by CPUID is a "hardware reported" | |
632 | * frequency and is the most accurate one so far we have. This | |
633 | * is considered a known frequency. | |
634 | */ | |
635 | setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); | |
636 | ||
4635fdc6 BG |
637 | /* |
638 | * For Atom SoCs TSC is the only reliable clocksource. | |
639 | * Mark TSC reliable so no watchdog on it. | |
640 | */ | |
641 | if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT) | |
642 | setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); | |
643 | ||
aa297292 LB |
644 | return crystal_khz * ebx_numerator / eax_denominator; |
645 | } | |
646 | ||
647 | static unsigned long cpu_khz_from_cpuid(void) | |
648 | { | |
649 | unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx; | |
650 | ||
651 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
652 | return 0; | |
653 | ||
654 | if (boot_cpu_data.cpuid_level < 0x16) | |
655 | return 0; | |
656 | ||
657 | eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0; | |
658 | ||
659 | cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); | |
660 | ||
661 | return eax_base_mhz * 1000; | |
662 | } | |
663 | ||
664 | /** | |
665 | * native_calibrate_cpu - calibrate the cpu on boot | |
666 | */ | |
667 | unsigned long native_calibrate_cpu(void) | |
bfc0f594 | 668 | { |
827014be | 669 | u64 tsc1, tsc2, delta, ref1, ref2; |
fbb16e24 | 670 | unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; |
2d826404 | 671 | unsigned long flags, latch, ms, fast_calibrate; |
a977c400 | 672 | int hpet = is_hpet_enabled(), i, loopmin; |
bfc0f594 | 673 | |
aa297292 LB |
674 | fast_calibrate = cpu_khz_from_cpuid(); |
675 | if (fast_calibrate) | |
676 | return fast_calibrate; | |
677 | ||
02c0cd2d | 678 | fast_calibrate = cpu_khz_from_msr(); |
5f0e0309 | 679 | if (fast_calibrate) |
7da7c156 | 680 | return fast_calibrate; |
7da7c156 | 681 | |
6ac40ed0 LT |
682 | local_irq_save(flags); |
683 | fast_calibrate = quick_pit_calibrate(); | |
bfc0f594 | 684 | local_irq_restore(flags); |
6ac40ed0 LT |
685 | if (fast_calibrate) |
686 | return fast_calibrate; | |
bfc0f594 | 687 | |
fbb16e24 TG |
688 | /* |
689 | * Run 5 calibration loops to get the lowest frequency value | |
690 | * (the best estimate). We use two different calibration modes | |
691 | * here: | |
692 | * | |
693 | * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and | |
694 | * load a timeout of 50ms. We read the time right after we | |
695 | * started the timer and wait until the PIT count down reaches | |
696 | * zero. In each wait loop iteration we read the TSC and check | |
697 | * the delta to the previous read. We keep track of the min | |
698 | * and max values of that delta. The delta is mostly defined | |
699 | * by the IO time of the PIT access, so we can detect when a | |
0d2eb44f | 700 | * SMI/SMM disturbance happened between the two reads. If the |
fbb16e24 TG |
701 | * maximum time is significantly larger than the minimum time, |
702 | * then we discard the result and have another try. | |
703 | * | |
704 | * 2) Reference counter. If available we use the HPET or the | |
705 | * PMTIMER as a reference to check the sanity of that value. | |
706 | * We use separate TSC readouts and check inside of the | |
707 | * reference read for a SMI/SMM disturbance. We dicard | |
708 | * disturbed values here as well. We do that around the PIT | |
709 | * calibration delay loop as we have to wait for a certain | |
710 | * amount of time anyway. | |
711 | */ | |
a977c400 TG |
712 | |
713 | /* Preset PIT loop values */ | |
714 | latch = CAL_LATCH; | |
715 | ms = CAL_MS; | |
716 | loopmin = CAL_PIT_LOOPS; | |
717 | ||
718 | for (i = 0; i < 3; i++) { | |
ec0c15af | 719 | unsigned long tsc_pit_khz; |
fbb16e24 TG |
720 | |
721 | /* | |
722 | * Read the start value and the reference count of | |
ec0c15af LT |
723 | * hpet/pmtimer when available. Then do the PIT |
724 | * calibration, which will take at least 50ms, and | |
725 | * read the end value. | |
fbb16e24 | 726 | */ |
ec0c15af | 727 | local_irq_save(flags); |
827014be | 728 | tsc1 = tsc_read_refs(&ref1, hpet); |
a977c400 | 729 | tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); |
827014be | 730 | tsc2 = tsc_read_refs(&ref2, hpet); |
fbb16e24 TG |
731 | local_irq_restore(flags); |
732 | ||
ec0c15af LT |
733 | /* Pick the lowest PIT TSC calibration so far */ |
734 | tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); | |
fbb16e24 TG |
735 | |
736 | /* hpet or pmtimer available ? */ | |
62627bec | 737 | if (ref1 == ref2) |
fbb16e24 TG |
738 | continue; |
739 | ||
740 | /* Check, whether the sampling was disturbed by an SMI */ | |
741 | if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) | |
742 | continue; | |
743 | ||
744 | tsc2 = (tsc2 - tsc1) * 1000000LL; | |
d683ef7a | 745 | if (hpet) |
827014be | 746 | tsc2 = calc_hpet_ref(tsc2, ref1, ref2); |
d683ef7a | 747 | else |
827014be | 748 | tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); |
fbb16e24 | 749 | |
fbb16e24 | 750 | tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); |
a977c400 TG |
751 | |
752 | /* Check the reference deviation */ | |
753 | delta = ((u64) tsc_pit_min) * 100; | |
754 | do_div(delta, tsc_ref_min); | |
755 | ||
756 | /* | |
757 | * If both calibration results are inside a 10% window | |
758 | * then we can be sure, that the calibration | |
759 | * succeeded. We break out of the loop right away. We | |
760 | * use the reference value, as it is more precise. | |
761 | */ | |
762 | if (delta >= 90 && delta <= 110) { | |
c767a54b JP |
763 | pr_info("PIT calibration matches %s. %d loops\n", |
764 | hpet ? "HPET" : "PMTIMER", i + 1); | |
a977c400 | 765 | return tsc_ref_min; |
fbb16e24 TG |
766 | } |
767 | ||
a977c400 TG |
768 | /* |
769 | * Check whether PIT failed more than once. This | |
770 | * happens in virtualized environments. We need to | |
771 | * give the virtual PC a slightly longer timeframe for | |
772 | * the HPET/PMTIMER to make the result precise. | |
773 | */ | |
774 | if (i == 1 && tsc_pit_min == ULONG_MAX) { | |
775 | latch = CAL2_LATCH; | |
776 | ms = CAL2_MS; | |
777 | loopmin = CAL2_PIT_LOOPS; | |
778 | } | |
fbb16e24 | 779 | } |
bfc0f594 AK |
780 | |
781 | /* | |
fbb16e24 | 782 | * Now check the results. |
bfc0f594 | 783 | */ |
fbb16e24 TG |
784 | if (tsc_pit_min == ULONG_MAX) { |
785 | /* PIT gave no useful value */ | |
c767a54b | 786 | pr_warn("Unable to calibrate against PIT\n"); |
fbb16e24 TG |
787 | |
788 | /* We don't have an alternative source, disable TSC */ | |
827014be | 789 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 790 | pr_notice("No reference (HPET/PMTIMER) available\n"); |
fbb16e24 TG |
791 | return 0; |
792 | } | |
793 | ||
794 | /* The alternative source failed as well, disable TSC */ | |
795 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 796 | pr_warn("HPET/PMTIMER calibration failed\n"); |
fbb16e24 TG |
797 | return 0; |
798 | } | |
799 | ||
800 | /* Use the alternative source */ | |
c767a54b JP |
801 | pr_info("using %s reference calibration\n", |
802 | hpet ? "HPET" : "PMTIMER"); | |
fbb16e24 TG |
803 | |
804 | return tsc_ref_min; | |
805 | } | |
bfc0f594 | 806 | |
fbb16e24 | 807 | /* We don't have an alternative source, use the PIT calibration value */ |
827014be | 808 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 809 | pr_info("Using PIT calibration value\n"); |
fbb16e24 | 810 | return tsc_pit_min; |
bfc0f594 AK |
811 | } |
812 | ||
fbb16e24 TG |
813 | /* The alternative source failed, use the PIT calibration value */ |
814 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 815 | pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); |
fbb16e24 | 816 | return tsc_pit_min; |
bfc0f594 AK |
817 | } |
818 | ||
fbb16e24 TG |
819 | /* |
820 | * The calibration values differ too much. In doubt, we use | |
821 | * the PIT value as we know that there are PMTIMERs around | |
a977c400 | 822 | * running at double speed. At least we let the user know: |
fbb16e24 | 823 | */ |
c767a54b JP |
824 | pr_warn("PIT calibration deviates from %s: %lu %lu\n", |
825 | hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); | |
826 | pr_info("Using PIT calibration value\n"); | |
fbb16e24 | 827 | return tsc_pit_min; |
bfc0f594 AK |
828 | } |
829 | ||
af576850 | 830 | void recalibrate_cpu_khz(void) |
bfc0f594 AK |
831 | { |
832 | #ifndef CONFIG_SMP | |
833 | unsigned long cpu_khz_old = cpu_khz; | |
834 | ||
eff4677e | 835 | if (!boot_cpu_has(X86_FEATURE_TSC)) |
af576850 | 836 | return; |
eff4677e | 837 | |
aa297292 | 838 | cpu_khz = x86_platform.calibrate_cpu(); |
eff4677e | 839 | tsc_khz = x86_platform.calibrate_tsc(); |
aa297292 LB |
840 | if (tsc_khz == 0) |
841 | tsc_khz = cpu_khz; | |
ff4c8663 LB |
842 | else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) |
843 | cpu_khz = tsc_khz; | |
eff4677e BP |
844 | cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy, |
845 | cpu_khz_old, cpu_khz); | |
bfc0f594 AK |
846 | #endif |
847 | } | |
848 | ||
849 | EXPORT_SYMBOL(recalibrate_cpu_khz); | |
850 | ||
2dbe06fa | 851 | |
cd7240c0 SS |
852 | static unsigned long long cyc2ns_suspend; |
853 | ||
b74f05d6 | 854 | void tsc_save_sched_clock_state(void) |
cd7240c0 | 855 | { |
35af99e6 | 856 | if (!sched_clock_stable()) |
cd7240c0 SS |
857 | return; |
858 | ||
859 | cyc2ns_suspend = sched_clock(); | |
860 | } | |
861 | ||
862 | /* | |
863 | * Even on processors with invariant TSC, TSC gets reset in some the | |
864 | * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to | |
865 | * arbitrary value (still sync'd across cpu's) during resume from such sleep | |
866 | * states. To cope up with this, recompute the cyc2ns_offset for each cpu so | |
867 | * that sched_clock() continues from the point where it was left off during | |
868 | * suspend. | |
869 | */ | |
b74f05d6 | 870 | void tsc_restore_sched_clock_state(void) |
cd7240c0 SS |
871 | { |
872 | unsigned long long offset; | |
873 | unsigned long flags; | |
874 | int cpu; | |
875 | ||
35af99e6 | 876 | if (!sched_clock_stable()) |
cd7240c0 SS |
877 | return; |
878 | ||
879 | local_irq_save(flags); | |
880 | ||
20d1c86a | 881 | /* |
6a6256f9 | 882 | * We're coming out of suspend, there's no concurrency yet; don't |
20d1c86a PZ |
883 | * bother being nice about the RCU stuff, just write to both |
884 | * data fields. | |
885 | */ | |
886 | ||
887 | this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0); | |
888 | this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0); | |
889 | ||
cd7240c0 SS |
890 | offset = cyc2ns_suspend - sched_clock(); |
891 | ||
20d1c86a PZ |
892 | for_each_possible_cpu(cpu) { |
893 | per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset; | |
894 | per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset; | |
895 | } | |
cd7240c0 SS |
896 | |
897 | local_irq_restore(flags); | |
898 | } | |
899 | ||
2dbe06fa | 900 | #ifdef CONFIG_CPU_FREQ |
2dbe06fa AK |
901 | /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency |
902 | * changes. | |
903 | * | |
904 | * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's | |
905 | * not that important because current Opteron setups do not support | |
906 | * scaling on SMP anyroads. | |
907 | * | |
908 | * Should fix up last_tsc too. Currently gettimeofday in the | |
909 | * first tick after the change will be slightly wrong. | |
910 | */ | |
911 | ||
912 | static unsigned int ref_freq; | |
913 | static unsigned long loops_per_jiffy_ref; | |
914 | static unsigned long tsc_khz_ref; | |
915 | ||
916 | static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
917 | void *data) | |
918 | { | |
919 | struct cpufreq_freqs *freq = data; | |
931db6a3 | 920 | unsigned long *lpj; |
2dbe06fa | 921 | |
931db6a3 | 922 | lpj = &boot_cpu_data.loops_per_jiffy; |
2dbe06fa | 923 | #ifdef CONFIG_SMP |
931db6a3 | 924 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) |
2dbe06fa | 925 | lpj = &cpu_data(freq->cpu).loops_per_jiffy; |
2dbe06fa AK |
926 | #endif |
927 | ||
928 | if (!ref_freq) { | |
929 | ref_freq = freq->old; | |
930 | loops_per_jiffy_ref = *lpj; | |
931 | tsc_khz_ref = tsc_khz; | |
932 | } | |
933 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 934 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
878f4f53 | 935 | *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); |
2dbe06fa AK |
936 | |
937 | tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); | |
938 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
939 | mark_tsc_unstable("cpufreq changes"); | |
2dbe06fa | 940 | |
5c3c2ea6 | 941 | set_cyc2ns_scale(tsc_khz, freq->cpu, rdtsc()); |
3896c329 | 942 | } |
2dbe06fa AK |
943 | |
944 | return 0; | |
945 | } | |
946 | ||
947 | static struct notifier_block time_cpufreq_notifier_block = { | |
948 | .notifier_call = time_cpufreq_notifier | |
949 | }; | |
950 | ||
a841cca7 | 951 | static int __init cpufreq_register_tsc_scaling(void) |
2dbe06fa | 952 | { |
59e21e3d | 953 | if (!boot_cpu_has(X86_FEATURE_TSC)) |
060700b5 LT |
954 | return 0; |
955 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
956 | return 0; | |
2dbe06fa AK |
957 | cpufreq_register_notifier(&time_cpufreq_notifier_block, |
958 | CPUFREQ_TRANSITION_NOTIFIER); | |
959 | return 0; | |
960 | } | |
961 | ||
a841cca7 | 962 | core_initcall(cpufreq_register_tsc_scaling); |
2dbe06fa AK |
963 | |
964 | #endif /* CONFIG_CPU_FREQ */ | |
8fbbc4b4 | 965 | |
f9677e0f CH |
966 | #define ART_CPUID_LEAF (0x15) |
967 | #define ART_MIN_DENOMINATOR (1) | |
968 | ||
969 | ||
970 | /* | |
971 | * If ART is present detect the numerator:denominator to convert to TSC | |
972 | */ | |
120fc3fb | 973 | static void __init detect_art(void) |
f9677e0f CH |
974 | { |
975 | unsigned int unused[2]; | |
976 | ||
977 | if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) | |
978 | return; | |
979 | ||
6c66350d | 980 | /* |
981 | * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required, | |
982 | * and the TSC counter resets must not occur asynchronously. | |
983 | */ | |
f9677e0f CH |
984 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR) || |
985 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) || | |
6c66350d | 986 | !boot_cpu_has(X86_FEATURE_TSC_ADJUST) || |
987 | tsc_async_resets) | |
f9677e0f CH |
988 | return; |
989 | ||
7b3d2f6e TG |
990 | cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator, |
991 | &art_to_tsc_numerator, unused, unused+1); | |
992 | ||
993 | if (art_to_tsc_denominator < ART_MIN_DENOMINATOR) | |
f9677e0f CH |
994 | return; |
995 | ||
7b3d2f6e TG |
996 | rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset); |
997 | ||
f9677e0f CH |
998 | /* Make this sticky over multiple CPU init calls */ |
999 | setup_force_cpu_cap(X86_FEATURE_ART); | |
1000 | } | |
1001 | ||
1002 | ||
8fbbc4b4 AK |
1003 | /* clocksource code */ |
1004 | ||
6a369583 TG |
1005 | static void tsc_resume(struct clocksource *cs) |
1006 | { | |
1007 | tsc_verify_tsc_adjust(true); | |
1008 | } | |
1009 | ||
8fbbc4b4 | 1010 | /* |
09ec5442 | 1011 | * We used to compare the TSC to the cycle_last value in the clocksource |
8fbbc4b4 AK |
1012 | * structure to avoid a nasty time-warp. This can be observed in a |
1013 | * very small window right after one CPU updated cycle_last under | |
1014 | * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which | |
1015 | * is smaller than the cycle_last reference value due to a TSC which | |
1016 | * is slighty behind. This delta is nowhere else observable, but in | |
1017 | * that case it results in a forward time jump in the range of hours | |
1018 | * due to the unsigned delta calculation of the time keeping core | |
1019 | * code, which is necessary to support wrapping clocksources like pm | |
1020 | * timer. | |
09ec5442 TG |
1021 | * |
1022 | * This sanity check is now done in the core timekeeping code. | |
1023 | * checking the result of read_tsc() - cycle_last for being negative. | |
1024 | * That works because CLOCKSOURCE_MASK(64) does not mask out any bit. | |
8fbbc4b4 | 1025 | */ |
a5a1d1c2 | 1026 | static u64 read_tsc(struct clocksource *cs) |
8fbbc4b4 | 1027 | { |
a5a1d1c2 | 1028 | return (u64)rdtsc_ordered(); |
1be39679 MS |
1029 | } |
1030 | ||
12907fbb TG |
1031 | static void tsc_cs_mark_unstable(struct clocksource *cs) |
1032 | { | |
1033 | if (tsc_unstable) | |
1034 | return; | |
f94c8d11 | 1035 | |
12907fbb | 1036 | tsc_unstable = 1; |
f94c8d11 PZ |
1037 | if (using_native_sched_clock()) |
1038 | clear_sched_clock_stable(); | |
12907fbb TG |
1039 | disable_sched_clock_irqtime(); |
1040 | pr_info("Marking TSC unstable due to clocksource watchdog\n"); | |
1041 | } | |
1042 | ||
b421b22b PZ |
1043 | static void tsc_cs_tick_stable(struct clocksource *cs) |
1044 | { | |
1045 | if (tsc_unstable) | |
1046 | return; | |
1047 | ||
1048 | if (using_native_sched_clock()) | |
1049 | sched_clock_tick_stable(); | |
1050 | } | |
1051 | ||
09ec5442 TG |
1052 | /* |
1053 | * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() | |
1054 | */ | |
aa83c457 PZ |
1055 | static struct clocksource clocksource_tsc_early = { |
1056 | .name = "tsc-early", | |
1057 | .rating = 299, | |
1058 | .read = read_tsc, | |
1059 | .mask = CLOCKSOURCE_MASK(64), | |
1060 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | | |
1061 | CLOCK_SOURCE_MUST_VERIFY, | |
1062 | .archdata = { .vclock_mode = VCLOCK_TSC }, | |
1063 | .resume = tsc_resume, | |
1064 | .mark_unstable = tsc_cs_mark_unstable, | |
1065 | .tick_stable = tsc_cs_tick_stable, | |
e3b4f790 | 1066 | .list = LIST_HEAD_INIT(clocksource_tsc_early.list), |
aa83c457 PZ |
1067 | }; |
1068 | ||
1069 | /* | |
1070 | * Must mark VALID_FOR_HRES early such that when we unregister tsc_early | |
1071 | * this one will immediately take over. We will only register if TSC has | |
1072 | * been found good. | |
1073 | */ | |
8fbbc4b4 AK |
1074 | static struct clocksource clocksource_tsc = { |
1075 | .name = "tsc", | |
1076 | .rating = 300, | |
1077 | .read = read_tsc, | |
1078 | .mask = CLOCKSOURCE_MASK(64), | |
8fbbc4b4 | 1079 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | |
aa83c457 | 1080 | CLOCK_SOURCE_VALID_FOR_HRES | |
8fbbc4b4 | 1081 | CLOCK_SOURCE_MUST_VERIFY, |
98d0ac38 | 1082 | .archdata = { .vclock_mode = VCLOCK_TSC }, |
6a369583 | 1083 | .resume = tsc_resume, |
12907fbb | 1084 | .mark_unstable = tsc_cs_mark_unstable, |
b421b22b | 1085 | .tick_stable = tsc_cs_tick_stable, |
e3b4f790 | 1086 | .list = LIST_HEAD_INIT(clocksource_tsc.list), |
8fbbc4b4 AK |
1087 | }; |
1088 | ||
1089 | void mark_tsc_unstable(char *reason) | |
1090 | { | |
f94c8d11 PZ |
1091 | if (tsc_unstable) |
1092 | return; | |
1093 | ||
1094 | tsc_unstable = 1; | |
1095 | if (using_native_sched_clock()) | |
35af99e6 | 1096 | clear_sched_clock_stable(); |
f94c8d11 PZ |
1097 | disable_sched_clock_irqtime(); |
1098 | pr_info("Marking TSC unstable due to %s\n", reason); | |
e3b4f790 PZ |
1099 | |
1100 | clocksource_mark_unstable(&clocksource_tsc_early); | |
1101 | clocksource_mark_unstable(&clocksource_tsc); | |
8fbbc4b4 AK |
1102 | } |
1103 | ||
1104 | EXPORT_SYMBOL_GPL(mark_tsc_unstable); | |
1105 | ||
395628ef AK |
1106 | static void __init check_system_tsc_reliable(void) |
1107 | { | |
03da3ff1 DW |
1108 | #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC) |
1109 | if (is_geode_lx()) { | |
1110 | /* RTSC counts during suspend */ | |
8fbbc4b4 | 1111 | #define RTSC_SUSP 0x100 |
03da3ff1 | 1112 | unsigned long res_low, res_high; |
8fbbc4b4 | 1113 | |
03da3ff1 DW |
1114 | rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); |
1115 | /* Geode_LX - the OLPC CPU has a very reliable TSC */ | |
1116 | if (res_low & RTSC_SUSP) | |
1117 | tsc_clocksource_reliable = 1; | |
1118 | } | |
8fbbc4b4 | 1119 | #endif |
395628ef AK |
1120 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) |
1121 | tsc_clocksource_reliable = 1; | |
1122 | } | |
8fbbc4b4 AK |
1123 | |
1124 | /* | |
1125 | * Make an educated guess if the TSC is trustworthy and synchronized | |
1126 | * over all CPUs. | |
1127 | */ | |
148f9bb8 | 1128 | int unsynchronized_tsc(void) |
8fbbc4b4 | 1129 | { |
59e21e3d | 1130 | if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable) |
8fbbc4b4 AK |
1131 | return 1; |
1132 | ||
3e5095d1 | 1133 | #ifdef CONFIG_SMP |
8fbbc4b4 AK |
1134 | if (apic_is_clustered_box()) |
1135 | return 1; | |
1136 | #endif | |
1137 | ||
1138 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
1139 | return 0; | |
d3b8f889 | 1140 | |
1141 | if (tsc_clocksource_reliable) | |
1142 | return 0; | |
8fbbc4b4 AK |
1143 | /* |
1144 | * Intel systems are normally all synchronized. | |
1145 | * Exceptions must mark TSC as unstable: | |
1146 | */ | |
1147 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { | |
1148 | /* assume multi socket systems are not synchronized: */ | |
1149 | if (num_possible_cpus() > 1) | |
d3b8f889 | 1150 | return 1; |
8fbbc4b4 AK |
1151 | } |
1152 | ||
d3b8f889 | 1153 | return 0; |
8fbbc4b4 AK |
1154 | } |
1155 | ||
f9677e0f CH |
1156 | /* |
1157 | * Convert ART to TSC given numerator/denominator found in detect_art() | |
1158 | */ | |
a5a1d1c2 | 1159 | struct system_counterval_t convert_art_to_tsc(u64 art) |
f9677e0f CH |
1160 | { |
1161 | u64 tmp, res, rem; | |
1162 | ||
1163 | rem = do_div(art, art_to_tsc_denominator); | |
1164 | ||
1165 | res = art * art_to_tsc_numerator; | |
1166 | tmp = rem * art_to_tsc_numerator; | |
1167 | ||
1168 | do_div(tmp, art_to_tsc_denominator); | |
1169 | res += tmp + art_to_tsc_offset; | |
1170 | ||
1171 | return (struct system_counterval_t) {.cs = art_related_clocksource, | |
1172 | .cycles = res}; | |
1173 | } | |
1174 | EXPORT_SYMBOL(convert_art_to_tsc); | |
08ec0c58 | 1175 | |
fc804f65 RJ |
1176 | /** |
1177 | * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC. | |
1178 | * @art_ns: ART (Always Running Timer) in unit of nanoseconds | |
1179 | * | |
1180 | * PTM requires all timestamps to be in units of nanoseconds. When user | |
1181 | * software requests a cross-timestamp, this function converts system timestamp | |
1182 | * to TSC. | |
1183 | * | |
1184 | * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set | |
1185 | * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check | |
1186 | * that this flag is set before conversion to TSC is attempted. | |
1187 | * | |
1188 | * Return: | |
1189 | * struct system_counterval_t - system counter value with the pointer to the | |
1190 | * corresponding clocksource | |
1191 | * @cycles: System counter value | |
1192 | * @cs: Clocksource corresponding to system counter value. Used | |
1193 | * by timekeeping code to verify comparibility of two cycle | |
1194 | * values. | |
1195 | */ | |
1196 | ||
1197 | struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns) | |
1198 | { | |
1199 | u64 tmp, res, rem; | |
1200 | ||
1201 | rem = do_div(art_ns, USEC_PER_SEC); | |
1202 | ||
1203 | res = art_ns * tsc_khz; | |
1204 | tmp = rem * tsc_khz; | |
1205 | ||
1206 | do_div(tmp, USEC_PER_SEC); | |
1207 | res += tmp; | |
1208 | ||
1209 | return (struct system_counterval_t) { .cs = art_related_clocksource, | |
1210 | .cycles = res}; | |
1211 | } | |
1212 | EXPORT_SYMBOL(convert_art_ns_to_tsc); | |
1213 | ||
1214 | ||
08ec0c58 JS |
1215 | static void tsc_refine_calibration_work(struct work_struct *work); |
1216 | static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); | |
1217 | /** | |
1218 | * tsc_refine_calibration_work - Further refine tsc freq calibration | |
1219 | * @work - ignored. | |
1220 | * | |
1221 | * This functions uses delayed work over a period of a | |
1222 | * second to further refine the TSC freq value. Since this is | |
1223 | * timer based, instead of loop based, we don't block the boot | |
1224 | * process while this longer calibration is done. | |
1225 | * | |
0d2eb44f | 1226 | * If there are any calibration anomalies (too many SMIs, etc), |
08ec0c58 JS |
1227 | * or the refined calibration is off by 1% of the fast early |
1228 | * calibration, we throw out the new calibration and use the | |
1229 | * early calibration. | |
1230 | */ | |
1231 | static void tsc_refine_calibration_work(struct work_struct *work) | |
1232 | { | |
1233 | static u64 tsc_start = -1, ref_start; | |
1234 | static int hpet; | |
1235 | u64 tsc_stop, ref_stop, delta; | |
1236 | unsigned long freq; | |
aa7b630e | 1237 | int cpu; |
08ec0c58 JS |
1238 | |
1239 | /* Don't bother refining TSC on unstable systems */ | |
aa83c457 | 1240 | if (tsc_unstable) |
e9088add | 1241 | goto unreg; |
08ec0c58 JS |
1242 | |
1243 | /* | |
1244 | * Since the work is started early in boot, we may be | |
1245 | * delayed the first time we expire. So set the workqueue | |
1246 | * again once we know timers are working. | |
1247 | */ | |
1248 | if (tsc_start == -1) { | |
1249 | /* | |
1250 | * Only set hpet once, to avoid mixing hardware | |
1251 | * if the hpet becomes enabled later. | |
1252 | */ | |
1253 | hpet = is_hpet_enabled(); | |
1254 | schedule_delayed_work(&tsc_irqwork, HZ); | |
1255 | tsc_start = tsc_read_refs(&ref_start, hpet); | |
1256 | return; | |
1257 | } | |
1258 | ||
1259 | tsc_stop = tsc_read_refs(&ref_stop, hpet); | |
1260 | ||
1261 | /* hpet or pmtimer available ? */ | |
62627bec | 1262 | if (ref_start == ref_stop) |
08ec0c58 JS |
1263 | goto out; |
1264 | ||
1265 | /* Check, whether the sampling was disturbed by an SMI */ | |
1266 | if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX) | |
1267 | goto out; | |
1268 | ||
1269 | delta = tsc_stop - tsc_start; | |
1270 | delta *= 1000000LL; | |
1271 | if (hpet) | |
1272 | freq = calc_hpet_ref(delta, ref_start, ref_stop); | |
1273 | else | |
1274 | freq = calc_pmtimer_ref(delta, ref_start, ref_stop); | |
1275 | ||
1276 | /* Make sure we're within 1% */ | |
1277 | if (abs(tsc_khz - freq) > tsc_khz/100) | |
1278 | goto out; | |
1279 | ||
1280 | tsc_khz = freq; | |
c767a54b JP |
1281 | pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", |
1282 | (unsigned long)tsc_khz / 1000, | |
1283 | (unsigned long)tsc_khz % 1000); | |
08ec0c58 | 1284 | |
6731b0d6 NS |
1285 | /* Inform the TSC deadline clockevent devices about the recalibration */ |
1286 | lapic_update_tsc_freq(); | |
1287 | ||
aa7b630e PZ |
1288 | /* Update the sched_clock() rate to match the clocksource one */ |
1289 | for_each_possible_cpu(cpu) | |
5c3c2ea6 | 1290 | set_cyc2ns_scale(tsc_khz, cpu, tsc_stop); |
aa7b630e | 1291 | |
08ec0c58 | 1292 | out: |
aa83c457 | 1293 | if (tsc_unstable) |
e9088add | 1294 | goto unreg; |
aa83c457 | 1295 | |
f9677e0f CH |
1296 | if (boot_cpu_has(X86_FEATURE_ART)) |
1297 | art_related_clocksource = &clocksource_tsc; | |
08ec0c58 | 1298 | clocksource_register_khz(&clocksource_tsc, tsc_khz); |
e9088add | 1299 | unreg: |
aa83c457 | 1300 | clocksource_unregister(&clocksource_tsc_early); |
08ec0c58 JS |
1301 | } |
1302 | ||
1303 | ||
1304 | static int __init init_tsc_clocksource(void) | |
8fbbc4b4 | 1305 | { |
fe9af81e | 1306 | if (!boot_cpu_has(X86_FEATURE_TSC) || !tsc_khz) |
a8760eca TG |
1307 | return 0; |
1308 | ||
e9088add PZ |
1309 | if (tsc_unstable) |
1310 | goto unreg; | |
aa83c457 | 1311 | |
395628ef AK |
1312 | if (tsc_clocksource_reliable) |
1313 | clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; | |
57779dc2 | 1314 | |
82f9c080 FT |
1315 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) |
1316 | clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
1317 | ||
57779dc2 | 1318 | /* |
47c95a46 BG |
1319 | * When TSC frequency is known (retrieved via MSR or CPUID), we skip |
1320 | * the refined calibration and directly register it as a clocksource. | |
57779dc2 | 1321 | */ |
984feceb | 1322 | if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { |
44fee88c PZ |
1323 | if (boot_cpu_has(X86_FEATURE_ART)) |
1324 | art_related_clocksource = &clocksource_tsc; | |
57779dc2 | 1325 | clocksource_register_khz(&clocksource_tsc, tsc_khz); |
e9088add | 1326 | unreg: |
aa83c457 | 1327 | clocksource_unregister(&clocksource_tsc_early); |
57779dc2 AK |
1328 | return 0; |
1329 | } | |
1330 | ||
08ec0c58 JS |
1331 | schedule_delayed_work(&tsc_irqwork, 0); |
1332 | return 0; | |
8fbbc4b4 | 1333 | } |
08ec0c58 JS |
1334 | /* |
1335 | * We use device_initcall here, to ensure we run after the hpet | |
1336 | * is fully initialized, which may occur at fs_initcall time. | |
1337 | */ | |
1338 | device_initcall(init_tsc_clocksource); | |
8fbbc4b4 | 1339 | |
cf7a63ef | 1340 | static bool __init determine_cpu_tsc_frequencies(void) |
8fbbc4b4 | 1341 | { |
cf7a63ef PT |
1342 | /* Make sure that cpu and tsc are not already calibrated */ |
1343 | WARN_ON(cpu_khz || tsc_khz); | |
8fbbc4b4 | 1344 | |
aa297292 | 1345 | cpu_khz = x86_platform.calibrate_cpu(); |
2d826404 | 1346 | tsc_khz = x86_platform.calibrate_tsc(); |
ff4c8663 LB |
1347 | |
1348 | /* | |
1349 | * Trust non-zero tsc_khz as authorative, | |
1350 | * and use it to sanity check cpu_khz, | |
1351 | * which will be off if system timer is off. | |
1352 | */ | |
aa297292 LB |
1353 | if (tsc_khz == 0) |
1354 | tsc_khz = cpu_khz; | |
ff4c8663 LB |
1355 | else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) |
1356 | cpu_khz = tsc_khz; | |
8fbbc4b4 | 1357 | |
cf7a63ef PT |
1358 | if (tsc_khz == 0) |
1359 | return false; | |
8fbbc4b4 | 1360 | |
c767a54b | 1361 | pr_info("Detected %lu.%03lu MHz processor\n", |
cf7a63ef PT |
1362 | (unsigned long)cpu_khz / KHZ, |
1363 | (unsigned long)cpu_khz % KHZ); | |
8fbbc4b4 | 1364 | |
4b5b2127 LB |
1365 | if (cpu_khz != tsc_khz) { |
1366 | pr_info("Detected %lu.%03lu MHz TSC", | |
cf7a63ef PT |
1367 | (unsigned long)tsc_khz / KHZ, |
1368 | (unsigned long)tsc_khz % KHZ); | |
1369 | } | |
1370 | return true; | |
1371 | } | |
1372 | ||
1373 | static unsigned long __init get_loops_per_jiffy(void) | |
1374 | { | |
1375 | unsigned long lpj = tsc_khz * KHZ; | |
1376 | ||
1377 | do_div(lpj, HZ); | |
1378 | return lpj; | |
1379 | } | |
1380 | ||
1381 | void __init tsc_early_init(void) | |
1382 | { | |
1383 | if (!boot_cpu_has(X86_FEATURE_TSC)) | |
1384 | return; | |
1385 | if (!determine_cpu_tsc_frequencies()) | |
1386 | return; | |
1387 | loops_per_jiffy = get_loops_per_jiffy(); | |
1388 | } | |
1389 | ||
1390 | void __init tsc_init(void) | |
1391 | { | |
1392 | if (!boot_cpu_has(X86_FEATURE_TSC)) { | |
1393 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); | |
1394 | return; | |
1395 | } | |
1396 | ||
1397 | if (!tsc_khz) { | |
1398 | /* We failed to determine frequencies earlier, try again */ | |
1399 | if (!determine_cpu_tsc_frequencies()) { | |
1400 | mark_tsc_unstable("could not calculate TSC khz"); | |
1401 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); | |
1402 | return; | |
1403 | } | |
4b5b2127 LB |
1404 | } |
1405 | ||
f2e04214 TG |
1406 | /* Sanitize TSC ADJUST before cyc2ns gets initialized */ |
1407 | tsc_store_and_check_tsc_adjust(true); | |
1408 | ||
8fbbc4b4 AK |
1409 | /* |
1410 | * Secondary CPUs do not run through tsc_init(), so set up | |
1411 | * all the scale factors for all CPUs, assuming the same | |
1412 | * speed as the bootup CPU. (cpufreq notifiers will fix this | |
1413 | * up if their speed diverges) | |
1414 | */ | |
615cd033 | 1415 | cyc = rdtsc(); |
20d1c86a PZ |
1416 | for_each_possible_cpu(cpu) { |
1417 | cyc2ns_init(cpu); | |
5c3c2ea6 | 1418 | set_cyc2ns_scale(tsc_khz, cpu, cyc); |
20d1c86a | 1419 | } |
8fbbc4b4 | 1420 | |
3bbfafb7 | 1421 | static_branch_enable(&__use_tsc); |
8fbbc4b4 | 1422 | |
e82b8e4e VP |
1423 | if (!no_sched_irq_time) |
1424 | enable_sched_clock_irqtime(); | |
1425 | ||
cf7a63ef | 1426 | lpj_fine = get_loops_per_jiffy(); |
8fbbc4b4 | 1427 | use_tsc_delay(); |
8fbbc4b4 | 1428 | |
a1272dd5 ZD |
1429 | check_system_tsc_reliable(); |
1430 | ||
aa83c457 | 1431 | if (unsynchronized_tsc()) { |
8fbbc4b4 | 1432 | mark_tsc_unstable("TSCs unsynchronized"); |
aa83c457 PZ |
1433 | return; |
1434 | } | |
8fbbc4b4 | 1435 | |
aa83c457 | 1436 | clocksource_register_khz(&clocksource_tsc_early, tsc_khz); |
f9677e0f | 1437 | detect_art(); |
8fbbc4b4 AK |
1438 | } |
1439 | ||
b565201c JS |
1440 | #ifdef CONFIG_SMP |
1441 | /* | |
1442 | * If we have a constant TSC and are using the TSC for the delay loop, | |
1443 | * we can skip clock calibration if another cpu in the same socket has already | |
1444 | * been calibrated. This assumes that CONSTANT_TSC applies to all | |
1445 | * cpus in the socket - this should be a safe assumption. | |
1446 | */ | |
148f9bb8 | 1447 | unsigned long calibrate_delay_is_known(void) |
b565201c | 1448 | { |
c25323c0 | 1449 | int sibling, cpu = smp_processor_id(); |
76ce7cfe PT |
1450 | int constant_tsc = cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC); |
1451 | const struct cpumask *mask = topology_core_cpumask(cpu); | |
b565201c | 1452 | |
fe9af81e | 1453 | if (!constant_tsc || !mask) |
f508a5ba TG |
1454 | return 0; |
1455 | ||
1456 | sibling = cpumask_any_but(mask, cpu); | |
c25323c0 TG |
1457 | if (sibling < nr_cpu_ids) |
1458 | return cpu_data(sibling).loops_per_jiffy; | |
b565201c JS |
1459 | return 0; |
1460 | } | |
1461 | #endif |