admin-guide: pm: intel_epb: Add SPDX license tag and copyright notice
[linux-2.6-block.git] / arch / x86 / kernel / tsc.c
CommitLineData
c767a54b
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1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
bfc0f594 3#include <linux/kernel.h>
0ef95533 4#include <linux/sched.h>
e6017571 5#include <linux/sched/clock.h>
0ef95533 6#include <linux/init.h>
186f4360 7#include <linux/export.h>
0ef95533 8#include <linux/timer.h>
bfc0f594 9#include <linux/acpi_pmtmr.h>
2dbe06fa 10#include <linux/cpufreq.h>
8fbbc4b4
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11#include <linux/delay.h>
12#include <linux/clocksource.h>
13#include <linux/percpu.h>
08604bd9 14#include <linux/timex.h>
10b033d4 15#include <linux/static_key.h>
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16
17#include <asm/hpet.h>
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18#include <asm/timer.h>
19#include <asm/vgtod.h>
20#include <asm/time.h>
21#include <asm/delay.h>
88b094fb 22#include <asm/hypervisor.h>
08047c4f 23#include <asm/nmi.h>
2d826404 24#include <asm/x86_init.h>
03da3ff1 25#include <asm/geode.h>
6731b0d6 26#include <asm/apic.h>
655e52d2 27#include <asm/intel-family.h>
30c7e5b1 28#include <asm/i8259.h>
2647c43c 29#include <asm/uv/uv.h>
0ef95533 30
f24ade3a 31unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
0ef95533 32EXPORT_SYMBOL(cpu_khz);
f24ade3a
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33
34unsigned int __read_mostly tsc_khz;
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35EXPORT_SYMBOL(tsc_khz);
36
cf7a63ef
PT
37#define KHZ 1000
38
0ef95533
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39/*
40 * TSC can be unstable due to cpufreq or due to unsynced TSCs
41 */
f24ade3a 42static int __read_mostly tsc_unstable;
0ef95533 43
3bbfafb7 44static DEFINE_STATIC_KEY_FALSE(__use_tsc);
10b033d4 45
28a00184 46int tsc_clocksource_reliable;
57c67da2 47
f9677e0f
CH
48static u32 art_to_tsc_numerator;
49static u32 art_to_tsc_denominator;
50static u64 art_to_tsc_offset;
51struct clocksource *art_related_clocksource;
52
20d1c86a 53struct cyc2ns {
59eaef78
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54 struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */
55 seqcount_t seq; /* 32 + 4 = 36 */
20d1c86a 56
59eaef78 57}; /* fits one cacheline */
20d1c86a 58
59eaef78 59static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
20d1c86a 60
4907c68a 61void __always_inline cyc2ns_read_begin(struct cyc2ns_data *data)
20d1c86a 62{
59eaef78 63 int seq, idx;
20d1c86a 64
59eaef78 65 preempt_disable_notrace();
20d1c86a 66
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67 do {
68 seq = this_cpu_read(cyc2ns.seq.sequence);
69 idx = seq & 1;
20d1c86a 70
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71 data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset);
72 data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul);
73 data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift);
20d1c86a 74
59eaef78 75 } while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence)));
20d1c86a
PZ
76}
77
4907c68a 78void __always_inline cyc2ns_read_end(void)
20d1c86a 79{
59eaef78 80 preempt_enable_notrace();
20d1c86a
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81}
82
83/*
84 * Accelerators for sched_clock()
57c67da2
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85 * convert from cycles(64bits) => nanoseconds (64bits)
86 * basic equation:
87 * ns = cycles / (freq / ns_per_sec)
88 * ns = cycles * (ns_per_sec / freq)
89 * ns = cycles * (10^9 / (cpu_khz * 10^3))
90 * ns = cycles * (10^6 / cpu_khz)
91 *
92 * Then we use scaling math (suggested by george@mvista.com) to get:
93 * ns = cycles * (10^6 * SC / cpu_khz) / SC
94 * ns = cycles * cyc2ns_scale / SC
95 *
96 * And since SC is a constant power of two, we can convert the div
b20112ed
AH
97 * into a shift. The larger SC is, the more accurate the conversion, but
98 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
99 * (64-bit result) can be used.
57c67da2 100 *
b20112ed 101 * We can use khz divisor instead of mhz to keep a better precision.
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102 * (mathieu.desnoyers@polymtl.ca)
103 *
104 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
105 */
106
4907c68a 107static __always_inline unsigned long long cycles_2_ns(unsigned long long cyc)
57c67da2 108{
59eaef78 109 struct cyc2ns_data data;
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110 unsigned long long ns;
111
59eaef78 112 cyc2ns_read_begin(&data);
20d1c86a 113
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114 ns = data.cyc2ns_offset;
115 ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift);
20d1c86a 116
59eaef78 117 cyc2ns_read_end();
20d1c86a 118
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119 return ns;
120}
121
e2a9ca29 122static void __set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now)
57c67da2 123{
615cd033 124 unsigned long long ns_now;
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125 struct cyc2ns_data data;
126 struct cyc2ns *c2n;
20d1c86a 127
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128 ns_now = cycles_2_ns(tsc_now);
129
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130 /*
131 * Compute a new multiplier as per the above comment and ensure our
132 * time function is continuous; see the comment near struct
133 * cyc2ns_data.
134 */
59eaef78 135 clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz,
b20112ed
AH
136 NSEC_PER_MSEC, 0);
137
b9511cd7
AH
138 /*
139 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
140 * not expected to be greater than 31 due to the original published
141 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
142 * value) - refer perf_event_mmap_page documentation in perf_event.h.
143 */
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144 if (data.cyc2ns_shift == 32) {
145 data.cyc2ns_shift = 31;
146 data.cyc2ns_mul >>= 1;
b9511cd7
AH
147 }
148
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149 data.cyc2ns_offset = ns_now -
150 mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift);
151
152 c2n = per_cpu_ptr(&cyc2ns, cpu);
20d1c86a 153
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154 raw_write_seqcount_latch(&c2n->seq);
155 c2n->data[0] = data;
156 raw_write_seqcount_latch(&c2n->seq);
157 c2n->data[1] = data;
e2a9ca29
PT
158}
159
160static void set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now)
161{
162 unsigned long flags;
163
164 local_irq_save(flags);
165 sched_clock_idle_sleep_event();
166
167 if (khz)
168 __set_cyc2ns_scale(khz, cpu, tsc_now);
57c67da2 169
ac1e843f 170 sched_clock_idle_wakeup_event();
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171 local_irq_restore(flags);
172}
615cd033 173
e2a9ca29
PT
174/*
175 * Initialize cyc2ns for boot cpu
176 */
177static void __init cyc2ns_init_boot_cpu(void)
178{
179 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns);
180
181 seqcount_init(&c2n->seq);
182 __set_cyc2ns_scale(tsc_khz, smp_processor_id(), rdtsc());
183}
184
185/*
608008a4 186 * Secondary CPUs do not run through tsc_init(), so set up
e2a9ca29
PT
187 * all the scale factors for all CPUs, assuming the same
188 * speed as the bootup CPU. (cpufreq notifiers will fix this
189 * up if their speed diverges)
190 */
191static void __init cyc2ns_init_secondary_cpus(void)
192{
193 unsigned int cpu, this_cpu = smp_processor_id();
194 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns);
195 struct cyc2ns_data *data = c2n->data;
196
197 for_each_possible_cpu(cpu) {
198 if (cpu != this_cpu) {
199 seqcount_init(&c2n->seq);
200 c2n = per_cpu_ptr(&cyc2ns, cpu);
201 c2n->data[0] = data[0];
202 c2n->data[1] = data[1];
203 }
204 }
205}
206
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207/*
208 * Scheduler clock - returns current time in nanosec units.
209 */
210u64 native_sched_clock(void)
211{
3bbfafb7
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212 if (static_branch_likely(&__use_tsc)) {
213 u64 tsc_now = rdtsc();
214
215 /* return the value in ns */
216 return cycles_2_ns(tsc_now);
217 }
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218
219 /*
220 * Fall back to jiffies if there's no TSC available:
221 * ( But note that we still use it if the TSC is marked
222 * unstable. We do this because unlike Time Of Day,
223 * the scheduler clock tolerates small errors and it's
224 * very important for it to be as fast as the platform
3ad2f3fb 225 * can achieve it. )
0ef95533 226 */
0ef95533 227
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228 /* No locking but a rare wrong value is not a big deal: */
229 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
0ef95533
AK
230}
231
a94cab23
AK
232/*
233 * Generate a sched_clock if you already have a TSC value.
234 */
235u64 native_sched_clock_from_tsc(u64 tsc)
236{
237 return cycles_2_ns(tsc);
238}
239
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240/* We need to define a real function for sched_clock, to override the
241 weak default version */
242#ifdef CONFIG_PARAVIRT
243unsigned long long sched_clock(void)
244{
245 return paravirt_sched_clock();
246}
f94c8d11 247
698eff63 248bool using_native_sched_clock(void)
f94c8d11 249{
5c83511b 250 return pv_ops.time.sched_clock == native_sched_clock;
f94c8d11 251}
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252#else
253unsigned long long
254sched_clock(void) __attribute__((alias("native_sched_clock")));
f94c8d11 255
698eff63 256bool using_native_sched_clock(void) { return true; }
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257#endif
258
259int check_tsc_unstable(void)
260{
261 return tsc_unstable;
262}
263EXPORT_SYMBOL_GPL(check_tsc_unstable);
264
265#ifdef CONFIG_X86_TSC
266int __init notsc_setup(char *str)
267{
fe9af81e 268 mark_tsc_unstable("boot parameter notsc");
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269 return 1;
270}
271#else
272/*
273 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
274 * in cpu/common.c
275 */
276int __init notsc_setup(char *str)
277{
278 setup_clear_cpu_cap(X86_FEATURE_TSC);
279 return 1;
280}
281#endif
282
283__setup("notsc", notsc_setup);
bfc0f594 284
e82b8e4e
VP
285static int no_sched_irq_time;
286
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AK
287static int __init tsc_setup(char *str)
288{
289 if (!strcmp(str, "reliable"))
290 tsc_clocksource_reliable = 1;
e82b8e4e
VP
291 if (!strncmp(str, "noirqtime", 9))
292 no_sched_irq_time = 1;
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PZ
293 if (!strcmp(str, "unstable"))
294 mark_tsc_unstable("boot parameter");
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AK
295 return 1;
296}
297
298__setup("tsc=", tsc_setup);
299
a786ef15
DV
300#define MAX_RETRIES 5
301#define TSC_DEFAULT_THRESHOLD 0x20000
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AK
302
303/*
a786ef15 304 * Read TSC and the reference counters. Take care of any disturbances
bfc0f594 305 */
827014be 306static u64 tsc_read_refs(u64 *p, int hpet)
bfc0f594
AK
307{
308 u64 t1, t2;
a786ef15 309 u64 thresh = tsc_khz ? tsc_khz >> 5 : TSC_DEFAULT_THRESHOLD;
bfc0f594
AK
310 int i;
311
312 for (i = 0; i < MAX_RETRIES; i++) {
313 t1 = get_cycles();
314 if (hpet)
827014be 315 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
bfc0f594 316 else
827014be 317 *p = acpi_pm_read_early();
bfc0f594 318 t2 = get_cycles();
a786ef15 319 if ((t2 - t1) < thresh)
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AK
320 return t2;
321 }
322 return ULLONG_MAX;
323}
324
d683ef7a
TG
325/*
326 * Calculate the TSC frequency from HPET reference
bfc0f594 327 */
d683ef7a 328static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
bfc0f594 329{
d683ef7a 330 u64 tmp;
bfc0f594 331
d683ef7a
TG
332 if (hpet2 < hpet1)
333 hpet2 += 0x100000000ULL;
334 hpet2 -= hpet1;
335 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
336 do_div(tmp, 1000000);
d3878e16 337 deltatsc = div64_u64(deltatsc, tmp);
d683ef7a
TG
338
339 return (unsigned long) deltatsc;
340}
341
342/*
343 * Calculate the TSC frequency from PMTimer reference
344 */
345static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
346{
347 u64 tmp;
bfc0f594 348
d683ef7a
TG
349 if (!pm1 && !pm2)
350 return ULONG_MAX;
351
352 if (pm2 < pm1)
353 pm2 += (u64)ACPI_PM_OVRRUN;
354 pm2 -= pm1;
355 tmp = pm2 * 1000000000LL;
356 do_div(tmp, PMTMR_TICKS_PER_SEC);
357 do_div(deltatsc, tmp);
358
359 return (unsigned long) deltatsc;
360}
361
a977c400 362#define CAL_MS 10
b7743970 363#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
a977c400
TG
364#define CAL_PIT_LOOPS 1000
365
366#define CAL2_MS 50
b7743970 367#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
a977c400
TG
368#define CAL2_PIT_LOOPS 5000
369
cce3e057 370
ec0c15af
LT
371/*
372 * Try to calibrate the TSC against the Programmable
373 * Interrupt Timer and return the frequency of the TSC
374 * in kHz.
375 *
376 * Return ULONG_MAX on failure to calibrate.
377 */
a977c400 378static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
ec0c15af
LT
379{
380 u64 tsc, t1, t2, delta;
381 unsigned long tscmin, tscmax;
382 int pitcnt;
383
30c7e5b1
PZ
384 if (!has_legacy_pic()) {
385 /*
386 * Relies on tsc_early_delay_calibrate() to have given us semi
387 * usable udelay(), wait for the same 50ms we would have with
388 * the PIT loop below.
389 */
390 udelay(10 * USEC_PER_MSEC);
391 udelay(10 * USEC_PER_MSEC);
392 udelay(10 * USEC_PER_MSEC);
393 udelay(10 * USEC_PER_MSEC);
394 udelay(10 * USEC_PER_MSEC);
395 return ULONG_MAX;
396 }
397
ec0c15af
LT
398 /* Set the Gate high, disable speaker */
399 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
400
401 /*
402 * Setup CTC channel 2* for mode 0, (interrupt on terminal
403 * count mode), binary count. Set the latch register to 50ms
404 * (LSB then MSB) to begin countdown.
405 */
406 outb(0xb0, 0x43);
a977c400
TG
407 outb(latch & 0xff, 0x42);
408 outb(latch >> 8, 0x42);
ec0c15af
LT
409
410 tsc = t1 = t2 = get_cycles();
411
412 pitcnt = 0;
413 tscmax = 0;
414 tscmin = ULONG_MAX;
415 while ((inb(0x61) & 0x20) == 0) {
416 t2 = get_cycles();
417 delta = t2 - tsc;
418 tsc = t2;
419 if ((unsigned long) delta < tscmin)
420 tscmin = (unsigned int) delta;
421 if ((unsigned long) delta > tscmax)
422 tscmax = (unsigned int) delta;
423 pitcnt++;
424 }
425
426 /*
427 * Sanity checks:
428 *
a977c400 429 * If we were not able to read the PIT more than loopmin
ec0c15af
LT
430 * times, then we have been hit by a massive SMI
431 *
432 * If the maximum is 10 times larger than the minimum,
433 * then we got hit by an SMI as well.
434 */
a977c400 435 if (pitcnt < loopmin || tscmax > 10 * tscmin)
ec0c15af
LT
436 return ULONG_MAX;
437
438 /* Calculate the PIT value */
439 delta = t2 - t1;
a977c400 440 do_div(delta, ms);
ec0c15af
LT
441 return delta;
442}
443
6ac40ed0
LT
444/*
445 * This reads the current MSB of the PIT counter, and
446 * checks if we are running on sufficiently fast and
447 * non-virtualized hardware.
448 *
449 * Our expectations are:
450 *
451 * - the PIT is running at roughly 1.19MHz
452 *
453 * - each IO is going to take about 1us on real hardware,
454 * but we allow it to be much faster (by a factor of 10) or
455 * _slightly_ slower (ie we allow up to a 2us read+counter
456 * update - anything else implies a unacceptably slow CPU
457 * or PIT for the fast calibration to work.
458 *
459 * - with 256 PIT ticks to read the value, we have 214us to
460 * see the same MSB (and overhead like doing a single TSC
461 * read per MSB value etc).
462 *
463 * - We're doing 2 reads per loop (LSB, MSB), and we expect
464 * them each to take about a microsecond on real hardware.
465 * So we expect a count value of around 100. But we'll be
466 * generous, and accept anything over 50.
467 *
468 * - if the PIT is stuck, and we see *many* more reads, we
469 * return early (and the next caller of pit_expect_msb()
470 * then consider it a failure when they don't see the
471 * next expected value).
472 *
473 * These expectations mean that we know that we have seen the
474 * transition from one expected value to another with a fairly
475 * high accuracy, and we didn't miss any events. We can thus
476 * use the TSC value at the transitions to calculate a pretty
477 * good value for the TSC frequencty.
478 */
b6e61eef
LT
479static inline int pit_verify_msb(unsigned char val)
480{
481 /* Ignore LSB */
482 inb(0x42);
483 return inb(0x42) == val;
484}
485
9e8912e0 486static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
6ac40ed0 487{
9e8912e0 488 int count;
68f30fbe 489 u64 tsc = 0, prev_tsc = 0;
bfc0f594 490
6ac40ed0 491 for (count = 0; count < 50000; count++) {
b6e61eef 492 if (!pit_verify_msb(val))
6ac40ed0 493 break;
68f30fbe 494 prev_tsc = tsc;
9e8912e0 495 tsc = get_cycles();
6ac40ed0 496 }
68f30fbe 497 *deltap = get_cycles() - prev_tsc;
9e8912e0
LT
498 *tscp = tsc;
499
500 /*
501 * We require _some_ success, but the quality control
502 * will be based on the error terms on the TSC values.
503 */
504 return count > 5;
6ac40ed0
LT
505}
506
507/*
9e8912e0
LT
508 * How many MSB values do we want to see? We aim for
509 * a maximum error rate of 500ppm (in practice the
510 * real error is much smaller), but refuse to spend
68f30fbe 511 * more than 50ms on it.
6ac40ed0 512 */
68f30fbe 513#define MAX_QUICK_PIT_MS 50
9e8912e0 514#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
bfc0f594 515
6ac40ed0
LT
516static unsigned long quick_pit_calibrate(void)
517{
9e8912e0
LT
518 int i;
519 u64 tsc, delta;
520 unsigned long d1, d2;
521
30c7e5b1
PZ
522 if (!has_legacy_pic())
523 return 0;
524
6ac40ed0 525 /* Set the Gate high, disable speaker */
bfc0f594
AK
526 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
527
6ac40ed0
LT
528 /*
529 * Counter 2, mode 0 (one-shot), binary count
530 *
531 * NOTE! Mode 2 decrements by two (and then the
532 * output is flipped each time, giving the same
533 * final output frequency as a decrement-by-one),
534 * so mode 0 is much better when looking at the
535 * individual counts.
536 */
bfc0f594 537 outb(0xb0, 0x43);
bfc0f594 538
6ac40ed0
LT
539 /* Start at 0xffff */
540 outb(0xff, 0x42);
541 outb(0xff, 0x42);
542
a6a80e1d
LT
543 /*
544 * The PIT starts counting at the next edge, so we
545 * need to delay for a microsecond. The easiest way
546 * to do that is to just read back the 16-bit counter
547 * once from the PIT.
548 */
b6e61eef 549 pit_verify_msb(0);
a6a80e1d 550
9e8912e0
LT
551 if (pit_expect_msb(0xff, &tsc, &d1)) {
552 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
553 if (!pit_expect_msb(0xff-i, &delta, &d2))
554 break;
555
5aac644a
AH
556 delta -= tsc;
557
558 /*
559 * Extrapolate the error and fail fast if the error will
560 * never be below 500 ppm.
561 */
562 if (i == 1 &&
563 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
564 return 0;
565
9e8912e0
LT
566 /*
567 * Iterate until the error is less than 500 ppm
568 */
b6e61eef
LT
569 if (d1+d2 >= delta >> 11)
570 continue;
571
572 /*
573 * Check the PIT one more time to verify that
574 * all TSC reads were stable wrt the PIT.
575 *
576 * This also guarantees serialization of the
577 * last cycle read ('d2') in pit_expect_msb.
578 */
579 if (!pit_verify_msb(0xfe - i))
580 break;
581 goto success;
6ac40ed0 582 }
6ac40ed0 583 }
52045217 584 pr_info("Fast TSC calibration failed\n");
6ac40ed0 585 return 0;
9e8912e0
LT
586
587success:
588 /*
589 * Ok, if we get here, then we've seen the
590 * MSB of the PIT decrement 'i' times, and the
591 * error has shrunk to less than 500 ppm.
592 *
593 * As a result, we can depend on there not being
594 * any odd delays anywhere, and the TSC reads are
68f30fbe 595 * reliable (within the error).
9e8912e0
LT
596 *
597 * kHz = ticks / time-in-seconds / 1000;
598 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
599 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
600 */
9e8912e0
LT
601 delta *= PIT_TICK_RATE;
602 do_div(delta, i*256*1000);
c767a54b 603 pr_info("Fast TSC calibration using PIT\n");
9e8912e0 604 return delta;
6ac40ed0 605}
ec0c15af 606
bfc0f594 607/**
aa297292
LB
608 * native_calibrate_tsc
609 * Determine TSC frequency via CPUID, else return 0.
bfc0f594 610 */
e93ef949 611unsigned long native_calibrate_tsc(void)
aa297292
LB
612{
613 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
614 unsigned int crystal_khz;
615
616 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
617 return 0;
618
619 if (boot_cpu_data.cpuid_level < 0x15)
620 return 0;
621
622 eax_denominator = ebx_numerator = ecx_hz = edx = 0;
623
624 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
625 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
626
627 if (ebx_numerator == 0 || eax_denominator == 0)
628 return 0;
629
630 crystal_khz = ecx_hz / 1000;
631
632 if (crystal_khz == 0) {
633 switch (boot_cpu_data.x86_model) {
655e52d2
PB
634 case INTEL_FAM6_SKYLAKE_MOBILE:
635 case INTEL_FAM6_SKYLAKE_DESKTOP:
6baf3d61
PB
636 case INTEL_FAM6_KABYLAKE_MOBILE:
637 case INTEL_FAM6_KABYLAKE_DESKTOP:
ff4c8663
LB
638 crystal_khz = 24000; /* 24.0 MHz */
639 break;
f2c4db1b 640 case INTEL_FAM6_ATOM_GOLDMONT_X:
6baf3d61
PB
641 crystal_khz = 25000; /* 25.0 MHz */
642 break;
655e52d2 643 case INTEL_FAM6_ATOM_GOLDMONT:
ff4c8663
LB
644 crystal_khz = 19200; /* 19.2 MHz */
645 break;
aa297292
LB
646 }
647 }
648
da4ae6c4
LB
649 if (crystal_khz == 0)
650 return 0;
4ca4df0b
BG
651 /*
652 * TSC frequency determined by CPUID is a "hardware reported"
653 * frequency and is the most accurate one so far we have. This
654 * is considered a known frequency.
655 */
656 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
657
4635fdc6
BG
658 /*
659 * For Atom SoCs TSC is the only reliable clocksource.
660 * Mark TSC reliable so no watchdog on it.
661 */
662 if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
663 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
664
aa297292
LB
665 return crystal_khz * ebx_numerator / eax_denominator;
666}
667
668static unsigned long cpu_khz_from_cpuid(void)
669{
670 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
671
672 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
673 return 0;
674
675 if (boot_cpu_data.cpuid_level < 0x16)
676 return 0;
677
678 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
679
680 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
681
682 return eax_base_mhz * 1000;
683}
684
03821f45
PT
685/*
686 * calibrate cpu using pit, hpet, and ptimer methods. They are available
687 * later in boot after acpi is initialized.
aa297292 688 */
03821f45 689static unsigned long pit_hpet_ptimer_calibrate_cpu(void)
bfc0f594 690{
827014be 691 u64 tsc1, tsc2, delta, ref1, ref2;
fbb16e24 692 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
03821f45 693 unsigned long flags, latch, ms;
a977c400 694 int hpet = is_hpet_enabled(), i, loopmin;
bfc0f594 695
fbb16e24
TG
696 /*
697 * Run 5 calibration loops to get the lowest frequency value
698 * (the best estimate). We use two different calibration modes
699 * here:
700 *
701 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
702 * load a timeout of 50ms. We read the time right after we
703 * started the timer and wait until the PIT count down reaches
704 * zero. In each wait loop iteration we read the TSC and check
705 * the delta to the previous read. We keep track of the min
706 * and max values of that delta. The delta is mostly defined
a786ef15
DV
707 * by the IO time of the PIT access, so we can detect when
708 * any disturbance happened between the two reads. If the
fbb16e24
TG
709 * maximum time is significantly larger than the minimum time,
710 * then we discard the result and have another try.
711 *
712 * 2) Reference counter. If available we use the HPET or the
713 * PMTIMER as a reference to check the sanity of that value.
714 * We use separate TSC readouts and check inside of the
a786ef15 715 * reference read for any possible disturbance. We dicard
fbb16e24
TG
716 * disturbed values here as well. We do that around the PIT
717 * calibration delay loop as we have to wait for a certain
718 * amount of time anyway.
719 */
a977c400
TG
720
721 /* Preset PIT loop values */
722 latch = CAL_LATCH;
723 ms = CAL_MS;
724 loopmin = CAL_PIT_LOOPS;
725
726 for (i = 0; i < 3; i++) {
ec0c15af 727 unsigned long tsc_pit_khz;
fbb16e24
TG
728
729 /*
730 * Read the start value and the reference count of
ec0c15af
LT
731 * hpet/pmtimer when available. Then do the PIT
732 * calibration, which will take at least 50ms, and
733 * read the end value.
fbb16e24 734 */
ec0c15af 735 local_irq_save(flags);
827014be 736 tsc1 = tsc_read_refs(&ref1, hpet);
a977c400 737 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
827014be 738 tsc2 = tsc_read_refs(&ref2, hpet);
fbb16e24
TG
739 local_irq_restore(flags);
740
ec0c15af
LT
741 /* Pick the lowest PIT TSC calibration so far */
742 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
fbb16e24
TG
743
744 /* hpet or pmtimer available ? */
62627bec 745 if (ref1 == ref2)
fbb16e24
TG
746 continue;
747
a786ef15 748 /* Check, whether the sampling was disturbed */
fbb16e24
TG
749 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
750 continue;
751
752 tsc2 = (tsc2 - tsc1) * 1000000LL;
d683ef7a 753 if (hpet)
827014be 754 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
d683ef7a 755 else
827014be 756 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
fbb16e24 757
fbb16e24 758 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
a977c400
TG
759
760 /* Check the reference deviation */
761 delta = ((u64) tsc_pit_min) * 100;
762 do_div(delta, tsc_ref_min);
763
764 /*
765 * If both calibration results are inside a 10% window
766 * then we can be sure, that the calibration
767 * succeeded. We break out of the loop right away. We
768 * use the reference value, as it is more precise.
769 */
770 if (delta >= 90 && delta <= 110) {
c767a54b
JP
771 pr_info("PIT calibration matches %s. %d loops\n",
772 hpet ? "HPET" : "PMTIMER", i + 1);
a977c400 773 return tsc_ref_min;
fbb16e24
TG
774 }
775
a977c400
TG
776 /*
777 * Check whether PIT failed more than once. This
778 * happens in virtualized environments. We need to
779 * give the virtual PC a slightly longer timeframe for
780 * the HPET/PMTIMER to make the result precise.
781 */
782 if (i == 1 && tsc_pit_min == ULONG_MAX) {
783 latch = CAL2_LATCH;
784 ms = CAL2_MS;
785 loopmin = CAL2_PIT_LOOPS;
786 }
fbb16e24 787 }
bfc0f594
AK
788
789 /*
fbb16e24 790 * Now check the results.
bfc0f594 791 */
fbb16e24
TG
792 if (tsc_pit_min == ULONG_MAX) {
793 /* PIT gave no useful value */
c767a54b 794 pr_warn("Unable to calibrate against PIT\n");
fbb16e24
TG
795
796 /* We don't have an alternative source, disable TSC */
827014be 797 if (!hpet && !ref1 && !ref2) {
c767a54b 798 pr_notice("No reference (HPET/PMTIMER) available\n");
fbb16e24
TG
799 return 0;
800 }
801
802 /* The alternative source failed as well, disable TSC */
803 if (tsc_ref_min == ULONG_MAX) {
c767a54b 804 pr_warn("HPET/PMTIMER calibration failed\n");
fbb16e24
TG
805 return 0;
806 }
807
808 /* Use the alternative source */
c767a54b
JP
809 pr_info("using %s reference calibration\n",
810 hpet ? "HPET" : "PMTIMER");
fbb16e24
TG
811
812 return tsc_ref_min;
813 }
bfc0f594 814
fbb16e24 815 /* We don't have an alternative source, use the PIT calibration value */
827014be 816 if (!hpet && !ref1 && !ref2) {
c767a54b 817 pr_info("Using PIT calibration value\n");
fbb16e24 818 return tsc_pit_min;
bfc0f594
AK
819 }
820
fbb16e24
TG
821 /* The alternative source failed, use the PIT calibration value */
822 if (tsc_ref_min == ULONG_MAX) {
c767a54b 823 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
fbb16e24 824 return tsc_pit_min;
bfc0f594
AK
825 }
826
fbb16e24
TG
827 /*
828 * The calibration values differ too much. In doubt, we use
829 * the PIT value as we know that there are PMTIMERs around
a977c400 830 * running at double speed. At least we let the user know:
fbb16e24 831 */
c767a54b
JP
832 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
833 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
834 pr_info("Using PIT calibration value\n");
fbb16e24 835 return tsc_pit_min;
bfc0f594
AK
836}
837
03821f45
PT
838/**
839 * native_calibrate_cpu_early - can calibrate the cpu early in boot
840 */
841unsigned long native_calibrate_cpu_early(void)
842{
843 unsigned long flags, fast_calibrate = cpu_khz_from_cpuid();
844
845 if (!fast_calibrate)
846 fast_calibrate = cpu_khz_from_msr();
847 if (!fast_calibrate) {
848 local_irq_save(flags);
849 fast_calibrate = quick_pit_calibrate();
850 local_irq_restore(flags);
851 }
852 return fast_calibrate;
853}
854
855
856/**
857 * native_calibrate_cpu - calibrate the cpu
858 */
8dbe4385 859static unsigned long native_calibrate_cpu(void)
03821f45
PT
860{
861 unsigned long tsc_freq = native_calibrate_cpu_early();
862
863 if (!tsc_freq)
864 tsc_freq = pit_hpet_ptimer_calibrate_cpu();
865
866 return tsc_freq;
867}
868
af576850 869void recalibrate_cpu_khz(void)
bfc0f594
AK
870{
871#ifndef CONFIG_SMP
872 unsigned long cpu_khz_old = cpu_khz;
873
eff4677e 874 if (!boot_cpu_has(X86_FEATURE_TSC))
af576850 875 return;
eff4677e 876
aa297292 877 cpu_khz = x86_platform.calibrate_cpu();
eff4677e 878 tsc_khz = x86_platform.calibrate_tsc();
aa297292
LB
879 if (tsc_khz == 0)
880 tsc_khz = cpu_khz;
ff4c8663
LB
881 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
882 cpu_khz = tsc_khz;
eff4677e
BP
883 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
884 cpu_khz_old, cpu_khz);
bfc0f594
AK
885#endif
886}
887
888EXPORT_SYMBOL(recalibrate_cpu_khz);
889
2dbe06fa 890
cd7240c0
SS
891static unsigned long long cyc2ns_suspend;
892
b74f05d6 893void tsc_save_sched_clock_state(void)
cd7240c0 894{
35af99e6 895 if (!sched_clock_stable())
cd7240c0
SS
896 return;
897
898 cyc2ns_suspend = sched_clock();
899}
900
901/*
902 * Even on processors with invariant TSC, TSC gets reset in some the
903 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
904 * arbitrary value (still sync'd across cpu's) during resume from such sleep
905 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
906 * that sched_clock() continues from the point where it was left off during
907 * suspend.
908 */
b74f05d6 909void tsc_restore_sched_clock_state(void)
cd7240c0
SS
910{
911 unsigned long long offset;
912 unsigned long flags;
913 int cpu;
914
35af99e6 915 if (!sched_clock_stable())
cd7240c0
SS
916 return;
917
918 local_irq_save(flags);
919
20d1c86a 920 /*
6a6256f9 921 * We're coming out of suspend, there's no concurrency yet; don't
20d1c86a
PZ
922 * bother being nice about the RCU stuff, just write to both
923 * data fields.
924 */
925
926 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
927 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
928
cd7240c0
SS
929 offset = cyc2ns_suspend - sched_clock();
930
20d1c86a
PZ
931 for_each_possible_cpu(cpu) {
932 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
933 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
934 }
cd7240c0
SS
935
936 local_irq_restore(flags);
937}
938
2dbe06fa 939#ifdef CONFIG_CPU_FREQ
2dbe06fa
AK
940/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
941 * changes.
942 *
943 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
944 * not that important because current Opteron setups do not support
945 * scaling on SMP anyroads.
946 *
947 * Should fix up last_tsc too. Currently gettimeofday in the
948 * first tick after the change will be slightly wrong.
949 */
950
951static unsigned int ref_freq;
952static unsigned long loops_per_jiffy_ref;
953static unsigned long tsc_khz_ref;
954
955static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
956 void *data)
957{
958 struct cpufreq_freqs *freq = data;
931db6a3 959 unsigned long *lpj;
2dbe06fa 960
931db6a3 961 lpj = &boot_cpu_data.loops_per_jiffy;
2dbe06fa 962#ifdef CONFIG_SMP
931db6a3 963 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
2dbe06fa 964 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
2dbe06fa
AK
965#endif
966
967 if (!ref_freq) {
968 ref_freq = freq->old;
969 loops_per_jiffy_ref = *lpj;
970 tsc_khz_ref = tsc_khz;
971 }
972 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
0b443ead 973 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
878f4f53 974 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
2dbe06fa
AK
975
976 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
977 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
978 mark_tsc_unstable("cpufreq changes");
2dbe06fa 979
5c3c2ea6 980 set_cyc2ns_scale(tsc_khz, freq->cpu, rdtsc());
3896c329 981 }
2dbe06fa
AK
982
983 return 0;
984}
985
986static struct notifier_block time_cpufreq_notifier_block = {
987 .notifier_call = time_cpufreq_notifier
988};
989
a841cca7 990static int __init cpufreq_register_tsc_scaling(void)
2dbe06fa 991{
59e21e3d 992 if (!boot_cpu_has(X86_FEATURE_TSC))
060700b5
LT
993 return 0;
994 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
995 return 0;
2dbe06fa
AK
996 cpufreq_register_notifier(&time_cpufreq_notifier_block,
997 CPUFREQ_TRANSITION_NOTIFIER);
998 return 0;
999}
1000
a841cca7 1001core_initcall(cpufreq_register_tsc_scaling);
2dbe06fa
AK
1002
1003#endif /* CONFIG_CPU_FREQ */
8fbbc4b4 1004
f9677e0f
CH
1005#define ART_CPUID_LEAF (0x15)
1006#define ART_MIN_DENOMINATOR (1)
1007
1008
1009/*
1010 * If ART is present detect the numerator:denominator to convert to TSC
1011 */
120fc3fb 1012static void __init detect_art(void)
f9677e0f
CH
1013{
1014 unsigned int unused[2];
1015
1016 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
1017 return;
1018
6c66350d 1019 /*
1020 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,
1021 * and the TSC counter resets must not occur asynchronously.
1022 */
f9677e0f
CH
1023 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
1024 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
6c66350d 1025 !boot_cpu_has(X86_FEATURE_TSC_ADJUST) ||
1026 tsc_async_resets)
f9677e0f
CH
1027 return;
1028
7b3d2f6e
TG
1029 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
1030 &art_to_tsc_numerator, unused, unused+1);
1031
1032 if (art_to_tsc_denominator < ART_MIN_DENOMINATOR)
f9677e0f
CH
1033 return;
1034
7b3d2f6e
TG
1035 rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset);
1036
f9677e0f
CH
1037 /* Make this sticky over multiple CPU init calls */
1038 setup_force_cpu_cap(X86_FEATURE_ART);
1039}
1040
1041
8fbbc4b4
AK
1042/* clocksource code */
1043
6a369583
TG
1044static void tsc_resume(struct clocksource *cs)
1045{
1046 tsc_verify_tsc_adjust(true);
1047}
1048
8fbbc4b4 1049/*
09ec5442 1050 * We used to compare the TSC to the cycle_last value in the clocksource
8fbbc4b4
AK
1051 * structure to avoid a nasty time-warp. This can be observed in a
1052 * very small window right after one CPU updated cycle_last under
1053 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1054 * is smaller than the cycle_last reference value due to a TSC which
1055 * is slighty behind. This delta is nowhere else observable, but in
1056 * that case it results in a forward time jump in the range of hours
1057 * due to the unsigned delta calculation of the time keeping core
1058 * code, which is necessary to support wrapping clocksources like pm
1059 * timer.
09ec5442
TG
1060 *
1061 * This sanity check is now done in the core timekeeping code.
1062 * checking the result of read_tsc() - cycle_last for being negative.
1063 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
8fbbc4b4 1064 */
a5a1d1c2 1065static u64 read_tsc(struct clocksource *cs)
8fbbc4b4 1066{
a5a1d1c2 1067 return (u64)rdtsc_ordered();
1be39679
MS
1068}
1069
12907fbb
TG
1070static void tsc_cs_mark_unstable(struct clocksource *cs)
1071{
1072 if (tsc_unstable)
1073 return;
f94c8d11 1074
12907fbb 1075 tsc_unstable = 1;
f94c8d11
PZ
1076 if (using_native_sched_clock())
1077 clear_sched_clock_stable();
12907fbb
TG
1078 disable_sched_clock_irqtime();
1079 pr_info("Marking TSC unstable due to clocksource watchdog\n");
1080}
1081
b421b22b
PZ
1082static void tsc_cs_tick_stable(struct clocksource *cs)
1083{
1084 if (tsc_unstable)
1085 return;
1086
1087 if (using_native_sched_clock())
1088 sched_clock_tick_stable();
1089}
1090
09ec5442
TG
1091/*
1092 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1093 */
aa83c457
PZ
1094static struct clocksource clocksource_tsc_early = {
1095 .name = "tsc-early",
1096 .rating = 299,
1097 .read = read_tsc,
1098 .mask = CLOCKSOURCE_MASK(64),
1099 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1100 CLOCK_SOURCE_MUST_VERIFY,
1101 .archdata = { .vclock_mode = VCLOCK_TSC },
1102 .resume = tsc_resume,
1103 .mark_unstable = tsc_cs_mark_unstable,
1104 .tick_stable = tsc_cs_tick_stable,
e3b4f790 1105 .list = LIST_HEAD_INIT(clocksource_tsc_early.list),
aa83c457
PZ
1106};
1107
1108/*
1109 * Must mark VALID_FOR_HRES early such that when we unregister tsc_early
1110 * this one will immediately take over. We will only register if TSC has
1111 * been found good.
1112 */
8fbbc4b4
AK
1113static struct clocksource clocksource_tsc = {
1114 .name = "tsc",
1115 .rating = 300,
1116 .read = read_tsc,
1117 .mask = CLOCKSOURCE_MASK(64),
8fbbc4b4 1118 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
aa83c457 1119 CLOCK_SOURCE_VALID_FOR_HRES |
8fbbc4b4 1120 CLOCK_SOURCE_MUST_VERIFY,
98d0ac38 1121 .archdata = { .vclock_mode = VCLOCK_TSC },
6a369583 1122 .resume = tsc_resume,
12907fbb 1123 .mark_unstable = tsc_cs_mark_unstable,
b421b22b 1124 .tick_stable = tsc_cs_tick_stable,
e3b4f790 1125 .list = LIST_HEAD_INIT(clocksource_tsc.list),
8fbbc4b4
AK
1126};
1127
1128void mark_tsc_unstable(char *reason)
1129{
f94c8d11
PZ
1130 if (tsc_unstable)
1131 return;
1132
1133 tsc_unstable = 1;
1134 if (using_native_sched_clock())
35af99e6 1135 clear_sched_clock_stable();
f94c8d11
PZ
1136 disable_sched_clock_irqtime();
1137 pr_info("Marking TSC unstable due to %s\n", reason);
e3b4f790
PZ
1138
1139 clocksource_mark_unstable(&clocksource_tsc_early);
1140 clocksource_mark_unstable(&clocksource_tsc);
8fbbc4b4
AK
1141}
1142
1143EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1144
395628ef
AK
1145static void __init check_system_tsc_reliable(void)
1146{
03da3ff1
DW
1147#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1148 if (is_geode_lx()) {
1149 /* RTSC counts during suspend */
8fbbc4b4 1150#define RTSC_SUSP 0x100
03da3ff1 1151 unsigned long res_low, res_high;
8fbbc4b4 1152
03da3ff1
DW
1153 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1154 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1155 if (res_low & RTSC_SUSP)
1156 tsc_clocksource_reliable = 1;
1157 }
8fbbc4b4 1158#endif
395628ef
AK
1159 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1160 tsc_clocksource_reliable = 1;
1161}
8fbbc4b4
AK
1162
1163/*
1164 * Make an educated guess if the TSC is trustworthy and synchronized
1165 * over all CPUs.
1166 */
148f9bb8 1167int unsynchronized_tsc(void)
8fbbc4b4 1168{
59e21e3d 1169 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
8fbbc4b4
AK
1170 return 1;
1171
3e5095d1 1172#ifdef CONFIG_SMP
8fbbc4b4
AK
1173 if (apic_is_clustered_box())
1174 return 1;
1175#endif
1176
1177 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1178 return 0;
d3b8f889 1179
1180 if (tsc_clocksource_reliable)
1181 return 0;
8fbbc4b4
AK
1182 /*
1183 * Intel systems are normally all synchronized.
1184 * Exceptions must mark TSC as unstable:
1185 */
1186 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1187 /* assume multi socket systems are not synchronized: */
1188 if (num_possible_cpus() > 1)
d3b8f889 1189 return 1;
8fbbc4b4
AK
1190 }
1191
d3b8f889 1192 return 0;
8fbbc4b4
AK
1193}
1194
f9677e0f
CH
1195/*
1196 * Convert ART to TSC given numerator/denominator found in detect_art()
1197 */
a5a1d1c2 1198struct system_counterval_t convert_art_to_tsc(u64 art)
f9677e0f
CH
1199{
1200 u64 tmp, res, rem;
1201
1202 rem = do_div(art, art_to_tsc_denominator);
1203
1204 res = art * art_to_tsc_numerator;
1205 tmp = rem * art_to_tsc_numerator;
1206
1207 do_div(tmp, art_to_tsc_denominator);
1208 res += tmp + art_to_tsc_offset;
1209
1210 return (struct system_counterval_t) {.cs = art_related_clocksource,
1211 .cycles = res};
1212}
1213EXPORT_SYMBOL(convert_art_to_tsc);
08ec0c58 1214
fc804f65
RJ
1215/**
1216 * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC.
1217 * @art_ns: ART (Always Running Timer) in unit of nanoseconds
1218 *
1219 * PTM requires all timestamps to be in units of nanoseconds. When user
1220 * software requests a cross-timestamp, this function converts system timestamp
1221 * to TSC.
1222 *
1223 * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set
1224 * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check
1225 * that this flag is set before conversion to TSC is attempted.
1226 *
1227 * Return:
1228 * struct system_counterval_t - system counter value with the pointer to the
1229 * corresponding clocksource
1230 * @cycles: System counter value
1231 * @cs: Clocksource corresponding to system counter value. Used
1232 * by timekeeping code to verify comparibility of two cycle
1233 * values.
1234 */
1235
1236struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns)
1237{
1238 u64 tmp, res, rem;
1239
1240 rem = do_div(art_ns, USEC_PER_SEC);
1241
1242 res = art_ns * tsc_khz;
1243 tmp = rem * tsc_khz;
1244
1245 do_div(tmp, USEC_PER_SEC);
1246 res += tmp;
1247
1248 return (struct system_counterval_t) { .cs = art_related_clocksource,
1249 .cycles = res};
1250}
1251EXPORT_SYMBOL(convert_art_ns_to_tsc);
1252
1253
08ec0c58
JS
1254static void tsc_refine_calibration_work(struct work_struct *work);
1255static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1256/**
1257 * tsc_refine_calibration_work - Further refine tsc freq calibration
1258 * @work - ignored.
1259 *
1260 * This functions uses delayed work over a period of a
1261 * second to further refine the TSC freq value. Since this is
1262 * timer based, instead of loop based, we don't block the boot
1263 * process while this longer calibration is done.
1264 *
0d2eb44f 1265 * If there are any calibration anomalies (too many SMIs, etc),
08ec0c58
JS
1266 * or the refined calibration is off by 1% of the fast early
1267 * calibration, we throw out the new calibration and use the
1268 * early calibration.
1269 */
1270static void tsc_refine_calibration_work(struct work_struct *work)
1271{
a786ef15 1272 static u64 tsc_start = ULLONG_MAX, ref_start;
08ec0c58
JS
1273 static int hpet;
1274 u64 tsc_stop, ref_stop, delta;
1275 unsigned long freq;
aa7b630e 1276 int cpu;
08ec0c58
JS
1277
1278 /* Don't bother refining TSC on unstable systems */
aa83c457 1279 if (tsc_unstable)
e9088add 1280 goto unreg;
08ec0c58
JS
1281
1282 /*
1283 * Since the work is started early in boot, we may be
1284 * delayed the first time we expire. So set the workqueue
1285 * again once we know timers are working.
1286 */
a786ef15
DV
1287 if (tsc_start == ULLONG_MAX) {
1288restart:
08ec0c58
JS
1289 /*
1290 * Only set hpet once, to avoid mixing hardware
1291 * if the hpet becomes enabled later.
1292 */
1293 hpet = is_hpet_enabled();
08ec0c58 1294 tsc_start = tsc_read_refs(&ref_start, hpet);
a786ef15 1295 schedule_delayed_work(&tsc_irqwork, HZ);
08ec0c58
JS
1296 return;
1297 }
1298
1299 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1300
1301 /* hpet or pmtimer available ? */
62627bec 1302 if (ref_start == ref_stop)
08ec0c58
JS
1303 goto out;
1304
a786ef15
DV
1305 /* Check, whether the sampling was disturbed */
1306 if (tsc_stop == ULLONG_MAX)
1307 goto restart;
08ec0c58
JS
1308
1309 delta = tsc_stop - tsc_start;
1310 delta *= 1000000LL;
1311 if (hpet)
1312 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1313 else
1314 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1315
1316 /* Make sure we're within 1% */
1317 if (abs(tsc_khz - freq) > tsc_khz/100)
1318 goto out;
1319
1320 tsc_khz = freq;
c767a54b
JP
1321 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1322 (unsigned long)tsc_khz / 1000,
1323 (unsigned long)tsc_khz % 1000);
08ec0c58 1324
6731b0d6
NS
1325 /* Inform the TSC deadline clockevent devices about the recalibration */
1326 lapic_update_tsc_freq();
1327
aa7b630e
PZ
1328 /* Update the sched_clock() rate to match the clocksource one */
1329 for_each_possible_cpu(cpu)
5c3c2ea6 1330 set_cyc2ns_scale(tsc_khz, cpu, tsc_stop);
aa7b630e 1331
08ec0c58 1332out:
aa83c457 1333 if (tsc_unstable)
e9088add 1334 goto unreg;
aa83c457 1335
f9677e0f
CH
1336 if (boot_cpu_has(X86_FEATURE_ART))
1337 art_related_clocksource = &clocksource_tsc;
08ec0c58 1338 clocksource_register_khz(&clocksource_tsc, tsc_khz);
e9088add 1339unreg:
aa83c457 1340 clocksource_unregister(&clocksource_tsc_early);
08ec0c58
JS
1341}
1342
1343
1344static int __init init_tsc_clocksource(void)
8fbbc4b4 1345{
fe9af81e 1346 if (!boot_cpu_has(X86_FEATURE_TSC) || !tsc_khz)
a8760eca
TG
1347 return 0;
1348
e9088add
PZ
1349 if (tsc_unstable)
1350 goto unreg;
aa83c457 1351
395628ef
AK
1352 if (tsc_clocksource_reliable)
1353 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
57779dc2 1354
82f9c080
FT
1355 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1356 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1357
57779dc2 1358 /*
47c95a46
BG
1359 * When TSC frequency is known (retrieved via MSR or CPUID), we skip
1360 * the refined calibration and directly register it as a clocksource.
57779dc2 1361 */
984feceb 1362 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
44fee88c
PZ
1363 if (boot_cpu_has(X86_FEATURE_ART))
1364 art_related_clocksource = &clocksource_tsc;
57779dc2 1365 clocksource_register_khz(&clocksource_tsc, tsc_khz);
e9088add 1366unreg:
aa83c457 1367 clocksource_unregister(&clocksource_tsc_early);
57779dc2
AK
1368 return 0;
1369 }
1370
08ec0c58
JS
1371 schedule_delayed_work(&tsc_irqwork, 0);
1372 return 0;
8fbbc4b4 1373}
08ec0c58
JS
1374/*
1375 * We use device_initcall here, to ensure we run after the hpet
1376 * is fully initialized, which may occur at fs_initcall time.
1377 */
1378device_initcall(init_tsc_clocksource);
8fbbc4b4 1379
8dbe4385 1380static bool __init determine_cpu_tsc_frequencies(bool early)
8fbbc4b4 1381{
cf7a63ef
PT
1382 /* Make sure that cpu and tsc are not already calibrated */
1383 WARN_ON(cpu_khz || tsc_khz);
8fbbc4b4 1384
8dbe4385
PT
1385 if (early) {
1386 cpu_khz = x86_platform.calibrate_cpu();
1387 tsc_khz = x86_platform.calibrate_tsc();
1388 } else {
1389 /* We should not be here with non-native cpu calibration */
1390 WARN_ON(x86_platform.calibrate_cpu != native_calibrate_cpu);
1391 cpu_khz = pit_hpet_ptimer_calibrate_cpu();
1392 }
ff4c8663
LB
1393
1394 /*
608008a4 1395 * Trust non-zero tsc_khz as authoritative,
ff4c8663
LB
1396 * and use it to sanity check cpu_khz,
1397 * which will be off if system timer is off.
1398 */
aa297292
LB
1399 if (tsc_khz == 0)
1400 tsc_khz = cpu_khz;
ff4c8663
LB
1401 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
1402 cpu_khz = tsc_khz;
8fbbc4b4 1403
cf7a63ef
PT
1404 if (tsc_khz == 0)
1405 return false;
8fbbc4b4 1406
c767a54b 1407 pr_info("Detected %lu.%03lu MHz processor\n",
cf7a63ef
PT
1408 (unsigned long)cpu_khz / KHZ,
1409 (unsigned long)cpu_khz % KHZ);
8fbbc4b4 1410
4b5b2127
LB
1411 if (cpu_khz != tsc_khz) {
1412 pr_info("Detected %lu.%03lu MHz TSC",
cf7a63ef
PT
1413 (unsigned long)tsc_khz / KHZ,
1414 (unsigned long)tsc_khz % KHZ);
1415 }
1416 return true;
1417}
1418
1419static unsigned long __init get_loops_per_jiffy(void)
1420{
17f6bac2 1421 u64 lpj = (u64)tsc_khz * KHZ;
cf7a63ef
PT
1422
1423 do_div(lpj, HZ);
1424 return lpj;
1425}
1426
608008a4
DL
1427static void __init tsc_enable_sched_clock(void)
1428{
1429 /* Sanitize TSC ADJUST before cyc2ns gets initialized */
1430 tsc_store_and_check_tsc_adjust(true);
1431 cyc2ns_init_boot_cpu();
1432 static_branch_enable(&__use_tsc);
1433}
1434
cf7a63ef
PT
1435void __init tsc_early_init(void)
1436{
1437 if (!boot_cpu_has(X86_FEATURE_TSC))
1438 return;
2647c43c
MT
1439 /* Don't change UV TSC multi-chassis synchronization */
1440 if (is_early_uv_system())
1441 return;
8dbe4385 1442 if (!determine_cpu_tsc_frequencies(true))
cf7a63ef
PT
1443 return;
1444 loops_per_jiffy = get_loops_per_jiffy();
e2a9ca29 1445
608008a4 1446 tsc_enable_sched_clock();
cf7a63ef
PT
1447}
1448
1449void __init tsc_init(void)
1450{
8dbe4385
PT
1451 /*
1452 * native_calibrate_cpu_early can only calibrate using methods that are
1453 * available early in boot.
1454 */
1455 if (x86_platform.calibrate_cpu == native_calibrate_cpu_early)
1456 x86_platform.calibrate_cpu = native_calibrate_cpu;
1457
cf7a63ef
PT
1458 if (!boot_cpu_has(X86_FEATURE_TSC)) {
1459 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1460 return;
1461 }
1462
1463 if (!tsc_khz) {
1464 /* We failed to determine frequencies earlier, try again */
8dbe4385 1465 if (!determine_cpu_tsc_frequencies(false)) {
cf7a63ef
PT
1466 mark_tsc_unstable("could not calculate TSC khz");
1467 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1468 return;
1469 }
608008a4 1470 tsc_enable_sched_clock();
4b5b2127
LB
1471 }
1472
e2a9ca29 1473 cyc2ns_init_secondary_cpus();
8fbbc4b4 1474
e82b8e4e
VP
1475 if (!no_sched_irq_time)
1476 enable_sched_clock_irqtime();
1477
cf7a63ef 1478 lpj_fine = get_loops_per_jiffy();
8fbbc4b4 1479 use_tsc_delay();
8fbbc4b4 1480
a1272dd5
ZD
1481 check_system_tsc_reliable();
1482
aa83c457 1483 if (unsynchronized_tsc()) {
8fbbc4b4 1484 mark_tsc_unstable("TSCs unsynchronized");
aa83c457
PZ
1485 return;
1486 }
8fbbc4b4 1487
aa83c457 1488 clocksource_register_khz(&clocksource_tsc_early, tsc_khz);
f9677e0f 1489 detect_art();
8fbbc4b4
AK
1490}
1491
b565201c
JS
1492#ifdef CONFIG_SMP
1493/*
1494 * If we have a constant TSC and are using the TSC for the delay loop,
1495 * we can skip clock calibration if another cpu in the same socket has already
1496 * been calibrated. This assumes that CONSTANT_TSC applies to all
1497 * cpus in the socket - this should be a safe assumption.
1498 */
148f9bb8 1499unsigned long calibrate_delay_is_known(void)
b565201c 1500{
c25323c0 1501 int sibling, cpu = smp_processor_id();
76ce7cfe
PT
1502 int constant_tsc = cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC);
1503 const struct cpumask *mask = topology_core_cpumask(cpu);
b565201c 1504
fe9af81e 1505 if (!constant_tsc || !mask)
f508a5ba
TG
1506 return 0;
1507
1508 sibling = cpumask_any_but(mask, cpu);
c25323c0
TG
1509 if (sibling < nr_cpu_ids)
1510 return cpu_data(sibling).loops_per_jiffy;
b565201c
JS
1511 return 0;
1512}
1513#endif