Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69575d38 | 50 | #include <linux/tboot.h> |
35f720c5 | 51 | #include <linux/stackprotector.h> |
5a0e3ad6 | 52 | #include <linux/gfp.h> |
69c18c15 | 53 | |
8aef135c | 54 | #include <asm/acpi.h> |
cb3c8b90 | 55 | #include <asm/desc.h> |
69c18c15 GC |
56 | #include <asm/nmi.h> |
57 | #include <asm/irq.h> | |
07bbc16a | 58 | #include <asm/idle.h> |
e44b7b75 | 59 | #include <asm/trampoline.h> |
69c18c15 GC |
60 | #include <asm/cpu.h> |
61 | #include <asm/numa.h> | |
cb3c8b90 GOC |
62 | #include <asm/pgtable.h> |
63 | #include <asm/tlbflush.h> | |
64 | #include <asm/mtrr.h> | |
ea530692 | 65 | #include <asm/mwait.h> |
bbc2ff6a | 66 | #include <asm/vmi.h> |
7b6aa335 | 67 | #include <asm/apic.h> |
569712b2 | 68 | #include <asm/setup.h> |
bdbcdd48 | 69 | #include <asm/uv/uv.h> |
cb3c8b90 | 70 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 71 | |
1164dd00 | 72 | #include <asm/smpboot_hooks.h> |
b81bb373 | 73 | #include <asm/i8259.h> |
cb3c8b90 | 74 | |
16ecf7a4 | 75 | #ifdef CONFIG_X86_32 |
4cedb334 | 76 | u8 apicid_2_node[MAX_APICID]; |
acbb6734 GOC |
77 | #endif |
78 | ||
a8db8453 GOC |
79 | /* State of each CPU */ |
80 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
81 | ||
cb3c8b90 GOC |
82 | /* Store all idle threads, this can be reused instead of creating |
83 | * a new thread. Also avoids complicated thread destroy functionality | |
84 | * for idle threads. | |
85 | */ | |
86 | #ifdef CONFIG_HOTPLUG_CPU | |
87 | /* | |
88 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
89 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
90 | */ | |
91 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
92 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
93 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
d7c53c9e BP |
94 | |
95 | /* | |
96 | * We need this for trampoline_base protection from concurrent accesses when | |
97 | * off- and onlining cores wildly. | |
98 | */ | |
99 | static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); | |
100 | ||
101 | void cpu_hotplug_driver_lock() | |
102 | { | |
103 | mutex_lock(&x86_cpu_hotplug_driver_mutex); | |
104 | } | |
105 | ||
106 | void cpu_hotplug_driver_unlock() | |
107 | { | |
108 | mutex_unlock(&x86_cpu_hotplug_driver_mutex); | |
109 | } | |
110 | ||
111 | ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } | |
112 | ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } | |
cb3c8b90 | 113 | #else |
f86c9985 | 114 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
115 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
116 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
117 | #endif | |
f6bc4029 | 118 | |
a355352b GC |
119 | /* Number of siblings per CPU package */ |
120 | int smp_num_siblings = 1; | |
121 | EXPORT_SYMBOL(smp_num_siblings); | |
122 | ||
123 | /* Last level cache ID of each logical CPU */ | |
124 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
125 | ||
a355352b | 126 | /* representing HT siblings of each logical CPU */ |
7ad728f9 | 127 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
128 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
129 | ||
130 | /* representing HT and core siblings of each logical CPU */ | |
7ad728f9 | 131 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
a355352b GC |
132 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
133 | ||
134 | /* Per CPU bogomips and other parameters */ | |
135 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
136 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 137 | |
2b6163bf | 138 | atomic_t init_deasserted; |
cb3c8b90 | 139 | |
7cc3959e | 140 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
7cc3959e GOC |
141 | /* which node each logical CPU is on */ |
142 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
143 | EXPORT_SYMBOL(cpu_to_node_map); | |
144 | ||
145 | /* set up a mapping between cpu and node. */ | |
146 | static void map_cpu_to_node(int cpu, int node) | |
147 | { | |
148 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
c032ef60 | 149 | cpumask_set_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
150 | cpu_to_node_map[cpu] = node; |
151 | } | |
152 | ||
153 | /* undo a mapping between cpu and node. */ | |
154 | static void unmap_cpu_to_node(int cpu) | |
155 | { | |
156 | int node; | |
157 | ||
158 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
159 | for (node = 0; node < MAX_NUMNODES; node++) | |
c032ef60 | 160 | cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
161 | cpu_to_node_map[cpu] = 0; |
162 | } | |
163 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
164 | #define map_cpu_to_node(cpu, node) ({}) | |
165 | #define unmap_cpu_to_node(cpu) ({}) | |
166 | #endif | |
167 | ||
168 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
169 | static int boot_cpu_logical_apicid; |
170 | ||
7cc3959e GOC |
171 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
172 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
173 | ||
a4928cff | 174 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
175 | { |
176 | int cpu = smp_processor_id(); | |
177 | int apicid = logical_smp_processor_id(); | |
3f57a318 | 178 | int node = apic->apicid_to_node(apicid); |
7cc3959e GOC |
179 | |
180 | if (!node_online(node)) | |
181 | node = first_online_node; | |
182 | ||
183 | cpu_2_logical_apicid[cpu] = apicid; | |
184 | map_cpu_to_node(cpu, node); | |
185 | } | |
186 | ||
1481a3dd | 187 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
188 | { |
189 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
190 | unmap_cpu_to_node(cpu); | |
191 | } | |
192 | #else | |
7cc3959e GOC |
193 | #define map_cpu_to_logical_apicid() do {} while (0) |
194 | #endif | |
195 | ||
cb3c8b90 GOC |
196 | /* |
197 | * Report back to the Boot Processor. | |
198 | * Running on AP. | |
199 | */ | |
a4928cff | 200 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
201 | { |
202 | int cpuid, phys_id; | |
203 | unsigned long timeout; | |
204 | ||
205 | /* | |
206 | * If waken up by an INIT in an 82489DX configuration | |
207 | * we may get here before an INIT-deassert IPI reaches | |
208 | * our local APIC. We have to wait for the IPI or we'll | |
209 | * lock up on an APIC access. | |
210 | */ | |
a9659366 IM |
211 | if (apic->wait_for_init_deassert) |
212 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
213 | |
214 | /* | |
215 | * (This works even if the APIC is not enabled.) | |
216 | */ | |
4c9961d5 | 217 | phys_id = read_apic_id(); |
cb3c8b90 | 218 | cpuid = smp_processor_id(); |
c2d1cec1 | 219 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
220 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
221 | phys_id, cpuid); | |
222 | } | |
cfc1b9a6 | 223 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
224 | |
225 | /* | |
226 | * STARTUP IPIs are fragile beasts as they might sometimes | |
227 | * trigger some glue motherboard logic. Complete APIC bus | |
228 | * silence for 1 second, this overestimates the time the | |
229 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
230 | * by a factor of two. This should be enough. | |
231 | */ | |
232 | ||
233 | /* | |
234 | * Waiting 2s total for startup (udelay is not yet working) | |
235 | */ | |
236 | timeout = jiffies + 2*HZ; | |
237 | while (time_before(jiffies, timeout)) { | |
238 | /* | |
239 | * Has the boot CPU finished it's STARTUP sequence? | |
240 | */ | |
c2d1cec1 | 241 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
242 | break; |
243 | cpu_relax(); | |
244 | } | |
245 | ||
246 | if (!time_before(jiffies, timeout)) { | |
247 | panic("%s: CPU%d started up but did not get a callout!\n", | |
248 | __func__, cpuid); | |
249 | } | |
250 | ||
251 | /* | |
252 | * the boot CPU has finished the init stage and is spinning | |
253 | * on callin_map until we finish. We are free to set up this | |
254 | * CPU, first the APIC. (this is probably redundant on most | |
255 | * boards) | |
256 | */ | |
257 | ||
cfc1b9a6 | 258 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
259 | if (apic->smp_callin_clear_local_apic) |
260 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
261 | setup_local_APIC(); |
262 | end_local_APIC_setup(); | |
263 | map_cpu_to_logical_apicid(); | |
264 | ||
9d133e5d SS |
265 | /* |
266 | * Need to setup vector mappings before we enable interrupts. | |
267 | */ | |
36e9e1ea | 268 | setup_vector_irq(smp_processor_id()); |
cb3c8b90 GOC |
269 | /* |
270 | * Get our bogomips. | |
271 | * | |
272 | * Need to enable IRQs because it can take longer and then | |
273 | * the NMI watchdog might kill us. | |
274 | */ | |
275 | local_irq_enable(); | |
276 | calibrate_delay(); | |
277 | local_irq_disable(); | |
cfc1b9a6 | 278 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
279 | |
280 | /* | |
281 | * Save our processor parameters | |
282 | */ | |
283 | smp_store_cpu_info(cpuid); | |
284 | ||
85257024 PZ |
285 | notify_cpu_starting(cpuid); |
286 | ||
cb3c8b90 GOC |
287 | /* |
288 | * Allow the master to continue. | |
289 | */ | |
c2d1cec1 | 290 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
291 | } |
292 | ||
bbc2ff6a GOC |
293 | /* |
294 | * Activate a secondary processor. | |
295 | */ | |
0ca59dd9 | 296 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
297 | { |
298 | /* | |
299 | * Don't put *anything* before cpu_init(), SMP booting is too | |
300 | * fragile that we want to limit the things done here to the | |
301 | * most necessary things. | |
302 | */ | |
fd89a137 JR |
303 | |
304 | #ifdef CONFIG_X86_32 | |
305 | /* | |
306 | * Switch away from the trampoline page-table | |
307 | * | |
308 | * Do this before cpu_init() because it needs to access per-cpu | |
309 | * data which may not be mapped in the trampoline page-table. | |
310 | */ | |
311 | load_cr3(swapper_pg_dir); | |
312 | __flush_tlb_all(); | |
313 | #endif | |
314 | ||
bbc2ff6a | 315 | vmi_bringup(); |
bbc2ff6a GOC |
316 | cpu_init(); |
317 | preempt_disable(); | |
318 | smp_callin(); | |
319 | ||
320 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
321 | barrier(); | |
322 | /* | |
323 | * Check TSC synchronization with the BP: | |
324 | */ | |
325 | check_tsc_sync_target(); | |
326 | ||
327 | if (nmi_watchdog == NMI_IO_APIC) { | |
b81bb373 | 328 | legacy_pic->chip->mask(0); |
bbc2ff6a | 329 | enable_NMI_through_LVT0(); |
b81bb373 | 330 | legacy_pic->chip->unmask(0); |
bbc2ff6a GOC |
331 | } |
332 | ||
4f062896 | 333 | /* This must be done before setting cpu_online_mask */ |
bbc2ff6a GOC |
334 | set_cpu_sibling_map(raw_smp_processor_id()); |
335 | wmb(); | |
336 | ||
337 | /* | |
338 | * We need to hold call_lock, so there is no inconsistency | |
339 | * between the time smp_call_function() determines number of | |
340 | * IPI recipients, and the time when the determination is made | |
341 | * for which cpus receive the IPI. Holding this | |
342 | * lock helps us to not include this cpu in a currently in progress | |
343 | * smp_call_function(). | |
d388e5fd EB |
344 | * |
345 | * We need to hold vector_lock so there the set of online cpus | |
346 | * does not change while we are assigning vectors to cpus. Holding | |
347 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 348 | */ |
0cefa5b9 | 349 | ipi_call_lock(); |
d388e5fd | 350 | lock_vector_lock(); |
c2d1cec1 | 351 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 352 | unlock_vector_lock(); |
0cefa5b9 | 353 | ipi_call_unlock(); |
bbc2ff6a | 354 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 355 | x86_platform.nmi_init(); |
bbc2ff6a | 356 | |
0cefa5b9 MS |
357 | /* enable local interrupts */ |
358 | local_irq_enable(); | |
359 | ||
35f720c5 JP |
360 | /* to prevent fake stack check failure in clock setup */ |
361 | boot_init_stack_canary(); | |
0cefa5b9 | 362 | |
736decac | 363 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
364 | |
365 | wmb(); | |
366 | cpu_idle(); | |
367 | } | |
368 | ||
155dd720 RR |
369 | #ifdef CONFIG_CPUMASK_OFFSTACK |
370 | /* In this case, llc_shared_map is a pointer to a cpumask. */ | |
371 | static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, | |
372 | const struct cpuinfo_x86 *src) | |
373 | { | |
374 | struct cpumask *llc = dst->llc_shared_map; | |
375 | *dst = *src; | |
376 | dst->llc_shared_map = llc; | |
377 | } | |
378 | #else | |
379 | static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, | |
380 | const struct cpuinfo_x86 *src) | |
381 | { | |
382 | *dst = *src; | |
383 | } | |
384 | #endif /* CONFIG_CPUMASK_OFFSTACK */ | |
385 | ||
1d89a7f0 GOC |
386 | /* |
387 | * The bootstrap kernel entry code has set these up. Save them for | |
388 | * a given CPU | |
389 | */ | |
390 | ||
391 | void __cpuinit smp_store_cpu_info(int id) | |
392 | { | |
393 | struct cpuinfo_x86 *c = &cpu_data(id); | |
394 | ||
155dd720 | 395 | copy_cpuinfo_x86(c, &boot_cpu_data); |
1d89a7f0 GOC |
396 | c->cpu_index = id; |
397 | if (id != 0) | |
398 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
399 | } |
400 | ||
401 | ||
768d9505 GC |
402 | void __cpuinit set_cpu_sibling_map(int cpu) |
403 | { | |
404 | int i; | |
405 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
406 | ||
c2d1cec1 | 407 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
408 | |
409 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
410 | for_each_cpu(i, cpu_sibling_setup_mask) { |
411 | struct cpuinfo_x86 *o = &cpu_data(i); | |
412 | ||
413 | if (c->phys_proc_id == o->phys_proc_id && | |
414 | c->cpu_core_id == o->cpu_core_id) { | |
415 | cpumask_set_cpu(i, cpu_sibling_mask(cpu)); | |
416 | cpumask_set_cpu(cpu, cpu_sibling_mask(i)); | |
417 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
418 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
155dd720 RR |
419 | cpumask_set_cpu(i, c->llc_shared_map); |
420 | cpumask_set_cpu(cpu, o->llc_shared_map); | |
768d9505 GC |
421 | } |
422 | } | |
423 | } else { | |
c2d1cec1 | 424 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
425 | } |
426 | ||
155dd720 | 427 | cpumask_set_cpu(cpu, c->llc_shared_map); |
768d9505 GC |
428 | |
429 | if (current_cpu_data.x86_max_cores == 1) { | |
c2d1cec1 | 430 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
431 | c->booted_cores = 1; |
432 | return; | |
433 | } | |
434 | ||
c2d1cec1 | 435 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
436 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
437 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
155dd720 RR |
438 | cpumask_set_cpu(i, c->llc_shared_map); |
439 | cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); | |
768d9505 GC |
440 | } |
441 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
442 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
443 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
444 | /* |
445 | * Does this new cpu bringup a new core? | |
446 | */ | |
c2d1cec1 | 447 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
448 | /* |
449 | * for each core in package, increment | |
450 | * the booted_cores for this new cpu | |
451 | */ | |
c2d1cec1 | 452 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
453 | c->booted_cores++; |
454 | /* | |
455 | * increment the core count for all | |
456 | * the other cpus in this package | |
457 | */ | |
458 | if (i != cpu) | |
459 | cpu_data(i).booted_cores++; | |
460 | } else if (i != cpu && !c->booted_cores) | |
461 | c->booted_cores = cpu_data(i).booted_cores; | |
462 | } | |
463 | } | |
464 | } | |
465 | ||
70708a18 | 466 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 467 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
468 | { |
469 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
470 | /* | |
471 | * For perf, we return last level cache shared map. | |
472 | * And for power savings, we return cpu_core_map | |
473 | */ | |
5a925b42 AH |
474 | if ((sched_mc_power_savings || sched_smt_power_savings) && |
475 | !(cpu_has(c, X86_FEATURE_AMD_DCM))) | |
c2d1cec1 | 476 | return cpu_core_mask(cpu); |
70708a18 | 477 | else |
155dd720 | 478 | return c->llc_shared_map; |
030bb203 RR |
479 | } |
480 | ||
a4928cff | 481 | static void impress_friends(void) |
904541e2 GOC |
482 | { |
483 | int cpu; | |
484 | unsigned long bogosum = 0; | |
485 | /* | |
486 | * Allow the user to impress friends. | |
487 | */ | |
cfc1b9a6 | 488 | pr_debug("Before bogomips.\n"); |
904541e2 | 489 | for_each_possible_cpu(cpu) |
c2d1cec1 | 490 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
491 | bogosum += cpu_data(cpu).loops_per_jiffy; |
492 | printk(KERN_INFO | |
493 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 494 | num_online_cpus(), |
904541e2 GOC |
495 | bogosum/(500000/HZ), |
496 | (bogosum/(5000/HZ))%100); | |
497 | ||
cfc1b9a6 | 498 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
499 | } |
500 | ||
569712b2 | 501 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
502 | { |
503 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
504 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
505 | int timeout; | |
506 | u32 status; | |
507 | ||
823b259b | 508 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
509 | |
510 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 511 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
512 | |
513 | /* | |
514 | * Wait for idle. | |
515 | */ | |
516 | status = safe_apic_wait_icr_idle(); | |
517 | if (status) | |
518 | printk(KERN_CONT | |
519 | "a previous APIC delivery may have failed\n"); | |
520 | ||
1b374e4d | 521 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
522 | |
523 | timeout = 0; | |
524 | do { | |
525 | udelay(100); | |
526 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
527 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
528 | ||
529 | switch (status) { | |
530 | case APIC_ICR_RR_VALID: | |
531 | status = apic_read(APIC_RRR); | |
532 | printk(KERN_CONT "%08x\n", status); | |
533 | break; | |
534 | default: | |
535 | printk(KERN_CONT "failed\n"); | |
536 | } | |
537 | } | |
538 | } | |
539 | ||
cb3c8b90 GOC |
540 | /* |
541 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
542 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
543 | * won't ... remember to clear down the APIC, etc later. | |
544 | */ | |
cece3155 | 545 | int __cpuinit |
569712b2 | 546 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
547 | { |
548 | unsigned long send_status, accept_status = 0; | |
549 | int maxlvt; | |
550 | ||
551 | /* Target chip */ | |
cb3c8b90 GOC |
552 | /* Boot on the stack */ |
553 | /* Kick the second */ | |
bdb1a9b6 | 554 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 555 | |
cfc1b9a6 | 556 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
557 | send_status = safe_apic_wait_icr_idle(); |
558 | ||
559 | /* | |
560 | * Give the other CPU some time to accept the IPI. | |
561 | */ | |
562 | udelay(200); | |
569712b2 | 563 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
564 | maxlvt = lapic_get_maxlvt(); |
565 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
566 | apic_write(APIC_ESR, 0); | |
567 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
568 | } | |
cfc1b9a6 | 569 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
570 | |
571 | if (send_status) | |
572 | printk(KERN_ERR "APIC never delivered???\n"); | |
573 | if (accept_status) | |
574 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
575 | ||
576 | return (send_status | accept_status); | |
577 | } | |
cb3c8b90 | 578 | |
cece3155 | 579 | static int __cpuinit |
569712b2 | 580 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
581 | { |
582 | unsigned long send_status, accept_status = 0; | |
583 | int maxlvt, num_starts, j; | |
584 | ||
593f4a78 MR |
585 | maxlvt = lapic_get_maxlvt(); |
586 | ||
cb3c8b90 GOC |
587 | /* |
588 | * Be paranoid about clearing APIC errors. | |
589 | */ | |
590 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
591 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
592 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
593 | apic_read(APIC_ESR); |
594 | } | |
595 | ||
cfc1b9a6 | 596 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
597 | |
598 | /* | |
599 | * Turn INIT on target chip | |
600 | */ | |
cb3c8b90 GOC |
601 | /* |
602 | * Send IPI | |
603 | */ | |
1b374e4d SS |
604 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
605 | phys_apicid); | |
cb3c8b90 | 606 | |
cfc1b9a6 | 607 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
608 | send_status = safe_apic_wait_icr_idle(); |
609 | ||
610 | mdelay(10); | |
611 | ||
cfc1b9a6 | 612 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
613 | |
614 | /* Target chip */ | |
cb3c8b90 | 615 | /* Send IPI */ |
1b374e4d | 616 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 617 | |
cfc1b9a6 | 618 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
619 | send_status = safe_apic_wait_icr_idle(); |
620 | ||
621 | mb(); | |
622 | atomic_set(&init_deasserted, 1); | |
623 | ||
624 | /* | |
625 | * Should we send STARTUP IPIs ? | |
626 | * | |
627 | * Determine this based on the APIC version. | |
628 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
629 | */ | |
630 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
631 | num_starts = 2; | |
632 | else | |
633 | num_starts = 0; | |
634 | ||
635 | /* | |
636 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
637 | * target processor state. | |
638 | */ | |
639 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 640 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
641 | |
642 | /* | |
643 | * Run STARTUP IPI loop. | |
644 | */ | |
cfc1b9a6 | 645 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 646 | |
cb3c8b90 | 647 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 648 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
649 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
650 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 651 | apic_read(APIC_ESR); |
cfc1b9a6 | 652 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
653 | |
654 | /* | |
655 | * STARTUP IPI | |
656 | */ | |
657 | ||
658 | /* Target chip */ | |
cb3c8b90 GOC |
659 | /* Boot on the stack */ |
660 | /* Kick the second */ | |
1b374e4d SS |
661 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
662 | phys_apicid); | |
cb3c8b90 GOC |
663 | |
664 | /* | |
665 | * Give the other CPU some time to accept the IPI. | |
666 | */ | |
667 | udelay(300); | |
668 | ||
cfc1b9a6 | 669 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 670 | |
cfc1b9a6 | 671 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
672 | send_status = safe_apic_wait_icr_idle(); |
673 | ||
674 | /* | |
675 | * Give the other CPU some time to accept the IPI. | |
676 | */ | |
677 | udelay(200); | |
593f4a78 | 678 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 679 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
680 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
681 | if (send_status || accept_status) | |
682 | break; | |
683 | } | |
cfc1b9a6 | 684 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
685 | |
686 | if (send_status) | |
687 | printk(KERN_ERR "APIC never delivered???\n"); | |
688 | if (accept_status) | |
689 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
690 | ||
691 | return (send_status | accept_status); | |
692 | } | |
cb3c8b90 GOC |
693 | |
694 | struct create_idle { | |
695 | struct work_struct work; | |
696 | struct task_struct *idle; | |
697 | struct completion done; | |
698 | int cpu; | |
699 | }; | |
700 | ||
701 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
702 | { | |
703 | struct create_idle *c_idle = | |
704 | container_of(work, struct create_idle, work); | |
705 | ||
706 | c_idle->idle = fork_idle(c_idle->cpu); | |
707 | complete(&c_idle->done); | |
708 | } | |
709 | ||
2eaad1fd MT |
710 | /* reduce the number of lines printed when booting a large cpu count system */ |
711 | static void __cpuinit announce_cpu(int cpu, int apicid) | |
712 | { | |
713 | static int current_node = -1; | |
4adc8b71 | 714 | int node = early_cpu_to_node(cpu); |
2eaad1fd MT |
715 | |
716 | if (system_state == SYSTEM_BOOTING) { | |
717 | if (node != current_node) { | |
718 | if (current_node > (-1)) | |
719 | pr_cont(" Ok.\n"); | |
720 | current_node = node; | |
721 | pr_info("Booting Node %3d, Processors ", node); | |
722 | } | |
723 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); | |
724 | return; | |
725 | } else | |
726 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
727 | node, cpu, apicid); | |
728 | } | |
729 | ||
cb3c8b90 GOC |
730 | /* |
731 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
732 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
733 | * Returns zero if CPU booted OK, else error code from |
734 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 735 | */ |
ab6fb7c0 | 736 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
737 | { |
738 | unsigned long boot_error = 0; | |
cb3c8b90 | 739 | unsigned long start_ip; |
ab6fb7c0 | 740 | int timeout; |
cb3c8b90 | 741 | struct create_idle c_idle = { |
ab6fb7c0 IM |
742 | .cpu = cpu, |
743 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 744 | }; |
ab6fb7c0 | 745 | |
dc186ad7 | 746 | INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 747 | |
cb3c8b90 GOC |
748 | alternatives_smp_switch(1); |
749 | ||
750 | c_idle.idle = get_idle_for_cpu(cpu); | |
751 | ||
752 | /* | |
753 | * We can't use kernel_thread since we must avoid to | |
754 | * reschedule the child. | |
755 | */ | |
756 | if (c_idle.idle) { | |
757 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
758 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
759 | init_idle(c_idle.idle, cpu); | |
760 | goto do_rest; | |
761 | } | |
762 | ||
d7a7c573 SS |
763 | schedule_work(&c_idle.work); |
764 | wait_for_completion(&c_idle.done); | |
cb3c8b90 GOC |
765 | |
766 | if (IS_ERR(c_idle.idle)) { | |
767 | printk("failed fork for CPU %d\n", cpu); | |
dc186ad7 | 768 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
769 | return PTR_ERR(c_idle.idle); |
770 | } | |
771 | ||
772 | set_idle_for_cpu(cpu, c_idle.idle); | |
773 | do_rest: | |
cb3c8b90 | 774 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 775 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 776 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 | 777 | irq_ctx_init(cpu); |
fd89a137 | 778 | initial_page_table = __pa(&trampoline_pg_dir); |
cb3c8b90 | 779 | #else |
cb3c8b90 | 780 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 781 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
782 | per_cpu(kernel_stack, cpu) = |
783 | (unsigned long)task_stack_page(c_idle.idle) - | |
784 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 785 | #endif |
a939098a | 786 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 787 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 788 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
789 | |
790 | /* start_ip had better be page-aligned! */ | |
791 | start_ip = setup_trampoline(); | |
792 | ||
2eaad1fd MT |
793 | /* So we see what's up */ |
794 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
795 | |
796 | /* | |
797 | * This grunge runs the startup process for | |
798 | * the targeted processor. | |
799 | */ | |
800 | ||
801 | atomic_set(&init_deasserted, 0); | |
802 | ||
34d05591 | 803 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 804 | |
cfc1b9a6 | 805 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 806 | |
34d05591 JS |
807 | smpboot_setup_warm_reset_vector(start_ip); |
808 | /* | |
809 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
810 | */ |
811 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
812 | apic_write(APIC_ESR, 0); | |
813 | apic_read(APIC_ESR); | |
814 | } | |
34d05591 | 815 | } |
cb3c8b90 | 816 | |
cb3c8b90 | 817 | /* |
1f5bcabf IM |
818 | * Kick the secondary CPU. Use the method in the APIC driver |
819 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 820 | */ |
1f5bcabf IM |
821 | if (apic->wakeup_secondary_cpu) |
822 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
823 | else | |
824 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
825 | |
826 | if (!boot_error) { | |
827 | /* | |
828 | * allow APs to start initializing. | |
829 | */ | |
cfc1b9a6 | 830 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 831 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 832 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
833 | |
834 | /* | |
835 | * Wait 5s total for a response | |
836 | */ | |
837 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 838 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
839 | break; /* It has booted */ |
840 | udelay(100); | |
68f202e4 SS |
841 | /* |
842 | * Allow other tasks to run while we wait for the | |
843 | * AP to come online. This also gives a chance | |
844 | * for the MTRR work(triggered by the AP coming online) | |
845 | * to be completed in the stop machine context. | |
846 | */ | |
847 | schedule(); | |
cb3c8b90 GOC |
848 | } |
849 | ||
2eaad1fd MT |
850 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
851 | pr_debug("CPU%d: has booted.\n", cpu); | |
852 | else { | |
cb3c8b90 GOC |
853 | boot_error = 1; |
854 | if (*((volatile unsigned char *)trampoline_base) | |
855 | == 0xA5) | |
856 | /* trampoline started but...? */ | |
2eaad1fd | 857 | pr_err("CPU%d: Stuck ??\n", cpu); |
cb3c8b90 GOC |
858 | else |
859 | /* trampoline code not run */ | |
2eaad1fd | 860 | pr_err("CPU%d: Not responding.\n", cpu); |
25dc0049 IM |
861 | if (apic->inquire_remote_apic) |
862 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
863 | } |
864 | } | |
1a51e3a0 | 865 | |
cb3c8b90 GOC |
866 | if (boot_error) { |
867 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 868 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
869 | |
870 | /* was set by do_boot_cpu() */ | |
871 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
872 | ||
873 | /* was set by cpu_init() */ | |
874 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
875 | ||
876 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
877 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
878 | } | |
879 | ||
880 | /* mark "stuck" area as not stuck */ | |
881 | *((volatile unsigned long *)trampoline_base) = 0; | |
882 | ||
02421f98 YL |
883 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
884 | /* | |
885 | * Cleanup possible dangling ends... | |
886 | */ | |
887 | smpboot_restore_warm_reset_vector(); | |
888 | } | |
63d38198 | 889 | |
dc186ad7 | 890 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
891 | return boot_error; |
892 | } | |
893 | ||
894 | int __cpuinit native_cpu_up(unsigned int cpu) | |
895 | { | |
a21769a4 | 896 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
897 | unsigned long flags; |
898 | int err; | |
899 | ||
900 | WARN_ON(irqs_disabled()); | |
901 | ||
cfc1b9a6 | 902 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
903 | |
904 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
905 | !physid_isset(apicid, phys_cpu_present_map)) { | |
906 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
907 | return -EINVAL; | |
908 | } | |
909 | ||
910 | /* | |
911 | * Already booted CPU? | |
912 | */ | |
c2d1cec1 | 913 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 914 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
915 | return -ENOSYS; |
916 | } | |
917 | ||
918 | /* | |
919 | * Save current MTRR state in case it was changed since early boot | |
920 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
921 | */ | |
922 | mtrr_save_state(); | |
923 | ||
924 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
925 | ||
cb3c8b90 | 926 | err = do_boot_cpu(apicid, cpu); |
61165d7a | 927 | |
61165d7a | 928 | if (err) { |
cfc1b9a6 | 929 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 930 | return -EIO; |
cb3c8b90 GOC |
931 | } |
932 | ||
933 | /* | |
934 | * Check TSC synchronization with the AP (keep irqs disabled | |
935 | * while doing so): | |
936 | */ | |
937 | local_irq_save(flags); | |
938 | check_tsc_sync_source(cpu); | |
939 | local_irq_restore(flags); | |
940 | ||
7c04e64a | 941 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
942 | cpu_relax(); |
943 | touch_nmi_watchdog(); | |
944 | } | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
8aef135c GOC |
949 | /* |
950 | * Fall back to non SMP mode after errors. | |
951 | * | |
952 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
953 | */ | |
954 | static __init void disable_smp(void) | |
955 | { | |
4f062896 RR |
956 | init_cpu_present(cpumask_of(0)); |
957 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 958 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 959 | |
8aef135c | 960 | if (smp_found_config) |
b6df1b8b | 961 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 962 | else |
b6df1b8b | 963 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c | 964 | map_cpu_to_logical_apicid(); |
c2d1cec1 MT |
965 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
966 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
967 | } |
968 | ||
969 | /* | |
970 | * Various sanity checks. | |
971 | */ | |
972 | static int __init smp_sanity_check(unsigned max_cpus) | |
973 | { | |
ac23d4ee | 974 | preempt_disable(); |
a58f03b0 | 975 | |
1ff2f20d | 976 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
977 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
978 | unsigned int cpu; | |
979 | unsigned nr; | |
980 | ||
981 | printk(KERN_WARNING | |
982 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 983 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
984 | |
985 | nr = 0; | |
986 | for_each_present_cpu(cpu) { | |
987 | if (nr >= 8) | |
c2d1cec1 | 988 | set_cpu_present(cpu, false); |
a58f03b0 YL |
989 | nr++; |
990 | } | |
991 | ||
992 | nr = 0; | |
993 | for_each_possible_cpu(cpu) { | |
994 | if (nr >= 8) | |
c2d1cec1 | 995 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
996 | nr++; |
997 | } | |
998 | ||
999 | nr_cpu_ids = 8; | |
1000 | } | |
1001 | #endif | |
1002 | ||
8aef135c | 1003 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
1004 | printk(KERN_WARNING |
1005 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1006 | hard_smp_processor_id()); | |
1007 | ||
8aef135c GOC |
1008 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1009 | } | |
1010 | ||
1011 | /* | |
1012 | * If we couldn't find an SMP configuration at boot time, | |
1013 | * get out of here now! | |
1014 | */ | |
1015 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1016 | preempt_enable(); |
8aef135c GOC |
1017 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
1018 | disable_smp(); | |
1019 | if (APIC_init_uniprocessor()) | |
1020 | printk(KERN_NOTICE "Local APIC not detected." | |
1021 | " Using dummy APIC emulation.\n"); | |
1022 | return -1; | |
1023 | } | |
1024 | ||
1025 | /* | |
1026 | * Should not be necessary because the MP table should list the boot | |
1027 | * CPU too, but we do it for the sake of robustness anyway. | |
1028 | */ | |
a27a6210 | 1029 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
1030 | printk(KERN_NOTICE |
1031 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1032 | boot_cpu_physical_apicid); | |
1033 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1034 | } | |
ac23d4ee | 1035 | preempt_enable(); |
8aef135c GOC |
1036 | |
1037 | /* | |
1038 | * If we couldn't find a local APIC, then get out of here now! | |
1039 | */ | |
1040 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1041 | !cpu_has_apic) { | |
103428e5 CG |
1042 | if (!disable_apic) { |
1043 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1044 | boot_cpu_physical_apicid); | |
1045 | pr_err("... forcing use of dummy APIC emulation." | |
8aef135c | 1046 | "(tell your hw vendor)\n"); |
103428e5 | 1047 | } |
8aef135c | 1048 | smpboot_clear_io_apic(); |
65a4e574 | 1049 | arch_disable_smp_support(); |
8aef135c GOC |
1050 | return -1; |
1051 | } | |
1052 | ||
1053 | verify_local_APIC(); | |
1054 | ||
1055 | /* | |
1056 | * If SMP should be disabled, then really disable it! | |
1057 | */ | |
1058 | if (!max_cpus) { | |
73d08e63 | 1059 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1060 | smpboot_clear_io_apic(); |
d54db1ac MR |
1061 | |
1062 | localise_nmi_watchdog(); | |
1063 | ||
e90955c2 | 1064 | connect_bsp_APIC(); |
e90955c2 JB |
1065 | setup_local_APIC(); |
1066 | end_local_APIC_setup(); | |
8aef135c GOC |
1067 | return -1; |
1068 | } | |
1069 | ||
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | static void __init smp_cpu_index_default(void) | |
1074 | { | |
1075 | int i; | |
1076 | struct cpuinfo_x86 *c; | |
1077 | ||
7c04e64a | 1078 | for_each_possible_cpu(i) { |
8aef135c GOC |
1079 | c = &cpu_data(i); |
1080 | /* mark all to hotplug */ | |
9628937d | 1081 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1082 | } |
1083 | } | |
1084 | ||
1085 | /* | |
1086 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1087 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1088 | */ | |
1089 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1090 | { | |
7ad728f9 RR |
1091 | unsigned int i; |
1092 | ||
deef3250 | 1093 | preempt_disable(); |
8aef135c GOC |
1094 | smp_cpu_index_default(); |
1095 | current_cpu_data = boot_cpu_data; | |
c2d1cec1 | 1096 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
8aef135c GOC |
1097 | mb(); |
1098 | /* | |
1099 | * Setup boot CPU information | |
1100 | */ | |
1101 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1102 | #ifdef CONFIG_X86_32 |
8aef135c | 1103 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1104 | #endif |
8aef135c | 1105 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1106 | for_each_possible_cpu(i) { |
79f55997 LZ |
1107 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1108 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
1109 | zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); | |
7ad728f9 | 1110 | } |
8aef135c GOC |
1111 | set_cpu_sibling_map(0); |
1112 | ||
6e1cb38a | 1113 | enable_IR_x2apic(); |
72ce0165 | 1114 | default_setup_apic_routing(); |
6e1cb38a | 1115 | |
8aef135c GOC |
1116 | if (smp_sanity_check(max_cpus) < 0) { |
1117 | printk(KERN_INFO "SMP disabled\n"); | |
1118 | disable_smp(); | |
deef3250 | 1119 | goto out; |
8aef135c GOC |
1120 | } |
1121 | ||
ac23d4ee | 1122 | preempt_disable(); |
4c9961d5 | 1123 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1124 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1125 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1126 | /* Or can we switch back to PIC here? */ |
1127 | } | |
ac23d4ee | 1128 | preempt_enable(); |
8aef135c | 1129 | |
8aef135c | 1130 | connect_bsp_APIC(); |
b5841765 | 1131 | |
8aef135c GOC |
1132 | /* |
1133 | * Switch from PIC to APIC mode. | |
1134 | */ | |
1135 | setup_local_APIC(); | |
1136 | ||
8aef135c GOC |
1137 | /* |
1138 | * Enable IO APIC before setting up error vector | |
1139 | */ | |
1140 | if (!skip_ioapic_setup && nr_ioapics) | |
1141 | enable_IO_APIC(); | |
88d0f550 | 1142 | |
8aef135c GOC |
1143 | end_local_APIC_setup(); |
1144 | ||
1145 | map_cpu_to_logical_apicid(); | |
1146 | ||
d83093b5 IM |
1147 | if (apic->setup_portio_remap) |
1148 | apic->setup_portio_remap(); | |
8aef135c GOC |
1149 | |
1150 | smpboot_setup_io_apic(); | |
1151 | /* | |
1152 | * Set up local APIC timer on boot CPU. | |
1153 | */ | |
1154 | ||
1155 | printk(KERN_INFO "CPU%d: ", 0); | |
1156 | print_cpu_info(&cpu_data(0)); | |
736decac | 1157 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1158 | |
1159 | if (is_uv_system()) | |
1160 | uv_system_init(); | |
d0af9eed SS |
1161 | |
1162 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1163 | out: |
1164 | preempt_enable(); | |
8aef135c | 1165 | } |
d0af9eed SS |
1166 | |
1167 | void arch_enable_nonboot_cpus_begin(void) | |
1168 | { | |
1169 | set_mtrr_aps_delayed_init(); | |
1170 | } | |
1171 | ||
1172 | void arch_enable_nonboot_cpus_end(void) | |
1173 | { | |
1174 | mtrr_aps_init(); | |
1175 | } | |
1176 | ||
a8db8453 GOC |
1177 | /* |
1178 | * Early setup to make printk work. | |
1179 | */ | |
1180 | void __init native_smp_prepare_boot_cpu(void) | |
1181 | { | |
1182 | int me = smp_processor_id(); | |
552be871 | 1183 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1184 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1185 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1186 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1187 | } | |
1188 | ||
83f7eb9c GOC |
1189 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1190 | { | |
cfc1b9a6 | 1191 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1192 | |
1193 | impress_friends(); | |
83f7eb9c GOC |
1194 | #ifdef CONFIG_X86_IO_APIC |
1195 | setup_ioapic_dest(); | |
1196 | #endif | |
1197 | check_nmi_watchdog(); | |
d0af9eed | 1198 | mtrr_aps_init(); |
83f7eb9c GOC |
1199 | } |
1200 | ||
3b11ce7f MT |
1201 | static int __initdata setup_possible_cpus = -1; |
1202 | static int __init _setup_possible_cpus(char *str) | |
1203 | { | |
1204 | get_option(&str, &setup_possible_cpus); | |
1205 | return 0; | |
1206 | } | |
1207 | early_param("possible_cpus", _setup_possible_cpus); | |
1208 | ||
1209 | ||
68a1c3f8 | 1210 | /* |
4f062896 | 1211 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1212 | * are onlined, or offlined. The reason is per-cpu data-structures |
1213 | * are allocated by some modules at init time, and dont expect to | |
1214 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1215 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1216 | * In case when cpu_hotplug is not compiled, then we resort to current |
1217 | * behaviour, which is cpu_possible == cpu_present. | |
1218 | * - Ashok Raj | |
1219 | * | |
1220 | * Three ways to find out the number of additional hotplug CPUs: | |
1221 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1222 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1223 | * - Otherwise don't reserve additional CPUs. |
1224 | * We do this because additional CPUs waste a lot of memory. | |
1225 | * -AK | |
1226 | */ | |
1227 | __init void prefill_possible_map(void) | |
1228 | { | |
cb48bb59 | 1229 | int i, possible; |
68a1c3f8 | 1230 | |
329513a3 YL |
1231 | /* no processor from mptable or madt */ |
1232 | if (!num_processors) | |
1233 | num_processors = 1; | |
1234 | ||
5f2eb550 JB |
1235 | i = setup_max_cpus ?: 1; |
1236 | if (setup_possible_cpus == -1) { | |
1237 | possible = num_processors; | |
1238 | #ifdef CONFIG_HOTPLUG_CPU | |
1239 | if (setup_max_cpus) | |
1240 | possible += disabled_cpus; | |
1241 | #else | |
1242 | if (possible > i) | |
1243 | possible = i; | |
1244 | #endif | |
1245 | } else | |
3b11ce7f MT |
1246 | possible = setup_possible_cpus; |
1247 | ||
730cf272 MT |
1248 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1249 | ||
2b633e3f YL |
1250 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1251 | if (possible > nr_cpu_ids) { | |
3b11ce7f MT |
1252 | printk(KERN_WARNING |
1253 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
2b633e3f YL |
1254 | possible, nr_cpu_ids); |
1255 | possible = nr_cpu_ids; | |
3b11ce7f | 1256 | } |
68a1c3f8 | 1257 | |
5f2eb550 JB |
1258 | #ifdef CONFIG_HOTPLUG_CPU |
1259 | if (!setup_max_cpus) | |
1260 | #endif | |
1261 | if (possible > i) { | |
1262 | printk(KERN_WARNING | |
1263 | "%d Processors exceeds max_cpus limit of %u\n", | |
1264 | possible, setup_max_cpus); | |
1265 | possible = i; | |
1266 | } | |
1267 | ||
68a1c3f8 GC |
1268 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", |
1269 | possible, max_t(int, possible - num_processors, 0)); | |
1270 | ||
1271 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1272 | set_cpu_possible(i, true); |
5f2eb550 JB |
1273 | for (; i < NR_CPUS; i++) |
1274 | set_cpu_possible(i, false); | |
3461b0af MT |
1275 | |
1276 | nr_cpu_ids = possible; | |
68a1c3f8 | 1277 | } |
69c18c15 | 1278 | |
14adf855 CE |
1279 | #ifdef CONFIG_HOTPLUG_CPU |
1280 | ||
1281 | static void remove_siblinginfo(int cpu) | |
1282 | { | |
1283 | int sibling; | |
1284 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1285 | ||
c2d1cec1 MT |
1286 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1287 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1288 | /*/ |
1289 | * last thread sibling in this cpu core going down | |
1290 | */ | |
c2d1cec1 | 1291 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1292 | cpu_data(sibling).booted_cores--; |
1293 | } | |
1294 | ||
c2d1cec1 MT |
1295 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1296 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1297 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1298 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1299 | c->phys_proc_id = 0; |
1300 | c->cpu_core_id = 0; | |
c2d1cec1 | 1301 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1302 | } |
1303 | ||
69c18c15 GC |
1304 | static void __ref remove_cpu_from_maps(int cpu) |
1305 | { | |
c2d1cec1 MT |
1306 | set_cpu_online(cpu, false); |
1307 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1308 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1309 | /* was set by cpu_init() */ |
c2d1cec1 | 1310 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1311 | numa_remove_cpu(cpu); |
69c18c15 GC |
1312 | } |
1313 | ||
8227dce7 | 1314 | void cpu_disable_common(void) |
69c18c15 GC |
1315 | { |
1316 | int cpu = smp_processor_id(); | |
69c18c15 | 1317 | |
69c18c15 GC |
1318 | remove_siblinginfo(cpu); |
1319 | ||
1320 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1321 | lock_vector_lock(); |
69c18c15 | 1322 | remove_cpu_from_maps(cpu); |
d388e5fd | 1323 | unlock_vector_lock(); |
d7b381bb | 1324 | fixup_irqs(); |
8227dce7 AN |
1325 | } |
1326 | ||
1327 | int native_cpu_disable(void) | |
1328 | { | |
1329 | int cpu = smp_processor_id(); | |
1330 | ||
1331 | /* | |
1332 | * Perhaps use cpufreq to drop frequency, but that could go | |
1333 | * into generic code. | |
1334 | * | |
1335 | * We won't take down the boot processor on i386 due to some | |
1336 | * interrupts only being able to be serviced by the BSP. | |
1337 | * Especially so if we're not using an IOAPIC -zwane | |
1338 | */ | |
1339 | if (cpu == 0) | |
1340 | return -EBUSY; | |
1341 | ||
1342 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1343 | stop_apic_nmi_watchdog(NULL); | |
1344 | clear_local_APIC(); | |
1345 | ||
1346 | cpu_disable_common(); | |
69c18c15 GC |
1347 | return 0; |
1348 | } | |
1349 | ||
93be71b6 | 1350 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1351 | { |
1352 | /* We don't do anything here: idle task is faking death itself. */ | |
1353 | unsigned int i; | |
1354 | ||
1355 | for (i = 0; i < 10; i++) { | |
1356 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1357 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
2eaad1fd MT |
1358 | if (system_state == SYSTEM_RUNNING) |
1359 | pr_info("CPU %u is now offline\n", cpu); | |
1360 | ||
69c18c15 GC |
1361 | if (1 == num_online_cpus()) |
1362 | alternatives_smp_switch(0); | |
1363 | return; | |
1364 | } | |
1365 | msleep(100); | |
1366 | } | |
2eaad1fd | 1367 | pr_err("CPU %u didn't die...\n", cpu); |
69c18c15 | 1368 | } |
a21f5d88 AN |
1369 | |
1370 | void play_dead_common(void) | |
1371 | { | |
1372 | idle_task_exit(); | |
1373 | reset_lazy_tlbstate(); | |
1374 | irq_ctx_exit(raw_smp_processor_id()); | |
07bbc16a | 1375 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1376 | |
1377 | mb(); | |
1378 | /* Ack it */ | |
1379 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
1380 | ||
1381 | /* | |
1382 | * With physical CPU hotplug, we should halt the cpu | |
1383 | */ | |
1384 | local_irq_disable(); | |
1385 | } | |
1386 | ||
ea530692 PA |
1387 | /* |
1388 | * We need to flush the caches before going to sleep, lest we have | |
1389 | * dirty data in our caches when we come back up. | |
1390 | */ | |
1391 | static inline void mwait_play_dead(void) | |
1392 | { | |
1393 | unsigned int eax, ebx, ecx, edx; | |
1394 | unsigned int highest_cstate = 0; | |
1395 | unsigned int highest_subcstate = 0; | |
1396 | int i; | |
1397 | ||
1398 | if (!cpu_has(¤t_cpu_data, X86_FEATURE_MWAIT)) | |
1399 | return; | |
1400 | if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) | |
1401 | return; | |
1402 | ||
1403 | eax = CPUID_MWAIT_LEAF; | |
1404 | ecx = 0; | |
1405 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1406 | ||
1407 | /* | |
1408 | * eax will be 0 if EDX enumeration is not valid. | |
1409 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1410 | */ | |
1411 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1412 | eax = 0; | |
1413 | } else { | |
1414 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1415 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1416 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1417 | highest_cstate = i; | |
1418 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1419 | } | |
1420 | } | |
1421 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1422 | (highest_subcstate - 1); | |
1423 | } | |
1424 | ||
1425 | while (1) { | |
1426 | mb(); | |
1427 | wbinvd(); | |
1428 | __monitor(¤t_thread_info()->flags, 0, 0); | |
1429 | mb(); | |
1430 | __mwait(eax, 0); | |
1431 | } | |
1432 | } | |
1433 | ||
1434 | static inline void hlt_play_dead(void) | |
1435 | { | |
1436 | while (1) { | |
1437 | mb(); | |
1438 | if (current_cpu_data.x86 >= 4) | |
1439 | wbinvd(); | |
1440 | mb(); | |
1441 | native_halt(); | |
1442 | } | |
1443 | } | |
1444 | ||
a21f5d88 AN |
1445 | void native_play_dead(void) |
1446 | { | |
1447 | play_dead_common(); | |
86886e55 | 1448 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1449 | |
1450 | mwait_play_dead(); /* Only returns on failure */ | |
1451 | hlt_play_dead(); | |
a21f5d88 AN |
1452 | } |
1453 | ||
69c18c15 | 1454 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1455 | int native_cpu_disable(void) |
69c18c15 GC |
1456 | { |
1457 | return -ENOSYS; | |
1458 | } | |
1459 | ||
93be71b6 | 1460 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1461 | { |
1462 | /* We said "no" in __cpu_disable */ | |
1463 | BUG(); | |
1464 | } | |
a21f5d88 AN |
1465 | |
1466 | void native_play_dead(void) | |
1467 | { | |
1468 | BUG(); | |
1469 | } | |
1470 | ||
68a1c3f8 | 1471 | #endif |